1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007 Marvell Semiconductor, Inc. 5 * Copyright (c) 2007 Sam Leffler, Errno Consulting 6 * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 17 * redistribution must be conditioned upon including a substantially 18 * similar Disclaimer requirement for further binary redistribution. 19 * 20 * NO WARRANTY 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGES. 32 */ 33 34 #include <sys/cdefs.h> 35 #ifdef __FreeBSD__ 36 __FBSDID("$FreeBSD$"); 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/endian.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/firmware.h> 45 #include <sys/socket.h> 46 47 #include <machine/bus.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/ethernet.h> 55 56 #include <net80211/ieee80211_var.h> 57 58 #include <dev/malo/if_malo.h> 59 60 #define MALO_WAITOK 1 61 #define MALO_NOWAIT 0 62 63 #define _CMD_SETUP(pCmd, _type, _cmd) do { \ 64 pCmd = (_type *)&mh->mh_cmdbuf[0]; \ 65 memset(pCmd, 0, sizeof(_type)); \ 66 pCmd->cmdhdr.cmd = htole16(_cmd); \ 67 pCmd->cmdhdr.length = htole16(sizeof(_type)); \ 68 } while (0) 69 70 static __inline uint32_t 71 malo_hal_read4(struct malo_hal *mh, bus_size_t off) 72 { 73 return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off); 74 } 75 76 static __inline void 77 malo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val) 78 { 79 bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val); 80 } 81 82 static void 83 malo_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 84 { 85 bus_addr_t *paddr = (bus_addr_t*) arg; 86 87 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 88 *paddr = segs->ds_addr; 89 } 90 91 /* 92 * Setup for communication with the device. We allocate 93 * a command buffer and map it for bus dma use. The pci 94 * device id is used to identify whether the device has 95 * SRAM on it (in which case f/w download must include a 96 * memory controller reset). All bus i/o operations happen 97 * in BAR 1; the driver passes in the tag and handle we need. 98 */ 99 struct malo_hal * 100 malo_hal_attach(device_t dev, uint16_t devid, 101 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag) 102 { 103 int error; 104 struct malo_hal *mh; 105 106 mh = malloc(sizeof(struct malo_hal), M_DEVBUF, M_NOWAIT | M_ZERO); 107 if (mh == NULL) 108 return NULL; 109 110 mh->mh_dev = dev; 111 mh->mh_ioh = ioh; 112 mh->mh_iot = iot; 113 114 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname), 115 "%s_hal", device_get_nameunit(dev)); 116 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF); 117 118 /* 119 * Allocate the command buffer and map into the address 120 * space of the h/w. We request "coherent" memory which 121 * will be uncached on some architectures. 122 */ 123 error = bus_dma_tag_create(tag, /* parent */ 124 PAGE_SIZE, 0, /* alignment, bounds */ 125 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 126 BUS_SPACE_MAXADDR, /* highaddr */ 127 NULL, NULL, /* filter, filterarg */ 128 MALO_CMDBUF_SIZE, /* maxsize */ 129 1, /* nsegments */ 130 MALO_CMDBUF_SIZE, /* maxsegsize */ 131 BUS_DMA_ALLOCNOW, /* flags */ 132 NULL, /* lockfunc */ 133 NULL, /* lockarg */ 134 &mh->mh_dmat); 135 if (error != 0) { 136 device_printf(dev, "unable to allocate memory for cmd tag, " 137 "error %u\n", error); 138 goto fail; 139 } 140 141 /* allocate descriptors */ 142 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf, 143 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 144 &mh->mh_dmamap); 145 if (error != 0) { 146 device_printf(dev, "unable to allocate memory for cmd buffer, " 147 "error %u\n", error); 148 goto fail; 149 } 150 151 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap, 152 mh->mh_cmdbuf, MALO_CMDBUF_SIZE, 153 malo_hal_load_cb, &mh->mh_cmdaddr, 154 BUS_DMA_NOWAIT); 155 if (error != 0) { 156 device_printf(dev, "unable to load cmd buffer, error %u\n", 157 error); 158 goto fail; 159 } 160 161 return (mh); 162 163 fail: 164 if (mh->mh_cmdbuf != NULL) 165 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, 166 mh->mh_dmamap); 167 if (mh->mh_dmat) 168 bus_dma_tag_destroy(mh->mh_dmat); 169 free(mh, M_DEVBUF); 170 171 return (NULL); 172 } 173 174 /* 175 * Low level firmware cmd block handshake support. 176 */ 177 178 static void 179 malo_hal_send_cmd(struct malo_hal *mh) 180 { 181 182 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 183 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 184 185 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 186 malo_hal_read4(mh, MALO_REG_INT_CODE); 187 188 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 189 MALO_H2ARIC_BIT_DOOR_BELL); 190 } 191 192 static int 193 malo_hal_waitforcmd(struct malo_hal *mh, uint16_t cmd) 194 { 195 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000 196 int i; 197 198 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) { 199 if (mh->mh_cmdbuf[0] == le16toh(cmd)) 200 return 1; 201 202 DELAY(1 * 1000); 203 } 204 205 return 0; 206 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS 207 } 208 209 static int 210 malo_hal_execute_cmd(struct malo_hal *mh, unsigned short cmd) 211 { 212 MALO_HAL_LOCK_ASSERT(mh); 213 214 if ((mh->mh_flags & MHF_FWHANG) && 215 (mh->mh_debug & MALO_HAL_DEBUG_IGNHANG) == 0) { 216 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n", 217 cmd); 218 return ENXIO; 219 } 220 221 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 222 device_printf(mh->mh_dev, "%s: device not present!\n", 223 __func__); 224 return EIO; 225 } 226 227 malo_hal_send_cmd(mh); 228 if (!malo_hal_waitforcmd(mh, cmd | 0x8000)) { 229 device_printf(mh->mh_dev, 230 "timeout waiting for f/w cmd 0x%x\n", cmd); 231 mh->mh_flags |= MHF_FWHANG; 232 return ETIMEDOUT; 233 } 234 235 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 236 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 237 238 return 0; 239 } 240 241 static int 242 malo_hal_get_cal_table(struct malo_hal *mh, uint8_t annex, uint8_t index) 243 { 244 struct malo_cmd_caltable *cmd; 245 int ret; 246 247 MALO_HAL_LOCK_ASSERT(mh); 248 249 _CMD_SETUP(cmd, struct malo_cmd_caltable, MALO_HOSTCMD_GET_CALTABLE); 250 cmd->annex = annex; 251 cmd->index = index; 252 253 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_CALTABLE); 254 if (ret == 0 && cmd->caltbl[0] != annex && annex != 0 && annex != 255) 255 ret = EIO; 256 return ret; 257 } 258 259 static int 260 malo_hal_get_pwrcal_table(struct malo_hal *mh, struct malo_hal_caldata *cal) 261 { 262 const uint8_t *data; 263 int len; 264 265 MALO_HAL_LOCK(mh); 266 /* NB: we hold the lock so it's ok to use cmdbuf */ 267 data = ((const struct malo_cmd_caltable *) mh->mh_cmdbuf)->caltbl; 268 if (malo_hal_get_cal_table(mh, 33, 0) == 0) { 269 len = (data[2] | (data[3] << 8)) - 12; 270 /* XXX validate len */ 271 memcpy(cal->pt_ratetable_20m, &data[12], len); 272 } 273 mh->mh_flags |= MHF_CALDATA; 274 MALO_HAL_UNLOCK(mh); 275 276 return 0; 277 } 278 279 /* 280 * Reset internal state after a firmware download. 281 */ 282 static int 283 malo_hal_resetstate(struct malo_hal *mh) 284 { 285 /* 286 * Fetch cal data for later use. 287 * XXX may want to fetch other stuff too. 288 */ 289 if ((mh->mh_flags & MHF_CALDATA) == 0) 290 malo_hal_get_pwrcal_table(mh, &mh->mh_caldata); 291 return 0; 292 } 293 294 static void 295 malo_hal_fw_reset(struct malo_hal *mh) 296 { 297 298 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 299 device_printf(mh->mh_dev, "%s: device not present!\n", 300 __func__); 301 return; 302 } 303 304 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, MALO_ISR_RESET); 305 mh->mh_flags &= ~MHF_FWHANG; 306 } 307 308 static void 309 malo_hal_trigger_pcicmd(struct malo_hal *mh) 310 { 311 312 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE); 313 314 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 315 malo_hal_read4(mh, MALO_REG_INT_CODE); 316 317 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 318 malo_hal_read4(mh, MALO_REG_INT_CODE); 319 320 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 321 MALO_H2ARIC_BIT_DOOR_BELL); 322 malo_hal_read4(mh, MALO_REG_INT_CODE); 323 } 324 325 static int 326 malo_hal_waitfor(struct malo_hal *mh, uint32_t val) 327 { 328 int i; 329 330 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 331 DELAY(MALO_FW_CHECK_USECS); 332 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == val) 333 return 0; 334 } 335 336 return -1; 337 } 338 339 /* 340 * Firmware block xmit when talking to the boot-rom. 341 */ 342 static int 343 malo_hal_send_helper(struct malo_hal *mh, int bsize, 344 const void *data, size_t dsize, int waitfor) 345 { 346 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 347 mh->mh_cmdbuf[1] = htole16(bsize); 348 memcpy(&mh->mh_cmdbuf[4], data , dsize); 349 350 malo_hal_trigger_pcicmd(mh); 351 352 if (waitfor == MALO_NOWAIT) 353 goto pass; 354 355 /* XXX 2000 vs 200 */ 356 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 357 device_printf(mh->mh_dev, 358 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 359 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 360 361 return ETIMEDOUT; 362 } 363 364 pass: 365 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 366 367 return (0); 368 } 369 370 static int 371 malo_hal_fwload_helper(struct malo_hal *mh, char *helper) 372 { 373 const struct firmware *fw; 374 int error; 375 376 fw = firmware_get(helper); 377 if (fw == NULL) { 378 device_printf(mh->mh_dev, "could not read microcode %s!\n", 379 helper); 380 return (EIO); 381 } 382 383 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 384 helper, fw->datasize); 385 386 error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize, 387 MALO_WAITOK); 388 if (error != 0) 389 goto fail; 390 391 /* tell the card we're done and... */ 392 error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT); 393 394 fail: 395 firmware_put(fw, FIRMWARE_UNLOAD); 396 397 return (error); 398 } 399 400 /* 401 * Firmware block xmit when talking to the 1st-stage loader. 402 */ 403 static int 404 malo_hal_send_main(struct malo_hal *mh, const void *data, size_t dsize, 405 uint16_t seqnum, int waitfor) 406 { 407 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 408 mh->mh_cmdbuf[1] = htole16(dsize); 409 mh->mh_cmdbuf[2] = htole16(seqnum); 410 mh->mh_cmdbuf[3] = 0; 411 memcpy(&mh->mh_cmdbuf[4], data, dsize); 412 413 malo_hal_trigger_pcicmd(mh); 414 415 if (waitfor == MALO_NOWAIT) 416 goto pass; 417 418 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 419 device_printf(mh->mh_dev, 420 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 421 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 422 423 return ETIMEDOUT; 424 } 425 426 pass: 427 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 428 429 return 0; 430 } 431 432 static int 433 malo_hal_fwload_main(struct malo_hal *mh, char *firmware) 434 { 435 const struct firmware *fw; 436 const uint8_t *fp; 437 int error; 438 size_t count; 439 uint16_t seqnum; 440 uint32_t blocksize; 441 442 error = 0; 443 444 fw = firmware_get(firmware); 445 if (fw == NULL) { 446 device_printf(mh->mh_dev, "could not read firmware %s!\n", 447 firmware); 448 return (EIO); 449 } 450 451 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 452 firmware, fw->datasize); 453 454 seqnum = 1; 455 for (count = 0; count < fw->datasize; count += blocksize) { 456 blocksize = MIN(256, fw->datasize - count); 457 fp = (const uint8_t *)fw->data + count; 458 459 error = malo_hal_send_main(mh, fp, blocksize, seqnum++, 460 MALO_NOWAIT); 461 if (error != 0) 462 goto fail; 463 DELAY(500); 464 } 465 466 /* 467 * send a command with size 0 to tell that the firmware has been 468 * uploaded 469 */ 470 error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT); 471 DELAY(100); 472 473 fail: 474 firmware_put(fw, FIRMWARE_UNLOAD); 475 476 return (error); 477 } 478 479 int 480 malo_hal_fwload(struct malo_hal *mh, char *helper, char *firmware) 481 { 482 int error, i; 483 uint32_t fwreadysig, opmode; 484 485 /* 486 * NB: now malo(4) supports only STA mode. It will be better if it 487 * supports AP mode. 488 */ 489 fwreadysig = MALO_HOSTCMD_STA_FWRDY_SIGNATURE; 490 opmode = MALO_HOSTCMD_STA_MODE; 491 492 malo_hal_fw_reset(mh); 493 494 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CLEAR_SEL, 495 MALO_A2HRIC_BIT_MASK); 496 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CAUSE, 0x00); 497 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0x00); 498 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 499 MALO_A2HRIC_BIT_MASK); 500 501 error = malo_hal_fwload_helper(mh, helper); 502 if (error != 0) { 503 device_printf(mh->mh_dev, "failed to load bootrom loader.\n"); 504 goto fail; 505 } 506 507 DELAY(200 * MALO_FW_CHECK_USECS); 508 509 error = malo_hal_fwload_main(mh, firmware); 510 if (error != 0) { 511 device_printf(mh->mh_dev, "failed to load firmware.\n"); 512 goto fail; 513 } 514 515 /* 516 * Wait for firmware to startup; we monitor the INT_CODE register 517 * waiting for a signature to written back indicating it's ready to go. 518 */ 519 mh->mh_cmdbuf[1] = 0; 520 521 if (opmode != MALO_HOSTCMD_STA_MODE) 522 malo_hal_trigger_pcicmd(mh); 523 524 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 525 malo_hal_write4(mh, MALO_REG_GEN_PTR, opmode); 526 DELAY(MALO_FW_CHECK_USECS); 527 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == fwreadysig) { 528 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 529 return malo_hal_resetstate(mh); 530 } 531 } 532 533 return ETIMEDOUT; 534 fail: 535 malo_hal_fw_reset(mh); 536 537 return (error); 538 } 539 540 /* 541 * Return "hw specs". Note this must be the first cmd MUST be done after 542 * a firmware download or the f/w will lockup. 543 */ 544 int 545 malo_hal_gethwspecs(struct malo_hal *mh, struct malo_hal_hwspec *hw) 546 { 547 struct malo_cmd_get_hwspec *cmd; 548 int ret; 549 550 MALO_HAL_LOCK(mh); 551 552 _CMD_SETUP(cmd, struct malo_cmd_get_hwspec, MALO_HOSTCMD_GET_HW_SPEC); 553 memset(&cmd->permaddr[0], 0xff, IEEE80211_ADDR_LEN); 554 cmd->ul_fw_awakecookie = htole32((unsigned int)mh->mh_cmdaddr + 2048); 555 556 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_HW_SPEC); 557 if (ret == 0) { 558 IEEE80211_ADDR_COPY(hw->macaddr, cmd->permaddr); 559 hw->wcbbase[0] = le32toh(cmd->wcbbase0) & 0x0000ffff; 560 hw->wcbbase[1] = le32toh(cmd->wcbbase1) & 0x0000ffff; 561 hw->wcbbase[2] = le32toh(cmd->wcbbase2) & 0x0000ffff; 562 hw->wcbbase[3] = le32toh(cmd->wcbbase3) & 0x0000ffff; 563 hw->rxdesc_read = le32toh(cmd->rxpdrd_ptr)& 0x0000ffff; 564 hw->rxdesc_write = le32toh(cmd->rxpdwr_ptr)& 0x0000ffff; 565 hw->regioncode = le16toh(cmd->regioncode) & 0x00ff; 566 hw->fw_releasenum = le32toh(cmd->fw_releasenum); 567 hw->maxnum_wcb = le16toh(cmd->num_wcb); 568 hw->maxnum_mcaddr = le16toh(cmd->num_mcastaddr); 569 hw->num_antenna = le16toh(cmd->num_antenna); 570 hw->hwversion = cmd->version; 571 hw->hostinterface = cmd->hostif; 572 } 573 574 MALO_HAL_UNLOCK(mh); 575 576 return ret; 577 } 578 579 void 580 malo_hal_detach(struct malo_hal *mh) 581 { 582 583 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap); 584 bus_dma_tag_destroy(mh->mh_dmat); 585 mtx_destroy(&mh->mh_mtx); 586 free(mh, M_DEVBUF); 587 } 588 589 /* 590 * Configure antenna use. Takes effect immediately. 591 * 592 * XXX tx antenna setting ignored 593 * XXX rx antenna setting should always be 3 (for now) 594 */ 595 int 596 malo_hal_setantenna(struct malo_hal *mh, enum malo_hal_antenna dirset, int ant) 597 { 598 struct malo_cmd_rf_antenna *cmd; 599 int ret; 600 601 if (!(dirset == MHA_ANTENNATYPE_RX || dirset == MHA_ANTENNATYPE_TX)) 602 return EINVAL; 603 604 MALO_HAL_LOCK(mh); 605 606 _CMD_SETUP(cmd, struct malo_cmd_rf_antenna, 607 MALO_HOSTCMD_802_11_RF_ANTENNA); 608 cmd->action = htole16(dirset); 609 if (ant == 0) { /* default to all/both antennae */ 610 /* XXX never reach now. */ 611 ant = 3; 612 } 613 cmd->mode = htole16(ant); 614 615 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_ANTENNA); 616 617 MALO_HAL_UNLOCK(mh); 618 619 return ret; 620 } 621 622 /* 623 * Configure radio. Takes effect immediately. 624 * 625 * XXX preamble installed after set fixed rate cmd 626 */ 627 int 628 malo_hal_setradio(struct malo_hal *mh, int onoff, 629 enum malo_hal_preamble preamble) 630 { 631 struct malo_cmd_radio_control *cmd; 632 int ret; 633 634 MALO_HAL_LOCK(mh); 635 636 _CMD_SETUP(cmd, struct malo_cmd_radio_control, 637 MALO_HOSTCMD_802_11_RADIO_CONTROL); 638 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 639 if (onoff == 0) 640 cmd->control = 0; 641 else 642 cmd->control = htole16(preamble); 643 cmd->radio_on = htole16(onoff); 644 645 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RADIO_CONTROL); 646 647 MALO_HAL_UNLOCK(mh); 648 649 return ret; 650 } 651 652 /* 653 * Set the interrupt mask. 654 */ 655 void 656 malo_hal_intrset(struct malo_hal *mh, uint32_t mask) 657 { 658 659 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0); 660 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 661 662 mh->mh_imask = mask; 663 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, mask); 664 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 665 } 666 667 int 668 malo_hal_setchannel(struct malo_hal *mh, const struct malo_hal_channel *chan) 669 { 670 struct malo_cmd_fw_set_rf_channel *cmd; 671 int ret; 672 673 MALO_HAL_LOCK(mh); 674 675 _CMD_SETUP(cmd, struct malo_cmd_fw_set_rf_channel, 676 MALO_HOSTCMD_SET_RF_CHANNEL); 677 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 678 cmd->cur_channel = chan->channel; 679 680 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RF_CHANNEL); 681 682 MALO_HAL_UNLOCK(mh); 683 684 return ret; 685 } 686 687 int 688 malo_hal_settxpower(struct malo_hal *mh, const struct malo_hal_channel *c) 689 { 690 struct malo_cmd_rf_tx_power *cmd; 691 const struct malo_hal_caldata *cal = &mh->mh_caldata; 692 uint8_t chan = c->channel; 693 uint16_t pow; 694 int i, idx, ret; 695 696 MALO_HAL_LOCK(mh); 697 698 _CMD_SETUP(cmd, struct malo_cmd_rf_tx_power, 699 MALO_HOSTCMD_802_11_RF_TX_POWER); 700 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET_LIST); 701 for (i = 0; i < 4; i++) { 702 idx = (chan - 1) * 4 + i; 703 pow = cal->pt_ratetable_20m[idx]; 704 cmd->power_levellist[i] = htole16(pow); 705 } 706 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_TX_POWER); 707 708 MALO_HAL_UNLOCK(mh); 709 710 return ret; 711 } 712 713 int 714 malo_hal_setpromisc(struct malo_hal *mh, int enable) 715 { 716 /* XXX need host cmd */ 717 return 0; 718 } 719 720 int 721 malo_hal_setassocid(struct malo_hal *mh, 722 const uint8_t bssid[IEEE80211_ADDR_LEN], uint16_t associd) 723 { 724 struct malo_cmd_fw_set_aid *cmd; 725 int ret; 726 727 MALO_HAL_LOCK(mh); 728 729 _CMD_SETUP(cmd, struct malo_cmd_fw_set_aid, 730 MALO_HOSTCMD_SET_AID); 731 cmd->cmdhdr.seqnum = 1; 732 cmd->associd = htole16(associd); 733 IEEE80211_ADDR_COPY(&cmd->macaddr[0], bssid); 734 735 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_AID); 736 MALO_HAL_UNLOCK(mh); 737 return ret; 738 } 739 740 /* 741 * Kick the firmware to tell it there are new tx descriptors 742 * for processing. The driver says what h/w q has work in 743 * case the f/w ever gets smarter. 744 */ 745 void 746 malo_hal_txstart(struct malo_hal *mh, int qnum) 747 { 748 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 749 MALO_REG_H2A_INTERRUPT_EVENTS, MALO_H2ARIC_BIT_PPA_READY); 750 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MALO_REG_INT_CODE); 751 } 752 753 /* 754 * Return the current ISR setting and clear the cause. 755 */ 756 void 757 malo_hal_getisr(struct malo_hal *mh, uint32_t *status) 758 { 759 uint32_t cause; 760 761 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, 762 MALO_REG_A2H_INTERRUPT_CAUSE); 763 if (cause == 0xffffffff) { /* card removed */ 764 cause = 0; 765 } else if (cause != 0) { 766 /* clear cause bits */ 767 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 768 MALO_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); 769 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, 770 MALO_REG_INT_CODE); 771 cause &= mh->mh_imask; 772 } 773 774 *status = cause; 775 } 776 777 /* 778 * Callback from the driver on a cmd done interrupt. Nothing to do right 779 * now as we spin waiting for cmd completion. 780 */ 781 void 782 malo_hal_cmddone(struct malo_hal *mh) 783 { 784 /* NB : do nothing. */ 785 } 786 787 int 788 malo_hal_prescan(struct malo_hal *mh) 789 { 790 struct malo_cmd_prescan *cmd; 791 int ret; 792 793 MALO_HAL_LOCK(mh); 794 795 _CMD_SETUP(cmd, struct malo_cmd_prescan, MALO_HOSTCMD_SET_PRE_SCAN); 796 cmd->cmdhdr.seqnum = 1; 797 798 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_PRE_SCAN); 799 800 MALO_HAL_UNLOCK(mh); 801 802 return ret; 803 } 804 805 int 806 malo_hal_postscan(struct malo_hal *mh, uint8_t *macaddr, uint8_t ibsson) 807 { 808 struct malo_cmd_postscan *cmd; 809 int ret; 810 811 MALO_HAL_LOCK(mh); 812 813 _CMD_SETUP(cmd, struct malo_cmd_postscan, MALO_HOSTCMD_SET_POST_SCAN); 814 cmd->cmdhdr.seqnum = 1; 815 cmd->isibss = htole32(ibsson); 816 IEEE80211_ADDR_COPY(&cmd->bssid[0], macaddr); 817 818 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_POST_SCAN); 819 820 MALO_HAL_UNLOCK(mh); 821 822 return ret; 823 } 824 825 int 826 malo_hal_set_slot(struct malo_hal *mh, int is_short) 827 { 828 int ret; 829 struct malo_cmd_fw_setslot *cmd; 830 831 MALO_HAL_LOCK(mh); 832 833 _CMD_SETUP(cmd, struct malo_cmd_fw_setslot, MALO_HOSTCMD_SET_SLOT); 834 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 835 cmd->slot = (is_short == 1 ? 1 : 0); 836 837 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_SLOT); 838 839 MALO_HAL_UNLOCK(mh); 840 841 return ret; 842 } 843 844 int 845 malo_hal_set_rate(struct malo_hal *mh, uint16_t curmode, uint8_t rate) 846 { 847 int i, ret; 848 struct malo_cmd_set_rate *cmd; 849 850 MALO_HAL_LOCK(mh); 851 852 _CMD_SETUP(cmd, struct malo_cmd_set_rate, MALO_HOSTCMD_SET_RATE); 853 cmd->aprates[0] = 2; 854 cmd->aprates[1] = 4; 855 cmd->aprates[2] = 11; 856 cmd->aprates[3] = 22; 857 if (curmode == IEEE80211_MODE_11G) { 858 cmd->aprates[4] = 0; /* XXX reserved? */ 859 cmd->aprates[5] = 12; 860 cmd->aprates[6] = 18; 861 cmd->aprates[7] = 24; 862 cmd->aprates[8] = 36; 863 cmd->aprates[9] = 48; 864 cmd->aprates[10] = 72; 865 cmd->aprates[11] = 96; 866 cmd->aprates[12] = 108; 867 } 868 869 if (rate != 0) { 870 /* fixed rate */ 871 for (i = 0; i < 13; i++) { 872 if (cmd->aprates[i] == rate) { 873 cmd->rateindex = i; 874 cmd->dataratetype = 1; 875 break; 876 } 877 } 878 } 879 880 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RATE); 881 882 MALO_HAL_UNLOCK(mh); 883 884 return ret; 885 } 886 887 int 888 malo_hal_setmcast(struct malo_hal *mh, int nmc, const uint8_t macs[]) 889 { 890 struct malo_cmd_mcast *cmd; 891 int ret; 892 893 if (nmc > MALO_HAL_MCAST_MAX) 894 return EINVAL; 895 896 MALO_HAL_LOCK(mh); 897 898 _CMD_SETUP(cmd, struct malo_cmd_mcast, MALO_HOSTCMD_MAC_MULTICAST_ADR); 899 memcpy(cmd->maclist, macs, nmc * IEEE80211_ADDR_LEN); 900 cmd->numaddr = htole16(nmc); 901 cmd->action = htole16(0xffff); 902 903 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_MAC_MULTICAST_ADR); 904 905 MALO_HAL_UNLOCK(mh); 906 907 return ret; 908 } 909