1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007 Marvell Semiconductor, Inc. 5 * Copyright (c) 2007 Sam Leffler, Errno Consulting 6 * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 17 * redistribution must be conditioned upon including a substantially 18 * similar Disclaimer requirement for further binary redistribution. 19 * 20 * NO WARRANTY 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGES. 32 */ 33 34 #include <sys/cdefs.h> 35 #ifdef __FreeBSD__ 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/endian.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/firmware.h> 44 #include <sys/socket.h> 45 46 #include <machine/bus.h> 47 #include <sys/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/ethernet.h> 54 55 #include <net80211/ieee80211_var.h> 56 57 #include <dev/malo/if_malo.h> 58 59 #define MALO_WAITOK 1 60 #define MALO_NOWAIT 0 61 62 #define _CMD_SETUP(pCmd, _type, _cmd) do { \ 63 pCmd = (_type *)&mh->mh_cmdbuf[0]; \ 64 memset(pCmd, 0, sizeof(_type)); \ 65 pCmd->cmdhdr.cmd = htole16(_cmd); \ 66 pCmd->cmdhdr.length = htole16(sizeof(_type)); \ 67 } while (0) 68 69 static __inline uint32_t 70 malo_hal_read4(struct malo_hal *mh, bus_size_t off) 71 { 72 return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off); 73 } 74 75 static __inline void 76 malo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val) 77 { 78 bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val); 79 } 80 81 static void 82 malo_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 83 { 84 bus_addr_t *paddr = (bus_addr_t*) arg; 85 86 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 87 *paddr = segs->ds_addr; 88 } 89 90 /* 91 * Setup for communication with the device. We allocate 92 * a command buffer and map it for bus dma use. The pci 93 * device id is used to identify whether the device has 94 * SRAM on it (in which case f/w download must include a 95 * memory controller reset). All bus i/o operations happen 96 * in BAR 1; the driver passes in the tag and handle we need. 97 */ 98 struct malo_hal * 99 malo_hal_attach(device_t dev, uint16_t devid, 100 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag) 101 { 102 int error; 103 struct malo_hal *mh; 104 105 mh = malloc(sizeof(struct malo_hal), M_DEVBUF, M_NOWAIT | M_ZERO); 106 if (mh == NULL) 107 return NULL; 108 109 mh->mh_dev = dev; 110 mh->mh_ioh = ioh; 111 mh->mh_iot = iot; 112 113 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname), 114 "%s_hal", device_get_nameunit(dev)); 115 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF); 116 117 /* 118 * Allocate the command buffer and map into the address 119 * space of the h/w. We request "coherent" memory which 120 * will be uncached on some architectures. 121 */ 122 error = bus_dma_tag_create(tag, /* parent */ 123 PAGE_SIZE, 0, /* alignment, bounds */ 124 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 125 BUS_SPACE_MAXADDR, /* highaddr */ 126 NULL, NULL, /* filter, filterarg */ 127 MALO_CMDBUF_SIZE, /* maxsize */ 128 1, /* nsegments */ 129 MALO_CMDBUF_SIZE, /* maxsegsize */ 130 BUS_DMA_ALLOCNOW, /* flags */ 131 NULL, /* lockfunc */ 132 NULL, /* lockarg */ 133 &mh->mh_dmat); 134 if (error != 0) { 135 device_printf(dev, "unable to allocate memory for cmd tag, " 136 "error %u\n", error); 137 goto fail; 138 } 139 140 /* allocate descriptors */ 141 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf, 142 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 143 &mh->mh_dmamap); 144 if (error != 0) { 145 device_printf(dev, "unable to allocate memory for cmd buffer, " 146 "error %u\n", error); 147 goto fail; 148 } 149 150 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap, 151 mh->mh_cmdbuf, MALO_CMDBUF_SIZE, 152 malo_hal_load_cb, &mh->mh_cmdaddr, 153 BUS_DMA_NOWAIT); 154 if (error != 0) { 155 device_printf(dev, "unable to load cmd buffer, error %u\n", 156 error); 157 goto fail; 158 } 159 160 return (mh); 161 162 fail: 163 if (mh->mh_cmdbuf != NULL) 164 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, 165 mh->mh_dmamap); 166 if (mh->mh_dmat) 167 bus_dma_tag_destroy(mh->mh_dmat); 168 free(mh, M_DEVBUF); 169 170 return (NULL); 171 } 172 173 /* 174 * Low level firmware cmd block handshake support. 175 */ 176 177 static void 178 malo_hal_send_cmd(struct malo_hal *mh) 179 { 180 181 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 182 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 183 184 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 185 malo_hal_read4(mh, MALO_REG_INT_CODE); 186 187 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 188 MALO_H2ARIC_BIT_DOOR_BELL); 189 } 190 191 static int 192 malo_hal_waitforcmd(struct malo_hal *mh, uint16_t cmd) 193 { 194 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000 195 int i; 196 197 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) { 198 if (mh->mh_cmdbuf[0] == le16toh(cmd)) 199 return 1; 200 201 DELAY(1 * 1000); 202 } 203 204 return 0; 205 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS 206 } 207 208 static int 209 malo_hal_execute_cmd(struct malo_hal *mh, unsigned short cmd) 210 { 211 MALO_HAL_LOCK_ASSERT(mh); 212 213 if ((mh->mh_flags & MHF_FWHANG) && 214 (mh->mh_debug & MALO_HAL_DEBUG_IGNHANG) == 0) { 215 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n", 216 cmd); 217 return ENXIO; 218 } 219 220 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 221 device_printf(mh->mh_dev, "%s: device not present!\n", 222 __func__); 223 return EIO; 224 } 225 226 malo_hal_send_cmd(mh); 227 if (!malo_hal_waitforcmd(mh, cmd | 0x8000)) { 228 device_printf(mh->mh_dev, 229 "timeout waiting for f/w cmd 0x%x\n", cmd); 230 mh->mh_flags |= MHF_FWHANG; 231 return ETIMEDOUT; 232 } 233 234 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 235 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 236 237 return 0; 238 } 239 240 static int 241 malo_hal_get_cal_table(struct malo_hal *mh, uint8_t annex, uint8_t index) 242 { 243 struct malo_cmd_caltable *cmd; 244 int ret; 245 246 MALO_HAL_LOCK_ASSERT(mh); 247 248 _CMD_SETUP(cmd, struct malo_cmd_caltable, MALO_HOSTCMD_GET_CALTABLE); 249 cmd->annex = annex; 250 cmd->index = index; 251 252 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_CALTABLE); 253 if (ret == 0 && cmd->caltbl[0] != annex && annex != 0 && annex != 255) 254 ret = EIO; 255 return ret; 256 } 257 258 static int 259 malo_hal_get_pwrcal_table(struct malo_hal *mh, struct malo_hal_caldata *cal) 260 { 261 const uint8_t *data; 262 int len; 263 264 MALO_HAL_LOCK(mh); 265 /* NB: we hold the lock so it's ok to use cmdbuf */ 266 data = ((const struct malo_cmd_caltable *) mh->mh_cmdbuf)->caltbl; 267 if (malo_hal_get_cal_table(mh, 33, 0) == 0) { 268 len = (data[2] | (data[3] << 8)) - 12; 269 /* XXX validate len */ 270 memcpy(cal->pt_ratetable_20m, &data[12], len); 271 } 272 mh->mh_flags |= MHF_CALDATA; 273 MALO_HAL_UNLOCK(mh); 274 275 return 0; 276 } 277 278 /* 279 * Reset internal state after a firmware download. 280 */ 281 static int 282 malo_hal_resetstate(struct malo_hal *mh) 283 { 284 /* 285 * Fetch cal data for later use. 286 * XXX may want to fetch other stuff too. 287 */ 288 if ((mh->mh_flags & MHF_CALDATA) == 0) 289 malo_hal_get_pwrcal_table(mh, &mh->mh_caldata); 290 return 0; 291 } 292 293 static void 294 malo_hal_fw_reset(struct malo_hal *mh) 295 { 296 297 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 298 device_printf(mh->mh_dev, "%s: device not present!\n", 299 __func__); 300 return; 301 } 302 303 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, MALO_ISR_RESET); 304 mh->mh_flags &= ~MHF_FWHANG; 305 } 306 307 static void 308 malo_hal_trigger_pcicmd(struct malo_hal *mh) 309 { 310 311 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE); 312 313 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 314 malo_hal_read4(mh, MALO_REG_INT_CODE); 315 316 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 317 malo_hal_read4(mh, MALO_REG_INT_CODE); 318 319 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 320 MALO_H2ARIC_BIT_DOOR_BELL); 321 malo_hal_read4(mh, MALO_REG_INT_CODE); 322 } 323 324 static int 325 malo_hal_waitfor(struct malo_hal *mh, uint32_t val) 326 { 327 int i; 328 329 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 330 DELAY(MALO_FW_CHECK_USECS); 331 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == val) 332 return 0; 333 } 334 335 return -1; 336 } 337 338 /* 339 * Firmware block xmit when talking to the boot-rom. 340 */ 341 static int 342 malo_hal_send_helper(struct malo_hal *mh, int bsize, 343 const void *data, size_t dsize, int waitfor) 344 { 345 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 346 mh->mh_cmdbuf[1] = htole16(bsize); 347 memcpy(&mh->mh_cmdbuf[4], data , dsize); 348 349 malo_hal_trigger_pcicmd(mh); 350 351 if (waitfor == MALO_NOWAIT) 352 goto pass; 353 354 /* XXX 2000 vs 200 */ 355 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 356 device_printf(mh->mh_dev, 357 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 358 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 359 360 return ETIMEDOUT; 361 } 362 363 pass: 364 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 365 366 return (0); 367 } 368 369 static int 370 malo_hal_fwload_helper(struct malo_hal *mh, char *helper) 371 { 372 const struct firmware *fw; 373 int error; 374 375 fw = firmware_get(helper); 376 if (fw == NULL) { 377 device_printf(mh->mh_dev, "could not read microcode %s!\n", 378 helper); 379 return (EIO); 380 } 381 382 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 383 helper, fw->datasize); 384 385 error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize, 386 MALO_WAITOK); 387 if (error != 0) 388 goto fail; 389 390 /* tell the card we're done and... */ 391 error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT); 392 393 fail: 394 firmware_put(fw, FIRMWARE_UNLOAD); 395 396 return (error); 397 } 398 399 /* 400 * Firmware block xmit when talking to the 1st-stage loader. 401 */ 402 static int 403 malo_hal_send_main(struct malo_hal *mh, const void *data, size_t dsize, 404 uint16_t seqnum, int waitfor) 405 { 406 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 407 mh->mh_cmdbuf[1] = htole16(dsize); 408 mh->mh_cmdbuf[2] = htole16(seqnum); 409 mh->mh_cmdbuf[3] = 0; 410 memcpy(&mh->mh_cmdbuf[4], data, dsize); 411 412 malo_hal_trigger_pcicmd(mh); 413 414 if (waitfor == MALO_NOWAIT) 415 goto pass; 416 417 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 418 device_printf(mh->mh_dev, 419 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 420 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 421 422 return ETIMEDOUT; 423 } 424 425 pass: 426 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 427 428 return 0; 429 } 430 431 static int 432 malo_hal_fwload_main(struct malo_hal *mh, char *firmware) 433 { 434 const struct firmware *fw; 435 const uint8_t *fp; 436 int error; 437 size_t count; 438 uint16_t seqnum; 439 uint32_t blocksize; 440 441 error = 0; 442 443 fw = firmware_get(firmware); 444 if (fw == NULL) { 445 device_printf(mh->mh_dev, "could not read firmware %s!\n", 446 firmware); 447 return (EIO); 448 } 449 450 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 451 firmware, fw->datasize); 452 453 seqnum = 1; 454 for (count = 0; count < fw->datasize; count += blocksize) { 455 blocksize = MIN(256, fw->datasize - count); 456 fp = (const uint8_t *)fw->data + count; 457 458 error = malo_hal_send_main(mh, fp, blocksize, seqnum++, 459 MALO_NOWAIT); 460 if (error != 0) 461 goto fail; 462 DELAY(500); 463 } 464 465 /* 466 * send a command with size 0 to tell that the firmware has been 467 * uploaded 468 */ 469 error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT); 470 DELAY(100); 471 472 fail: 473 firmware_put(fw, FIRMWARE_UNLOAD); 474 475 return (error); 476 } 477 478 int 479 malo_hal_fwload(struct malo_hal *mh, char *helper, char *firmware) 480 { 481 int error, i; 482 uint32_t fwreadysig, opmode; 483 484 /* 485 * NB: now malo(4) supports only STA mode. It will be better if it 486 * supports AP mode. 487 */ 488 fwreadysig = MALO_HOSTCMD_STA_FWRDY_SIGNATURE; 489 opmode = MALO_HOSTCMD_STA_MODE; 490 491 malo_hal_fw_reset(mh); 492 493 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CLEAR_SEL, 494 MALO_A2HRIC_BIT_MASK); 495 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CAUSE, 0x00); 496 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0x00); 497 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 498 MALO_A2HRIC_BIT_MASK); 499 500 error = malo_hal_fwload_helper(mh, helper); 501 if (error != 0) { 502 device_printf(mh->mh_dev, "failed to load bootrom loader.\n"); 503 goto fail; 504 } 505 506 DELAY(200 * MALO_FW_CHECK_USECS); 507 508 error = malo_hal_fwload_main(mh, firmware); 509 if (error != 0) { 510 device_printf(mh->mh_dev, "failed to load firmware.\n"); 511 goto fail; 512 } 513 514 /* 515 * Wait for firmware to startup; we monitor the INT_CODE register 516 * waiting for a signature to written back indicating it's ready to go. 517 */ 518 mh->mh_cmdbuf[1] = 0; 519 520 if (opmode != MALO_HOSTCMD_STA_MODE) 521 malo_hal_trigger_pcicmd(mh); 522 523 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 524 malo_hal_write4(mh, MALO_REG_GEN_PTR, opmode); 525 DELAY(MALO_FW_CHECK_USECS); 526 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == fwreadysig) { 527 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 528 return malo_hal_resetstate(mh); 529 } 530 } 531 532 return ETIMEDOUT; 533 fail: 534 malo_hal_fw_reset(mh); 535 536 return (error); 537 } 538 539 /* 540 * Return "hw specs". Note this must be the first cmd MUST be done after 541 * a firmware download or the f/w will lockup. 542 */ 543 int 544 malo_hal_gethwspecs(struct malo_hal *mh, struct malo_hal_hwspec *hw) 545 { 546 struct malo_cmd_get_hwspec *cmd; 547 int ret; 548 549 MALO_HAL_LOCK(mh); 550 551 _CMD_SETUP(cmd, struct malo_cmd_get_hwspec, MALO_HOSTCMD_GET_HW_SPEC); 552 memset(&cmd->permaddr[0], 0xff, IEEE80211_ADDR_LEN); 553 cmd->ul_fw_awakecookie = htole32((unsigned int)mh->mh_cmdaddr + 2048); 554 555 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_HW_SPEC); 556 if (ret == 0) { 557 IEEE80211_ADDR_COPY(hw->macaddr, cmd->permaddr); 558 hw->wcbbase[0] = le32toh(cmd->wcbbase0) & 0x0000ffff; 559 hw->wcbbase[1] = le32toh(cmd->wcbbase1) & 0x0000ffff; 560 hw->wcbbase[2] = le32toh(cmd->wcbbase2) & 0x0000ffff; 561 hw->wcbbase[3] = le32toh(cmd->wcbbase3) & 0x0000ffff; 562 hw->rxdesc_read = le32toh(cmd->rxpdrd_ptr)& 0x0000ffff; 563 hw->rxdesc_write = le32toh(cmd->rxpdwr_ptr)& 0x0000ffff; 564 hw->regioncode = le16toh(cmd->regioncode) & 0x00ff; 565 hw->fw_releasenum = le32toh(cmd->fw_releasenum); 566 hw->maxnum_wcb = le16toh(cmd->num_wcb); 567 hw->maxnum_mcaddr = le16toh(cmd->num_mcastaddr); 568 hw->num_antenna = le16toh(cmd->num_antenna); 569 hw->hwversion = cmd->version; 570 hw->hostinterface = cmd->hostif; 571 } 572 573 MALO_HAL_UNLOCK(mh); 574 575 return ret; 576 } 577 578 void 579 malo_hal_detach(struct malo_hal *mh) 580 { 581 582 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap); 583 bus_dma_tag_destroy(mh->mh_dmat); 584 mtx_destroy(&mh->mh_mtx); 585 free(mh, M_DEVBUF); 586 } 587 588 /* 589 * Configure antenna use. Takes effect immediately. 590 * 591 * XXX tx antenna setting ignored 592 * XXX rx antenna setting should always be 3 (for now) 593 */ 594 int 595 malo_hal_setantenna(struct malo_hal *mh, enum malo_hal_antenna dirset, int ant) 596 { 597 struct malo_cmd_rf_antenna *cmd; 598 int ret; 599 600 if (!(dirset == MHA_ANTENNATYPE_RX || dirset == MHA_ANTENNATYPE_TX)) 601 return EINVAL; 602 603 MALO_HAL_LOCK(mh); 604 605 _CMD_SETUP(cmd, struct malo_cmd_rf_antenna, 606 MALO_HOSTCMD_802_11_RF_ANTENNA); 607 cmd->action = htole16(dirset); 608 if (ant == 0) { /* default to all/both antennae */ 609 /* XXX never reach now. */ 610 ant = 3; 611 } 612 cmd->mode = htole16(ant); 613 614 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_ANTENNA); 615 616 MALO_HAL_UNLOCK(mh); 617 618 return ret; 619 } 620 621 /* 622 * Configure radio. Takes effect immediately. 623 * 624 * XXX preamble installed after set fixed rate cmd 625 */ 626 int 627 malo_hal_setradio(struct malo_hal *mh, int onoff, 628 enum malo_hal_preamble preamble) 629 { 630 struct malo_cmd_radio_control *cmd; 631 int ret; 632 633 MALO_HAL_LOCK(mh); 634 635 _CMD_SETUP(cmd, struct malo_cmd_radio_control, 636 MALO_HOSTCMD_802_11_RADIO_CONTROL); 637 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 638 if (onoff == 0) 639 cmd->control = 0; 640 else 641 cmd->control = htole16(preamble); 642 cmd->radio_on = htole16(onoff); 643 644 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RADIO_CONTROL); 645 646 MALO_HAL_UNLOCK(mh); 647 648 return ret; 649 } 650 651 /* 652 * Set the interrupt mask. 653 */ 654 void 655 malo_hal_intrset(struct malo_hal *mh, uint32_t mask) 656 { 657 658 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0); 659 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 660 661 mh->mh_imask = mask; 662 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, mask); 663 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 664 } 665 666 int 667 malo_hal_setchannel(struct malo_hal *mh, const struct malo_hal_channel *chan) 668 { 669 struct malo_cmd_fw_set_rf_channel *cmd; 670 int ret; 671 672 MALO_HAL_LOCK(mh); 673 674 _CMD_SETUP(cmd, struct malo_cmd_fw_set_rf_channel, 675 MALO_HOSTCMD_SET_RF_CHANNEL); 676 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 677 cmd->cur_channel = chan->channel; 678 679 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RF_CHANNEL); 680 681 MALO_HAL_UNLOCK(mh); 682 683 return ret; 684 } 685 686 int 687 malo_hal_settxpower(struct malo_hal *mh, const struct malo_hal_channel *c) 688 { 689 struct malo_cmd_rf_tx_power *cmd; 690 const struct malo_hal_caldata *cal = &mh->mh_caldata; 691 uint8_t chan = c->channel; 692 uint16_t pow; 693 int i, idx, ret; 694 695 MALO_HAL_LOCK(mh); 696 697 _CMD_SETUP(cmd, struct malo_cmd_rf_tx_power, 698 MALO_HOSTCMD_802_11_RF_TX_POWER); 699 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET_LIST); 700 for (i = 0; i < 4; i++) { 701 idx = (chan - 1) * 4 + i; 702 pow = cal->pt_ratetable_20m[idx]; 703 cmd->power_levellist[i] = htole16(pow); 704 } 705 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_TX_POWER); 706 707 MALO_HAL_UNLOCK(mh); 708 709 return ret; 710 } 711 712 int 713 malo_hal_setpromisc(struct malo_hal *mh, int enable) 714 { 715 /* XXX need host cmd */ 716 return 0; 717 } 718 719 int 720 malo_hal_setassocid(struct malo_hal *mh, 721 const uint8_t bssid[IEEE80211_ADDR_LEN], uint16_t associd) 722 { 723 struct malo_cmd_fw_set_aid *cmd; 724 int ret; 725 726 MALO_HAL_LOCK(mh); 727 728 _CMD_SETUP(cmd, struct malo_cmd_fw_set_aid, 729 MALO_HOSTCMD_SET_AID); 730 cmd->cmdhdr.seqnum = 1; 731 cmd->associd = htole16(associd); 732 IEEE80211_ADDR_COPY(&cmd->macaddr[0], bssid); 733 734 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_AID); 735 MALO_HAL_UNLOCK(mh); 736 return ret; 737 } 738 739 /* 740 * Kick the firmware to tell it there are new tx descriptors 741 * for processing. The driver says what h/w q has work in 742 * case the f/w ever gets smarter. 743 */ 744 void 745 malo_hal_txstart(struct malo_hal *mh, int qnum) 746 { 747 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 748 MALO_REG_H2A_INTERRUPT_EVENTS, MALO_H2ARIC_BIT_PPA_READY); 749 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MALO_REG_INT_CODE); 750 } 751 752 /* 753 * Return the current ISR setting and clear the cause. 754 */ 755 void 756 malo_hal_getisr(struct malo_hal *mh, uint32_t *status) 757 { 758 uint32_t cause; 759 760 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, 761 MALO_REG_A2H_INTERRUPT_CAUSE); 762 if (cause == 0xffffffff) { /* card removed */ 763 cause = 0; 764 } else if (cause != 0) { 765 /* clear cause bits */ 766 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 767 MALO_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); 768 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, 769 MALO_REG_INT_CODE); 770 cause &= mh->mh_imask; 771 } 772 773 *status = cause; 774 } 775 776 /* 777 * Callback from the driver on a cmd done interrupt. Nothing to do right 778 * now as we spin waiting for cmd completion. 779 */ 780 void 781 malo_hal_cmddone(struct malo_hal *mh) 782 { 783 /* NB : do nothing. */ 784 } 785 786 int 787 malo_hal_prescan(struct malo_hal *mh) 788 { 789 struct malo_cmd_prescan *cmd; 790 int ret; 791 792 MALO_HAL_LOCK(mh); 793 794 _CMD_SETUP(cmd, struct malo_cmd_prescan, MALO_HOSTCMD_SET_PRE_SCAN); 795 cmd->cmdhdr.seqnum = 1; 796 797 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_PRE_SCAN); 798 799 MALO_HAL_UNLOCK(mh); 800 801 return ret; 802 } 803 804 int 805 malo_hal_postscan(struct malo_hal *mh, uint8_t *macaddr, uint8_t ibsson) 806 { 807 struct malo_cmd_postscan *cmd; 808 int ret; 809 810 MALO_HAL_LOCK(mh); 811 812 _CMD_SETUP(cmd, struct malo_cmd_postscan, MALO_HOSTCMD_SET_POST_SCAN); 813 cmd->cmdhdr.seqnum = 1; 814 cmd->isibss = htole32(ibsson); 815 IEEE80211_ADDR_COPY(&cmd->bssid[0], macaddr); 816 817 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_POST_SCAN); 818 819 MALO_HAL_UNLOCK(mh); 820 821 return ret; 822 } 823 824 int 825 malo_hal_set_slot(struct malo_hal *mh, int is_short) 826 { 827 int ret; 828 struct malo_cmd_fw_setslot *cmd; 829 830 MALO_HAL_LOCK(mh); 831 832 _CMD_SETUP(cmd, struct malo_cmd_fw_setslot, MALO_HOSTCMD_SET_SLOT); 833 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 834 cmd->slot = (is_short == 1 ? 1 : 0); 835 836 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_SLOT); 837 838 MALO_HAL_UNLOCK(mh); 839 840 return ret; 841 } 842 843 int 844 malo_hal_set_rate(struct malo_hal *mh, uint16_t curmode, uint8_t rate) 845 { 846 int i, ret; 847 struct malo_cmd_set_rate *cmd; 848 849 MALO_HAL_LOCK(mh); 850 851 _CMD_SETUP(cmd, struct malo_cmd_set_rate, MALO_HOSTCMD_SET_RATE); 852 cmd->aprates[0] = 2; 853 cmd->aprates[1] = 4; 854 cmd->aprates[2] = 11; 855 cmd->aprates[3] = 22; 856 if (curmode == IEEE80211_MODE_11G) { 857 cmd->aprates[4] = 0; /* XXX reserved? */ 858 cmd->aprates[5] = 12; 859 cmd->aprates[6] = 18; 860 cmd->aprates[7] = 24; 861 cmd->aprates[8] = 36; 862 cmd->aprates[9] = 48; 863 cmd->aprates[10] = 72; 864 cmd->aprates[11] = 96; 865 cmd->aprates[12] = 108; 866 } 867 868 if (rate != 0) { 869 /* fixed rate */ 870 for (i = 0; i < 13; i++) { 871 if (cmd->aprates[i] == rate) { 872 cmd->rateindex = i; 873 cmd->dataratetype = 1; 874 break; 875 } 876 } 877 } 878 879 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RATE); 880 881 MALO_HAL_UNLOCK(mh); 882 883 return ret; 884 } 885 886 int 887 malo_hal_setmcast(struct malo_hal *mh, int nmc, const uint8_t macs[]) 888 { 889 struct malo_cmd_mcast *cmd; 890 int ret; 891 892 if (nmc > MALO_HAL_MCAST_MAX) 893 return EINVAL; 894 895 MALO_HAL_LOCK(mh); 896 897 _CMD_SETUP(cmd, struct malo_cmd_mcast, MALO_HOSTCMD_MAC_MULTICAST_ADR); 898 memcpy(cmd->maclist, macs, nmc * IEEE80211_ADDR_LEN); 899 cmd->numaddr = htole16(nmc); 900 cmd->action = htole16(0xffff); 901 902 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_MAC_MULTICAST_ADR); 903 904 MALO_HAL_UNLOCK(mh); 905 906 return ret; 907 } 908