1 /* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Cavium, Inc. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* \file lio_common.h 35 * \brief Common: Structures and macros used in PCI-NIC package by core and 36 * host driver. 37 */ 38 39 #ifndef __LIO_COMMON_H__ 40 #define __LIO_COMMON_H__ 41 42 #include "lio_config.h" 43 44 #define LIO_STR_HELPER(x) #x 45 #define LIO_STR(x) LIO_STR_HELPER(x) 46 #define LIO_BASE_MAJOR_VERSION 1 47 #define LIO_BASE_MINOR_VERSION 6 48 #define LIO_BASE_MICRO_VERSION 1 49 #define LIO_BASE_VERSION LIO_STR(LIO_BASE_MAJOR_VERSION) "." \ 50 LIO_STR(LIO_BASE_MINOR_VERSION) 51 #define LIO_VERSION LIO_STR(LIO_BASE_MAJOR_VERSION) "." \ 52 LIO_STR(LIO_BASE_MINOR_VERSION) \ 53 "." LIO_STR(LIO_BASE_MICRO_VERSION) 54 55 struct lio_version { 56 uint16_t major; 57 uint16_t minor; 58 uint16_t micro; 59 uint16_t reserved; 60 }; 61 62 /* Tag types used by Octeon cores in its work. */ 63 enum lio_tag_type { 64 LIO_ORDERED_TAG = 0, 65 LIO_ATOMIC_TAG = 1, 66 LIO_NULL_TAG = 2, 67 LIO_NULL_NULL_TAG = 3 68 }; 69 70 /* pre-defined host->NIC tag values */ 71 #define LIO_CONTROL (0x11111110) 72 #define LIO_DATA(i) (0x11111111 + (i)) 73 74 /* 75 * Opcodes used by host driver/apps to perform operations on the core. 76 * These are used to identify the major subsystem that the operation 77 * is for. 78 */ 79 #define LIO_OPCODE_NIC 1 /* used for NIC operations */ 80 81 /* 82 * Subcodes are used by host driver/apps to identify the sub-operation 83 * for the core. They only need to by unique for a given subsystem. 84 */ 85 #define LIO_OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 86 87 /* OPCODE_CORE subcodes. For future use. */ 88 89 /* OPCODE_NIC subcodes */ 90 91 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 92 #define LIO_OPCODE_NIC_CORE_DRV_ACTIVE 0x01 93 #define LIO_OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 94 #define LIO_OPCODE_NIC_CMD 0x03 95 #define LIO_OPCODE_NIC_INFO 0x04 96 #define LIO_OPCODE_NIC_PORT_STATS 0x05 97 #define LIO_OPCODE_NIC_INTRMOD_CFG 0x08 98 #define LIO_OPCODE_NIC_IF_CFG 0x09 99 #define LIO_OPCODE_NIC_INTRMOD_PARAMS 0x0B 100 101 /* Application codes advertised by the core driver initialization packet. */ 102 #define LIO_DRV_APP_START 0x0 103 #define LIO_DRV_APP_COUNT 0x2 104 #define LIO_DRV_NIC_APP (LIO_DRV_APP_START + 0x1) 105 #define LIO_DRV_INVALID_APP (LIO_DRV_APP_START + 0x2) 106 #define LIO_DRV_APP_END (LIO_DRV_INVALID_APP - 1) 107 108 #define BYTES_PER_DHLEN_UNIT 8 109 110 #define SCR2_BIT_FW_LOADED 63 111 #define SCR2_BIT_FW_RELOADED 62 112 113 static inline uint32_t 114 lio_incr_index(uint32_t index, uint32_t count, uint32_t max) 115 { 116 if ((index + count) >= max) 117 index = index + count - max; 118 else 119 index += count; 120 121 return (index); 122 } 123 124 #define LIO_BOARD_NAME 32 125 #define LIO_SERIAL_NUM_LEN 64 126 127 /* 128 * Structure used by core driver to send indication that the Octeon 129 * application is ready. 130 */ 131 struct lio_core_setup { 132 uint64_t corefreq; 133 134 char boardname[LIO_BOARD_NAME]; 135 136 char board_serial_number[LIO_SERIAL_NUM_LEN]; 137 138 uint64_t board_rev_major; 139 140 uint64_t board_rev_minor; 141 142 }; 143 144 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 145 146 /* 147 * The Scatter-Gather List Entry. The scatter or gather component used with 148 * a Octeon input instruction has this format. 149 */ 150 struct lio_sg_entry { 151 /* The first 64 bit gives the size of data in each dptr. */ 152 union { 153 uint16_t size[4]; 154 uint64_t size64; 155 } u; 156 157 /* The 4 dptr pointers for this entry. */ 158 uint64_t ptr[4]; 159 160 }; 161 162 #define LIO_SG_ENTRY_SIZE (sizeof(struct lio_sg_entry)) 163 164 /* 165 * \brief Add size to gather list 166 * @param sg_entry scatter/gather entry 167 * @param size size to add 168 * @param pos position to add it. 169 */ 170 static inline void 171 lio_add_sg_size(struct lio_sg_entry *sg_entry, uint16_t size, uint32_t pos) 172 { 173 174 #if BYTE_ORDER == BIG_ENDIAN 175 sg_entry->u.size[pos] = size; 176 #else /* BYTE_ORDER != BIG_ENDIAN */ 177 sg_entry->u.size[3 - pos] = size; 178 #endif /* BYTE_ORDER == BIG_ENDIAN */ 179 } 180 181 /*------------------------- End Scatter/Gather ---------------------------*/ 182 183 #define LIO_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 184 185 #define LIO_MAX_FRM_SIZE (16000 + LIO_FRM_HEADER_SIZE) 186 187 #define LIO_DEFAULT_FRM_SIZE (1500 + LIO_FRM_HEADER_SIZE) 188 189 /* NIC Command types */ 190 #define LIO_CMD_CHANGE_MTU 0x1 191 #define LIO_CMD_CHANGE_MACADDR 0x2 192 #define LIO_CMD_CHANGE_DEVFLAGS 0x3 193 #define LIO_CMD_RX_CTL 0x4 194 #define LIO_CMD_SET_MULTI_LIST 0x5 195 196 /* command for setting the speed, duplex & autoneg */ 197 #define LIO_CMD_SET_SETTINGS 0x7 198 #define LIO_CMD_SET_FLOW_CTL 0x8 199 200 #define LIO_CMD_GPIO_ACCESS 0xA 201 #define LIO_CMD_LRO_ENABLE 0xB 202 #define LIO_CMD_LRO_DISABLE 0xC 203 #define LIO_CMD_SET_RSS 0xD 204 205 #define LIO_CMD_TNL_RX_CSUM_CTL 0x10 206 #define LIO_CMD_TNL_TX_CSUM_CTL 0x11 207 #define LIO_CMD_VERBOSE_ENABLE 0x14 208 #define LIO_CMD_VERBOSE_DISABLE 0x15 209 210 #define LIO_CMD_VLAN_FILTER_CTL 0x16 211 #define LIO_CMD_ADD_VLAN_FILTER 0x17 212 #define LIO_CMD_DEL_VLAN_FILTER 0x18 213 #define LIO_CMD_VXLAN_PORT_CONFIG 0x19 214 215 #define LIO_CMD_ID_ACTIVE 0x1a 216 217 #define LIO_CMD_SET_FNV 0x1d 218 219 #define LIO_CMD_PKT_STEERING_CTL 0x1e 220 221 #define LIO_CMD_QUEUE_COUNT_CTL 0x1f 222 223 #define LIO_CMD_VXLAN_PORT_ADD 0x0 224 #define LIO_CMD_VXLAN_PORT_DEL 0x1 225 #define LIO_CMD_RXCSUM_ENABLE 0x0 226 #define LIO_CMD_RXCSUM_DISABLE 0x1 227 #define LIO_CMD_TXCSUM_ENABLE 0x0 228 #define LIO_CMD_TXCSUM_DISABLE 0x1 229 #define LIO_CMD_FNV_ENABLE 0x1 230 #define LIO_CMD_FNV_DISABLE 0x0 231 #define LIO_CMD_PKT_STEERING_ENABLE 0x0 232 #define LIO_CMD_PKT_STEERING_DISABLE 0x1 233 234 /* RX(packets coming from wire) Checksum verification flags */ 235 /* TCP/UDP csum */ 236 #define LIO_L4SUM_VERIFIED 0x1 237 #define LIO_IPSUM_VERIFIED 0x2 238 239 /*LROIPV4 and LROIPV6 Flags*/ 240 #define LIO_LROIPV4 0x1 241 #define LIO_LROIPV6 0x2 242 243 /* Interface flags communicated between host driver and core app. */ 244 enum lio_ifflags { 245 LIO_IFFLAG_PROMISC = 0x01, 246 LIO_IFFLAG_ALLMULTI = 0x02, 247 LIO_IFFLAG_MULTICAST = 0x04, 248 LIO_IFFLAG_BROADCAST = 0x08, 249 LIO_IFFLAG_UNICAST = 0x10 250 }; 251 252 /* 253 * wqe 254 * --------------- 0 255 * | wqe word0-3 | 256 * --------------- 32 257 * | PCI IH | 258 * --------------- 40 259 * | RPTR | 260 * --------------- 48 261 * | PCI IRH | 262 * --------------- 56 263 * | OCT_NET_CMD | 264 * --------------- 64 265 * | Addtl 8-BData | 266 * | | 267 * --------------- 268 */ 269 union octeon_cmd { 270 uint64_t cmd64; 271 272 struct { 273 #if BYTE_ORDER == BIG_ENDIAN 274 uint64_t cmd:5; 275 276 uint64_t more:6; /* How many udd words follow the command */ 277 278 uint64_t reserved:29; 279 280 uint64_t param1:16; 281 282 uint64_t param2:8; 283 284 #else /* BYTE_ORDER != BIG_ENDIAN */ 285 286 uint64_t param2:8; 287 288 uint64_t param1:16; 289 290 uint64_t reserved:29; 291 292 uint64_t more:6; 293 294 uint64_t cmd:5; 295 296 #endif /* BYTE_ORDER == BIG_ENDIAN */ 297 } s; 298 299 }; 300 301 #define OCTEON_CMD_SIZE (sizeof(union octeon_cmd)) 302 303 /* pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 304 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 305 306 #define LIO_PCICMD_O3 (24 + 8) 307 308 /* Instruction Header(DPI) - for OCTEON-III models */ 309 struct octeon_instr_ih3 { 310 #if BYTE_ORDER == BIG_ENDIAN 311 312 /* Reserved3 */ 313 uint64_t reserved3:1; 314 315 /* Gather indicator 1=gather */ 316 uint64_t gather:1; 317 318 /* Data length OR no. of entries in gather list */ 319 uint64_t dlengsz:14; 320 321 /* Front Data size */ 322 uint64_t fsz:6; 323 324 /* Reserved2 */ 325 uint64_t reserved2:4; 326 327 /* PKI port kind - PKIND */ 328 uint64_t pkind:6; 329 330 /* Reserved1 */ 331 uint64_t reserved1:32; 332 333 #else /* BYTE_ORDER != BIG_ENDIAN */ 334 335 /* Reserved1 */ 336 uint64_t reserved1:32; 337 338 /* PKI port kind - PKIND */ 339 uint64_t pkind:6; 340 341 /* Reserved2 */ 342 uint64_t reserved2:4; 343 344 /* Front Data size */ 345 uint64_t fsz:6; 346 347 /* Data length OR no. of entries in gather list */ 348 uint64_t dlengsz:14; 349 350 /* Gather indicator 1=gather */ 351 uint64_t gather:1; 352 353 /* Reserved3 */ 354 uint64_t reserved3:1; 355 356 #endif /* BYTE_ORDER == BIG_ENDIAN */ 357 }; 358 359 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 360 /* BIG ENDIAN format. */ 361 struct octeon_instr_pki_ih3 { 362 #if BYTE_ORDER == BIG_ENDIAN 363 364 /* Wider bit */ 365 uint64_t w:1; 366 367 /* Raw mode indicator 1 = RAW */ 368 uint64_t raw:1; 369 370 /* Use Tag */ 371 uint64_t utag:1; 372 373 /* Use QPG */ 374 uint64_t uqpg:1; 375 376 /* Reserved2 */ 377 uint64_t reserved2:1; 378 379 /* Parse Mode */ 380 uint64_t pm:3; 381 382 /* Skip Length */ 383 uint64_t sl:8; 384 385 /* Use Tag Type */ 386 uint64_t utt:1; 387 388 /* Tag type */ 389 uint64_t tagtype:2; 390 391 /* Reserved1 */ 392 uint64_t reserved1:2; 393 394 /* QPG Value */ 395 uint64_t qpg:11; 396 397 /* Tag Value */ 398 uint64_t tag:32; 399 400 #else /* BYTE_ORDER != BIG_ENDIAN */ 401 402 /* Tag Value */ 403 uint64_t tag:32; 404 405 /* QPG Value */ 406 uint64_t qpg:11; 407 408 /* Reserved1 */ 409 uint64_t reserved1:2; 410 411 /* Tag type */ 412 uint64_t tagtype:2; 413 414 /* Use Tag Type */ 415 uint64_t utt:1; 416 417 /* Skip Length */ 418 uint64_t sl:8; 419 420 /* Parse Mode */ 421 uint64_t pm:3; 422 423 /* Reserved2 */ 424 uint64_t reserved2:1; 425 426 /* Use QPG */ 427 uint64_t uqpg:1; 428 429 /* Use Tag */ 430 uint64_t utag:1; 431 432 /* Raw mode indicator 1 = RAW */ 433 uint64_t raw:1; 434 435 /* Wider bit */ 436 uint64_t w:1; 437 #endif /* BYTE_ORDER == BIG_ENDIAN */ 438 439 }; 440 441 /* Input Request Header */ 442 struct octeon_instr_irh { 443 #if BYTE_ORDER == BIG_ENDIAN 444 uint64_t opcode:4; 445 uint64_t rflag:1; 446 uint64_t subcode:7; 447 uint64_t vlan:12; 448 uint64_t priority:3; 449 uint64_t reserved:5; 450 uint64_t ossp:32; /* opcode/subcode specific parameters */ 451 452 #else /* BYTE_ORDER != BIG_ENDIAN */ 453 454 uint64_t ossp:32; /* opcode/subcode specific parameters */ 455 uint64_t reserved:5; 456 uint64_t priority:3; 457 uint64_t vlan:12; 458 uint64_t subcode:7; 459 uint64_t rflag:1; 460 uint64_t opcode:4; 461 #endif /* BYTE_ORDER == BIG_ENDIAN */ 462 }; 463 464 /* Return Data Parameters */ 465 struct octeon_instr_rdp { 466 #if BYTE_ORDER == BIG_ENDIAN 467 uint64_t reserved:49; 468 uint64_t pcie_port:3; 469 uint64_t rlen:12; 470 471 #else /* BYTE_ORDER != BIG_ENDIAN */ 472 473 uint64_t rlen:12; 474 uint64_t pcie_port:3; 475 uint64_t reserved:49; 476 #endif /* BYTE_ORDER == BIG_ENDIAN */ 477 }; 478 479 /* Receive Header */ 480 union octeon_rh { 481 #if BYTE_ORDER == BIG_ENDIAN 482 uint64_t rh64; 483 struct { 484 uint64_t opcode:4; 485 uint64_t subcode:8; 486 uint64_t len:3; /* additional 64-bit words */ 487 uint64_t reserved:17; 488 uint64_t ossp:32; /* opcode/subcode specific parameters */ 489 } r; 490 struct { 491 uint64_t opcode:4; 492 uint64_t subcode:8; 493 uint64_t len:3; /* additional 64-bit words */ 494 uint64_t extra:28; 495 uint64_t vlan:12; 496 uint64_t priority:3; 497 uint64_t csum_verified:3;/* checksum verified. */ 498 uint64_t has_hwtstamp:1; /* Has hardware timestamp. 1 = yes. */ 499 uint64_t encap_on:1; 500 uint64_t has_hash:1; /* Has hash (rth or rss). 1 = yes. */ 501 } r_dh; 502 struct { 503 uint64_t opcode:4; 504 uint64_t subcode:8; 505 uint64_t len:3; /* additional 64-bit words */ 506 uint64_t reserved:11; 507 uint64_t num_gmx_ports:8; 508 uint64_t max_nic_ports:10; 509 uint64_t app_cap_flags:4; 510 uint64_t app_mode:8; 511 uint64_t pkind:8; 512 } r_core_drv_init; 513 struct { 514 uint64_t opcode:4; 515 uint64_t subcode:8; 516 uint64_t len:3; /* additional 64-bit words */ 517 uint64_t reserved:8; 518 uint64_t extra:25; 519 uint64_t gmxport:16; 520 } r_nic_info; 521 #else /* BYTE_ORDER != BIG_ENDIAN */ 522 uint64_t rh64; 523 struct { 524 uint64_t ossp:32; /* opcode/subcode specific parameters */ 525 uint64_t reserved:17; 526 uint64_t len:3; /* additional 64-bit words */ 527 uint64_t subcode:8; 528 uint64_t opcode:4; 529 } r; 530 struct { 531 uint64_t has_hash:1; /* Has hash (rth or rss). 1 = yes. */ 532 uint64_t encap_on:1; 533 uint64_t has_hwtstamp:1; /* 1 = has hwtstamp */ 534 uint64_t csum_verified:3; /* checksum verified. */ 535 uint64_t priority:3; 536 uint64_t vlan:12; 537 uint64_t extra:28; 538 uint64_t len:3; /* additional 64-bit words */ 539 uint64_t subcode:8; 540 uint64_t opcode:4; 541 } r_dh; 542 struct { 543 uint64_t pkind:8; 544 uint64_t app_mode:8; 545 uint64_t app_cap_flags:4; 546 uint64_t max_nic_ports:10; 547 uint64_t num_gmx_ports:8; 548 uint64_t reserved:11; 549 uint64_t len:3; /* additional 64-bit words */ 550 uint64_t subcode:8; 551 uint64_t opcode:4; 552 } r_core_drv_init; 553 struct { 554 uint64_t gmxport:16; 555 uint64_t extra:25; 556 uint64_t reserved:8; 557 uint64_t len:3; /* additional 64-bit words */ 558 uint64_t subcode:8; 559 uint64_t opcode:4; 560 } r_nic_info; 561 #endif /* BYTE_ORDER == BIG_ENDIAN */ 562 }; 563 564 #define OCTEON_RH_SIZE (sizeof(union octeon_rh)) 565 566 union octeon_packet_params { 567 uint32_t pkt_params32; 568 struct { 569 #if BYTE_ORDER == BIG_ENDIAN 570 uint32_t reserved:24; 571 uint32_t ip_csum:1; /* Perform IP header checksum(s) */ 572 /* Perform Outer transport header checksum */ 573 uint32_t transport_csum:1; 574 /* Find tunnel, and perform transport csum. */ 575 uint32_t tnl_csum:1; 576 uint32_t tsflag:1; /* Timestamp this packet */ 577 uint32_t ipsec_ops:4; /* IPsec operation */ 578 579 #else /* BYTE_ORDER != BIG_ENDIAN */ 580 581 uint32_t ipsec_ops:4; 582 uint32_t tsflag:1; 583 uint32_t tnl_csum:1; 584 uint32_t transport_csum:1; 585 uint32_t ip_csum:1; 586 uint32_t reserved:24; 587 #endif /* BYTE_ORDER == BIG_ENDIAN */ 588 } s; 589 }; 590 591 /* Status of a RGMII Link on Octeon as seen by core driver. */ 592 union octeon_link_status { 593 uint64_t link_status64; 594 595 struct { 596 #if BYTE_ORDER == BIG_ENDIAN 597 uint64_t duplex:8; 598 uint64_t mtu:16; 599 uint64_t speed:16; 600 uint64_t link_up:1; 601 uint64_t autoneg:1; 602 uint64_t if_mode:5; 603 uint64_t pause:1; 604 uint64_t flashing:1; 605 uint64_t reserved:15; 606 607 #else /* BYTE_ORDER != BIG_ENDIAN */ 608 609 uint64_t reserved:15; 610 uint64_t flashing:1; 611 uint64_t pause:1; 612 uint64_t if_mode:5; 613 uint64_t autoneg:1; 614 uint64_t link_up:1; 615 uint64_t speed:16; 616 uint64_t mtu:16; 617 uint64_t duplex:8; 618 #endif /* BYTE_ORDER == BIG_ENDIAN */ 619 } s; 620 }; 621 622 /* The txpciq info passed to host from the firmware */ 623 624 union octeon_txpciq { 625 uint64_t txpciq64; 626 627 struct { 628 #if BYTE_ORDER == BIG_ENDIAN 629 uint64_t q_no:8; 630 uint64_t port:8; 631 uint64_t pkind:6; 632 uint64_t use_qpg:1; 633 uint64_t qpg:11; 634 uint64_t aura_num:10; 635 uint64_t reserved:20; 636 637 #else /* BYTE_ORDER != BIG_ENDIAN */ 638 639 uint64_t reserved:20; 640 uint64_t aura_num:10; 641 uint64_t qpg:11; 642 uint64_t use_qpg:1; 643 uint64_t pkind:6; 644 uint64_t port:8; 645 uint64_t q_no:8; 646 #endif /* BYTE_ORDER == BIG_ENDIAN */ 647 } s; 648 }; 649 650 /* The rxpciq info passed to host from the firmware */ 651 652 union octeon_rxpciq { 653 uint64_t rxpciq64; 654 655 struct { 656 #if BYTE_ORDER == BIG_ENDIAN 657 uint64_t q_no:8; 658 uint64_t reserved:56; 659 660 #else /* BYTE_ORDER != BIG_ENDIAN */ 661 662 uint64_t reserved:56; 663 uint64_t q_no:8; 664 #endif /* BYTE_ORDER == BIG_ENDIAN */ 665 } s; 666 }; 667 668 /* Information for a OCTEON ethernet interface shared between core & host. */ 669 struct octeon_link_info { 670 union octeon_link_status link; 671 uint64_t hw_addr; 672 673 #if BYTE_ORDER == BIG_ENDIAN 674 uint64_t gmxport:16; 675 uint64_t macaddr_is_admin_asgnd:1; 676 uint64_t vlan_is_admin_assigned:1; 677 uint64_t rsvd:30; 678 uint64_t num_txpciq:8; 679 uint64_t num_rxpciq:8; 680 681 #else /* BYTE_ORDER != BIG_ENDIAN */ 682 683 uint64_t num_rxpciq:8; 684 uint64_t num_txpciq:8; 685 uint64_t rsvd:30; 686 uint64_t vlan_is_admin_assigned:1; 687 uint64_t macaddr_is_admin_asgnd:1; 688 uint64_t gmxport:16; 689 #endif /* BYTE_ORDER == BIG_ENDIAN */ 690 691 union octeon_txpciq txpciq[LIO_MAX_IOQS_PER_NICIF]; 692 union octeon_rxpciq rxpciq[LIO_MAX_IOQS_PER_NICIF]; 693 }; 694 695 struct octeon_if_cfg_info { 696 uint64_t iqmask; /* mask for IQs enabled for the port */ 697 uint64_t oqmask; /* mask for OQs enabled for the port */ 698 struct octeon_link_info linfo; /* initial link information */ 699 char lio_firmware_version[32]; 700 }; 701 702 /* Stats for each NIC port in RX direction. */ 703 struct octeon_rx_stats { 704 /* link-level stats */ 705 uint64_t total_rcvd; 706 uint64_t bytes_rcvd; 707 uint64_t total_bcst; 708 uint64_t total_mcst; 709 uint64_t runts; 710 uint64_t ctl_rcvd; 711 uint64_t fifo_err; /* Accounts for over/under-run of buffers */ 712 uint64_t dmac_drop; 713 uint64_t fcs_err; 714 uint64_t jabber_err; 715 uint64_t l2_err; 716 uint64_t frame_err; 717 718 /* firmware stats */ 719 uint64_t fw_total_rcvd; 720 uint64_t fw_total_fwd; 721 uint64_t fw_total_fwd_bytes; 722 uint64_t fw_err_pko; 723 uint64_t fw_err_link; 724 uint64_t fw_err_drop; 725 uint64_t fw_rx_vxlan; 726 uint64_t fw_rx_vxlan_err; 727 728 /* LRO */ 729 uint64_t fw_lro_pkts; /* Number of packets that are LROed */ 730 uint64_t fw_lro_octs; /* Number of octets that are LROed */ 731 uint64_t fw_total_lro; /* Number of LRO packets formed */ 732 uint64_t fw_lro_aborts; /* Number of times lRO of packet aborted */ 733 uint64_t fw_lro_aborts_port; 734 uint64_t fw_lro_aborts_seq; 735 uint64_t fw_lro_aborts_tsval; 736 uint64_t fw_lro_aborts_timer; 737 /* intrmod: packet forward rate */ 738 uint64_t fwd_rate; 739 }; 740 741 /* Stats for each NIC port in RX direction. */ 742 struct octeon_tx_stats { 743 /* link-level stats */ 744 uint64_t total_pkts_sent; 745 uint64_t total_bytes_sent; 746 uint64_t mcast_pkts_sent; 747 uint64_t bcast_pkts_sent; 748 uint64_t ctl_sent; 749 uint64_t one_collision_sent; /* Packets sent after one collision */ 750 uint64_t multi_collision_sent; /* Packets sent after multiple collision */ 751 uint64_t max_collision_fail; /* Packets not sent due to max collisions */ 752 uint64_t max_deferral_fail; /* Packets not sent due to max deferrals */ 753 uint64_t fifo_err; /* Accounts for over/under-run of buffers */ 754 uint64_t runts; 755 uint64_t total_collisions; /* Total number of collisions detected */ 756 757 /* firmware stats */ 758 uint64_t fw_total_sent; 759 uint64_t fw_total_fwd; 760 uint64_t fw_total_fwd_bytes; 761 uint64_t fw_err_pko; 762 uint64_t fw_err_link; 763 uint64_t fw_err_drop; 764 uint64_t fw_err_tso; 765 uint64_t fw_tso; /* number of tso requests */ 766 uint64_t fw_tso_fwd; /* number of packets segmented in tso */ 767 uint64_t fw_tx_vxlan; 768 uint64_t fw_err_pki; 769 }; 770 771 struct octeon_link_stats { 772 struct octeon_rx_stats fromwire; 773 struct octeon_tx_stats fromhost; 774 775 }; 776 777 static inline int 778 lio_opcode_slow_path(union octeon_rh *rh) 779 { 780 uint16_t subcode1, subcode2; 781 782 subcode1 = LIO_OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 783 subcode2 = LIO_OPCODE_SUBCODE(LIO_OPCODE_NIC, LIO_OPCODE_NIC_NW_DATA); 784 785 return (subcode2 != subcode1); 786 } 787 788 struct octeon_mdio_cmd { 789 uint64_t op; 790 uint64_t mdio_addr; 791 uint64_t value1; 792 uint64_t value2; 793 uint64_t value3; 794 }; 795 796 struct octeon_intrmod_cfg { 797 uint64_t rx_enable; 798 uint64_t tx_enable; 799 uint64_t check_intrvl; 800 uint64_t maxpkt_ratethr; 801 uint64_t minpkt_ratethr; 802 uint64_t rx_maxcnt_trigger; 803 uint64_t rx_mincnt_trigger; 804 uint64_t rx_maxtmr_trigger; 805 uint64_t rx_mintmr_trigger; 806 uint64_t tx_mincnt_trigger; 807 uint64_t tx_maxcnt_trigger; 808 uint64_t rx_frames; 809 uint64_t tx_frames; 810 uint64_t rx_usecs; 811 }; 812 813 #define LIO_BASE_QUEUE_NOT_REQUESTED 65535 814 815 union octeon_if_cfg { 816 uint64_t if_cfg64; 817 struct { 818 #if BYTE_ORDER == BIG_ENDIAN 819 uint64_t base_queue:16; 820 uint64_t num_iqueues:16; 821 uint64_t num_oqueues:16; 822 uint64_t gmx_port_id:8; 823 uint64_t vf_id:8; 824 825 #else /* BYTE_ORDER != BIG_ENDIAN */ 826 827 uint64_t vf_id:8; 828 uint64_t gmx_port_id:8; 829 uint64_t num_oqueues:16; 830 uint64_t num_iqueues:16; 831 uint64_t base_queue:16; 832 #endif /* BYTE_ORDER == BIG_ENDIAN */ 833 } s; 834 }; 835 836 #endif /* __LIO_COMMON_H__ */ 837