1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37 #define LGE_MODE1 0x00 /* CSR00 */ 38 #define LGE_MODE2 0x04 /* CSR01 */ 39 #define LGE_PPTXBUF_IDX 0x08 /* CSR02 */ 40 #define LGE_PRODID 0x0C /* CSR03 */ 41 #define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */ 42 #define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */ 43 #define LGE_RSVD0 0x18 /* CSR06 */ 44 #define LGE_PPRXBUF_IDX 0x1C /* CSR07 */ 45 #define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */ 46 #define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */ 47 #define LGE_EECTL 0x28 /* CSR10 */ 48 #define LGE_CHIPSTS 0x2C /* CSR11 */ 49 #define LGE_TXDESC_ADDR_LO 0x30 /* CSR12 */ 50 #define LGE_TXDESC_ADDR_HI 0x34 /* CSR13 */ 51 #define LGE_RXDESC_ADDR_LO 0x38 /* CSR14 */ 52 #define LGE_RXDESC_ADDR_HI 0x3C /* CSR15 */ 53 #define LGE_PPTXCTL 0x40 /* CSR16 */ 54 #define LGE_PPRXCTL 0x44 /* CSR17 */ 55 #define LGE_INTR_PERIOD 0x48 /* CSR18 */ 56 #define LGE_TXFIFO_PKTCNT 0x4C /* CSR19 */ 57 #define LGE_TXFIFO_LOWAT 0x50 /* CSR20 */ 58 #define LGE_TXFIFO_FREEDWORDS 0x54 /* CSR21 */ 59 #define LGE_TXFIFO_WRITE 0x58 /* CSR22 */ 60 #define LGE_RSVD1 0x5C /* CSR23 */ 61 #define LGE_RXFIFO_READ 0x60 /* CSR24 */ 62 #define LGE_RSVD2 0x64 /* CSR25 */ 63 #define LGE_RXFIFO_DWORDCNT 0x68 /* CSR26 */ 64 #define LGE_RXFIFO_HIWAT 0x6C /* CSR27 */ 65 #define LGE_RXFIFO_PKTCNT 0x70 /* CSR28 */ 66 #define LGE_CMD 0x74 /* CSR29 */ 67 #define LGE_IMR 0x78 /* CSR30 */ 68 #define LGE_RSVD3 0x7C /* CSR31 */ 69 #define LGE_ISR 0x80 /* CSR32 */ 70 #define LGE_RSVD4 0x84 /* CSR33 */ 71 #define LGE_MAR0 0x88 /* CSR34 */ 72 #define LGE_MAR1 0x8C /* CSR35 */ 73 #define LGE_LEDCFG0 0x90 /* CSR36 */ 74 #define LGE_LEDCFG1 0x84 /* CSR37 */ 75 #define LGE_LEDCFG2 0x98 /* CSR38 */ 76 #define LGE_LEDCFG3 0x9C /* CSR39 */ 77 #define LGE_RSVD5 0xA0 /* CSR40 */ 78 #define LGE_EEDATA 0xA4 /* CSR41 */ 79 #define LGE_PAR0 0xA8 /* CSR42 */ 80 #define LGE_PAR1 0xAC /* CSR43 */ 81 #define LGE_GMIICTL 0xB0 /* CSR44 */ 82 #define LGE_GMIIMODE 0xB4 /* CSR45 */ 83 #define LGE_STATSIDX 0xB8 /* CSR46 */ 84 #define LGE_STATSVAL 0xBC /* CSR47 */ 85 #define LGE_VLANCTL 0xC0 /* CSR48 */ 86 #define LGE_RSVD6 0xC4 /* CSR49 */ 87 #define LGE_RSVD7 0xC8 /* CSR50 */ 88 #define LGE_CMDSTS 0xCC /* CSR51 */ 89 #define LGE_FLOWCTL_WAT 0xD0 /* CSR52 */ 90 #define LGE_RSVD8 0xD4 /* CSR53 */ 91 #define LGE_RSVD9 0xD8 /* CSR54 */ 92 #define LGE_RSVD10 0xDC /* CSR55 */ 93 #define LGE_RSVD11 0xE0 /* CSR56 */ 94 #define LGE_RSVD12 0xE4 /* CSR57 */ 95 #define LGE_TIMER0_CNT 0xE8 /* CSR58 */ 96 #define LGE_TIMER0_INT 0xEC /* CSR59 */ 97 #define LGE_TIMER1_CNT 0xF0 /* CSR60 */ 98 #define LGE_TIMER1_INT 0xF4 /* CSR61 */ 99 #define LGE_DBG_CMD 0xF8 /* CSR62 */ 100 #define LGE_DBG_DATA 0xFC /* CSR63 */ 101 102 103 /* Mode register 1 */ 104 #define LGE_MODE1_SETRST_CTL0 0x00000001 105 #define LGE_MODE1_SOFTRST 0x00000002 106 #define LGE_MODE1_DEBTOD 0x00000004 /* Not documented? */ 107 #define LGE_MODE1_TX_FLOWCTL 0x00000008 /* Not documented? */ 108 #define LGE_MODE1_RXTXRIO 0x00000010 109 #define LGE_MODE1_GMIIPOLL 0x00000020 110 #define LGE_MODE1_TXPAD 0x00000040 111 #define LGE_MODE1_RMVPAD 0x00000080 /* Not documented? */ 112 #define LGE_MODE1_SETRST_CTL1 0x00000100 113 #define LGE_MODE1_TX_ENB 0x00000200 114 #define LGE_MODE1_RX_ENB 0x00000400 115 #define LGE_MODE1_RX_MCAST 0x00000800 116 #define LGE_MODE1_RX_BCAST 0x00001000 117 #define LGE_MODE1_RX_PROMISC 0x00002000 118 #define LGE_MODE1_RX_UCAST 0x00004000 119 #define LGE_MODE1_RX_GIANTS 0x00008000 120 #define LGE_MODE1_SETRST_CTL2 0x00010000 121 #define LGE_MODE1_RX_CRC 0x00020000 122 #define LGE_MODE1_RX_ERRPKTS 0x00040000 123 #define LGE_MODE1_TX_CRC 0x00080000 124 #define LGE_MODE1_DEMDEN 0x00100000 /* Not documented? */ 125 #define LGE_MODE1_MPACK_ENB 0x00200000 126 #define LGE_MODE1_MPACK_BCAST 0x00400000 127 #define LGE_MODE1_RX_FLOWCTL 0x00800000 128 #define LGE_MODE1_SETRST_CTL3 0x01000000 129 #define LGE_MODE1_VLAN_RX 0x02000000 130 #define LGE_MODE1_VLAN_TX 0x04000000 131 #define LGE_MODE1_VLAN_STRIP 0x08000000 132 #define LGE_MODE1_VLAN_INSERT 0x10000000 133 #define LGE_MODE1_GPIO_CTL0 0x20000000 134 #define LGE_MODE1_GPIO_CTL1 0x40000000 135 #define LGE_MODE1_RX_LENCHK 0x80000000 136 137 138 /* Mode register 2 */ 139 #define LGE_MODE2_LOOPBACK 0x000000E0 140 #define LGE_MODE2_RX_IPCSUM 0x00001000 141 #define LGE_MODE2_RX_TCPCSUM 0x00002000 142 #define LGE_MODE2_RX_UDPCSUM 0x00004000 143 #define LGE_MODE2_RX_ERRCSUM 0x00008000 144 145 146 /* EEPROM register */ 147 #define LGE_EECTL_HAVE_EEPROM 0x00000001 148 #define LGE_EECTL_CMD_READ 0x00000002 149 #define LGE_EECTL_CMD_WRITE 0x00000004 150 #define LGE_EECTL_CSUMERR 0x00000010 151 #define LGE_EECTL_MULTIACCESS 0x00000020 152 #define LGE_EECTL_SINGLEACCESS 0x00000040 153 #define LGE_EECTL_ADDR 0x00001F00 154 #define LGE_EECTL_ROM_TIMING 0x000F0000 155 #define LGE_EECTL_HAVE_FLASH 0x00100000 156 #define LGE_EECTL_WRITEFLASH 0x00200000 157 158 #define LGE_EE_NODEADDR_0 0x12 159 #define LGE_EE_NODEADDR_1 0x13 160 #define LGE_EE_NODEADDR_2 0x10 161 162 163 /* Chip status register */ 164 #define LGE_CHIPSTS_HAVETXSPC 0x00000001 /* have room in TX FIFO for pkt */ 165 #define LGE_CHIPSTS_HAVERXPKT 0x00000002 /* RX FIFO holds complete pkt */ 166 #define LGE_CHIPSTS_FLOWCTL_STS 0x00000004 167 #define LGE_CHIPSTS_GPIO_STS0 0x00000008 168 #define LGE_CHIPSTS_GPIO_STS1 0x00000010 169 #define LGE_CHIPSTS_TXIDLE 0x00000020 170 #define LGE_CHIPSTS_RXIDLE 0x00000040 171 172 173 /* TX PacketPropulsion control register */ 174 #define LGE_PPTXCTL_BUFLEN 0x0000FFFF 175 #define LGE_PPTXCTL_BUFID 0x003F0000 176 #define LGE_PPTXCTL_WANTINTR 0x01000000 177 178 179 /* RX PacketPropulsion control register */ 180 #define LGE_PPRXCTL_BUFLEN 0x0000FFFF 181 #define LGE_PPRXCTL_BUFID 0x003F0000 182 #define LGE_PPRXCTL_WANTINTR 0x10000000 183 184 185 /* Command register */ 186 #define LGE_CMD_SETRST_CTL0 0x00000001 187 #define LGE_CMD_STARTTX 0x00000002 188 #define LGE_CMD_SKIP_RXPKT 0x00000004 189 #define LGE_CMD_DEL_INTREQ 0x00000008 190 #define LGE_CMD_PER_INTREQ 0x00000010 191 #define LGE_CMD_TIMER0 0x00000020 192 #define LGE_CMD_TIMER1 0x00000040 193 194 195 /* Interrupt mask register */ 196 #define LGE_IMR_SETRST_CTL0 0x00000001 197 #define LGE_IMR_TXCMDFIFO_EMPTY 0x00000002 198 #define LGE_IMR_TXFIFO_WAT 0x00000004 199 #define LGE_IMR_TXDMA_DONE 0x00000008 200 #define LGE_IMR_DELAYEDINTR 0x00000040 201 #define LGE_IMR_INTR_ENB 0x00000080 202 #define LGE_IMR_SETRST_CTL1 0x00000100 203 #define LGE_IMR_RXCMDFIFO_EMPTY 0x00000200 204 #define LGE_IMR_RXFIFO_WAT 0x00000400 205 #define LGE_IMR_RX_DONE 0x00000800 206 #define LGE_IMR_RXDMA_DONE 0x00001000 207 #define LGE_IMR_PHY_INTR 0x00002000 208 #define LGE_IMR_MAGICPKT 0x00004000 209 #define LGE_IMR_SETRST_CTL2 0x00010000 210 #define LGE_IMR_GPIO0 0x00020000 211 #define LGE_IMR_GPIO1 0x00040000 212 #define LGE_IMR_TIMER0 0x00080000 213 #define LGE_IMR_TIMER1 0x00100000 214 215 216 #define LGE_INTRS \ 217 (LGE_IMR_TXCMDFIFO_EMPTY|LGE_IMR_TXDMA_DONE|LGE_IMR_RX_DONE| \ 218 LGE_IMR_RXCMDFIFO_EMPTY|LGE_IMR_RXDMA_DONE|LGE_IMR_PHY_INTR) 219 220 221 /* Interrupt status register */ 222 #define LGE_ISR_TXCMDFIFO_EMPTY 0x00000002 223 #define LGE_ISR_TXFIFO_WAT 0x00000004 224 #define LGE_ISR_TXDMA_DONE 0x00000008 225 #define LGE_ISR_DELAYEDINTR 0x00000040 226 #define LGE_ISR_INTR_ENB 0x00000080 227 #define LGE_ISR_RXCMDFIFO_EMPTY 0x00000200 228 #define LGE_ISR_RXFIFO_WAT 0x00000400 229 #define LGE_ISR_RX_DONE 0x00000800 230 #define LGE_ISR_RXDMA_DONE 0x00001000 231 #define LGE_ISR_PHY_INTR 0x00002000 232 #define LGE_ISR_MAGICPKT 0x00004000 233 #define LGE_ISR_GPIO0 0x00020000 234 #define LGE_ISR_GPIO1 0x00040000 235 #define LGE_ISR_TIMER0 0x00080000 236 #define LGE_ISR_TIMER1 0x00100000 237 #define LGE_ISR_RXDMADONE_CNT 0xFF000000 238 #define LGE_RX_DMACNT(x) ((x & LGE_ISR_RXDMADONE_CNT) >> 24) 239 240 /* LED0 config register */ 241 #define LGE_LED0CFG_ENABLE 0x00000002 242 #define LGE_LED0CFG_INPUT_POL 0x00000004 243 #define LGE_LED0CFG_PULSE_EXP 0x00000008 244 #define LGE_LED0CFG_10MBPS 0x00000010 245 #define LGE_LED0CFG_100MBPS 0x00000100 246 #define LGE_LED0CFG_1000MBPS 0x00000200 247 #define LGE_LED0CFG_FDX 0x00000400 248 #define LGE_LED0CFG_ANEG 0x00000800 249 #define LGE_LED0CFG_LINKSTS 0x00001000 250 #define LGE_LED0CFG_RXMATCH 0x00002000 251 #define LGE_LED0CFG_TX 0x00004000 252 #define LGE_LED0CFG_RX 0x00008000 253 #define LGE_LED0CFG_JABBER 0x00010000 254 #define LGE_LED0CFG_COLLISION 0x00020000 255 #define LGE_LED0CFG_CARRIER 0x00040000 256 #define LGE_LED0CFG_LEDOUT 0x10000000 257 258 259 /* LED1 config register */ 260 #define LGE_LED1CFG_ENABLE 0x00000002 261 #define LGE_LED1CFG_INPUT_POL 0x00000004 262 #define LGE_LED1CFG_PULSE_EXP 0x00000008 263 #define LGE_LED1CFG_10MBPS 0x00000010 264 #define LGE_LED1CFG_100MBPS 0x00000100 265 #define LGE_LED1CFG_1000MBPS 0x00000200 266 #define LGE_LED1CFG_FDX 0x00000400 267 #define LGE_LED1CFG_ANEG 0x00000800 268 #define LGE_LED1CFG_LINKSTS 0x00001000 269 #define LGE_LED1CFG_RXMATCH 0x00002000 270 #define LGE_LED1CFG_TX 0x00004000 271 #define LGE_LED1CFG_RX 0x00008000 272 #define LGE_LED1CFG_JABBER 0x00010000 273 #define LGE_LED1CFG_COLLISION 0x00020000 274 #define LGE_LED1CFG_CARRIER 0x00040000 275 #define LGE_LED1CFG_LEDOUT 0x10000000 276 277 278 /* LED2 config register */ 279 #define LGE_LED2CFG_ENABLE 0x00000002 280 #define LGE_LED2CFG_INPUT_POL 0x00000004 281 #define LGE_LED2CFG_PULSE_EXP 0x00000008 282 #define LGE_LED2CFG_10MBPS 0x00000010 283 #define LGE_LED2CFG_100MBPS 0x00000100 284 #define LGE_LED2CFG_1000MBPS 0x00000200 285 #define LGE_LED2CFG_FDX 0x00000400 286 #define LGE_LED2CFG_ANEG 0x00000800 287 #define LGE_LED2CFG_LINKSTS 0x00001000 288 #define LGE_LED2CFG_RXMATCH 0x00002000 289 #define LGE_LED2CFG_TX 0x00004000 290 #define LGE_LED2CFG_RX 0x00008000 291 #define LGE_LED2CFG_JABBER 0x00010000 292 #define LGE_LED2CFG_COLLISION 0x00020000 293 #define LGE_LED2CFG_CARRIER 0x00040000 294 #define LGE_LED2CFG_LEDOUT 0x10000000 295 296 297 /* GMII PHY access register */ 298 #define LGE_GMIICTL_PHYREG 0x0000001F 299 #define LGE_GMIICTL_CMD 0x00000080 300 #define LGE_GMIICTL_PHYADDR 0x00001F00 301 #define LGE_GMIICTL_CMDBUSY 0x00008000 302 #define LGE_GMIICTL_DATA 0xFFFF0000 303 304 #define LGE_GMIICMD_READ 0x00000000 305 #define LGE_GMIICMD_WRITE 0x00000080 306 307 /* GMII PHY mode register */ 308 #define LGE_GMIIMODE_SPEED 0x00000003 309 #define LGE_GMIIMODE_FDX 0x00000004 310 #define LGE_GMIIMODE_PROTSEL 0x00000100 /* 0 == GMII, 1 == TBI */ 311 #define LGE_GMIIMODE_PCSENH 0x00000200 312 313 #define LGE_SPEED_10 0x00000000 314 #define LGE_SPEED_100 0x00000001 315 #define LGE_SPEED_1000 0x00000002 316 317 318 /* VLAN tag control register */ 319 #define LGE_VLANCTL_VLID 0x00000FFF 320 #define LGE_VLANCTL_USERPRIO 0x0000E000 321 #define LGE_VLANCTL_TCI_IDX 0x000D0000 322 #define LGE_VLANCTL_TBLCMD 0x00200000 323 324 325 /* Command status register */ 326 #define LGE_CMDSTS_TXDMADONE 0x000000FF 327 #define LGE_CMDSTS_RXDMADONE 0x0000FF00 328 #define LGE_CMDSTS_TXCMDFREE 0x003F0000 329 #define LGE_CMDSTS_RXCMDFREE 0x3F000000 330 331 #define LGE_TXDMADONE_8BIT LGE_CMDSTS 332 #define LGE_RXDMADONE_8BIT (LGE_CMDSTS + 1) 333 #define LGE_TXCMDFREE_8BIT (LGE_CMDSTS + 2) 334 #define LGE_RXCMDFREE_8BIT (LGE_CMDSTS + 3) 335 336 #define LGE_MAXCMDS 31 337 338 /* Index for statistics counters. */ 339 #define LGE_STATS_TX_PKTS_OK 0x00 340 #define LGE_STATS_SINGLE_COLL_PKTS 0x01 341 #define LGE_STATS_MULTI_COLL_PKTS 0x02 342 #define LGE_STATS_RX_PKTS_OK 0x03 343 #define LGE_STATS_FCS_ERRS 0x04 344 #define LGE_STATS_ALIGN_ERRS 0x05 345 #define LGE_STATS_DROPPED_PKTS 0x06 346 #define LGE_STATS_RX_ERR_PKTS 0x07 347 #define LGE_STATS_TX_ERR_PKTS 0x08 348 #define LGE_STATS_LATE_COLLS 0x09 349 #define LGE_STATS_RX_RUNTS 0x0A 350 #define LGE_STATS_RX_GIANTS 0x0B 351 #define LGE_STATS_VLAN_PKTS_ACCEPT 0x0C 352 #define LGE_STATS_VLAN_PKTS_REJECT 0x0D 353 #define LGE_STATS_IP_CSUM_ERR 0x0E 354 #define LGE_STATS_UDP_CSUM_ERR 0x0F 355 #define LGE_STATS_RANGELEN_ERRS 0x10 356 #define LGE_STATS_TCP_CSUM_ERR 0x11 357 #define LGE_STATS_RSVD0 0x12 358 #define LGE_STATS_TX_EXCESS_COLLS 0x13 359 #define LGE_STATS_RX_UCASTS 0x14 360 #define LGE_STATS_RX_MCASTS 0x15 361 #define LGE_STATS_RX_BCASTS 0x16 362 #define LGE_STATS_RX_PAUSE_PKTS 0x17 363 #define LGE_STATS_TX_PAUSE_PKTS 0x18 364 #define LGE_STATS_TX_PKTS_DEFERRED 0x19 365 #define LGE_STATS_TX_EXCESS_DEFER 0x1A 366 #define LGE_STATS_CARRIER_SENSE_ERR 0x1B 367 368 369 /* 370 * RX and TX DMA descriptor structures for scatter/gather. 371 * Each descriptor can have up to 31 fragments in it, however for 372 * RX we only need one fragment, and for transmit we only allocate 373 * 10 in order to reduce the amount of space we need for the 374 * descriptor lists. 375 * Note: descriptor structures must be 64-bit aligned. 376 */ 377 378 struct lge_rx_desc { 379 /* Hardware descriptor section */ 380 u_int32_t lge_ctl; 381 u_int32_t lge_sts; 382 u_int32_t lge_fragptr_lo; 383 u_int32_t lge_fragptr_hi; 384 u_int16_t lge_fraglen; 385 u_int16_t lge_rsvd0; 386 u_int32_t lge_rsvd1; 387 /* Driver software section */ 388 union { 389 struct mbuf *lge_mbuf; 390 u_int64_t lge_dummy; 391 } lge_u; 392 }; 393 394 struct lge_frag { 395 u_int32_t lge_rsvd0; 396 u_int32_t lge_fragptr_lo; 397 u_int32_t lge_fragptr_hi; 398 u_int16_t lge_fraglen; 399 u_int16_t lge_rsvd1; 400 }; 401 402 struct lge_tx_desc { 403 /* Hardware descriptor section */ 404 u_int32_t lge_ctl; 405 struct lge_frag lge_frags[10]; 406 u_int32_t lge_rsvd0; 407 union { 408 struct mbuf *lge_mbuf; 409 u_int64_t lge_dummy; 410 } lge_u; 411 }; 412 413 #define lge_mbuf lge_u.lge_mbuf 414 415 #define LGE_RXCTL_BUFLEN 0x0000FFFF 416 #define LGE_RXCTL_FRAGCNT 0x001F0000 417 #define LGE_RXCTL_LENERR 0x00400000 418 #define LGE_RXCTL_UCAST 0x00800000 419 #define LGR_RXCTL_BCAST 0x01000000 420 #define LGE_RXCTL_MCAST 0x02000000 421 #define LGE_RXCTL_GIANT 0x04000000 422 #define LGE_RXCTL_OFLOW 0x08000000 423 #define LGE_RXCTL_CRCERR 0x10000000 424 #define LGE_RXCTL_RUNT 0x20000000 425 #define LGE_RXCTL_ALGNERR 0x40000000 426 #define LGE_RXCTL_WANTINTR 0x80000000 427 428 #define LGE_RXCTL_ERRMASK \ 429 (LGE_RXCTL_LENERR|LGE_RXCTL_OFLOW| \ 430 LGE_RXCTL_CRCERR|LGE_RXCTL_RUNT| \ 431 LGE_RXCTL_ALGNERR) 432 433 #define LGE_RXSTS_VLTBIDX 0x0000000F 434 #define LGE_RXSTS_VLTBLHIT 0x00000010 435 #define LGE_RXSTS_IPCSUMERR 0x00000100 436 #define LGE_RXSTS_TCPCSUMERR 0x00000200 437 #define LGE_RXSTS_UDPCSUMERR 0x00000400 438 #define LGE_RXSTS_ISIP 0x00000800 439 #define LGE_RXSTS_ISTCP 0x00001000 440 #define LGE_RXSTS_ISUDP 0x00002000 441 442 #define LGE_TXCTL_BUFLEN 0x0000FFFF 443 #define LGE_TXCTL_FRAGCNT 0x001F0000 444 #define LGE_TXCTL_VLTBIDX 0x0F000000 445 #define LGE_TXCTL_VLIS 0x10000000 446 #define LGE_TXCTL_WANTINTR 0x80000000 447 448 #define LGE_INC(x, y) (x) = (x + 1) % y 449 #define LGE_FRAGCNT_1 (1<<16) 450 #define LGE_FRAGCNT_10 (10<<16) 451 #define LGE_FRAGCNT(x) (x<<16) 452 #define LGE_RXBYTES(x) (x->lge_ctl & 0xFFFF) 453 #define LGE_RXTAIL(x) \ 454 (x->lge_ldata->lge_rx_list[x->lge_cdata.lge_rx_prod]) 455 456 #define LGE_RX_LIST_CNT 64 457 #define LGE_TX_LIST_CNT 128 458 459 struct lge_list_data { 460 struct lge_rx_desc lge_rx_list[LGE_RX_LIST_CNT]; 461 struct lge_tx_desc lge_tx_list[LGE_TX_LIST_CNT]; 462 }; 463 464 465 /* 466 * Level 1 PCI vendor ID. 467 */ 468 #define LGE_VENDORID 0x1394 469 470 /* 471 * LXT 1001 PCI device IDs 472 */ 473 #define LGE_DEVICEID 0x0001 474 475 struct lge_type { 476 u_int16_t lge_vid; 477 u_int16_t lge_did; 478 const char *lge_name; 479 }; 480 481 #define LGE_JUMBO_FRAMELEN 9018 482 #define LGE_JUMBO_MTU (LGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 483 #define LGE_JSLOTS 384 484 485 #define LGE_JRAWLEN (LGE_JUMBO_FRAMELEN + ETHER_ALIGN) 486 #define LGE_JLEN (LGE_JRAWLEN + (sizeof(u_int64_t) - \ 487 (LGE_JRAWLEN % sizeof(u_int64_t)))) 488 #define LGE_JPAGESZ PAGE_SIZE 489 #define LGE_RESID (LGE_JPAGESZ - (LGE_JLEN * LGE_JSLOTS) % LGE_JPAGESZ) 490 #define LGE_JMEM ((LGE_JLEN * LGE_JSLOTS) + LGE_RESID) 491 492 struct lge_jpool_entry { 493 int slot; 494 SLIST_ENTRY(lge_jpool_entry) jpool_entries; 495 }; 496 497 struct lge_ring_data { 498 int lge_rx_prod; 499 int lge_rx_cons; 500 int lge_tx_prod; 501 int lge_tx_cons; 502 /* Stick the jumbo mem management stuff here too. */ 503 caddr_t lge_jslots[LGE_JSLOTS]; 504 void *lge_jumbo_buf; 505 }; 506 507 struct lge_softc { 508 if_t lge_ifp; 509 device_t lge_dev; 510 bus_space_handle_t lge_bhandle; 511 bus_space_tag_t lge_btag; 512 struct resource *lge_res; 513 struct resource *lge_irq; 514 void *lge_intrhand; 515 device_t lge_miibus; 516 u_int8_t lge_type; 517 u_int8_t lge_link; 518 u_int8_t lge_pcs; 519 int lge_if_flags; 520 int lge_timer; 521 struct lge_list_data *lge_ldata; 522 struct lge_ring_data lge_cdata; 523 struct callout lge_stat_callout; 524 struct mtx lge_mtx; 525 SLIST_HEAD(__lge_jfreehead, lge_jpool_entry) lge_jfree_listhead; 526 SLIST_HEAD(__lge_jinusehead, lge_jpool_entry) lge_jinuse_listhead; 527 }; 528 529 /* 530 * register space access macros 531 */ 532 #define CSR_WRITE_4(sc, reg, val) \ 533 bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val) 534 535 #define CSR_READ_2(sc, reg) \ 536 bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg) 537 538 #define CSR_WRITE_2(sc, reg, val) \ 539 bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val) 540 541 #define CSR_READ_4(sc, reg) \ 542 bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg) 543 544 #define CSR_WRITE_1(sc, reg, val) \ 545 bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val) 546 547 #define CSR_READ_1(sc, reg) \ 548 bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg) 549 550 #define LGE_LOCK(sc) mtx_lock(&(sc)->lge_mtx) 551 #define LGE_UNLOCK(sc) mtx_unlock(&(sc)->lge_mtx) 552 #define LGE_LOCK_ASSERT(sc) mtx_assert(&(sc)->lge_mtx, MA_OWNED) 553 554 #define LGE_TIMEOUT 1000 555 #define LGE_RXLEN 1536 556 #define LGE_MIN_FRAMELEN 60 557 558 /* 559 * PCI low memory base and low I/O base register, and 560 * other PCI registers. 561 */ 562 563 #define LGE_PCI_VENDOR_ID 0x00 564 #define LGE_PCI_DEVICE_ID 0x02 565 #define LGE_PCI_COMMAND 0x04 566 #define LGE_PCI_STATUS 0x06 567 #define LGE_PCI_REVID 0x08 568 #define LGE_PCI_CLASSCODE 0x09 569 #define LGE_PCI_CACHELEN 0x0C 570 #define LGE_PCI_LATENCY_TIMER 0x0D 571 #define LGE_PCI_HEADER_TYPE 0x0E 572 #define LGE_PCI_LOIO 0x10 573 #define LGE_PCI_LOMEM 0x14 574 #define LGE_PCI_BIOSROM 0x30 575 #define LGE_PCI_INTLINE 0x3C 576 #define LGE_PCI_INTPIN 0x3D 577 #define LGE_PCI_MINGNT 0x3E 578 #define LGE_PCI_MINLAT 0x0F 579 #define LGE_PCI_RESETOPT 0x48 580 #define LGE_PCI_EEPROM_DATA 0x4C 581 582 /* power management registers */ 583 #define LGE_PCI_CAPID 0x50 /* 8 bits */ 584 #define LGE_PCI_NEXTPTR 0x51 /* 8 bits */ 585 #define LGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 586 #define LGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 587 588 #define LGE_PSTATE_MASK 0x0003 589 #define LGE_PSTATE_D0 0x0000 590 #define LGE_PSTATE_D1 0x0001 591 #define LGE_PSTATE_D2 0x0002 592 #define LGE_PSTATE_D3 0x0003 593 #define LGE_PME_EN 0x0010 594 #define LGE_PME_STATUS 0x8000 595