1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <william.paul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 #include <sys/socket.h> 80 81 #include <net/if.h> 82 #include <net/if_var.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_types.h> 88 89 #include <net/bpf.h> 90 91 #include <vm/vm.h> /* for vtophys */ 92 #include <vm/pmap.h> /* for vtophys */ 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 104 #define LGE_USEIOSPACE 105 106 #include <dev/lge/if_lgereg.h> 107 108 /* "device miibus" required. See GENERIC if you get errors here. */ 109 #include "miibus_if.h" 110 111 /* 112 * Various supported device vendors/types and their names. 113 */ 114 static const struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117 }; 118 119 static int lge_probe(device_t); 120 static int lge_attach(device_t); 121 static int lge_detach(device_t); 122 123 static int lge_alloc_jumbo_mem(struct lge_softc *); 124 static void lge_free_jumbo_mem(struct lge_softc *); 125 static void *lge_jalloc(struct lge_softc *); 126 static void lge_jfree(struct mbuf *); 127 128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130 static void lge_rxeof(struct lge_softc *, int); 131 static void lge_rxeoc(struct lge_softc *); 132 static void lge_txeof(struct lge_softc *); 133 static void lge_intr(void *); 134 static void lge_tick(void *); 135 static void lge_start(if_t); 136 static void lge_start_locked(if_t); 137 static int lge_ioctl(if_t, u_long, caddr_t); 138 static void lge_init(void *); 139 static void lge_init_locked(struct lge_softc *); 140 static void lge_stop(struct lge_softc *); 141 static void lge_watchdog(struct lge_softc *); 142 static int lge_shutdown(device_t); 143 static int lge_ifmedia_upd(if_t); 144 static void lge_ifmedia_upd_locked(if_t); 145 static void lge_ifmedia_sts(if_t, struct ifmediareq *); 146 147 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 148 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 149 150 static int lge_miibus_readreg(device_t, int, int); 151 static int lge_miibus_writereg(device_t, int, int, int); 152 static void lge_miibus_statchg(device_t); 153 154 static void lge_setmulti(struct lge_softc *); 155 static void lge_reset(struct lge_softc *); 156 static int lge_list_rx_init(struct lge_softc *); 157 static int lge_list_tx_init(struct lge_softc *); 158 159 #ifdef LGE_USEIOSPACE 160 #define LGE_RES SYS_RES_IOPORT 161 #define LGE_RID LGE_PCI_LOIO 162 #else 163 #define LGE_RES SYS_RES_MEMORY 164 #define LGE_RID LGE_PCI_LOMEM 165 #endif 166 167 static device_method_t lge_methods[] = { 168 /* Device interface */ 169 DEVMETHOD(device_probe, lge_probe), 170 DEVMETHOD(device_attach, lge_attach), 171 DEVMETHOD(device_detach, lge_detach), 172 DEVMETHOD(device_shutdown, lge_shutdown), 173 174 /* MII interface */ 175 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 176 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 177 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 178 179 DEVMETHOD_END 180 }; 181 182 static driver_t lge_driver = { 183 "lge", 184 lge_methods, 185 sizeof(struct lge_softc) 186 }; 187 188 DRIVER_MODULE(lge, pci, lge_driver, 0, 0); 189 DRIVER_MODULE(miibus, lge, miibus_driver, 0, 0); 190 MODULE_DEPEND(lge, pci, 1, 1, 1); 191 MODULE_DEPEND(lge, ether, 1, 1, 1); 192 MODULE_DEPEND(lge, miibus, 1, 1, 1); 193 194 #define LGE_SETBIT(sc, reg, x) \ 195 CSR_WRITE_4(sc, reg, \ 196 CSR_READ_4(sc, reg) | (x)) 197 198 #define LGE_CLRBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) & ~(x)) 201 202 #define SIO_SET(x) \ 203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 204 205 #define SIO_CLR(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 207 208 /* 209 * Read a word of data stored in the EEPROM at address 'addr.' 210 */ 211 static void 212 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest) 213 { 214 int i; 215 u_int32_t val; 216 217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 218 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 219 220 for (i = 0; i < LGE_TIMEOUT; i++) 221 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 222 break; 223 224 if (i == LGE_TIMEOUT) { 225 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 226 return; 227 } 228 229 val = CSR_READ_4(sc, LGE_EEDATA); 230 231 if (addr & 1) 232 *dest = (val >> 16) & 0xFFFF; 233 else 234 *dest = val & 0xFFFF; 235 236 return; 237 } 238 239 /* 240 * Read a sequence of words from the EEPROM. 241 */ 242 static void 243 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt, int swap) 244 { 245 int i; 246 u_int16_t word = 0, *ptr; 247 248 for (i = 0; i < cnt; i++) { 249 lge_eeprom_getword(sc, off + i, &word); 250 ptr = (u_int16_t *)(dest + (i * 2)); 251 if (swap) 252 *ptr = ntohs(word); 253 else 254 *ptr = word; 255 } 256 257 return; 258 } 259 260 static int 261 lge_miibus_readreg(device_t dev, int phy, int reg) 262 { 263 struct lge_softc *sc; 264 int i; 265 266 sc = device_get_softc(dev); 267 268 /* 269 * If we have a non-PCS PHY, pretend that the internal 270 * autoneg stuff at PHY address 0 isn't there so that 271 * the miibus code will find only the GMII PHY. 272 */ 273 if (sc->lge_pcs == 0 && phy == 0) 274 return(0); 275 276 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 277 278 for (i = 0; i < LGE_TIMEOUT; i++) 279 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 280 break; 281 282 if (i == LGE_TIMEOUT) { 283 device_printf(sc->lge_dev, "PHY read timed out\n"); 284 return(0); 285 } 286 287 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 288 } 289 290 static int 291 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 292 { 293 struct lge_softc *sc; 294 int i; 295 296 sc = device_get_softc(dev); 297 298 CSR_WRITE_4(sc, LGE_GMIICTL, 299 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 300 301 for (i = 0; i < LGE_TIMEOUT; i++) 302 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 303 break; 304 305 if (i == LGE_TIMEOUT) { 306 device_printf(sc->lge_dev, "PHY write timed out\n"); 307 return(0); 308 } 309 310 return(0); 311 } 312 313 static void 314 lge_miibus_statchg(device_t dev) 315 { 316 struct lge_softc *sc; 317 struct mii_data *mii; 318 319 sc = device_get_softc(dev); 320 mii = device_get_softc(sc->lge_miibus); 321 322 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 323 switch (IFM_SUBTYPE(mii->mii_media_active)) { 324 case IFM_1000_T: 325 case IFM_1000_SX: 326 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 327 break; 328 case IFM_100_TX: 329 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 330 break; 331 case IFM_10_T: 332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 333 break; 334 default: 335 /* 336 * Choose something, even if it's wrong. Clearing 337 * all the bits will hose autoneg on the internal 338 * PHY. 339 */ 340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 341 break; 342 } 343 344 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 345 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 346 } else { 347 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 348 } 349 350 return; 351 } 352 353 static u_int 354 lge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int count) 355 { 356 uint32_t h, *hashes = arg; 357 358 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 359 if (h < 32) 360 hashes[0] |= (1 << h); 361 else 362 hashes[1] |= (1 << (h - 32)); 363 return (1); 364 } 365 366 static void 367 lge_setmulti(struct lge_softc *sc) 368 { 369 if_t ifp; 370 uint32_t hashes[2] = { 0, 0 }; 371 372 ifp = sc->lge_ifp; 373 LGE_LOCK_ASSERT(sc); 374 375 /* Make sure multicast hash table is enabled. */ 376 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 377 378 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 379 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 380 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 381 return; 382 } 383 384 /* first, zot all the existing hash bits */ 385 CSR_WRITE_4(sc, LGE_MAR0, 0); 386 CSR_WRITE_4(sc, LGE_MAR1, 0); 387 388 /* now program new ones */ 389 if_foreach_llmaddr(ifp, lge_hash_maddr, hashes); 390 391 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 392 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 393 394 return; 395 } 396 397 static void 398 lge_reset(struct lge_softc *sc) 399 { 400 int i; 401 402 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 403 404 for (i = 0; i < LGE_TIMEOUT; i++) { 405 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 406 break; 407 } 408 409 if (i == LGE_TIMEOUT) 410 device_printf(sc->lge_dev, "reset never completed\n"); 411 412 /* Wait a little while for the chip to get its brains in order. */ 413 DELAY(1000); 414 415 return; 416 } 417 418 /* 419 * Probe for a Level 1 chip. Check the PCI vendor and device 420 * IDs against our list and return a device name if we find a match. 421 */ 422 static int 423 lge_probe(device_t dev) 424 { 425 const struct lge_type *t; 426 427 t = lge_devs; 428 429 while(t->lge_name != NULL) { 430 if ((pci_get_vendor(dev) == t->lge_vid) && 431 (pci_get_device(dev) == t->lge_did)) { 432 device_set_desc(dev, t->lge_name); 433 return(BUS_PROBE_DEFAULT); 434 } 435 t++; 436 } 437 438 return(ENXIO); 439 } 440 441 /* 442 * Attach the interface. Allocate softc structures, do ifmedia 443 * setup and ethernet/BPF attach. 444 */ 445 static int 446 lge_attach(device_t dev) 447 { 448 u_char eaddr[ETHER_ADDR_LEN]; 449 struct lge_softc *sc; 450 if_t ifp = NULL; 451 int error = 0, rid; 452 453 sc = device_get_softc(dev); 454 sc->lge_dev = dev; 455 456 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 457 MTX_DEF); 458 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 459 460 /* 461 * Map control/status registers. 462 */ 463 pci_enable_busmaster(dev); 464 465 rid = LGE_RID; 466 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 467 468 if (sc->lge_res == NULL) { 469 device_printf(dev, "couldn't map ports/memory\n"); 470 error = ENXIO; 471 goto fail; 472 } 473 474 sc->lge_btag = rman_get_bustag(sc->lge_res); 475 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 476 477 /* Allocate interrupt */ 478 rid = 0; 479 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 480 RF_SHAREABLE | RF_ACTIVE); 481 482 if (sc->lge_irq == NULL) { 483 device_printf(dev, "couldn't map interrupt\n"); 484 error = ENXIO; 485 goto fail; 486 } 487 488 /* Reset the adapter. */ 489 lge_reset(sc); 490 491 /* 492 * Get station address from the EEPROM. 493 */ 494 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 496 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 497 498 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 499 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 500 501 if (sc->lge_ldata == NULL) { 502 device_printf(dev, "no memory for list buffers!\n"); 503 error = ENXIO; 504 goto fail; 505 } 506 507 /* Try to allocate memory for jumbo buffers. */ 508 if (lge_alloc_jumbo_mem(sc)) { 509 device_printf(dev, "jumbo buffer allocation failed\n"); 510 error = ENXIO; 511 goto fail; 512 } 513 514 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 515 if_setsoftc(ifp, sc); 516 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 517 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 518 if_setioctlfn(ifp, lge_ioctl); 519 if_setstartfn(ifp, lge_start); 520 if_setinitfn(ifp, lge_init); 521 if_setsendqlen(ifp, LGE_TX_LIST_CNT - 1); 522 if_setcapabilities(ifp, IFCAP_RXCSUM); 523 if_setcapenable(ifp, if_getcapabilities(ifp)); 524 525 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 526 sc->lge_pcs = 1; 527 else 528 sc->lge_pcs = 0; 529 530 /* 531 * Do MII setup. 532 */ 533 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd, 534 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 535 if (error != 0) { 536 device_printf(dev, "attaching PHYs failed\n"); 537 goto fail; 538 } 539 540 /* 541 * Call MI attach routine. 542 */ 543 ether_ifattach(ifp, eaddr); 544 545 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 546 NULL, lge_intr, sc, &sc->lge_intrhand); 547 548 if (error) { 549 ether_ifdetach(ifp); 550 device_printf(dev, "couldn't set up irq\n"); 551 goto fail; 552 } 553 return (0); 554 555 fail: 556 lge_free_jumbo_mem(sc); 557 if (sc->lge_ldata) 558 contigfree(sc->lge_ldata, 559 sizeof(struct lge_list_data), M_DEVBUF); 560 if (ifp) 561 if_free(ifp); 562 if (sc->lge_irq) 563 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 564 if (sc->lge_res) 565 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 566 mtx_destroy(&sc->lge_mtx); 567 return(error); 568 } 569 570 static int 571 lge_detach(device_t dev) 572 { 573 struct lge_softc *sc; 574 if_t ifp; 575 576 sc = device_get_softc(dev); 577 ifp = sc->lge_ifp; 578 579 LGE_LOCK(sc); 580 lge_reset(sc); 581 lge_stop(sc); 582 LGE_UNLOCK(sc); 583 callout_drain(&sc->lge_stat_callout); 584 ether_ifdetach(ifp); 585 586 bus_generic_detach(dev); 587 device_delete_child(dev, sc->lge_miibus); 588 589 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 590 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 591 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 592 593 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 594 if_free(ifp); 595 lge_free_jumbo_mem(sc); 596 mtx_destroy(&sc->lge_mtx); 597 598 return(0); 599 } 600 601 /* 602 * Initialize the transmit descriptors. 603 */ 604 static int 605 lge_list_tx_init(struct lge_softc *sc) 606 { 607 struct lge_list_data *ld; 608 struct lge_ring_data *cd; 609 int i; 610 611 cd = &sc->lge_cdata; 612 ld = sc->lge_ldata; 613 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 614 ld->lge_tx_list[i].lge_mbuf = NULL; 615 ld->lge_tx_list[i].lge_ctl = 0; 616 } 617 618 cd->lge_tx_prod = cd->lge_tx_cons = 0; 619 620 return(0); 621 } 622 623 624 /* 625 * Initialize the RX descriptors and allocate mbufs for them. Note that 626 * we arralge the descriptors in a closed ring, so that the last descriptor 627 * points back to the first. 628 */ 629 static int 630 lge_list_rx_init(struct lge_softc *sc) 631 { 632 struct lge_list_data *ld; 633 struct lge_ring_data *cd; 634 int i; 635 636 ld = sc->lge_ldata; 637 cd = &sc->lge_cdata; 638 639 cd->lge_rx_prod = cd->lge_rx_cons = 0; 640 641 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 642 643 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 644 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 645 break; 646 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 647 return(ENOBUFS); 648 } 649 650 /* Clear possible 'rx command queue empty' interrupt. */ 651 CSR_READ_4(sc, LGE_ISR); 652 653 return(0); 654 } 655 656 /* 657 * Initialize an RX descriptor and attach an MBUF cluster. 658 */ 659 static int 660 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 661 { 662 struct mbuf *m_new = NULL; 663 char *buf = NULL; 664 665 if (m == NULL) { 666 MGETHDR(m_new, M_NOWAIT, MT_DATA); 667 if (m_new == NULL) { 668 device_printf(sc->lge_dev, "no memory for rx list " 669 "-- packet dropped!\n"); 670 return(ENOBUFS); 671 } 672 673 /* Allocate the jumbo buffer */ 674 buf = lge_jalloc(sc); 675 if (buf == NULL) { 676 #ifdef LGE_VERBOSE 677 device_printf(sc->lge_dev, "jumbo allocation failed " 678 "-- packet dropped!\n"); 679 #endif 680 m_freem(m_new); 681 return(ENOBUFS); 682 } 683 /* Attach the buffer to the mbuf */ 684 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 685 m_extadd(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, sc, NULL, 686 0, EXT_NET_DRV); 687 } else { 688 m_new = m; 689 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 690 m_new->m_data = m_new->m_ext.ext_buf; 691 } 692 693 /* 694 * Adjust alignment so packet payload begins on a 695 * longword boundary. Mandatory for Alpha, useful on 696 * x86 too. 697 */ 698 m_adj(m_new, ETHER_ALIGN); 699 700 c->lge_mbuf = m_new; 701 c->lge_fragptr_hi = 0; 702 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 703 c->lge_fraglen = m_new->m_len; 704 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 705 c->lge_sts = 0; 706 707 /* 708 * Put this buffer in the RX command FIFO. To do this, 709 * we just write the physical address of the descriptor 710 * into the RX descriptor address registers. Note that 711 * there are two registers, one high DWORD and one low 712 * DWORD, which lets us specify a 64-bit address if 713 * desired. We only use a 32-bit address for now. 714 * Writing to the low DWORD register is what actually 715 * causes the command to be issued, so we do that 716 * last. 717 */ 718 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 719 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 720 721 return(0); 722 } 723 724 static int 725 lge_alloc_jumbo_mem(struct lge_softc *sc) 726 { 727 caddr_t ptr; 728 int i; 729 struct lge_jpool_entry *entry; 730 731 /* Grab a big chunk o' storage. */ 732 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 733 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 734 735 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 736 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 737 return(ENOBUFS); 738 } 739 740 SLIST_INIT(&sc->lge_jfree_listhead); 741 SLIST_INIT(&sc->lge_jinuse_listhead); 742 743 /* 744 * Now divide it up into 9K pieces and save the addresses 745 * in an array. 746 */ 747 ptr = sc->lge_cdata.lge_jumbo_buf; 748 for (i = 0; i < LGE_JSLOTS; i++) { 749 sc->lge_cdata.lge_jslots[i] = ptr; 750 ptr += LGE_JLEN; 751 entry = malloc(sizeof(struct lge_jpool_entry), 752 M_DEVBUF, M_NOWAIT); 753 if (entry == NULL) { 754 device_printf(sc->lge_dev, "no memory for jumbo " 755 "buffer queue!\n"); 756 return(ENOBUFS); 757 } 758 entry->slot = i; 759 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 760 entry, jpool_entries); 761 } 762 763 return(0); 764 } 765 766 static void 767 lge_free_jumbo_mem(struct lge_softc *sc) 768 { 769 struct lge_jpool_entry *entry; 770 771 if (sc->lge_cdata.lge_jumbo_buf == NULL) 772 return; 773 774 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) { 775 device_printf(sc->lge_dev, 776 "asked to free buffer that is in use!\n"); 777 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 778 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, 779 jpool_entries); 780 } 781 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) { 782 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 783 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 784 free(entry, M_DEVBUF); 785 } 786 787 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 788 789 return; 790 } 791 792 /* 793 * Allocate a jumbo buffer. 794 */ 795 static void * 796 lge_jalloc(struct lge_softc *sc) 797 { 798 struct lge_jpool_entry *entry; 799 800 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 801 802 if (entry == NULL) { 803 #ifdef LGE_VERBOSE 804 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 805 #endif 806 return(NULL); 807 } 808 809 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 810 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 811 return(sc->lge_cdata.lge_jslots[entry->slot]); 812 } 813 814 /* 815 * Release a jumbo buffer. 816 */ 817 static void 818 lge_jfree(struct mbuf *m) 819 { 820 struct lge_softc *sc; 821 int i; 822 struct lge_jpool_entry *entry; 823 824 /* Extract the softc struct pointer. */ 825 sc = m->m_ext.ext_arg1; 826 827 if (sc == NULL) 828 panic("lge_jfree: can't find softc pointer!"); 829 830 /* calculate the slot this buffer belongs to */ 831 i = ((vm_offset_t)m->m_ext.ext_buf 832 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 833 834 if ((i < 0) || (i >= LGE_JSLOTS)) 835 panic("lge_jfree: asked to free buffer that we don't manage!"); 836 837 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 838 if (entry == NULL) 839 panic("lge_jfree: buffer not in use!"); 840 entry->slot = i; 841 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 842 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 843 } 844 845 /* 846 * A frame has been uploaded: pass the resulting mbuf chain up to 847 * the higher level protocols. 848 */ 849 static void 850 lge_rxeof(struct lge_softc *sc, int cnt) 851 { 852 struct mbuf *m; 853 if_t ifp; 854 struct lge_rx_desc *cur_rx; 855 int c, i, total_len = 0; 856 u_int32_t rxsts, rxctl; 857 858 ifp = sc->lge_ifp; 859 860 /* Find out how many frames were processed. */ 861 c = cnt; 862 i = sc->lge_cdata.lge_rx_cons; 863 864 /* Suck them in. */ 865 while(c) { 866 struct mbuf *m0 = NULL; 867 868 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 869 rxctl = cur_rx->lge_ctl; 870 rxsts = cur_rx->lge_sts; 871 m = cur_rx->lge_mbuf; 872 cur_rx->lge_mbuf = NULL; 873 total_len = LGE_RXBYTES(cur_rx); 874 LGE_INC(i, LGE_RX_LIST_CNT); 875 c--; 876 877 /* 878 * If an error occurs, update stats, clear the 879 * status word and leave the mbuf cluster in place: 880 * it should simply get re-used next time this descriptor 881 * comes up in the ring. 882 */ 883 if (rxctl & LGE_RXCTL_ERRMASK) { 884 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 885 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 886 continue; 887 } 888 889 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 890 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 891 ifp, NULL); 892 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 893 if (m0 == NULL) { 894 device_printf(sc->lge_dev, "no receive buffers " 895 "available -- packet dropped!\n"); 896 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 897 continue; 898 } 899 m = m0; 900 } else { 901 m->m_pkthdr.rcvif = ifp; 902 m->m_pkthdr.len = m->m_len = total_len; 903 } 904 905 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 906 907 /* Do IP checksum checking. */ 908 if (rxsts & LGE_RXSTS_ISIP) 909 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 910 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 911 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 912 if ((rxsts & LGE_RXSTS_ISTCP && 913 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 914 (rxsts & LGE_RXSTS_ISUDP && 915 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 916 m->m_pkthdr.csum_flags |= 917 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 918 m->m_pkthdr.csum_data = 0xffff; 919 } 920 921 LGE_UNLOCK(sc); 922 if_input(ifp, m); 923 LGE_LOCK(sc); 924 } 925 926 sc->lge_cdata.lge_rx_cons = i; 927 928 return; 929 } 930 931 static void 932 lge_rxeoc(struct lge_softc *sc) 933 { 934 if_t ifp; 935 936 ifp = sc->lge_ifp; 937 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 938 lge_init_locked(sc); 939 return; 940 } 941 942 /* 943 * A frame was downloaded to the chip. It's safe for us to clean up 944 * the list buffers. 945 */ 946 947 static void 948 lge_txeof(struct lge_softc *sc) 949 { 950 struct lge_tx_desc *cur_tx = NULL; 951 if_t ifp; 952 u_int32_t idx, txdone; 953 954 ifp = sc->lge_ifp; 955 956 /* Clear the timeout timer. */ 957 sc->lge_timer = 0; 958 959 /* 960 * Go through our tx list and free mbufs for those 961 * frames that have been transmitted. 962 */ 963 idx = sc->lge_cdata.lge_tx_cons; 964 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 965 966 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 967 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 968 969 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 970 if (cur_tx->lge_mbuf != NULL) { 971 m_freem(cur_tx->lge_mbuf); 972 cur_tx->lge_mbuf = NULL; 973 } 974 cur_tx->lge_ctl = 0; 975 976 txdone--; 977 LGE_INC(idx, LGE_TX_LIST_CNT); 978 sc->lge_timer = 0; 979 } 980 981 sc->lge_cdata.lge_tx_cons = idx; 982 983 if (cur_tx != NULL) 984 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 985 986 return; 987 } 988 989 static void 990 lge_tick(void *xsc) 991 { 992 struct lge_softc *sc; 993 struct mii_data *mii; 994 if_t ifp; 995 996 sc = xsc; 997 ifp = sc->lge_ifp; 998 LGE_LOCK_ASSERT(sc); 999 1000 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1001 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1002 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1003 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1004 1005 if (!sc->lge_link) { 1006 mii = device_get_softc(sc->lge_miibus); 1007 mii_tick(mii); 1008 if (mii->mii_media_status & IFM_ACTIVE && 1009 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1010 sc->lge_link++; 1011 if (bootverbose && 1012 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1013 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1014 device_printf(sc->lge_dev, "gigabit link up\n"); 1015 if (!if_sendq_empty(ifp)) 1016 lge_start_locked(ifp); 1017 } 1018 } 1019 1020 if (sc->lge_timer != 0 && --sc->lge_timer == 0) 1021 lge_watchdog(sc); 1022 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1023 1024 return; 1025 } 1026 1027 static void 1028 lge_intr(void *arg) 1029 { 1030 struct lge_softc *sc; 1031 if_t ifp; 1032 u_int32_t status; 1033 1034 sc = arg; 1035 ifp = sc->lge_ifp; 1036 LGE_LOCK(sc); 1037 1038 /* Suppress unwanted interrupts */ 1039 if (!(if_getflags(ifp) & IFF_UP)) { 1040 lge_stop(sc); 1041 LGE_UNLOCK(sc); 1042 return; 1043 } 1044 1045 for (;;) { 1046 /* 1047 * Reading the ISR register clears all interrupts, and 1048 * clears the 'interrupts enabled' bit in the IMR 1049 * register. 1050 */ 1051 status = CSR_READ_4(sc, LGE_ISR); 1052 1053 if ((status & LGE_INTRS) == 0) 1054 break; 1055 1056 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1057 lge_txeof(sc); 1058 1059 if (status & LGE_ISR_RXDMA_DONE) 1060 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1061 1062 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1063 lge_rxeoc(sc); 1064 1065 if (status & LGE_ISR_PHY_INTR) { 1066 sc->lge_link = 0; 1067 callout_stop(&sc->lge_stat_callout); 1068 lge_tick(sc); 1069 } 1070 } 1071 1072 /* Re-enable interrupts. */ 1073 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1074 1075 if (!if_sendq_empty(ifp)) 1076 lge_start_locked(ifp); 1077 1078 LGE_UNLOCK(sc); 1079 return; 1080 } 1081 1082 /* 1083 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1084 * pointers to the fragment pointers. 1085 */ 1086 static int 1087 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1088 { 1089 struct lge_frag *f = NULL; 1090 struct lge_tx_desc *cur_tx; 1091 struct mbuf *m; 1092 int frag = 0, tot_len = 0; 1093 1094 /* 1095 * Start packing the mbufs in this chain into 1096 * the fragment pointers. Stop when we run out 1097 * of fragments or hit the end of the mbuf chain. 1098 */ 1099 m = m_head; 1100 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1101 frag = 0; 1102 1103 for (m = m_head; m != NULL; m = m->m_next) { 1104 if (m->m_len != 0) { 1105 tot_len += m->m_len; 1106 f = &cur_tx->lge_frags[frag]; 1107 f->lge_fraglen = m->m_len; 1108 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1109 f->lge_fragptr_hi = 0; 1110 frag++; 1111 } 1112 } 1113 1114 if (m != NULL) 1115 return(ENOBUFS); 1116 1117 cur_tx->lge_mbuf = m_head; 1118 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1119 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1120 1121 /* Queue for transmit */ 1122 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1123 1124 return(0); 1125 } 1126 1127 /* 1128 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1129 * to the mbuf data regions directly in the transmit lists. We also save a 1130 * copy of the pointers since the transmit list fragment pointers are 1131 * physical addresses. 1132 */ 1133 1134 static void 1135 lge_start(if_t ifp) 1136 { 1137 struct lge_softc *sc; 1138 1139 sc = if_getsoftc(ifp); 1140 LGE_LOCK(sc); 1141 lge_start_locked(ifp); 1142 LGE_UNLOCK(sc); 1143 } 1144 1145 static void 1146 lge_start_locked(if_t ifp) 1147 { 1148 struct lge_softc *sc; 1149 struct mbuf *m_head = NULL; 1150 u_int32_t idx; 1151 1152 sc = if_getsoftc(ifp); 1153 1154 if (!sc->lge_link) 1155 return; 1156 1157 idx = sc->lge_cdata.lge_tx_prod; 1158 1159 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 1160 return; 1161 1162 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1163 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1164 break; 1165 1166 m_head = if_dequeue(ifp); 1167 if (m_head == NULL) 1168 break; 1169 1170 if (lge_encap(sc, m_head, &idx)) { 1171 if_sendq_prepend(ifp, m_head); 1172 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1173 break; 1174 } 1175 1176 /* 1177 * If there's a BPF listener, bounce a copy of this frame 1178 * to him. 1179 */ 1180 BPF_MTAP(ifp, m_head); 1181 } 1182 1183 sc->lge_cdata.lge_tx_prod = idx; 1184 1185 /* 1186 * Set a timeout in case the chip goes out to lunch. 1187 */ 1188 sc->lge_timer = 5; 1189 1190 return; 1191 } 1192 1193 static void 1194 lge_init(void *xsc) 1195 { 1196 struct lge_softc *sc = xsc; 1197 1198 LGE_LOCK(sc); 1199 lge_init_locked(sc); 1200 LGE_UNLOCK(sc); 1201 } 1202 1203 static void 1204 lge_init_locked(struct lge_softc *sc) 1205 { 1206 if_t ifp = sc->lge_ifp; 1207 1208 LGE_LOCK_ASSERT(sc); 1209 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1210 return; 1211 1212 /* 1213 * Cancel pending I/O and free all RX/TX buffers. 1214 */ 1215 lge_stop(sc); 1216 lge_reset(sc); 1217 1218 /* Set MAC address */ 1219 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[0])); 1220 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[4])); 1221 1222 /* Init circular RX list. */ 1223 if (lge_list_rx_init(sc) == ENOBUFS) { 1224 device_printf(sc->lge_dev, "initialization failed: no " 1225 "memory for rx buffers\n"); 1226 lge_stop(sc); 1227 return; 1228 } 1229 1230 /* 1231 * Init tx descriptors. 1232 */ 1233 lge_list_tx_init(sc); 1234 1235 /* Set initial value for MODE1 register. */ 1236 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1237 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1238 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1239 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1240 1241 /* If we want promiscuous mode, set the allframes bit. */ 1242 if (if_getflags(ifp) & IFF_PROMISC) { 1243 CSR_WRITE_4(sc, LGE_MODE1, 1244 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1245 } else { 1246 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1247 } 1248 1249 /* 1250 * Set the capture broadcast bit to capture broadcast frames. 1251 */ 1252 if (if_getflags(ifp) & IFF_BROADCAST) { 1253 CSR_WRITE_4(sc, LGE_MODE1, 1254 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1255 } else { 1256 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1257 } 1258 1259 /* Packet padding workaround? */ 1260 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1261 1262 /* No error frames */ 1263 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1264 1265 /* Receive large frames */ 1266 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1267 1268 /* Workaround: disable RX/TX flow control */ 1269 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1270 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1271 1272 /* Make sure to strip CRC from received frames */ 1273 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1274 1275 /* Turn off magic packet mode */ 1276 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1277 1278 /* Turn off all VLAN stuff */ 1279 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1280 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1281 1282 /* Workarond: FIFO overflow */ 1283 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1284 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1285 1286 /* 1287 * Load the multicast filter. 1288 */ 1289 lge_setmulti(sc); 1290 1291 /* 1292 * Enable hardware checksum validation for all received IPv4 1293 * packets, do not reject packets with bad checksums. 1294 */ 1295 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1296 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1297 LGE_MODE2_RX_ERRCSUM); 1298 1299 /* 1300 * Enable the delivery of PHY interrupts based on 1301 * link/speed/duplex status chalges. 1302 */ 1303 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1304 1305 /* Enable receiver and transmitter. */ 1306 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1308 1309 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1311 1312 /* 1313 * Enable interrupts. 1314 */ 1315 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1316 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1317 1318 lge_ifmedia_upd_locked(ifp); 1319 1320 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1321 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1322 1323 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1324 1325 return; 1326 } 1327 1328 /* 1329 * Set media options. 1330 */ 1331 static int 1332 lge_ifmedia_upd(if_t ifp) 1333 { 1334 struct lge_softc *sc; 1335 1336 sc = if_getsoftc(ifp); 1337 LGE_LOCK(sc); 1338 lge_ifmedia_upd_locked(ifp); 1339 LGE_UNLOCK(sc); 1340 1341 return(0); 1342 } 1343 1344 static void 1345 lge_ifmedia_upd_locked(if_t ifp) 1346 { 1347 struct lge_softc *sc; 1348 struct mii_data *mii; 1349 struct mii_softc *miisc; 1350 1351 sc = if_getsoftc(ifp); 1352 1353 LGE_LOCK_ASSERT(sc); 1354 mii = device_get_softc(sc->lge_miibus); 1355 sc->lge_link = 0; 1356 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1357 PHY_RESET(miisc); 1358 mii_mediachg(mii); 1359 } 1360 1361 /* 1362 * Report current media status. 1363 */ 1364 static void 1365 lge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1366 { 1367 struct lge_softc *sc; 1368 struct mii_data *mii; 1369 1370 sc = if_getsoftc(ifp); 1371 1372 LGE_LOCK(sc); 1373 mii = device_get_softc(sc->lge_miibus); 1374 mii_pollstat(mii); 1375 ifmr->ifm_active = mii->mii_media_active; 1376 ifmr->ifm_status = mii->mii_media_status; 1377 LGE_UNLOCK(sc); 1378 1379 return; 1380 } 1381 1382 static int 1383 lge_ioctl(if_t ifp, u_long command, caddr_t data) 1384 { 1385 struct lge_softc *sc = if_getsoftc(ifp); 1386 struct ifreq *ifr = (struct ifreq *) data; 1387 struct mii_data *mii; 1388 int error = 0; 1389 1390 switch(command) { 1391 case SIOCSIFMTU: 1392 LGE_LOCK(sc); 1393 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1394 error = EINVAL; 1395 else 1396 if_setmtu(ifp, ifr->ifr_mtu); 1397 LGE_UNLOCK(sc); 1398 break; 1399 case SIOCSIFFLAGS: 1400 LGE_LOCK(sc); 1401 if (if_getflags(ifp) & IFF_UP) { 1402 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 1403 if_getflags(ifp) & IFF_PROMISC && 1404 !(sc->lge_if_flags & IFF_PROMISC)) { 1405 CSR_WRITE_4(sc, LGE_MODE1, 1406 LGE_MODE1_SETRST_CTL1| 1407 LGE_MODE1_RX_PROMISC); 1408 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 1409 !(if_getflags(ifp) & IFF_PROMISC) && 1410 sc->lge_if_flags & IFF_PROMISC) { 1411 CSR_WRITE_4(sc, LGE_MODE1, 1412 LGE_MODE1_RX_PROMISC); 1413 } else { 1414 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1415 lge_init_locked(sc); 1416 } 1417 } else { 1418 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1419 lge_stop(sc); 1420 } 1421 sc->lge_if_flags = if_getflags(ifp); 1422 LGE_UNLOCK(sc); 1423 error = 0; 1424 break; 1425 case SIOCADDMULTI: 1426 case SIOCDELMULTI: 1427 LGE_LOCK(sc); 1428 lge_setmulti(sc); 1429 LGE_UNLOCK(sc); 1430 error = 0; 1431 break; 1432 case SIOCGIFMEDIA: 1433 case SIOCSIFMEDIA: 1434 mii = device_get_softc(sc->lge_miibus); 1435 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1436 break; 1437 default: 1438 error = ether_ioctl(ifp, command, data); 1439 break; 1440 } 1441 1442 return(error); 1443 } 1444 1445 static void 1446 lge_watchdog(struct lge_softc *sc) 1447 { 1448 if_t ifp; 1449 1450 LGE_LOCK_ASSERT(sc); 1451 ifp = sc->lge_ifp; 1452 1453 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1454 if_printf(ifp, "watchdog timeout\n"); 1455 1456 lge_stop(sc); 1457 lge_reset(sc); 1458 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1459 lge_init_locked(sc); 1460 1461 if (!if_sendq_empty(ifp)) 1462 lge_start_locked(ifp); 1463 } 1464 1465 /* 1466 * Stop the adapter and free any mbufs allocated to the 1467 * RX and TX lists. 1468 */ 1469 static void 1470 lge_stop(struct lge_softc *sc) 1471 { 1472 int i; 1473 if_t ifp; 1474 1475 LGE_LOCK_ASSERT(sc); 1476 ifp = sc->lge_ifp; 1477 sc->lge_timer = 0; 1478 callout_stop(&sc->lge_stat_callout); 1479 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1480 1481 /* Disable receiver and transmitter. */ 1482 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1483 sc->lge_link = 0; 1484 1485 /* 1486 * Free data in the RX lists. 1487 */ 1488 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1489 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1490 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1491 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1492 } 1493 } 1494 bzero((char *)&sc->lge_ldata->lge_rx_list, 1495 sizeof(sc->lge_ldata->lge_rx_list)); 1496 1497 /* 1498 * Free the TX list buffers. 1499 */ 1500 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1501 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1502 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1503 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1504 } 1505 } 1506 1507 bzero((char *)&sc->lge_ldata->lge_tx_list, 1508 sizeof(sc->lge_ldata->lge_tx_list)); 1509 1510 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1511 1512 return; 1513 } 1514 1515 /* 1516 * Stop all chip I/O so that the kernel's probe routines don't 1517 * get confused by errant DMAs when rebooting. 1518 */ 1519 static int 1520 lge_shutdown(device_t dev) 1521 { 1522 struct lge_softc *sc; 1523 1524 sc = device_get_softc(dev); 1525 1526 LGE_LOCK(sc); 1527 lge_reset(sc); 1528 lge_stop(sc); 1529 LGE_UNLOCK(sc); 1530 1531 return (0); 1532 } 1533