xref: /freebsd/sys/dev/lge/if_lge.c (revision d93a896ef95946b0bf1219866fcb324b78543444)
1 /*-
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2000, 2001
4  *	Bill Paul <william.paul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36 
37 /*
38  * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39  * documentation not available, but ask me nicely.
40  *
41  * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42  * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43  * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44  * are three supported methods for data transfer between host and
45  * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46  * Propulsion Technology (tm) DMA. The latter mechanism is a form
47  * of double buffer DMA where the packet data is copied to a
48  * pre-allocated DMA buffer who's physical address has been loaded
49  * into a table at device initialization time. The rationale is that
50  * the virtual to physical address translation needed for normal
51  * scatter/gather DMA is more expensive than the data copy needed
52  * for double buffering. This may be true in Windows NT and the like,
53  * but it isn't true for us, at least on the x86 arch. This driver
54  * uses the scatter/gather I/O method for both TX and RX.
55  *
56  * The LXT1001 only supports TCP/IP checksum offload on receive.
57  * Also, the VLAN tagging is done using a 16-entry table which allows
58  * the chip to perform hardware filtering based on VLAN tags. Sadly,
59  * our vlan support doesn't currently play well with this kind of
60  * hardware support.
61  *
62  * Special thanks to:
63  * - Jeff James at Intel, for arranging to have the LXT1001 manual
64  *   released (at long last)
65  * - Beny Chen at D-Link, for actually sending it to me
66  * - Brad Short and Keith Alexis at SMC, for sending me sample
67  *   SMC9462SX and SMC9462TX adapters for testing
68  * - Paul Saab at Y!, for not killing me (though it remains to be seen
69  *   if in fact he did me much of a favor)
70  */
71 
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
75 #include <sys/mbuf.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
80 
81 #include <net/if.h>
82 #include <net/if_var.h>
83 #include <net/if_arp.h>
84 #include <net/ethernet.h>
85 #include <net/if_dl.h>
86 #include <net/if_media.h>
87 #include <net/if_types.h>
88 
89 #include <net/bpf.h>
90 
91 #include <vm/vm.h>              /* for vtophys */
92 #include <vm/pmap.h>            /* for vtophys */
93 #include <machine/bus.h>
94 #include <machine/resource.h>
95 #include <sys/bus.h>
96 #include <sys/rman.h>
97 
98 #include <dev/mii/mii.h>
99 #include <dev/mii/miivar.h>
100 
101 #include <dev/pci/pcireg.h>
102 #include <dev/pci/pcivar.h>
103 
104 #define LGE_USEIOSPACE
105 
106 #include <dev/lge/if_lgereg.h>
107 
108 /* "device miibus" required.  See GENERIC if you get errors here. */
109 #include "miibus_if.h"
110 
111 /*
112  * Various supported device vendors/types and their names.
113  */
114 static const struct lge_type lge_devs[] = {
115 	{ LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
116 	{ 0, 0, NULL }
117 };
118 
119 static int lge_probe(device_t);
120 static int lge_attach(device_t);
121 static int lge_detach(device_t);
122 
123 static int lge_alloc_jumbo_mem(struct lge_softc *);
124 static void lge_free_jumbo_mem(struct lge_softc *);
125 static void *lge_jalloc(struct lge_softc *);
126 static void lge_jfree(struct mbuf *, void *, void *);
127 
128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
130 static void lge_rxeof(struct lge_softc *, int);
131 static void lge_rxeoc(struct lge_softc *);
132 static void lge_txeof(struct lge_softc *);
133 static void lge_intr(void *);
134 static void lge_tick(void *);
135 static void lge_start(struct ifnet *);
136 static void lge_start_locked(struct ifnet *);
137 static int lge_ioctl(struct ifnet *, u_long, caddr_t);
138 static void lge_init(void *);
139 static void lge_init_locked(struct lge_softc *);
140 static void lge_stop(struct lge_softc *);
141 static void lge_watchdog(struct lge_softc *);
142 static int lge_shutdown(device_t);
143 static int lge_ifmedia_upd(struct ifnet *);
144 static void lge_ifmedia_upd_locked(struct ifnet *);
145 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
146 
147 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
148 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
149 
150 static int lge_miibus_readreg(device_t, int, int);
151 static int lge_miibus_writereg(device_t, int, int, int);
152 static void lge_miibus_statchg(device_t);
153 
154 static void lge_setmulti(struct lge_softc *);
155 static void lge_reset(struct lge_softc *);
156 static int lge_list_rx_init(struct lge_softc *);
157 static int lge_list_tx_init(struct lge_softc *);
158 
159 #ifdef LGE_USEIOSPACE
160 #define LGE_RES			SYS_RES_IOPORT
161 #define LGE_RID			LGE_PCI_LOIO
162 #else
163 #define LGE_RES			SYS_RES_MEMORY
164 #define LGE_RID			LGE_PCI_LOMEM
165 #endif
166 
167 static device_method_t lge_methods[] = {
168 	/* Device interface */
169 	DEVMETHOD(device_probe,		lge_probe),
170 	DEVMETHOD(device_attach,	lge_attach),
171 	DEVMETHOD(device_detach,	lge_detach),
172 	DEVMETHOD(device_shutdown,	lge_shutdown),
173 
174 	/* MII interface */
175 	DEVMETHOD(miibus_readreg,	lge_miibus_readreg),
176 	DEVMETHOD(miibus_writereg,	lge_miibus_writereg),
177 	DEVMETHOD(miibus_statchg,	lge_miibus_statchg),
178 
179 	DEVMETHOD_END
180 };
181 
182 static driver_t lge_driver = {
183 	"lge",
184 	lge_methods,
185 	sizeof(struct lge_softc)
186 };
187 
188 static devclass_t lge_devclass;
189 
190 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
191 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
192 MODULE_DEPEND(lge, pci, 1, 1, 1);
193 MODULE_DEPEND(lge, ether, 1, 1, 1);
194 MODULE_DEPEND(lge, miibus, 1, 1, 1);
195 
196 #define LGE_SETBIT(sc, reg, x)				\
197 	CSR_WRITE_4(sc, reg,				\
198 		CSR_READ_4(sc, reg) | (x))
199 
200 #define LGE_CLRBIT(sc, reg, x)				\
201 	CSR_WRITE_4(sc, reg,				\
202 		CSR_READ_4(sc, reg) & ~(x))
203 
204 #define SIO_SET(x)					\
205 	CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
206 
207 #define SIO_CLR(x)					\
208 	CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
209 
210 /*
211  * Read a word of data stored in the EEPROM at address 'addr.'
212  */
213 static void
214 lge_eeprom_getword(sc, addr, dest)
215 	struct lge_softc	*sc;
216 	int			addr;
217 	u_int16_t		*dest;
218 {
219 	int			i;
220 	u_int32_t		val;
221 
222 	CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
223 	    LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
224 
225 	for (i = 0; i < LGE_TIMEOUT; i++)
226 		if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
227 			break;
228 
229 	if (i == LGE_TIMEOUT) {
230 		device_printf(sc->lge_dev, "EEPROM read timed out\n");
231 		return;
232 	}
233 
234 	val = CSR_READ_4(sc, LGE_EEDATA);
235 
236 	if (addr & 1)
237 		*dest = (val >> 16) & 0xFFFF;
238 	else
239 		*dest = val & 0xFFFF;
240 
241 	return;
242 }
243 
244 /*
245  * Read a sequence of words from the EEPROM.
246  */
247 static void
248 lge_read_eeprom(sc, dest, off, cnt, swap)
249 	struct lge_softc	*sc;
250 	caddr_t			dest;
251 	int			off;
252 	int			cnt;
253 	int			swap;
254 {
255 	int			i;
256 	u_int16_t		word = 0, *ptr;
257 
258 	for (i = 0; i < cnt; i++) {
259 		lge_eeprom_getword(sc, off + i, &word);
260 		ptr = (u_int16_t *)(dest + (i * 2));
261 		if (swap)
262 			*ptr = ntohs(word);
263 		else
264 			*ptr = word;
265 	}
266 
267 	return;
268 }
269 
270 static int
271 lge_miibus_readreg(dev, phy, reg)
272 	device_t		dev;
273 	int			phy, reg;
274 {
275 	struct lge_softc	*sc;
276 	int			i;
277 
278 	sc = device_get_softc(dev);
279 
280 	/*
281 	 * If we have a non-PCS PHY, pretend that the internal
282 	 * autoneg stuff at PHY address 0 isn't there so that
283 	 * the miibus code will find only the GMII PHY.
284 	 */
285 	if (sc->lge_pcs == 0 && phy == 0)
286 		return(0);
287 
288 	CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
289 
290 	for (i = 0; i < LGE_TIMEOUT; i++)
291 		if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
292 			break;
293 
294 	if (i == LGE_TIMEOUT) {
295 		device_printf(sc->lge_dev, "PHY read timed out\n");
296 		return(0);
297 	}
298 
299 	return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
300 }
301 
302 static int
303 lge_miibus_writereg(dev, phy, reg, data)
304 	device_t		dev;
305 	int			phy, reg, data;
306 {
307 	struct lge_softc	*sc;
308 	int			i;
309 
310 	sc = device_get_softc(dev);
311 
312 	CSR_WRITE_4(sc, LGE_GMIICTL,
313 	    (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
314 
315 	for (i = 0; i < LGE_TIMEOUT; i++)
316 		if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
317 			break;
318 
319 	if (i == LGE_TIMEOUT) {
320 		device_printf(sc->lge_dev, "PHY write timed out\n");
321 		return(0);
322 	}
323 
324 	return(0);
325 }
326 
327 static void
328 lge_miibus_statchg(dev)
329 	device_t		dev;
330 {
331 	struct lge_softc	*sc;
332 	struct mii_data		*mii;
333 
334 	sc = device_get_softc(dev);
335 	mii = device_get_softc(sc->lge_miibus);
336 
337 	LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
338 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
339 	case IFM_1000_T:
340 	case IFM_1000_SX:
341 		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
342 		break;
343 	case IFM_100_TX:
344 		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
345 		break;
346 	case IFM_10_T:
347 		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
348 		break;
349 	default:
350 		/*
351 		 * Choose something, even if it's wrong. Clearing
352 		 * all the bits will hose autoneg on the internal
353 		 * PHY.
354 		 */
355 		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
356 		break;
357 	}
358 
359 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
360 		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
361 	} else {
362 		LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
363 	}
364 
365 	return;
366 }
367 
368 static void
369 lge_setmulti(sc)
370 	struct lge_softc	*sc;
371 {
372 	struct ifnet		*ifp;
373 	struct ifmultiaddr	*ifma;
374 	u_int32_t		h = 0, hashes[2] = { 0, 0 };
375 
376 	ifp = sc->lge_ifp;
377 	LGE_LOCK_ASSERT(sc);
378 
379 	/* Make sure multicast hash table is enabled. */
380 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
381 
382 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
383 		CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
384 		CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
385 		return;
386 	}
387 
388 	/* first, zot all the existing hash bits */
389 	CSR_WRITE_4(sc, LGE_MAR0, 0);
390 	CSR_WRITE_4(sc, LGE_MAR1, 0);
391 
392 	/* now program new ones */
393 	if_maddr_rlock(ifp);
394 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
395 		if (ifma->ifma_addr->sa_family != AF_LINK)
396 			continue;
397 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
398 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
399 		if (h < 32)
400 			hashes[0] |= (1 << h);
401 		else
402 			hashes[1] |= (1 << (h - 32));
403 	}
404 	if_maddr_runlock(ifp);
405 
406 	CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
407 	CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
408 
409 	return;
410 }
411 
412 static void
413 lge_reset(sc)
414 	struct lge_softc	*sc;
415 {
416 	int			i;
417 
418 	LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
419 
420 	for (i = 0; i < LGE_TIMEOUT; i++) {
421 		if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
422 			break;
423 	}
424 
425 	if (i == LGE_TIMEOUT)
426 		device_printf(sc->lge_dev, "reset never completed\n");
427 
428 	/* Wait a little while for the chip to get its brains in order. */
429 	DELAY(1000);
430 
431         return;
432 }
433 
434 /*
435  * Probe for a Level 1 chip. Check the PCI vendor and device
436  * IDs against our list and return a device name if we find a match.
437  */
438 static int
439 lge_probe(dev)
440 	device_t		dev;
441 {
442 	const struct lge_type	*t;
443 
444 	t = lge_devs;
445 
446 	while(t->lge_name != NULL) {
447 		if ((pci_get_vendor(dev) == t->lge_vid) &&
448 		    (pci_get_device(dev) == t->lge_did)) {
449 			device_set_desc(dev, t->lge_name);
450 			return(BUS_PROBE_DEFAULT);
451 		}
452 		t++;
453 	}
454 
455 	return(ENXIO);
456 }
457 
458 /*
459  * Attach the interface. Allocate softc structures, do ifmedia
460  * setup and ethernet/BPF attach.
461  */
462 static int
463 lge_attach(dev)
464 	device_t		dev;
465 {
466 	u_char			eaddr[ETHER_ADDR_LEN];
467 	struct lge_softc	*sc;
468 	struct ifnet		*ifp = NULL;
469 	int			error = 0, rid;
470 
471 	sc = device_get_softc(dev);
472 	sc->lge_dev = dev;
473 
474 	mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
475 	    MTX_DEF);
476 	callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
477 
478 	/*
479 	 * Map control/status registers.
480 	 */
481 	pci_enable_busmaster(dev);
482 
483 	rid = LGE_RID;
484 	sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
485 
486 	if (sc->lge_res == NULL) {
487 		device_printf(dev, "couldn't map ports/memory\n");
488 		error = ENXIO;
489 		goto fail;
490 	}
491 
492 	sc->lge_btag = rman_get_bustag(sc->lge_res);
493 	sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
494 
495 	/* Allocate interrupt */
496 	rid = 0;
497 	sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
498 	    RF_SHAREABLE | RF_ACTIVE);
499 
500 	if (sc->lge_irq == NULL) {
501 		device_printf(dev, "couldn't map interrupt\n");
502 		error = ENXIO;
503 		goto fail;
504 	}
505 
506 	/* Reset the adapter. */
507 	lge_reset(sc);
508 
509 	/*
510 	 * Get station address from the EEPROM.
511 	 */
512 	lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
513 	lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
514 	lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
515 
516 	sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
517 	    M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
518 
519 	if (sc->lge_ldata == NULL) {
520 		device_printf(dev, "no memory for list buffers!\n");
521 		error = ENXIO;
522 		goto fail;
523 	}
524 
525 	/* Try to allocate memory for jumbo buffers. */
526 	if (lge_alloc_jumbo_mem(sc)) {
527 		device_printf(dev, "jumbo buffer allocation failed\n");
528 		error = ENXIO;
529 		goto fail;
530 	}
531 
532 	ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
533 	if (ifp == NULL) {
534 		device_printf(dev, "can not if_alloc()\n");
535 		error = ENOSPC;
536 		goto fail;
537 	}
538 	ifp->if_softc = sc;
539 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
540 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
541 	ifp->if_ioctl = lge_ioctl;
542 	ifp->if_start = lge_start;
543 	ifp->if_init = lge_init;
544 	ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
545 	ifp->if_capabilities = IFCAP_RXCSUM;
546 	ifp->if_capenable = ifp->if_capabilities;
547 
548 	if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
549 		sc->lge_pcs = 1;
550 	else
551 		sc->lge_pcs = 0;
552 
553 	/*
554 	 * Do MII setup.
555 	 */
556 	error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
557 	    lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
558 	if (error != 0) {
559 		device_printf(dev, "attaching PHYs failed\n");
560 		goto fail;
561 	}
562 
563 	/*
564 	 * Call MI attach routine.
565 	 */
566 	ether_ifattach(ifp, eaddr);
567 
568 	error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
569 	    NULL, lge_intr, sc, &sc->lge_intrhand);
570 
571 	if (error) {
572 		ether_ifdetach(ifp);
573 		device_printf(dev, "couldn't set up irq\n");
574 		goto fail;
575 	}
576 	return (0);
577 
578 fail:
579 	lge_free_jumbo_mem(sc);
580 	if (sc->lge_ldata)
581 		contigfree(sc->lge_ldata,
582 		    sizeof(struct lge_list_data), M_DEVBUF);
583 	if (ifp)
584 		if_free(ifp);
585 	if (sc->lge_irq)
586 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
587 	if (sc->lge_res)
588 		bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
589 	mtx_destroy(&sc->lge_mtx);
590 	return(error);
591 }
592 
593 static int
594 lge_detach(dev)
595 	device_t		dev;
596 {
597 	struct lge_softc	*sc;
598 	struct ifnet		*ifp;
599 
600 	sc = device_get_softc(dev);
601 	ifp = sc->lge_ifp;
602 
603 	LGE_LOCK(sc);
604 	lge_reset(sc);
605 	lge_stop(sc);
606 	LGE_UNLOCK(sc);
607 	callout_drain(&sc->lge_stat_callout);
608 	ether_ifdetach(ifp);
609 
610 	bus_generic_detach(dev);
611 	device_delete_child(dev, sc->lge_miibus);
612 
613 	bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
614 	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
615 	bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
616 
617 	contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
618 	if_free(ifp);
619 	lge_free_jumbo_mem(sc);
620 	mtx_destroy(&sc->lge_mtx);
621 
622 	return(0);
623 }
624 
625 /*
626  * Initialize the transmit descriptors.
627  */
628 static int
629 lge_list_tx_init(sc)
630 	struct lge_softc	*sc;
631 {
632 	struct lge_list_data	*ld;
633 	struct lge_ring_data	*cd;
634 	int			i;
635 
636 	cd = &sc->lge_cdata;
637 	ld = sc->lge_ldata;
638 	for (i = 0; i < LGE_TX_LIST_CNT; i++) {
639 		ld->lge_tx_list[i].lge_mbuf = NULL;
640 		ld->lge_tx_list[i].lge_ctl = 0;
641 	}
642 
643 	cd->lge_tx_prod = cd->lge_tx_cons = 0;
644 
645 	return(0);
646 }
647 
648 
649 /*
650  * Initialize the RX descriptors and allocate mbufs for them. Note that
651  * we arralge the descriptors in a closed ring, so that the last descriptor
652  * points back to the first.
653  */
654 static int
655 lge_list_rx_init(sc)
656 	struct lge_softc	*sc;
657 {
658 	struct lge_list_data	*ld;
659 	struct lge_ring_data	*cd;
660 	int			i;
661 
662 	ld = sc->lge_ldata;
663 	cd = &sc->lge_cdata;
664 
665 	cd->lge_rx_prod = cd->lge_rx_cons = 0;
666 
667 	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
668 
669 	for (i = 0; i < LGE_RX_LIST_CNT; i++) {
670 		if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
671 			break;
672 		if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
673 			return(ENOBUFS);
674 	}
675 
676 	/* Clear possible 'rx command queue empty' interrupt. */
677 	CSR_READ_4(sc, LGE_ISR);
678 
679 	return(0);
680 }
681 
682 /*
683  * Initialize an RX descriptor and attach an MBUF cluster.
684  */
685 static int
686 lge_newbuf(sc, c, m)
687 	struct lge_softc	*sc;
688 	struct lge_rx_desc	*c;
689 	struct mbuf		*m;
690 {
691 	struct mbuf		*m_new = NULL;
692 	caddr_t			*buf = NULL;
693 
694 	if (m == NULL) {
695 		MGETHDR(m_new, M_NOWAIT, MT_DATA);
696 		if (m_new == NULL) {
697 			device_printf(sc->lge_dev, "no memory for rx list "
698 			    "-- packet dropped!\n");
699 			return(ENOBUFS);
700 		}
701 
702 		/* Allocate the jumbo buffer */
703 		buf = lge_jalloc(sc);
704 		if (buf == NULL) {
705 #ifdef LGE_VERBOSE
706 			device_printf(sc->lge_dev, "jumbo allocation failed "
707 			    "-- packet dropped!\n");
708 #endif
709 			m_freem(m_new);
710 			return(ENOBUFS);
711 		}
712 		/* Attach the buffer to the mbuf */
713 		m_new->m_data = (void *)buf;
714 		m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
715 		MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
716 		    buf, (struct lge_softc *)sc, 0, EXT_NET_DRV);
717 	} else {
718 		m_new = m;
719 		m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
720 		m_new->m_data = m_new->m_ext.ext_buf;
721 	}
722 
723 	/*
724 	 * Adjust alignment so packet payload begins on a
725 	 * longword boundary. Mandatory for Alpha, useful on
726 	 * x86 too.
727 	*/
728 	m_adj(m_new, ETHER_ALIGN);
729 
730 	c->lge_mbuf = m_new;
731 	c->lge_fragptr_hi = 0;
732 	c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
733 	c->lge_fraglen = m_new->m_len;
734 	c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
735 	c->lge_sts = 0;
736 
737 	/*
738 	 * Put this buffer in the RX command FIFO. To do this,
739 	 * we just write the physical address of the descriptor
740 	 * into the RX descriptor address registers. Note that
741 	 * there are two registers, one high DWORD and one low
742 	 * DWORD, which lets us specify a 64-bit address if
743 	 * desired. We only use a 32-bit address for now.
744 	 * Writing to the low DWORD register is what actually
745 	 * causes the command to be issued, so we do that
746 	 * last.
747 	 */
748 	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
749 	LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
750 
751 	return(0);
752 }
753 
754 static int
755 lge_alloc_jumbo_mem(sc)
756 	struct lge_softc	*sc;
757 {
758 	caddr_t			ptr;
759 	int			i;
760 	struct lge_jpool_entry   *entry;
761 
762 	/* Grab a big chunk o' storage. */
763 	sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
764 	    M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
765 
766 	if (sc->lge_cdata.lge_jumbo_buf == NULL) {
767 		device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
768 		return(ENOBUFS);
769 	}
770 
771 	SLIST_INIT(&sc->lge_jfree_listhead);
772 	SLIST_INIT(&sc->lge_jinuse_listhead);
773 
774 	/*
775 	 * Now divide it up into 9K pieces and save the addresses
776 	 * in an array.
777 	 */
778 	ptr = sc->lge_cdata.lge_jumbo_buf;
779 	for (i = 0; i < LGE_JSLOTS; i++) {
780 		sc->lge_cdata.lge_jslots[i] = ptr;
781 		ptr += LGE_JLEN;
782 		entry = malloc(sizeof(struct lge_jpool_entry),
783 		    M_DEVBUF, M_NOWAIT);
784 		if (entry == NULL) {
785 			device_printf(sc->lge_dev, "no memory for jumbo "
786 			    "buffer queue!\n");
787 			return(ENOBUFS);
788 		}
789 		entry->slot = i;
790 		SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
791 		    entry, jpool_entries);
792 	}
793 
794 	return(0);
795 }
796 
797 static void
798 lge_free_jumbo_mem(sc)
799 	struct lge_softc	*sc;
800 {
801 	struct lge_jpool_entry	*entry;
802 
803 	if (sc->lge_cdata.lge_jumbo_buf == NULL)
804 		return;
805 
806 	while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
807 		device_printf(sc->lge_dev,
808 		    "asked to free buffer that is in use!\n");
809 		SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
810 		SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
811 		    jpool_entries);
812 	}
813 	while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
814 		entry = SLIST_FIRST(&sc->lge_jfree_listhead);
815 		SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
816 		free(entry, M_DEVBUF);
817 	}
818 
819 	contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
820 
821 	return;
822 }
823 
824 /*
825  * Allocate a jumbo buffer.
826  */
827 static void *
828 lge_jalloc(sc)
829 	struct lge_softc	*sc;
830 {
831 	struct lge_jpool_entry   *entry;
832 
833 	entry = SLIST_FIRST(&sc->lge_jfree_listhead);
834 
835 	if (entry == NULL) {
836 #ifdef LGE_VERBOSE
837 		device_printf(sc->lge_dev, "no free jumbo buffers\n");
838 #endif
839 		return(NULL);
840 	}
841 
842 	SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
843 	SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
844 	return(sc->lge_cdata.lge_jslots[entry->slot]);
845 }
846 
847 /*
848  * Release a jumbo buffer.
849  */
850 static void
851 lge_jfree(struct mbuf *m, void *buf, void *args)
852 {
853 	struct lge_softc	*sc;
854 	int		        i;
855 	struct lge_jpool_entry   *entry;
856 
857 	/* Extract the softc struct pointer. */
858 	sc = args;
859 
860 	if (sc == NULL)
861 		panic("lge_jfree: can't find softc pointer!");
862 
863 	/* calculate the slot this buffer belongs to */
864 	i = ((vm_offset_t)buf
865 	     - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
866 
867 	if ((i < 0) || (i >= LGE_JSLOTS))
868 		panic("lge_jfree: asked to free buffer that we don't manage!");
869 
870 	entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
871 	if (entry == NULL)
872 		panic("lge_jfree: buffer not in use!");
873 	entry->slot = i;
874 	SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
875 	SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
876 }
877 
878 /*
879  * A frame has been uploaded: pass the resulting mbuf chain up to
880  * the higher level protocols.
881  */
882 static void
883 lge_rxeof(sc, cnt)
884 	struct lge_softc	*sc;
885 	int			cnt;
886 {
887         struct mbuf		*m;
888         struct ifnet		*ifp;
889 	struct lge_rx_desc	*cur_rx;
890 	int			c, i, total_len = 0;
891 	u_int32_t		rxsts, rxctl;
892 
893 	ifp = sc->lge_ifp;
894 
895 	/* Find out how many frames were processed. */
896 	c = cnt;
897 	i = sc->lge_cdata.lge_rx_cons;
898 
899 	/* Suck them in. */
900 	while(c) {
901 		struct mbuf		*m0 = NULL;
902 
903 		cur_rx = &sc->lge_ldata->lge_rx_list[i];
904 		rxctl = cur_rx->lge_ctl;
905 		rxsts = cur_rx->lge_sts;
906 		m = cur_rx->lge_mbuf;
907 		cur_rx->lge_mbuf = NULL;
908 		total_len = LGE_RXBYTES(cur_rx);
909 		LGE_INC(i, LGE_RX_LIST_CNT);
910 		c--;
911 
912 		/*
913 		 * If an error occurs, update stats, clear the
914 		 * status word and leave the mbuf cluster in place:
915 		 * it should simply get re-used next time this descriptor
916 	 	 * comes up in the ring.
917 		 */
918 		if (rxctl & LGE_RXCTL_ERRMASK) {
919 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
920 			lge_newbuf(sc, &LGE_RXTAIL(sc), m);
921 			continue;
922 		}
923 
924 		if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
925 			m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
926 			    ifp, NULL);
927 			lge_newbuf(sc, &LGE_RXTAIL(sc), m);
928 			if (m0 == NULL) {
929 				device_printf(sc->lge_dev, "no receive buffers "
930 				    "available -- packet dropped!\n");
931 				if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
932 				continue;
933 			}
934 			m = m0;
935 		} else {
936 			m->m_pkthdr.rcvif = ifp;
937 			m->m_pkthdr.len = m->m_len = total_len;
938 		}
939 
940 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
941 
942 		/* Do IP checksum checking. */
943 		if (rxsts & LGE_RXSTS_ISIP)
944 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
945 		if (!(rxsts & LGE_RXSTS_IPCSUMERR))
946 			m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
947 		if ((rxsts & LGE_RXSTS_ISTCP &&
948 		    !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
949 		    (rxsts & LGE_RXSTS_ISUDP &&
950 		    !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
951 			m->m_pkthdr.csum_flags |=
952 			    CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
953 			m->m_pkthdr.csum_data = 0xffff;
954 		}
955 
956 		LGE_UNLOCK(sc);
957 		(*ifp->if_input)(ifp, m);
958 		LGE_LOCK(sc);
959 	}
960 
961 	sc->lge_cdata.lge_rx_cons = i;
962 
963 	return;
964 }
965 
966 static void
967 lge_rxeoc(sc)
968 	struct lge_softc	*sc;
969 {
970 	struct ifnet		*ifp;
971 
972 	ifp = sc->lge_ifp;
973 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
974 	lge_init_locked(sc);
975 	return;
976 }
977 
978 /*
979  * A frame was downloaded to the chip. It's safe for us to clean up
980  * the list buffers.
981  */
982 
983 static void
984 lge_txeof(sc)
985 	struct lge_softc	*sc;
986 {
987 	struct lge_tx_desc	*cur_tx = NULL;
988 	struct ifnet		*ifp;
989 	u_int32_t		idx, txdone;
990 
991 	ifp = sc->lge_ifp;
992 
993 	/* Clear the timeout timer. */
994 	sc->lge_timer = 0;
995 
996 	/*
997 	 * Go through our tx list and free mbufs for those
998 	 * frames that have been transmitted.
999 	 */
1000 	idx = sc->lge_cdata.lge_tx_cons;
1001 	txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1002 
1003 	while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1004 		cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1005 
1006 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1007 		if (cur_tx->lge_mbuf != NULL) {
1008 			m_freem(cur_tx->lge_mbuf);
1009 			cur_tx->lge_mbuf = NULL;
1010 		}
1011 		cur_tx->lge_ctl = 0;
1012 
1013 		txdone--;
1014 		LGE_INC(idx, LGE_TX_LIST_CNT);
1015 		sc->lge_timer = 0;
1016 	}
1017 
1018 	sc->lge_cdata.lge_tx_cons = idx;
1019 
1020 	if (cur_tx != NULL)
1021 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1022 
1023 	return;
1024 }
1025 
1026 static void
1027 lge_tick(xsc)
1028 	void			*xsc;
1029 {
1030 	struct lge_softc	*sc;
1031 	struct mii_data		*mii;
1032 	struct ifnet		*ifp;
1033 
1034 	sc = xsc;
1035 	ifp = sc->lge_ifp;
1036 	LGE_LOCK_ASSERT(sc);
1037 
1038 	CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1039 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1040 	CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1041 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1042 
1043 	if (!sc->lge_link) {
1044 		mii = device_get_softc(sc->lge_miibus);
1045 		mii_tick(mii);
1046 		if (mii->mii_media_status & IFM_ACTIVE &&
1047 		    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1048 			sc->lge_link++;
1049 			if (bootverbose &&
1050 		  	    (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1051 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1052 				device_printf(sc->lge_dev, "gigabit link up\n");
1053 			if (ifp->if_snd.ifq_head != NULL)
1054 				lge_start_locked(ifp);
1055 		}
1056 	}
1057 
1058 	if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1059 		lge_watchdog(sc);
1060 	callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1061 
1062 	return;
1063 }
1064 
1065 static void
1066 lge_intr(arg)
1067 	void			*arg;
1068 {
1069 	struct lge_softc	*sc;
1070 	struct ifnet		*ifp;
1071 	u_int32_t		status;
1072 
1073 	sc = arg;
1074 	ifp = sc->lge_ifp;
1075 	LGE_LOCK(sc);
1076 
1077 	/* Suppress unwanted interrupts */
1078 	if (!(ifp->if_flags & IFF_UP)) {
1079 		lge_stop(sc);
1080 		LGE_UNLOCK(sc);
1081 		return;
1082 	}
1083 
1084 	for (;;) {
1085 		/*
1086 		 * Reading the ISR register clears all interrupts, and
1087 		 * clears the 'interrupts enabled' bit in the IMR
1088 		 * register.
1089 		 */
1090 		status = CSR_READ_4(sc, LGE_ISR);
1091 
1092 		if ((status & LGE_INTRS) == 0)
1093 			break;
1094 
1095 		if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1096 			lge_txeof(sc);
1097 
1098 		if (status & LGE_ISR_RXDMA_DONE)
1099 			lge_rxeof(sc, LGE_RX_DMACNT(status));
1100 
1101 		if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1102 			lge_rxeoc(sc);
1103 
1104 		if (status & LGE_ISR_PHY_INTR) {
1105 			sc->lge_link = 0;
1106 			callout_stop(&sc->lge_stat_callout);
1107 			lge_tick(sc);
1108 		}
1109 	}
1110 
1111 	/* Re-enable interrupts. */
1112 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1113 
1114 	if (ifp->if_snd.ifq_head != NULL)
1115 		lge_start_locked(ifp);
1116 
1117 	LGE_UNLOCK(sc);
1118 	return;
1119 }
1120 
1121 /*
1122  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1123  * pointers to the fragment pointers.
1124  */
1125 static int
1126 lge_encap(sc, m_head, txidx)
1127 	struct lge_softc	*sc;
1128 	struct mbuf		*m_head;
1129 	u_int32_t		*txidx;
1130 {
1131 	struct lge_frag		*f = NULL;
1132 	struct lge_tx_desc	*cur_tx;
1133 	struct mbuf		*m;
1134 	int			frag = 0, tot_len = 0;
1135 
1136 	/*
1137  	 * Start packing the mbufs in this chain into
1138 	 * the fragment pointers. Stop when we run out
1139  	 * of fragments or hit the end of the mbuf chain.
1140 	 */
1141 	m = m_head;
1142 	cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1143 	frag = 0;
1144 
1145 	for (m = m_head; m != NULL; m = m->m_next) {
1146 		if (m->m_len != 0) {
1147 			tot_len += m->m_len;
1148 			f = &cur_tx->lge_frags[frag];
1149 			f->lge_fraglen = m->m_len;
1150 			f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1151 			f->lge_fragptr_hi = 0;
1152 			frag++;
1153 		}
1154 	}
1155 
1156 	if (m != NULL)
1157 		return(ENOBUFS);
1158 
1159 	cur_tx->lge_mbuf = m_head;
1160 	cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1161 	LGE_INC((*txidx), LGE_TX_LIST_CNT);
1162 
1163 	/* Queue for transmit */
1164 	CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1165 
1166 	return(0);
1167 }
1168 
1169 /*
1170  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1171  * to the mbuf data regions directly in the transmit lists. We also save a
1172  * copy of the pointers since the transmit list fragment pointers are
1173  * physical addresses.
1174  */
1175 
1176 static void
1177 lge_start(ifp)
1178 	struct ifnet		*ifp;
1179 {
1180 	struct lge_softc	*sc;
1181 
1182 	sc = ifp->if_softc;
1183 	LGE_LOCK(sc);
1184 	lge_start_locked(ifp);
1185 	LGE_UNLOCK(sc);
1186 }
1187 
1188 static void
1189 lge_start_locked(ifp)
1190 	struct ifnet		*ifp;
1191 {
1192 	struct lge_softc	*sc;
1193 	struct mbuf		*m_head = NULL;
1194 	u_int32_t		idx;
1195 
1196 	sc = ifp->if_softc;
1197 
1198 	if (!sc->lge_link)
1199 		return;
1200 
1201 	idx = sc->lge_cdata.lge_tx_prod;
1202 
1203 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1204 		return;
1205 
1206 	while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1207 		if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1208 			break;
1209 
1210 		IF_DEQUEUE(&ifp->if_snd, m_head);
1211 		if (m_head == NULL)
1212 			break;
1213 
1214 		if (lge_encap(sc, m_head, &idx)) {
1215 			IF_PREPEND(&ifp->if_snd, m_head);
1216 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1217 			break;
1218 		}
1219 
1220 		/*
1221 		 * If there's a BPF listener, bounce a copy of this frame
1222 		 * to him.
1223 		 */
1224 		BPF_MTAP(ifp, m_head);
1225 	}
1226 
1227 	sc->lge_cdata.lge_tx_prod = idx;
1228 
1229 	/*
1230 	 * Set a timeout in case the chip goes out to lunch.
1231 	 */
1232 	sc->lge_timer = 5;
1233 
1234 	return;
1235 }
1236 
1237 static void
1238 lge_init(xsc)
1239 	void			*xsc;
1240 {
1241 	struct lge_softc	*sc = xsc;
1242 
1243 	LGE_LOCK(sc);
1244 	lge_init_locked(sc);
1245 	LGE_UNLOCK(sc);
1246 }
1247 
1248 static void
1249 lge_init_locked(sc)
1250 	struct lge_softc	*sc;
1251 {
1252 	struct ifnet		*ifp = sc->lge_ifp;
1253 
1254 	LGE_LOCK_ASSERT(sc);
1255 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1256 		return;
1257 
1258 	/*
1259 	 * Cancel pending I/O and free all RX/TX buffers.
1260 	 */
1261 	lge_stop(sc);
1262 	lge_reset(sc);
1263 
1264 	/* Set MAC address */
1265 	CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0]));
1266 	CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4]));
1267 
1268 	/* Init circular RX list. */
1269 	if (lge_list_rx_init(sc) == ENOBUFS) {
1270 		device_printf(sc->lge_dev, "initialization failed: no "
1271 		    "memory for rx buffers\n");
1272 		lge_stop(sc);
1273 		return;
1274 	}
1275 
1276 	/*
1277 	 * Init tx descriptors.
1278 	 */
1279 	lge_list_tx_init(sc);
1280 
1281 	/* Set initial value for MODE1 register. */
1282 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1283 	    LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1284 	    LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1285 	    LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1286 
1287 	 /* If we want promiscuous mode, set the allframes bit. */
1288 	if (ifp->if_flags & IFF_PROMISC) {
1289 		CSR_WRITE_4(sc, LGE_MODE1,
1290 		    LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1291 	} else {
1292 		CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1293 	}
1294 
1295 	/*
1296 	 * Set the capture broadcast bit to capture broadcast frames.
1297 	 */
1298 	if (ifp->if_flags & IFF_BROADCAST) {
1299 		CSR_WRITE_4(sc, LGE_MODE1,
1300 		    LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1301 	} else {
1302 		CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1303 	}
1304 
1305 	/* Packet padding workaround? */
1306 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1307 
1308 	/* No error frames */
1309 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1310 
1311 	/* Receive large frames */
1312 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1313 
1314 	/* Workaround: disable RX/TX flow control */
1315 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1316 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1317 
1318 	/* Make sure to strip CRC from received frames */
1319 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1320 
1321 	/* Turn off magic packet mode */
1322 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1323 
1324 	/* Turn off all VLAN stuff */
1325 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1326 	    LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1327 
1328 	/* Workarond: FIFO overflow */
1329 	CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1330 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1331 
1332 	/*
1333 	 * Load the multicast filter.
1334 	 */
1335 	lge_setmulti(sc);
1336 
1337 	/*
1338 	 * Enable hardware checksum validation for all received IPv4
1339 	 * packets, do not reject packets with bad checksums.
1340 	 */
1341 	CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1342 	    LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1343 	    LGE_MODE2_RX_ERRCSUM);
1344 
1345 	/*
1346 	 * Enable the delivery of PHY interrupts based on
1347 	 * link/speed/duplex status chalges.
1348 	 */
1349 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1350 
1351 	/* Enable receiver and transmitter. */
1352 	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1353 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1354 
1355 	CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1356 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1357 
1358 	/*
1359 	 * Enable interrupts.
1360 	 */
1361 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1362 	    LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1363 
1364 	lge_ifmedia_upd_locked(ifp);
1365 
1366 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1367 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1368 
1369 	callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1370 
1371 	return;
1372 }
1373 
1374 /*
1375  * Set media options.
1376  */
1377 static int
1378 lge_ifmedia_upd(ifp)
1379 	struct ifnet		*ifp;
1380 {
1381 	struct lge_softc	*sc;
1382 
1383 	sc = ifp->if_softc;
1384 	LGE_LOCK(sc);
1385 	lge_ifmedia_upd_locked(ifp);
1386 	LGE_UNLOCK(sc);
1387 
1388 	return(0);
1389 }
1390 
1391 static void
1392 lge_ifmedia_upd_locked(ifp)
1393 	struct ifnet		*ifp;
1394 {
1395 	struct lge_softc	*sc;
1396 	struct mii_data		*mii;
1397 	struct mii_softc	*miisc;
1398 
1399 	sc = ifp->if_softc;
1400 
1401 	LGE_LOCK_ASSERT(sc);
1402 	mii = device_get_softc(sc->lge_miibus);
1403 	sc->lge_link = 0;
1404 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1405 		PHY_RESET(miisc);
1406 	mii_mediachg(mii);
1407 }
1408 
1409 /*
1410  * Report current media status.
1411  */
1412 static void
1413 lge_ifmedia_sts(ifp, ifmr)
1414 	struct ifnet		*ifp;
1415 	struct ifmediareq	*ifmr;
1416 {
1417 	struct lge_softc	*sc;
1418 	struct mii_data		*mii;
1419 
1420 	sc = ifp->if_softc;
1421 
1422 	LGE_LOCK(sc);
1423 	mii = device_get_softc(sc->lge_miibus);
1424 	mii_pollstat(mii);
1425 	ifmr->ifm_active = mii->mii_media_active;
1426 	ifmr->ifm_status = mii->mii_media_status;
1427 	LGE_UNLOCK(sc);
1428 
1429 	return;
1430 }
1431 
1432 static int
1433 lge_ioctl(ifp, command, data)
1434 	struct ifnet		*ifp;
1435 	u_long			command;
1436 	caddr_t			data;
1437 {
1438 	struct lge_softc	*sc = ifp->if_softc;
1439 	struct ifreq		*ifr = (struct ifreq *) data;
1440 	struct mii_data		*mii;
1441 	int			error = 0;
1442 
1443 	switch(command) {
1444 	case SIOCSIFMTU:
1445 		LGE_LOCK(sc);
1446 		if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1447 			error = EINVAL;
1448 		else
1449 			ifp->if_mtu = ifr->ifr_mtu;
1450 		LGE_UNLOCK(sc);
1451 		break;
1452 	case SIOCSIFFLAGS:
1453 		LGE_LOCK(sc);
1454 		if (ifp->if_flags & IFF_UP) {
1455 			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1456 			    ifp->if_flags & IFF_PROMISC &&
1457 			    !(sc->lge_if_flags & IFF_PROMISC)) {
1458 				CSR_WRITE_4(sc, LGE_MODE1,
1459 				    LGE_MODE1_SETRST_CTL1|
1460 				    LGE_MODE1_RX_PROMISC);
1461 			} else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1462 			    !(ifp->if_flags & IFF_PROMISC) &&
1463 			    sc->lge_if_flags & IFF_PROMISC) {
1464 				CSR_WRITE_4(sc, LGE_MODE1,
1465 				    LGE_MODE1_RX_PROMISC);
1466 			} else {
1467 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1468 				lge_init_locked(sc);
1469 			}
1470 		} else {
1471 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1472 				lge_stop(sc);
1473 		}
1474 		sc->lge_if_flags = ifp->if_flags;
1475 		LGE_UNLOCK(sc);
1476 		error = 0;
1477 		break;
1478 	case SIOCADDMULTI:
1479 	case SIOCDELMULTI:
1480 		LGE_LOCK(sc);
1481 		lge_setmulti(sc);
1482 		LGE_UNLOCK(sc);
1483 		error = 0;
1484 		break;
1485 	case SIOCGIFMEDIA:
1486 	case SIOCSIFMEDIA:
1487 		mii = device_get_softc(sc->lge_miibus);
1488 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1489 		break;
1490 	default:
1491 		error = ether_ioctl(ifp, command, data);
1492 		break;
1493 	}
1494 
1495 	return(error);
1496 }
1497 
1498 static void
1499 lge_watchdog(sc)
1500 	struct lge_softc	*sc;
1501 {
1502 	struct ifnet		*ifp;
1503 
1504 	LGE_LOCK_ASSERT(sc);
1505 	ifp = sc->lge_ifp;
1506 
1507 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1508 	if_printf(ifp, "watchdog timeout\n");
1509 
1510 	lge_stop(sc);
1511 	lge_reset(sc);
1512 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1513 	lge_init_locked(sc);
1514 
1515 	if (ifp->if_snd.ifq_head != NULL)
1516 		lge_start_locked(ifp);
1517 }
1518 
1519 /*
1520  * Stop the adapter and free any mbufs allocated to the
1521  * RX and TX lists.
1522  */
1523 static void
1524 lge_stop(sc)
1525 	struct lge_softc	*sc;
1526 {
1527 	int			i;
1528 	struct ifnet		*ifp;
1529 
1530 	LGE_LOCK_ASSERT(sc);
1531 	ifp = sc->lge_ifp;
1532 	sc->lge_timer = 0;
1533 	callout_stop(&sc->lge_stat_callout);
1534 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1535 
1536 	/* Disable receiver and transmitter. */
1537 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1538 	sc->lge_link = 0;
1539 
1540 	/*
1541 	 * Free data in the RX lists.
1542 	 */
1543 	for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1544 		if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1545 			m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1546 			sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1547 		}
1548 	}
1549 	bzero((char *)&sc->lge_ldata->lge_rx_list,
1550 		sizeof(sc->lge_ldata->lge_rx_list));
1551 
1552 	/*
1553 	 * Free the TX list buffers.
1554 	 */
1555 	for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1556 		if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1557 			m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1558 			sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1559 		}
1560 	}
1561 
1562 	bzero((char *)&sc->lge_ldata->lge_tx_list,
1563 		sizeof(sc->lge_ldata->lge_tx_list));
1564 
1565 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1566 
1567 	return;
1568 }
1569 
1570 /*
1571  * Stop all chip I/O so that the kernel's probe routines don't
1572  * get confused by errant DMAs when rebooting.
1573  */
1574 static int
1575 lge_shutdown(dev)
1576 	device_t		dev;
1577 {
1578 	struct lge_softc	*sc;
1579 
1580 	sc = device_get_softc(dev);
1581 
1582 	LGE_LOCK(sc);
1583 	lge_reset(sc);
1584 	lge_stop(sc);
1585 	LGE_UNLOCK(sc);
1586 
1587 	return (0);
1588 }
1589