1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 #include <sys/socket.h> 80 81 #include <net/if.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_types.h> 87 88 #include <net/bpf.h> 89 90 #include <vm/vm.h> /* for vtophys */ 91 #include <vm/pmap.h> /* for vtophys */ 92 #include <machine/clock.h> /* for DELAY */ 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 104 #define LGE_USEIOSPACE 105 106 #include <dev/lge/if_lgereg.h> 107 108 /* "controller miibus0" required. See GENERIC if you get errors here. */ 109 #include "miibus_if.h" 110 111 /* 112 * Various supported device vendors/types and their names. 113 */ 114 static struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117 }; 118 119 static int lge_probe(device_t); 120 static int lge_attach(device_t); 121 static int lge_detach(device_t); 122 123 static int lge_alloc_jumbo_mem(struct lge_softc *); 124 static void lge_free_jumbo_mem(struct lge_softc *); 125 static void *lge_jalloc(struct lge_softc *); 126 static void lge_jfree(void *, void *); 127 128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130 static void lge_rxeof(struct lge_softc *, int); 131 static void lge_rxeoc(struct lge_softc *); 132 static void lge_txeof(struct lge_softc *); 133 static void lge_intr(void *); 134 static void lge_tick(void *); 135 static void lge_start(struct ifnet *); 136 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137 static void lge_init(void *); 138 static void lge_stop(struct lge_softc *); 139 static void lge_watchdog(struct ifnet *); 140 static void lge_shutdown(device_t); 141 static int lge_ifmedia_upd(struct ifnet *); 142 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 145 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 146 147 static int lge_miibus_readreg(device_t, int, int); 148 static int lge_miibus_writereg(device_t, int, int, int); 149 static void lge_miibus_statchg(device_t); 150 151 static void lge_setmulti(struct lge_softc *); 152 static void lge_reset(struct lge_softc *); 153 static int lge_list_rx_init(struct lge_softc *); 154 static int lge_list_tx_init(struct lge_softc *); 155 156 #ifdef LGE_USEIOSPACE 157 #define LGE_RES SYS_RES_IOPORT 158 #define LGE_RID LGE_PCI_LOIO 159 #else 160 #define LGE_RES SYS_RES_MEMORY 161 #define LGE_RID LGE_PCI_LOMEM 162 #endif 163 164 static device_method_t lge_methods[] = { 165 /* Device interface */ 166 DEVMETHOD(device_probe, lge_probe), 167 DEVMETHOD(device_attach, lge_attach), 168 DEVMETHOD(device_detach, lge_detach), 169 DEVMETHOD(device_shutdown, lge_shutdown), 170 171 /* bus interface */ 172 DEVMETHOD(bus_print_child, bus_generic_print_child), 173 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 174 175 /* MII interface */ 176 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 177 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 178 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 179 180 { 0, 0 } 181 }; 182 183 static driver_t lge_driver = { 184 "lge", 185 lge_methods, 186 sizeof(struct lge_softc) 187 }; 188 189 static devclass_t lge_devclass; 190 191 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 192 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 193 MODULE_DEPEND(lge, pci, 1, 1, 1); 194 MODULE_DEPEND(lge, ether, 1, 1, 1); 195 MODULE_DEPEND(lge, miibus, 1, 1, 1); 196 197 #define LGE_SETBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, \ 199 CSR_READ_4(sc, reg) | (x)) 200 201 #define LGE_CLRBIT(sc, reg, x) \ 202 CSR_WRITE_4(sc, reg, \ 203 CSR_READ_4(sc, reg) & ~(x)) 204 205 #define SIO_SET(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 207 208 #define SIO_CLR(x) \ 209 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 210 211 /* 212 * Read a word of data stored in the EEPROM at address 'addr.' 213 */ 214 static void 215 lge_eeprom_getword(sc, addr, dest) 216 struct lge_softc *sc; 217 int addr; 218 u_int16_t *dest; 219 { 220 register int i; 221 u_int32_t val; 222 223 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 224 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 225 226 for (i = 0; i < LGE_TIMEOUT; i++) 227 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 228 break; 229 230 if (i == LGE_TIMEOUT) { 231 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 232 return; 233 } 234 235 val = CSR_READ_4(sc, LGE_EEDATA); 236 237 if (addr & 1) 238 *dest = (val >> 16) & 0xFFFF; 239 else 240 *dest = val & 0xFFFF; 241 242 return; 243 } 244 245 /* 246 * Read a sequence of words from the EEPROM. 247 */ 248 static void 249 lge_read_eeprom(sc, dest, off, cnt, swap) 250 struct lge_softc *sc; 251 caddr_t dest; 252 int off; 253 int cnt; 254 int swap; 255 { 256 int i; 257 u_int16_t word = 0, *ptr; 258 259 for (i = 0; i < cnt; i++) { 260 lge_eeprom_getword(sc, off + i, &word); 261 ptr = (u_int16_t *)(dest + (i * 2)); 262 if (swap) 263 *ptr = ntohs(word); 264 else 265 *ptr = word; 266 } 267 268 return; 269 } 270 271 static int 272 lge_miibus_readreg(dev, phy, reg) 273 device_t dev; 274 int phy, reg; 275 { 276 struct lge_softc *sc; 277 int i; 278 279 sc = device_get_softc(dev); 280 281 /* 282 * If we have a non-PCS PHY, pretend that the internal 283 * autoneg stuff at PHY address 0 isn't there so that 284 * the miibus code will find only the GMII PHY. 285 */ 286 if (sc->lge_pcs == 0 && phy == 0) 287 return(0); 288 289 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 290 291 for (i = 0; i < LGE_TIMEOUT; i++) 292 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 293 break; 294 295 if (i == LGE_TIMEOUT) { 296 printf("lge%d: PHY read timed out\n", sc->lge_unit); 297 return(0); 298 } 299 300 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 301 } 302 303 static int 304 lge_miibus_writereg(dev, phy, reg, data) 305 device_t dev; 306 int phy, reg, data; 307 { 308 struct lge_softc *sc; 309 int i; 310 311 sc = device_get_softc(dev); 312 313 CSR_WRITE_4(sc, LGE_GMIICTL, 314 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 315 316 for (i = 0; i < LGE_TIMEOUT; i++) 317 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 318 break; 319 320 if (i == LGE_TIMEOUT) { 321 printf("lge%d: PHY write timed out\n", sc->lge_unit); 322 return(0); 323 } 324 325 return(0); 326 } 327 328 static void 329 lge_miibus_statchg(dev) 330 device_t dev; 331 { 332 struct lge_softc *sc; 333 struct mii_data *mii; 334 335 sc = device_get_softc(dev); 336 mii = device_get_softc(sc->lge_miibus); 337 338 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 339 switch (IFM_SUBTYPE(mii->mii_media_active)) { 340 case IFM_1000_T: 341 case IFM_1000_SX: 342 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 343 break; 344 case IFM_100_TX: 345 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 346 break; 347 case IFM_10_T: 348 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 349 break; 350 default: 351 /* 352 * Choose something, even if it's wrong. Clearing 353 * all the bits will hose autoneg on the internal 354 * PHY. 355 */ 356 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 357 break; 358 } 359 360 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 361 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 362 } else { 363 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 364 } 365 366 return; 367 } 368 369 static void 370 lge_setmulti(sc) 371 struct lge_softc *sc; 372 { 373 struct ifnet *ifp; 374 struct ifmultiaddr *ifma; 375 u_int32_t h = 0, hashes[2] = { 0, 0 }; 376 377 ifp = sc->lge_ifp; 378 379 /* Make sure multicast hash table is enabled. */ 380 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 381 382 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 383 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 384 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 385 return; 386 } 387 388 /* first, zot all the existing hash bits */ 389 CSR_WRITE_4(sc, LGE_MAR0, 0); 390 CSR_WRITE_4(sc, LGE_MAR1, 0); 391 392 /* now program new ones */ 393 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 394 if (ifma->ifma_addr->sa_family != AF_LINK) 395 continue; 396 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 397 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 398 if (h < 32) 399 hashes[0] |= (1 << h); 400 else 401 hashes[1] |= (1 << (h - 32)); 402 } 403 404 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 405 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 406 407 return; 408 } 409 410 static void 411 lge_reset(sc) 412 struct lge_softc *sc; 413 { 414 register int i; 415 416 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 417 418 for (i = 0; i < LGE_TIMEOUT; i++) { 419 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 420 break; 421 } 422 423 if (i == LGE_TIMEOUT) 424 printf("lge%d: reset never completed\n", sc->lge_unit); 425 426 /* Wait a little while for the chip to get its brains in order. */ 427 DELAY(1000); 428 429 return; 430 } 431 432 /* 433 * Probe for a Level 1 chip. Check the PCI vendor and device 434 * IDs against our list and return a device name if we find a match. 435 */ 436 static int 437 lge_probe(dev) 438 device_t dev; 439 { 440 struct lge_type *t; 441 442 t = lge_devs; 443 444 while(t->lge_name != NULL) { 445 if ((pci_get_vendor(dev) == t->lge_vid) && 446 (pci_get_device(dev) == t->lge_did)) { 447 device_set_desc(dev, t->lge_name); 448 return(BUS_PROBE_DEFAULT); 449 } 450 t++; 451 } 452 453 return(ENXIO); 454 } 455 456 /* 457 * Attach the interface. Allocate softc structures, do ifmedia 458 * setup and ethernet/BPF attach. 459 */ 460 static int 461 lge_attach(dev) 462 device_t dev; 463 { 464 int s; 465 u_char eaddr[ETHER_ADDR_LEN]; 466 struct lge_softc *sc; 467 struct ifnet *ifp; 468 int unit, error = 0, rid; 469 470 s = splimp(); 471 472 sc = device_get_softc(dev); 473 unit = device_get_unit(dev); 474 bzero(sc, sizeof(struct lge_softc)); 475 /* 476 * Map control/status registers. 477 */ 478 pci_enable_busmaster(dev); 479 480 rid = LGE_RID; 481 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 482 483 if (sc->lge_res == NULL) { 484 printf("lge%d: couldn't map ports/memory\n", unit); 485 error = ENXIO; 486 goto fail; 487 } 488 489 sc->lge_btag = rman_get_bustag(sc->lge_res); 490 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 491 492 /* Allocate interrupt */ 493 rid = 0; 494 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 495 RF_SHAREABLE | RF_ACTIVE); 496 497 if (sc->lge_irq == NULL) { 498 printf("lge%d: couldn't map interrupt\n", unit); 499 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 500 error = ENXIO; 501 goto fail; 502 } 503 504 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 505 lge_intr, sc, &sc->lge_intrhand); 506 507 if (error) { 508 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 509 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 510 printf("lge%d: couldn't set up irq\n", unit); 511 goto fail; 512 } 513 514 /* Reset the adapter. */ 515 lge_reset(sc); 516 517 /* 518 * Get station address from the EEPROM. 519 */ 520 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 521 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 522 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 523 524 sc->lge_unit = unit; 525 callout_handle_init(&sc->lge_stat_ch); 526 527 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 528 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 529 530 if (sc->lge_ldata == NULL) { 531 printf("lge%d: no memory for list buffers!\n", unit); 532 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 534 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 535 error = ENXIO; 536 goto fail; 537 } 538 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 539 540 /* Try to allocate memory for jumbo buffers. */ 541 if (lge_alloc_jumbo_mem(sc)) { 542 printf("lge%d: jumbo buffer allocation failed\n", 543 sc->lge_unit); 544 contigfree(sc->lge_ldata, 545 sizeof(struct lge_list_data), M_DEVBUF); 546 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 547 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 548 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 549 error = ENXIO; 550 goto fail; 551 } 552 553 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 554 if (ifp == NULL) { 555 printf("lge%d: can not if_alloc()\n", sc->lge_unit); 556 contigfree(sc->lge_ldata, 557 sizeof(struct lge_list_data), M_DEVBUF); 558 lge_free_jumbo_mem(sc); 559 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 560 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 561 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 562 error = ENOSPC; 563 goto fail; 564 } 565 ifp->if_softc = sc; 566 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 567 ifp->if_mtu = ETHERMTU; 568 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 569 IFF_NEEDSGIANT; 570 ifp->if_ioctl = lge_ioctl; 571 ifp->if_start = lge_start; 572 ifp->if_watchdog = lge_watchdog; 573 ifp->if_init = lge_init; 574 ifp->if_baudrate = 1000000000; 575 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 576 ifp->if_capabilities = IFCAP_RXCSUM; 577 ifp->if_capenable = ifp->if_capabilities; 578 579 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 580 sc->lge_pcs = 1; 581 else 582 sc->lge_pcs = 0; 583 584 /* 585 * Do MII setup. 586 */ 587 if (mii_phy_probe(dev, &sc->lge_miibus, 588 lge_ifmedia_upd, lge_ifmedia_sts)) { 589 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 590 contigfree(sc->lge_ldata, 591 sizeof(struct lge_list_data), M_DEVBUF); 592 lge_free_jumbo_mem(sc); 593 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 594 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 595 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 596 if_free(ifp); 597 error = ENXIO; 598 goto fail; 599 } 600 601 /* 602 * Call MI attach routine. 603 */ 604 ether_ifattach(ifp, eaddr); 605 callout_handle_init(&sc->lge_stat_ch); 606 607 fail: 608 splx(s); 609 return(error); 610 } 611 612 static int 613 lge_detach(dev) 614 device_t dev; 615 { 616 struct lge_softc *sc; 617 struct ifnet *ifp; 618 int s; 619 620 s = splimp(); 621 622 sc = device_get_softc(dev); 623 ifp = sc->lge_ifp; 624 625 lge_reset(sc); 626 lge_stop(sc); 627 ether_ifdetach(ifp); 628 if_free(ifp); 629 630 bus_generic_detach(dev); 631 device_delete_child(dev, sc->lge_miibus); 632 633 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 634 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 635 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 636 637 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 638 lge_free_jumbo_mem(sc); 639 640 splx(s); 641 642 return(0); 643 } 644 645 /* 646 * Initialize the transmit descriptors. 647 */ 648 static int 649 lge_list_tx_init(sc) 650 struct lge_softc *sc; 651 { 652 struct lge_list_data *ld; 653 struct lge_ring_data *cd; 654 int i; 655 656 cd = &sc->lge_cdata; 657 ld = sc->lge_ldata; 658 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 659 ld->lge_tx_list[i].lge_mbuf = NULL; 660 ld->lge_tx_list[i].lge_ctl = 0; 661 } 662 663 cd->lge_tx_prod = cd->lge_tx_cons = 0; 664 665 return(0); 666 } 667 668 669 /* 670 * Initialize the RX descriptors and allocate mbufs for them. Note that 671 * we arralge the descriptors in a closed ring, so that the last descriptor 672 * points back to the first. 673 */ 674 static int 675 lge_list_rx_init(sc) 676 struct lge_softc *sc; 677 { 678 struct lge_list_data *ld; 679 struct lge_ring_data *cd; 680 int i; 681 682 ld = sc->lge_ldata; 683 cd = &sc->lge_cdata; 684 685 cd->lge_rx_prod = cd->lge_rx_cons = 0; 686 687 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 688 689 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 690 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 691 break; 692 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 693 return(ENOBUFS); 694 } 695 696 /* Clear possible 'rx command queue empty' interrupt. */ 697 CSR_READ_4(sc, LGE_ISR); 698 699 return(0); 700 } 701 702 /* 703 * Initialize an RX descriptor and attach an MBUF cluster. 704 */ 705 static int 706 lge_newbuf(sc, c, m) 707 struct lge_softc *sc; 708 struct lge_rx_desc *c; 709 struct mbuf *m; 710 { 711 struct mbuf *m_new = NULL; 712 caddr_t *buf = NULL; 713 714 if (m == NULL) { 715 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 716 if (m_new == NULL) { 717 printf("lge%d: no memory for rx list " 718 "-- packet dropped!\n", sc->lge_unit); 719 return(ENOBUFS); 720 } 721 722 /* Allocate the jumbo buffer */ 723 buf = lge_jalloc(sc); 724 if (buf == NULL) { 725 #ifdef LGE_VERBOSE 726 printf("lge%d: jumbo allocation failed " 727 "-- packet dropped!\n", sc->lge_unit); 728 #endif 729 m_freem(m_new); 730 return(ENOBUFS); 731 } 732 /* Attach the buffer to the mbuf */ 733 m_new->m_data = (void *)buf; 734 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 735 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 736 (struct lge_softc *)sc, 0, EXT_NET_DRV); 737 } else { 738 m_new = m; 739 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 740 m_new->m_data = m_new->m_ext.ext_buf; 741 } 742 743 /* 744 * Adjust alignment so packet payload begins on a 745 * longword boundary. Mandatory for Alpha, useful on 746 * x86 too. 747 */ 748 m_adj(m_new, ETHER_ALIGN); 749 750 c->lge_mbuf = m_new; 751 c->lge_fragptr_hi = 0; 752 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 753 c->lge_fraglen = m_new->m_len; 754 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 755 c->lge_sts = 0; 756 757 /* 758 * Put this buffer in the RX command FIFO. To do this, 759 * we just write the physical address of the descriptor 760 * into the RX descriptor address registers. Note that 761 * there are two registers, one high DWORD and one low 762 * DWORD, which lets us specify a 64-bit address if 763 * desired. We only use a 32-bit address for now. 764 * Writing to the low DWORD register is what actually 765 * causes the command to be issued, so we do that 766 * last. 767 */ 768 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 769 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 770 771 return(0); 772 } 773 774 static int 775 lge_alloc_jumbo_mem(sc) 776 struct lge_softc *sc; 777 { 778 caddr_t ptr; 779 register int i; 780 struct lge_jpool_entry *entry; 781 782 /* Grab a big chunk o' storage. */ 783 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 784 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 785 786 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 787 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 788 return(ENOBUFS); 789 } 790 791 SLIST_INIT(&sc->lge_jfree_listhead); 792 SLIST_INIT(&sc->lge_jinuse_listhead); 793 794 /* 795 * Now divide it up into 9K pieces and save the addresses 796 * in an array. 797 */ 798 ptr = sc->lge_cdata.lge_jumbo_buf; 799 for (i = 0; i < LGE_JSLOTS; i++) { 800 sc->lge_cdata.lge_jslots[i] = ptr; 801 ptr += LGE_JLEN; 802 entry = malloc(sizeof(struct lge_jpool_entry), 803 M_DEVBUF, M_NOWAIT); 804 if (entry == NULL) { 805 printf("lge%d: no memory for jumbo " 806 "buffer queue!\n", sc->lge_unit); 807 return(ENOBUFS); 808 } 809 entry->slot = i; 810 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 811 entry, jpool_entries); 812 } 813 814 return(0); 815 } 816 817 static void 818 lge_free_jumbo_mem(sc) 819 struct lge_softc *sc; 820 { 821 int i; 822 struct lge_jpool_entry *entry; 823 824 for (i = 0; i < LGE_JSLOTS; i++) { 825 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 826 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 827 free(entry, M_DEVBUF); 828 } 829 830 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 831 832 return; 833 } 834 835 /* 836 * Allocate a jumbo buffer. 837 */ 838 static void * 839 lge_jalloc(sc) 840 struct lge_softc *sc; 841 { 842 struct lge_jpool_entry *entry; 843 844 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 845 846 if (entry == NULL) { 847 #ifdef LGE_VERBOSE 848 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 849 #endif 850 return(NULL); 851 } 852 853 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 854 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 855 return(sc->lge_cdata.lge_jslots[entry->slot]); 856 } 857 858 /* 859 * Release a jumbo buffer. 860 */ 861 static void 862 lge_jfree(buf, args) 863 void *buf; 864 void *args; 865 { 866 struct lge_softc *sc; 867 int i; 868 struct lge_jpool_entry *entry; 869 870 /* Extract the softc struct pointer. */ 871 sc = args; 872 873 if (sc == NULL) 874 panic("lge_jfree: can't find softc pointer!"); 875 876 /* calculate the slot this buffer belongs to */ 877 i = ((vm_offset_t)buf 878 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 879 880 if ((i < 0) || (i >= LGE_JSLOTS)) 881 panic("lge_jfree: asked to free buffer that we don't manage!"); 882 883 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 884 if (entry == NULL) 885 panic("lge_jfree: buffer not in use!"); 886 entry->slot = i; 887 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 888 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 889 890 return; 891 } 892 893 /* 894 * A frame has been uploaded: pass the resulting mbuf chain up to 895 * the higher level protocols. 896 */ 897 static void 898 lge_rxeof(sc, cnt) 899 struct lge_softc *sc; 900 int cnt; 901 { 902 struct mbuf *m; 903 struct ifnet *ifp; 904 struct lge_rx_desc *cur_rx; 905 int c, i, total_len = 0; 906 u_int32_t rxsts, rxctl; 907 908 ifp = sc->lge_ifp; 909 910 /* Find out how many frames were processed. */ 911 c = cnt; 912 i = sc->lge_cdata.lge_rx_cons; 913 914 /* Suck them in. */ 915 while(c) { 916 struct mbuf *m0 = NULL; 917 918 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 919 rxctl = cur_rx->lge_ctl; 920 rxsts = cur_rx->lge_sts; 921 m = cur_rx->lge_mbuf; 922 cur_rx->lge_mbuf = NULL; 923 total_len = LGE_RXBYTES(cur_rx); 924 LGE_INC(i, LGE_RX_LIST_CNT); 925 c--; 926 927 /* 928 * If an error occurs, update stats, clear the 929 * status word and leave the mbuf cluster in place: 930 * it should simply get re-used next time this descriptor 931 * comes up in the ring. 932 */ 933 if (rxctl & LGE_RXCTL_ERRMASK) { 934 ifp->if_ierrors++; 935 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 936 continue; 937 } 938 939 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 940 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 941 ifp, NULL); 942 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 943 if (m0 == NULL) { 944 printf("lge%d: no receive buffers " 945 "available -- packet dropped!\n", 946 sc->lge_unit); 947 ifp->if_ierrors++; 948 continue; 949 } 950 m = m0; 951 } else { 952 m->m_pkthdr.rcvif = ifp; 953 m->m_pkthdr.len = m->m_len = total_len; 954 } 955 956 ifp->if_ipackets++; 957 958 /* Do IP checksum checking. */ 959 if (rxsts & LGE_RXSTS_ISIP) 960 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 961 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 962 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 963 if ((rxsts & LGE_RXSTS_ISTCP && 964 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 965 (rxsts & LGE_RXSTS_ISUDP && 966 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 967 m->m_pkthdr.csum_flags |= 968 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 969 m->m_pkthdr.csum_data = 0xffff; 970 } 971 972 (*ifp->if_input)(ifp, m); 973 } 974 975 sc->lge_cdata.lge_rx_cons = i; 976 977 return; 978 } 979 980 static void 981 lge_rxeoc(sc) 982 struct lge_softc *sc; 983 { 984 struct ifnet *ifp; 985 986 ifp = sc->lge_ifp; 987 ifp->if_flags &= ~IFF_RUNNING; 988 lge_init(sc); 989 return; 990 } 991 992 /* 993 * A frame was downloaded to the chip. It's safe for us to clean up 994 * the list buffers. 995 */ 996 997 static void 998 lge_txeof(sc) 999 struct lge_softc *sc; 1000 { 1001 struct lge_tx_desc *cur_tx = NULL; 1002 struct ifnet *ifp; 1003 u_int32_t idx, txdone; 1004 1005 ifp = sc->lge_ifp; 1006 1007 /* Clear the timeout timer. */ 1008 ifp->if_timer = 0; 1009 1010 /* 1011 * Go through our tx list and free mbufs for those 1012 * frames that have been transmitted. 1013 */ 1014 idx = sc->lge_cdata.lge_tx_cons; 1015 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1016 1017 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1018 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1019 1020 ifp->if_opackets++; 1021 if (cur_tx->lge_mbuf != NULL) { 1022 m_freem(cur_tx->lge_mbuf); 1023 cur_tx->lge_mbuf = NULL; 1024 } 1025 cur_tx->lge_ctl = 0; 1026 1027 txdone--; 1028 LGE_INC(idx, LGE_TX_LIST_CNT); 1029 ifp->if_timer = 0; 1030 } 1031 1032 sc->lge_cdata.lge_tx_cons = idx; 1033 1034 if (cur_tx != NULL) 1035 ifp->if_flags &= ~IFF_OACTIVE; 1036 1037 return; 1038 } 1039 1040 static void 1041 lge_tick(xsc) 1042 void *xsc; 1043 { 1044 struct lge_softc *sc; 1045 struct mii_data *mii; 1046 struct ifnet *ifp; 1047 int s; 1048 1049 s = splimp(); 1050 1051 sc = xsc; 1052 ifp = sc->lge_ifp; 1053 1054 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1055 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1056 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1057 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1058 1059 if (!sc->lge_link) { 1060 mii = device_get_softc(sc->lge_miibus); 1061 mii_tick(mii); 1062 if (mii->mii_media_status & IFM_ACTIVE && 1063 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1064 sc->lge_link++; 1065 if (bootverbose && 1066 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1067 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1068 printf("lge%d: gigabit link up\n", 1069 sc->lge_unit); 1070 if (ifp->if_snd.ifq_head != NULL) 1071 lge_start(ifp); 1072 } 1073 } 1074 1075 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1076 1077 splx(s); 1078 1079 return; 1080 } 1081 1082 static void 1083 lge_intr(arg) 1084 void *arg; 1085 { 1086 struct lge_softc *sc; 1087 struct ifnet *ifp; 1088 u_int32_t status; 1089 1090 sc = arg; 1091 ifp = sc->lge_ifp; 1092 1093 /* Supress unwanted interrupts */ 1094 if (!(ifp->if_flags & IFF_UP)) { 1095 lge_stop(sc); 1096 return; 1097 } 1098 1099 for (;;) { 1100 /* 1101 * Reading the ISR register clears all interrupts, and 1102 * clears the 'interrupts enabled' bit in the IMR 1103 * register. 1104 */ 1105 status = CSR_READ_4(sc, LGE_ISR); 1106 1107 if ((status & LGE_INTRS) == 0) 1108 break; 1109 1110 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1111 lge_txeof(sc); 1112 1113 if (status & LGE_ISR_RXDMA_DONE) 1114 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1115 1116 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1117 lge_rxeoc(sc); 1118 1119 if (status & LGE_ISR_PHY_INTR) { 1120 sc->lge_link = 0; 1121 untimeout(lge_tick, sc, sc->lge_stat_ch); 1122 lge_tick(sc); 1123 } 1124 } 1125 1126 /* Re-enable interrupts. */ 1127 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1128 1129 if (ifp->if_snd.ifq_head != NULL) 1130 lge_start(ifp); 1131 1132 return; 1133 } 1134 1135 /* 1136 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1137 * pointers to the fragment pointers. 1138 */ 1139 static int 1140 lge_encap(sc, m_head, txidx) 1141 struct lge_softc *sc; 1142 struct mbuf *m_head; 1143 u_int32_t *txidx; 1144 { 1145 struct lge_frag *f = NULL; 1146 struct lge_tx_desc *cur_tx; 1147 struct mbuf *m; 1148 int frag = 0, tot_len = 0; 1149 1150 /* 1151 * Start packing the mbufs in this chain into 1152 * the fragment pointers. Stop when we run out 1153 * of fragments or hit the end of the mbuf chain. 1154 */ 1155 m = m_head; 1156 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1157 frag = 0; 1158 1159 for (m = m_head; m != NULL; m = m->m_next) { 1160 if (m->m_len != 0) { 1161 tot_len += m->m_len; 1162 f = &cur_tx->lge_frags[frag]; 1163 f->lge_fraglen = m->m_len; 1164 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1165 f->lge_fragptr_hi = 0; 1166 frag++; 1167 } 1168 } 1169 1170 if (m != NULL) 1171 return(ENOBUFS); 1172 1173 cur_tx->lge_mbuf = m_head; 1174 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1175 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1176 1177 /* Queue for transmit */ 1178 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1179 1180 return(0); 1181 } 1182 1183 /* 1184 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1185 * to the mbuf data regions directly in the transmit lists. We also save a 1186 * copy of the pointers since the transmit list fragment pointers are 1187 * physical addresses. 1188 */ 1189 1190 static void 1191 lge_start(ifp) 1192 struct ifnet *ifp; 1193 { 1194 struct lge_softc *sc; 1195 struct mbuf *m_head = NULL; 1196 u_int32_t idx; 1197 1198 sc = ifp->if_softc; 1199 1200 if (!sc->lge_link) 1201 return; 1202 1203 idx = sc->lge_cdata.lge_tx_prod; 1204 1205 if (ifp->if_flags & IFF_OACTIVE) 1206 return; 1207 1208 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1209 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1210 break; 1211 1212 IF_DEQUEUE(&ifp->if_snd, m_head); 1213 if (m_head == NULL) 1214 break; 1215 1216 if (lge_encap(sc, m_head, &idx)) { 1217 IF_PREPEND(&ifp->if_snd, m_head); 1218 ifp->if_flags |= IFF_OACTIVE; 1219 break; 1220 } 1221 1222 /* 1223 * If there's a BPF listener, bounce a copy of this frame 1224 * to him. 1225 */ 1226 BPF_MTAP(ifp, m_head); 1227 } 1228 1229 sc->lge_cdata.lge_tx_prod = idx; 1230 1231 /* 1232 * Set a timeout in case the chip goes out to lunch. 1233 */ 1234 ifp->if_timer = 5; 1235 1236 return; 1237 } 1238 1239 static void 1240 lge_init(xsc) 1241 void *xsc; 1242 { 1243 struct lge_softc *sc = xsc; 1244 struct ifnet *ifp = sc->lge_ifp; 1245 struct mii_data *mii; 1246 int s; 1247 1248 if (ifp->if_flags & IFF_RUNNING) 1249 return; 1250 1251 s = splimp(); 1252 1253 /* 1254 * Cancel pending I/O and free all RX/TX buffers. 1255 */ 1256 lge_stop(sc); 1257 lge_reset(sc); 1258 1259 mii = device_get_softc(sc->lge_miibus); 1260 1261 /* Set MAC address */ 1262 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->lge_ifp)[0])); 1263 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->lge_ifp)[4])); 1264 1265 /* Init circular RX list. */ 1266 if (lge_list_rx_init(sc) == ENOBUFS) { 1267 printf("lge%d: initialization failed: no " 1268 "memory for rx buffers\n", sc->lge_unit); 1269 lge_stop(sc); 1270 (void)splx(s); 1271 return; 1272 } 1273 1274 /* 1275 * Init tx descriptors. 1276 */ 1277 lge_list_tx_init(sc); 1278 1279 /* Set initial value for MODE1 register. */ 1280 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1281 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1282 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1283 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1284 1285 /* If we want promiscuous mode, set the allframes bit. */ 1286 if (ifp->if_flags & IFF_PROMISC) { 1287 CSR_WRITE_4(sc, LGE_MODE1, 1288 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1289 } else { 1290 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1291 } 1292 1293 /* 1294 * Set the capture broadcast bit to capture broadcast frames. 1295 */ 1296 if (ifp->if_flags & IFF_BROADCAST) { 1297 CSR_WRITE_4(sc, LGE_MODE1, 1298 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1299 } else { 1300 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1301 } 1302 1303 /* Packet padding workaround? */ 1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1305 1306 /* No error frames */ 1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1308 1309 /* Receive large frames */ 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1311 1312 /* Workaround: disable RX/TX flow control */ 1313 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1314 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1315 1316 /* Make sure to strip CRC from received frames */ 1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1318 1319 /* Turn off magic packet mode */ 1320 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1321 1322 /* Turn off all VLAN stuff */ 1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1324 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1325 1326 /* Workarond: FIFO overflow */ 1327 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1328 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1329 1330 /* 1331 * Load the multicast filter. 1332 */ 1333 lge_setmulti(sc); 1334 1335 /* 1336 * Enable hardware checksum validation for all received IPv4 1337 * packets, do not reject packets with bad checksums. 1338 */ 1339 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1340 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1341 LGE_MODE2_RX_ERRCSUM); 1342 1343 /* 1344 * Enable the delivery of PHY interrupts based on 1345 * link/speed/duplex status chalges. 1346 */ 1347 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1348 1349 /* Enable receiver and transmitter. */ 1350 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1352 1353 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1355 1356 /* 1357 * Enable interrupts. 1358 */ 1359 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1360 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1361 1362 lge_ifmedia_upd(ifp); 1363 1364 ifp->if_flags |= IFF_RUNNING; 1365 ifp->if_flags &= ~IFF_OACTIVE; 1366 1367 (void)splx(s); 1368 1369 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1370 1371 return; 1372 } 1373 1374 /* 1375 * Set media options. 1376 */ 1377 static int 1378 lge_ifmedia_upd(ifp) 1379 struct ifnet *ifp; 1380 { 1381 struct lge_softc *sc; 1382 struct mii_data *mii; 1383 1384 sc = ifp->if_softc; 1385 1386 mii = device_get_softc(sc->lge_miibus); 1387 sc->lge_link = 0; 1388 if (mii->mii_instance) { 1389 struct mii_softc *miisc; 1390 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1391 miisc = LIST_NEXT(miisc, mii_list)) 1392 mii_phy_reset(miisc); 1393 } 1394 mii_mediachg(mii); 1395 1396 return(0); 1397 } 1398 1399 /* 1400 * Report current media status. 1401 */ 1402 static void 1403 lge_ifmedia_sts(ifp, ifmr) 1404 struct ifnet *ifp; 1405 struct ifmediareq *ifmr; 1406 { 1407 struct lge_softc *sc; 1408 struct mii_data *mii; 1409 1410 sc = ifp->if_softc; 1411 1412 mii = device_get_softc(sc->lge_miibus); 1413 mii_pollstat(mii); 1414 ifmr->ifm_active = mii->mii_media_active; 1415 ifmr->ifm_status = mii->mii_media_status; 1416 1417 return; 1418 } 1419 1420 static int 1421 lge_ioctl(ifp, command, data) 1422 struct ifnet *ifp; 1423 u_long command; 1424 caddr_t data; 1425 { 1426 struct lge_softc *sc = ifp->if_softc; 1427 struct ifreq *ifr = (struct ifreq *) data; 1428 struct mii_data *mii; 1429 int s, error = 0; 1430 1431 s = splimp(); 1432 1433 switch(command) { 1434 case SIOCSIFMTU: 1435 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1436 error = EINVAL; 1437 else 1438 ifp->if_mtu = ifr->ifr_mtu; 1439 break; 1440 case SIOCSIFFLAGS: 1441 if (ifp->if_flags & IFF_UP) { 1442 if (ifp->if_flags & IFF_RUNNING && 1443 ifp->if_flags & IFF_PROMISC && 1444 !(sc->lge_if_flags & IFF_PROMISC)) { 1445 CSR_WRITE_4(sc, LGE_MODE1, 1446 LGE_MODE1_SETRST_CTL1| 1447 LGE_MODE1_RX_PROMISC); 1448 } else if (ifp->if_flags & IFF_RUNNING && 1449 !(ifp->if_flags & IFF_PROMISC) && 1450 sc->lge_if_flags & IFF_PROMISC) { 1451 CSR_WRITE_4(sc, LGE_MODE1, 1452 LGE_MODE1_RX_PROMISC); 1453 } else { 1454 ifp->if_flags &= ~IFF_RUNNING; 1455 lge_init(sc); 1456 } 1457 } else { 1458 if (ifp->if_flags & IFF_RUNNING) 1459 lge_stop(sc); 1460 } 1461 sc->lge_if_flags = ifp->if_flags; 1462 error = 0; 1463 break; 1464 case SIOCADDMULTI: 1465 case SIOCDELMULTI: 1466 lge_setmulti(sc); 1467 error = 0; 1468 break; 1469 case SIOCGIFMEDIA: 1470 case SIOCSIFMEDIA: 1471 mii = device_get_softc(sc->lge_miibus); 1472 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1473 break; 1474 default: 1475 error = ether_ioctl(ifp, command, data); 1476 break; 1477 } 1478 1479 (void)splx(s); 1480 1481 return(error); 1482 } 1483 1484 static void 1485 lge_watchdog(ifp) 1486 struct ifnet *ifp; 1487 { 1488 struct lge_softc *sc; 1489 1490 sc = ifp->if_softc; 1491 1492 ifp->if_oerrors++; 1493 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1494 1495 lge_stop(sc); 1496 lge_reset(sc); 1497 ifp->if_flags &= ~IFF_RUNNING; 1498 lge_init(sc); 1499 1500 if (ifp->if_snd.ifq_head != NULL) 1501 lge_start(ifp); 1502 1503 return; 1504 } 1505 1506 /* 1507 * Stop the adapter and free any mbufs allocated to the 1508 * RX and TX lists. 1509 */ 1510 static void 1511 lge_stop(sc) 1512 struct lge_softc *sc; 1513 { 1514 register int i; 1515 struct ifnet *ifp; 1516 1517 ifp = sc->lge_ifp; 1518 ifp->if_timer = 0; 1519 untimeout(lge_tick, sc, sc->lge_stat_ch); 1520 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1521 1522 /* Disable receiver and transmitter. */ 1523 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1524 sc->lge_link = 0; 1525 1526 /* 1527 * Free data in the RX lists. 1528 */ 1529 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1530 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1531 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1532 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1533 } 1534 } 1535 bzero((char *)&sc->lge_ldata->lge_rx_list, 1536 sizeof(sc->lge_ldata->lge_rx_list)); 1537 1538 /* 1539 * Free the TX list buffers. 1540 */ 1541 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1542 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1543 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1544 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1545 } 1546 } 1547 1548 bzero((char *)&sc->lge_ldata->lge_tx_list, 1549 sizeof(sc->lge_ldata->lge_tx_list)); 1550 1551 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1552 1553 return; 1554 } 1555 1556 /* 1557 * Stop all chip I/O so that the kernel's probe routines don't 1558 * get confused by errant DMAs when rebooting. 1559 */ 1560 static void 1561 lge_shutdown(dev) 1562 device_t dev; 1563 { 1564 struct lge_softc *sc; 1565 1566 sc = device_get_softc(dev); 1567 1568 lge_reset(sc); 1569 lge_stop(sc); 1570 1571 return; 1572 } 1573