1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 38 * documentation not available, but ask me nicely. 39 * 40 * Written by Bill Paul <william.paul@windriver.com> 41 * Wind River Systems 42 */ 43 44 /* 45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 46 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 48 * are three supported methods for data transfer between host and 49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 50 * Propulsion Technology (tm) DMA. The latter mechanism is a form 51 * of double buffer DMA where the packet data is copied to a 52 * pre-allocated DMA buffer who's physical address has been loaded 53 * into a table at device initialization time. The rationale is that 54 * the virtual to physical address translation needed for normal 55 * scatter/gather DMA is more expensive than the data copy needed 56 * for double buffering. This may be true in Windows NT and the like, 57 * but it isn't true for us, at least on the x86 arch. This driver 58 * uses the scatter/gather I/O method for both TX and RX. 59 * 60 * The LXT1001 only supports TCP/IP checksum offload on receive. 61 * Also, the VLAN tagging is done using a 16-entry table which allows 62 * the chip to perform hardware filtering based on VLAN tags. Sadly, 63 * our vlan support doesn't currently play well with this kind of 64 * hardware support. 65 * 66 * Special thanks to: 67 * - Jeff James at Intel, for arranging to have the LXT1001 manual 68 * released (at long last) 69 * - Beny Chen at D-Link, for actually sending it to me 70 * - Brad Short and Keith Alexis at SMC, for sending me sample 71 * SMC9462SX and SMC9462TX adapters for testing 72 * - Paul Saab at Y!, for not killing me (though it remains to be seen 73 * if in fact he did me much of a favor) 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/sockio.h> 79 #include <sys/mbuf.h> 80 #include <sys/malloc.h> 81 #include <sys/kernel.h> 82 #include <sys/socket.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <vm/vm.h> /* for vtophys */ 93 #include <vm/pmap.h> /* for vtophys */ 94 #include <machine/clock.h> /* for DELAY */ 95 #include <machine/bus_pio.h> 96 #include <machine/bus_memio.h> 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 105 #include <pci/pcireg.h> 106 #include <pci/pcivar.h> 107 108 #define LGE_USEIOSPACE 109 110 #include <dev/lge/if_lgereg.h> 111 112 /* "controller miibus0" required. See GENERIC if you get errors here. */ 113 #include "miibus_if.h" 114 115 #ifndef lint 116 static const char rcsid[] = 117 "$FreeBSD$"; 118 #endif 119 120 /* 121 * Various supported device vendors/types and their names. 122 */ 123 static struct lge_type lge_devs[] = { 124 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 125 { 0, 0, NULL } 126 }; 127 128 static int lge_probe __P((device_t)); 129 static int lge_attach __P((device_t)); 130 static int lge_detach __P((device_t)); 131 132 static int lge_alloc_jumbo_mem __P((struct lge_softc *)); 133 static void lge_free_jumbo_mem __P((struct lge_softc *)); 134 static void *lge_jalloc __P((struct lge_softc *)); 135 static void lge_jfree __P((caddr_t, void *)); 136 137 static int lge_newbuf __P((struct lge_softc *, 138 struct lge_rx_desc *, 139 struct mbuf *)); 140 static int lge_encap __P((struct lge_softc *, 141 struct mbuf *, u_int32_t *)); 142 static void lge_rxeof __P((struct lge_softc *, int)); 143 static void lge_rxeoc __P((struct lge_softc *)); 144 static void lge_txeof __P((struct lge_softc *)); 145 static void lge_intr __P((void *)); 146 static void lge_tick __P((void *)); 147 static void lge_start __P((struct ifnet *)); 148 static int lge_ioctl __P((struct ifnet *, u_long, caddr_t)); 149 static void lge_init __P((void *)); 150 static void lge_stop __P((struct lge_softc *)); 151 static void lge_watchdog __P((struct ifnet *)); 152 static void lge_shutdown __P((device_t)); 153 static int lge_ifmedia_upd __P((struct ifnet *)); 154 static void lge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 155 156 static void lge_eeprom_getword __P((struct lge_softc *, int, u_int16_t *)); 157 static void lge_read_eeprom __P((struct lge_softc *, caddr_t, int, 158 int, int)); 159 160 static int lge_miibus_readreg __P((device_t, int, int)); 161 static int lge_miibus_writereg __P((device_t, int, int, int)); 162 static void lge_miibus_statchg __P((device_t)); 163 164 static void lge_setmulti __P((struct lge_softc *)); 165 static u_int32_t lge_crc __P((struct lge_softc *, caddr_t)); 166 static void lge_reset __P((struct lge_softc *)); 167 static int lge_list_rx_init __P((struct lge_softc *)); 168 static int lge_list_tx_init __P((struct lge_softc *)); 169 170 #ifdef LGE_USEIOSPACE 171 #define LGE_RES SYS_RES_IOPORT 172 #define LGE_RID LGE_PCI_LOIO 173 #else 174 #define LGE_RES SYS_RES_MEMORY 175 #define LGE_RID LGE_PCI_LOMEM 176 #endif 177 178 static device_method_t lge_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, lge_probe), 181 DEVMETHOD(device_attach, lge_attach), 182 DEVMETHOD(device_detach, lge_detach), 183 DEVMETHOD(device_shutdown, lge_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 191 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 192 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 193 194 { 0, 0 } 195 }; 196 197 static driver_t lge_driver = { 198 "lge", 199 lge_methods, 200 sizeof(struct lge_softc) 201 }; 202 203 static devclass_t lge_devclass; 204 205 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 206 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 207 208 #define LGE_SETBIT(sc, reg, x) \ 209 CSR_WRITE_4(sc, reg, \ 210 CSR_READ_4(sc, reg) | (x)) 211 212 #define LGE_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_4(sc, reg, \ 214 CSR_READ_4(sc, reg) & ~(x)) 215 216 #define SIO_SET(x) \ 217 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 218 219 #define SIO_CLR(x) \ 220 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 221 222 /* 223 * Read a word of data stored in the EEPROM at address 'addr.' 224 */ 225 static void lge_eeprom_getword(sc, addr, dest) 226 struct lge_softc *sc; 227 int addr; 228 u_int16_t *dest; 229 { 230 register int i; 231 u_int32_t val; 232 233 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 234 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 235 236 for (i = 0; i < LGE_TIMEOUT; i++) 237 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 238 break; 239 240 if (i == LGE_TIMEOUT) { 241 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 242 return; 243 } 244 245 val = CSR_READ_4(sc, LGE_EEDATA); 246 247 if (addr & 1) 248 *dest = (val >> 16) & 0xFFFF; 249 else 250 *dest = val & 0xFFFF; 251 252 return; 253 } 254 255 /* 256 * Read a sequence of words from the EEPROM. 257 */ 258 static void lge_read_eeprom(sc, dest, off, cnt, swap) 259 struct lge_softc *sc; 260 caddr_t dest; 261 int off; 262 int cnt; 263 int swap; 264 { 265 int i; 266 u_int16_t word = 0, *ptr; 267 268 for (i = 0; i < cnt; i++) { 269 lge_eeprom_getword(sc, off + i, &word); 270 ptr = (u_int16_t *)(dest + (i * 2)); 271 if (swap) 272 *ptr = ntohs(word); 273 else 274 *ptr = word; 275 } 276 277 return; 278 } 279 280 static int lge_miibus_readreg(dev, phy, reg) 281 device_t dev; 282 int phy, reg; 283 { 284 struct lge_softc *sc; 285 int i; 286 287 sc = device_get_softc(dev); 288 289 /* 290 * If we have a non-PCS PHY, pretend that the internal 291 * autoneg stuff at PHY address 0 isn't there so that 292 * the miibus code will find only the GMII PHY. 293 */ 294 if (sc->lge_pcs == 0 && phy == 0) 295 return(0); 296 297 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 298 299 for (i = 0; i < LGE_TIMEOUT; i++) 300 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 301 break; 302 303 if (i == LGE_TIMEOUT) { 304 printf("lge%d: PHY read timed out\n", sc->lge_unit); 305 return(0); 306 } 307 308 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 309 } 310 311 static int lge_miibus_writereg(dev, phy, reg, data) 312 device_t dev; 313 int phy, reg, data; 314 { 315 struct lge_softc *sc; 316 int i; 317 318 sc = device_get_softc(dev); 319 320 CSR_WRITE_4(sc, LGE_GMIICTL, 321 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 322 323 for (i = 0; i < LGE_TIMEOUT; i++) 324 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 325 break; 326 327 if (i == LGE_TIMEOUT) { 328 printf("lge%d: PHY write timed out\n", sc->lge_unit); 329 return(0); 330 } 331 332 return(0); 333 } 334 335 static void lge_miibus_statchg(dev) 336 device_t dev; 337 { 338 struct lge_softc *sc; 339 struct mii_data *mii; 340 341 sc = device_get_softc(dev); 342 mii = device_get_softc(sc->lge_miibus); 343 344 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 345 switch (IFM_SUBTYPE(mii->mii_media_active)) { 346 case IFM_1000_TX: 347 case IFM_1000_SX: 348 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 349 break; 350 case IFM_100_TX: 351 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 352 break; 353 case IFM_10_T: 354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 355 break; 356 default: 357 /* 358 * Choose something, even if it's wrong. Clearing 359 * all the bits will hose autoneg on the internal 360 * PHY. 361 */ 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 363 break; 364 } 365 366 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 367 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 368 } else { 369 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 370 } 371 372 return; 373 } 374 375 static u_int32_t lge_crc(sc, addr) 376 struct lge_softc *sc; 377 caddr_t addr; 378 { 379 u_int32_t crc, carry; 380 int i, j; 381 u_int8_t c; 382 383 /* Compute CRC for the address value. */ 384 crc = 0xFFFFFFFF; /* initial value */ 385 386 for (i = 0; i < 6; i++) { 387 c = *(addr + i); 388 for (j = 0; j < 8; j++) { 389 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 390 crc <<= 1; 391 c >>= 1; 392 if (carry) 393 crc = (crc ^ 0x04c11db6) | carry; 394 } 395 } 396 397 /* 398 * return the filter bit position 399 */ 400 return((crc >> 26) & 0x0000003F); 401 } 402 403 static void lge_setmulti(sc) 404 struct lge_softc *sc; 405 { 406 struct ifnet *ifp; 407 struct ifmultiaddr *ifma; 408 u_int32_t h = 0, hashes[2] = { 0, 0 }; 409 410 ifp = &sc->arpcom.ac_if; 411 412 /* Make sure multicast hash table is enabled. */ 413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 414 415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 416 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 417 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 418 return; 419 } 420 421 /* first, zot all the existing hash bits */ 422 CSR_WRITE_4(sc, LGE_MAR0, 0); 423 CSR_WRITE_4(sc, LGE_MAR1, 0); 424 425 /* now program new ones */ 426 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 427 if (ifma->ifma_addr->sa_family != AF_LINK) 428 continue; 429 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 430 if (h < 32) 431 hashes[0] |= (1 << h); 432 else 433 hashes[1] |= (1 << (h - 32)); 434 } 435 436 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 437 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 438 439 return; 440 } 441 442 static void lge_reset(sc) 443 struct lge_softc *sc; 444 { 445 register int i; 446 447 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 448 449 for (i = 0; i < LGE_TIMEOUT; i++) { 450 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 451 break; 452 } 453 454 if (i == LGE_TIMEOUT) 455 printf("lge%d: reset never completed\n", sc->lge_unit); 456 457 /* Wait a little while for the chip to get its brains in order. */ 458 DELAY(1000); 459 460 return; 461 } 462 463 /* 464 * Probe for a Level 1 chip. Check the PCI vendor and device 465 * IDs against our list and return a device name if we find a match. 466 */ 467 static int lge_probe(dev) 468 device_t dev; 469 { 470 struct lge_type *t; 471 472 t = lge_devs; 473 474 while(t->lge_name != NULL) { 475 if ((pci_get_vendor(dev) == t->lge_vid) && 476 (pci_get_device(dev) == t->lge_did)) { 477 device_set_desc(dev, t->lge_name); 478 return(0); 479 } 480 t++; 481 } 482 483 return(ENXIO); 484 } 485 486 /* 487 * Attach the interface. Allocate softc structures, do ifmedia 488 * setup and ethernet/BPF attach. 489 */ 490 static int lge_attach(dev) 491 device_t dev; 492 { 493 int s; 494 u_char eaddr[ETHER_ADDR_LEN]; 495 u_int32_t command; 496 struct lge_softc *sc; 497 struct ifnet *ifp; 498 int unit, error = 0, rid; 499 500 s = splimp(); 501 502 sc = device_get_softc(dev); 503 unit = device_get_unit(dev); 504 bzero(sc, sizeof(struct lge_softc)); 505 506 /* 507 * Handle power management nonsense. 508 */ 509 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 510 u_int32_t iobase, membase, irq; 511 512 /* Save important PCI config data. */ 513 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 514 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 515 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 516 517 /* Reset the power state. */ 518 printf("lge%d: chip is in D%d power mode " 519 "-- setting to D0\n", unit, 520 pci_get_powerstate(dev)); 521 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 522 523 /* Restore PCI config data. */ 524 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 525 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 526 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 527 } 528 529 /* 530 * Map control/status registers. 531 */ 532 pci_enable_busmaster(dev); 533 pci_enable_io(dev, SYS_RES_IOPORT); 534 pci_enable_io(dev, SYS_RES_MEMORY); 535 command = pci_read_config(dev, PCIR_COMMAND, 4); 536 537 #ifdef LGE_USEIOSPACE 538 if (!(command & PCIM_CMD_PORTEN)) { 539 printf("lge%d: failed to enable I/O ports!\n", unit); 540 error = ENXIO;; 541 goto fail; 542 } 543 #else 544 if (!(command & PCIM_CMD_MEMEN)) { 545 printf("lge%d: failed to enable memory mapping!\n", unit); 546 error = ENXIO;; 547 goto fail; 548 } 549 #endif 550 551 rid = LGE_RID; 552 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 553 0, ~0, 1, RF_ACTIVE); 554 555 if (sc->lge_res == NULL) { 556 printf("lge%d: couldn't map ports/memory\n", unit); 557 error = ENXIO; 558 goto fail; 559 } 560 561 sc->lge_btag = rman_get_bustag(sc->lge_res); 562 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 563 564 /* Allocate interrupt */ 565 rid = 0; 566 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 567 RF_SHAREABLE | RF_ACTIVE); 568 569 if (sc->lge_irq == NULL) { 570 printf("lge%d: couldn't map interrupt\n", unit); 571 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 572 error = ENXIO; 573 goto fail; 574 } 575 576 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 577 lge_intr, sc, &sc->lge_intrhand); 578 579 if (error) { 580 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 581 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 582 printf("lge%d: couldn't set up irq\n", unit); 583 goto fail; 584 } 585 586 /* Reset the adapter. */ 587 lge_reset(sc); 588 589 /* 590 * Get station address from the EEPROM. 591 */ 592 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 593 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 594 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 595 596 /* 597 * A Level 1 chip was detected. Inform the world. 598 */ 599 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 600 601 sc->lge_unit = unit; 602 callout_handle_init(&sc->lge_stat_ch); 603 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 604 605 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 606 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 607 608 if (sc->lge_ldata == NULL) { 609 printf("lge%d: no memory for list buffers!\n", unit); 610 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 611 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 612 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 613 error = ENXIO; 614 goto fail; 615 } 616 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 617 618 /* Try to allocate memory for jumbo buffers. */ 619 if (lge_alloc_jumbo_mem(sc)) { 620 printf("lge%d: jumbo buffer allocation failed\n", 621 sc->lge_unit); 622 contigfree(sc->lge_ldata, 623 sizeof(struct lge_list_data), M_DEVBUF); 624 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 625 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 626 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 627 error = ENXIO; 628 goto fail; 629 } 630 631 ifp = &sc->arpcom.ac_if; 632 ifp->if_softc = sc; 633 ifp->if_unit = unit; 634 ifp->if_name = "lge"; 635 ifp->if_mtu = ETHERMTU; 636 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 637 ifp->if_ioctl = lge_ioctl; 638 ifp->if_output = ether_output; 639 ifp->if_start = lge_start; 640 ifp->if_watchdog = lge_watchdog; 641 ifp->if_init = lge_init; 642 ifp->if_baudrate = 1000000000; 643 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 644 ifp->if_capabilities = IFCAP_RXCSUM; 645 ifp->if_capenable = ifp->if_capabilities; 646 647 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 648 sc->lge_pcs = 1; 649 else 650 sc->lge_pcs = 0; 651 652 /* 653 * Do MII setup. 654 */ 655 if (mii_phy_probe(dev, &sc->lge_miibus, 656 lge_ifmedia_upd, lge_ifmedia_sts)) { 657 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 658 contigfree(sc->lge_ldata, 659 sizeof(struct lge_list_data), M_DEVBUF); 660 lge_free_jumbo_mem(sc); 661 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 662 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 663 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 664 error = ENXIO; 665 goto fail; 666 } 667 668 /* 669 * Call MI attach routine. 670 */ 671 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 672 callout_handle_init(&sc->lge_stat_ch); 673 674 fail: 675 splx(s); 676 return(error); 677 } 678 679 static int lge_detach(dev) 680 device_t dev; 681 { 682 struct lge_softc *sc; 683 struct ifnet *ifp; 684 int s; 685 686 s = splimp(); 687 688 sc = device_get_softc(dev); 689 ifp = &sc->arpcom.ac_if; 690 691 lge_reset(sc); 692 lge_stop(sc); 693 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 694 695 bus_generic_detach(dev); 696 device_delete_child(dev, sc->lge_miibus); 697 698 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 699 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 700 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 701 702 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 703 lge_free_jumbo_mem(sc); 704 705 splx(s); 706 707 return(0); 708 } 709 710 /* 711 * Initialize the transmit descriptors. 712 */ 713 static int lge_list_tx_init(sc) 714 struct lge_softc *sc; 715 { 716 struct lge_list_data *ld; 717 struct lge_ring_data *cd; 718 int i; 719 720 cd = &sc->lge_cdata; 721 ld = sc->lge_ldata; 722 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 723 ld->lge_tx_list[i].lge_mbuf = NULL; 724 ld->lge_tx_list[i].lge_ctl = 0; 725 } 726 727 cd->lge_tx_prod = cd->lge_tx_cons = 0; 728 729 return(0); 730 } 731 732 733 /* 734 * Initialize the RX descriptors and allocate mbufs for them. Note that 735 * we arralge the descriptors in a closed ring, so that the last descriptor 736 * points back to the first. 737 */ 738 static int lge_list_rx_init(sc) 739 struct lge_softc *sc; 740 { 741 struct lge_list_data *ld; 742 struct lge_ring_data *cd; 743 int i; 744 745 ld = sc->lge_ldata; 746 cd = &sc->lge_cdata; 747 748 cd->lge_rx_prod = cd->lge_rx_cons = 0; 749 750 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 751 752 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 753 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 754 break; 755 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 756 return(ENOBUFS); 757 } 758 759 /* Clear possible 'rx command queue empty' interrupt. */ 760 CSR_READ_4(sc, LGE_ISR); 761 762 return(0); 763 } 764 765 /* 766 * Initialize an RX descriptor and attach an MBUF cluster. 767 */ 768 static int lge_newbuf(sc, c, m) 769 struct lge_softc *sc; 770 struct lge_rx_desc *c; 771 struct mbuf *m; 772 { 773 struct mbuf *m_new = NULL; 774 caddr_t *buf = NULL; 775 776 if (m == NULL) { 777 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 778 if (m_new == NULL) { 779 printf("lge%d: no memory for rx list " 780 "-- packet dropped!\n", sc->lge_unit); 781 return(ENOBUFS); 782 } 783 784 /* Allocate the jumbo buffer */ 785 buf = lge_jalloc(sc); 786 if (buf == NULL) { 787 #ifdef LGE_VERBOSE 788 printf("lge%d: jumbo allocation failed " 789 "-- packet dropped!\n", sc->lge_unit); 790 #endif 791 m_freem(m_new); 792 return(ENOBUFS); 793 } 794 /* Attach the buffer to the mbuf */ 795 m_new->m_data = (void *)buf; 796 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 797 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 798 (struct lge_softc *)sc, 0, EXT_NET_DRV); 799 } else { 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 805 /* 806 * Adjust alignment so packet payload begins on a 807 * longword boundary. Mandatory for Alpha, useful on 808 * x86 too. 809 */ 810 m_adj(m_new, ETHER_ALIGN); 811 812 c->lge_mbuf = m_new; 813 c->lge_fragptr_hi = 0; 814 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 815 c->lge_fraglen = m_new->m_len; 816 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 817 c->lge_sts = 0; 818 819 /* 820 * Put this buffer in the RX command FIFO. To do this, 821 * we just write the physical address of the descriptor 822 * into the RX descriptor address registers. Note that 823 * there are two registers, one high DWORD and one low 824 * DWORD, which lets us specify a 64-bit address if 825 * desired. We only use a 32-bit address for now. 826 * Writing to the low DWORD register is what actually 827 * causes the command to be issued, so we do that 828 * last. 829 */ 830 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 831 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 832 833 return(0); 834 } 835 836 static int lge_alloc_jumbo_mem(sc) 837 struct lge_softc *sc; 838 { 839 caddr_t ptr; 840 register int i; 841 struct lge_jpool_entry *entry; 842 843 /* Grab a big chunk o' storage. */ 844 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 845 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 846 847 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 848 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 849 return(ENOBUFS); 850 } 851 852 SLIST_INIT(&sc->lge_jfree_listhead); 853 SLIST_INIT(&sc->lge_jinuse_listhead); 854 855 /* 856 * Now divide it up into 9K pieces and save the addresses 857 * in an array. 858 */ 859 ptr = sc->lge_cdata.lge_jumbo_buf; 860 for (i = 0; i < LGE_JSLOTS; i++) { 861 sc->lge_cdata.lge_jslots[i] = ptr; 862 ptr += LGE_JLEN; 863 entry = malloc(sizeof(struct lge_jpool_entry), 864 M_DEVBUF, M_NOWAIT); 865 if (entry == NULL) { 866 printf("lge%d: no memory for jumbo " 867 "buffer queue!\n", sc->lge_unit); 868 return(ENOBUFS); 869 } 870 entry->slot = i; 871 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 872 entry, jpool_entries); 873 } 874 875 return(0); 876 } 877 878 static void lge_free_jumbo_mem(sc) 879 struct lge_softc *sc; 880 { 881 int i; 882 struct lge_jpool_entry *entry; 883 884 for (i = 0; i < LGE_JSLOTS; i++) { 885 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 886 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 887 free(entry, M_DEVBUF); 888 } 889 890 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 891 892 return; 893 } 894 895 /* 896 * Allocate a jumbo buffer. 897 */ 898 static void *lge_jalloc(sc) 899 struct lge_softc *sc; 900 { 901 struct lge_jpool_entry *entry; 902 903 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 904 905 if (entry == NULL) { 906 #ifdef LGE_VERBOSE 907 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 908 #endif 909 return(NULL); 910 } 911 912 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 913 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 914 return(sc->lge_cdata.lge_jslots[entry->slot]); 915 } 916 917 /* 918 * Release a jumbo buffer. 919 */ 920 static void lge_jfree(buf, args) 921 caddr_t buf; 922 void *args; 923 { 924 struct lge_softc *sc; 925 int i; 926 struct lge_jpool_entry *entry; 927 928 /* Extract the softc struct pointer. */ 929 sc = args; 930 931 if (sc == NULL) 932 panic("lge_jfree: can't find softc pointer!"); 933 934 /* calculate the slot this buffer belongs to */ 935 i = ((vm_offset_t)buf 936 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 937 938 if ((i < 0) || (i >= LGE_JSLOTS)) 939 panic("lge_jfree: asked to free buffer that we don't manage!"); 940 941 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 942 if (entry == NULL) 943 panic("lge_jfree: buffer not in use!"); 944 entry->slot = i; 945 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 946 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 947 948 return; 949 } 950 951 /* 952 * A frame has been uploaded: pass the resulting mbuf chain up to 953 * the higher level protocols. 954 */ 955 static void lge_rxeof(sc, cnt) 956 struct lge_softc *sc; 957 int cnt; 958 { 959 struct ether_header *eh; 960 struct mbuf *m; 961 struct ifnet *ifp; 962 struct lge_rx_desc *cur_rx; 963 int c, i, total_len = 0; 964 u_int32_t rxsts, rxctl; 965 966 ifp = &sc->arpcom.ac_if; 967 968 /* Find out how many frames were processed. */ 969 c = cnt; 970 i = sc->lge_cdata.lge_rx_cons; 971 972 /* Suck them in. */ 973 while(c) { 974 struct mbuf *m0 = NULL; 975 976 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 977 rxctl = cur_rx->lge_ctl; 978 rxsts = cur_rx->lge_sts; 979 m = cur_rx->lge_mbuf; 980 cur_rx->lge_mbuf = NULL; 981 total_len = LGE_RXBYTES(cur_rx); 982 LGE_INC(i, LGE_RX_LIST_CNT); 983 c--; 984 985 /* 986 * If an error occurs, update stats, clear the 987 * status word and leave the mbuf cluster in place: 988 * it should simply get re-used next time this descriptor 989 * comes up in the ring. 990 */ 991 if (rxctl & LGE_RXCTL_ERRMASK) { 992 ifp->if_ierrors++; 993 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 994 continue; 995 } 996 997 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 998 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 999 ifp, NULL); 1000 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1001 if (m0 == NULL) { 1002 printf("lge%d: no receive buffers " 1003 "available -- packet dropped!\n", 1004 sc->lge_unit); 1005 ifp->if_ierrors++; 1006 continue; 1007 } 1008 m = m0; 1009 } else { 1010 m->m_pkthdr.rcvif = ifp; 1011 m->m_pkthdr.len = m->m_len = total_len; 1012 } 1013 1014 ifp->if_ipackets++; 1015 eh = mtod(m, struct ether_header *); 1016 1017 /* Remove header from mbuf and pass it on. */ 1018 m_adj(m, sizeof(struct ether_header)); 1019 1020 /* Do IP checksum checking. */ 1021 if (rxsts & LGE_RXSTS_ISIP) 1022 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1023 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1024 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1025 if ((rxsts & LGE_RXSTS_ISTCP && 1026 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1027 (rxsts & LGE_RXSTS_ISUDP && 1028 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1029 m->m_pkthdr.csum_flags |= 1030 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1031 m->m_pkthdr.csum_data = 0xffff; 1032 } 1033 1034 ether_input(ifp, eh, m); 1035 } 1036 1037 sc->lge_cdata.lge_rx_cons = i; 1038 1039 return; 1040 } 1041 1042 void lge_rxeoc(sc) 1043 struct lge_softc *sc; 1044 { 1045 struct ifnet *ifp; 1046 1047 ifp = &sc->arpcom.ac_if; 1048 ifp->if_flags &= ~IFF_RUNNING; 1049 lge_init(sc); 1050 return; 1051 } 1052 1053 /* 1054 * A frame was downloaded to the chip. It's safe for us to clean up 1055 * the list buffers. 1056 */ 1057 1058 static void lge_txeof(sc) 1059 struct lge_softc *sc; 1060 { 1061 struct lge_tx_desc *cur_tx = NULL; 1062 struct ifnet *ifp; 1063 u_int32_t idx, txdone; 1064 1065 ifp = &sc->arpcom.ac_if; 1066 1067 /* Clear the timeout timer. */ 1068 ifp->if_timer = 0; 1069 1070 /* 1071 * Go through our tx list and free mbufs for those 1072 * frames that have been transmitted. 1073 */ 1074 idx = sc->lge_cdata.lge_tx_cons; 1075 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1076 1077 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1078 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1079 1080 ifp->if_opackets++; 1081 if (cur_tx->lge_mbuf != NULL) { 1082 m_freem(cur_tx->lge_mbuf); 1083 cur_tx->lge_mbuf = NULL; 1084 } 1085 cur_tx->lge_ctl = 0; 1086 1087 txdone--; 1088 LGE_INC(idx, LGE_TX_LIST_CNT); 1089 ifp->if_timer = 0; 1090 } 1091 1092 sc->lge_cdata.lge_tx_cons = idx; 1093 1094 if (cur_tx != NULL) 1095 ifp->if_flags &= ~IFF_OACTIVE; 1096 1097 return; 1098 } 1099 1100 static void lge_tick(xsc) 1101 void *xsc; 1102 { 1103 struct lge_softc *sc; 1104 struct mii_data *mii; 1105 struct ifnet *ifp; 1106 int s; 1107 1108 s = splimp(); 1109 1110 sc = xsc; 1111 ifp = &sc->arpcom.ac_if; 1112 1113 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1114 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1115 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1116 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1117 1118 if (!sc->lge_link) { 1119 mii = device_get_softc(sc->lge_miibus); 1120 mii_tick(mii); 1121 if (mii->mii_media_status & IFM_ACTIVE && 1122 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1123 sc->lge_link++; 1124 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1125 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1126 printf("lge%d: gigabit link up\n", 1127 sc->lge_unit); 1128 if (ifp->if_snd.ifq_head != NULL) 1129 lge_start(ifp); 1130 } 1131 } 1132 1133 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1134 1135 splx(s); 1136 1137 return; 1138 } 1139 1140 static void lge_intr(arg) 1141 void *arg; 1142 { 1143 struct lge_softc *sc; 1144 struct ifnet *ifp; 1145 u_int32_t status; 1146 1147 sc = arg; 1148 ifp = &sc->arpcom.ac_if; 1149 1150 /* Supress unwanted interrupts */ 1151 if (!(ifp->if_flags & IFF_UP)) { 1152 lge_stop(sc); 1153 return; 1154 } 1155 1156 for (;;) { 1157 /* 1158 * Reading the ISR register clears all interrupts, and 1159 * clears the 'interrupts enabled' bit in the IMR 1160 * register. 1161 */ 1162 status = CSR_READ_4(sc, LGE_ISR); 1163 1164 if ((status & LGE_INTRS) == 0) 1165 break; 1166 1167 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1168 lge_txeof(sc); 1169 1170 if (status & LGE_ISR_RXDMA_DONE) 1171 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1172 1173 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1174 lge_rxeoc(sc); 1175 1176 if (status & LGE_ISR_PHY_INTR) { 1177 sc->lge_link = 0; 1178 untimeout(lge_tick, sc, sc->lge_stat_ch); 1179 lge_tick(sc); 1180 } 1181 } 1182 1183 /* Re-enable interrupts. */ 1184 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1185 1186 if (ifp->if_snd.ifq_head != NULL) 1187 lge_start(ifp); 1188 1189 return; 1190 } 1191 1192 /* 1193 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1194 * pointers to the fragment pointers. 1195 */ 1196 static int lge_encap(sc, m_head, txidx) 1197 struct lge_softc *sc; 1198 struct mbuf *m_head; 1199 u_int32_t *txidx; 1200 { 1201 struct lge_frag *f = NULL; 1202 struct lge_tx_desc *cur_tx; 1203 struct mbuf *m; 1204 int frag = 0, tot_len = 0; 1205 1206 /* 1207 * Start packing the mbufs in this chain into 1208 * the fragment pointers. Stop when we run out 1209 * of fragments or hit the end of the mbuf chain. 1210 */ 1211 m = m_head; 1212 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1213 frag = 0; 1214 1215 for (m = m_head; m != NULL; m = m->m_next) { 1216 if (m->m_len != 0) { 1217 tot_len += m->m_len; 1218 f = &cur_tx->lge_frags[frag]; 1219 f->lge_fraglen = m->m_len; 1220 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1221 f->lge_fragptr_hi = 0; 1222 frag++; 1223 } 1224 } 1225 1226 if (m != NULL) 1227 return(ENOBUFS); 1228 1229 cur_tx->lge_mbuf = m_head; 1230 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1231 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1232 1233 /* Queue for transmit */ 1234 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1235 1236 return(0); 1237 } 1238 1239 /* 1240 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1241 * to the mbuf data regions directly in the transmit lists. We also save a 1242 * copy of the pointers since the transmit list fragment pointers are 1243 * physical addresses. 1244 */ 1245 1246 static void lge_start(ifp) 1247 struct ifnet *ifp; 1248 { 1249 struct lge_softc *sc; 1250 struct mbuf *m_head = NULL; 1251 u_int32_t idx; 1252 1253 sc = ifp->if_softc; 1254 1255 if (!sc->lge_link) 1256 return; 1257 1258 idx = sc->lge_cdata.lge_tx_prod; 1259 1260 if (ifp->if_flags & IFF_OACTIVE) 1261 return; 1262 1263 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1264 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1265 break; 1266 1267 IF_DEQUEUE(&ifp->if_snd, m_head); 1268 if (m_head == NULL) 1269 break; 1270 1271 if (lge_encap(sc, m_head, &idx)) { 1272 IF_PREPEND(&ifp->if_snd, m_head); 1273 ifp->if_flags |= IFF_OACTIVE; 1274 break; 1275 } 1276 1277 /* 1278 * If there's a BPF listener, bounce a copy of this frame 1279 * to him. 1280 */ 1281 if (ifp->if_bpf) 1282 bpf_mtap(ifp, m_head); 1283 } 1284 1285 sc->lge_cdata.lge_tx_prod = idx; 1286 1287 /* 1288 * Set a timeout in case the chip goes out to lunch. 1289 */ 1290 ifp->if_timer = 5; 1291 1292 return; 1293 } 1294 1295 static void lge_init(xsc) 1296 void *xsc; 1297 { 1298 struct lge_softc *sc = xsc; 1299 struct ifnet *ifp = &sc->arpcom.ac_if; 1300 struct mii_data *mii; 1301 int s; 1302 1303 if (ifp->if_flags & IFF_RUNNING) 1304 return; 1305 1306 s = splimp(); 1307 1308 /* 1309 * Cancel pending I/O and free all RX/TX buffers. 1310 */ 1311 lge_stop(sc); 1312 lge_reset(sc); 1313 1314 mii = device_get_softc(sc->lge_miibus); 1315 1316 /* Set MAC address */ 1317 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1318 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1319 1320 /* Init circular RX list. */ 1321 if (lge_list_rx_init(sc) == ENOBUFS) { 1322 printf("lge%d: initialization failed: no " 1323 "memory for rx buffers\n", sc->lge_unit); 1324 lge_stop(sc); 1325 (void)splx(s); 1326 return; 1327 } 1328 1329 /* 1330 * Init tx descriptors. 1331 */ 1332 lge_list_tx_init(sc); 1333 1334 /* Set initial value for MODE1 register. */ 1335 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1336 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1337 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1338 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1339 1340 /* If we want promiscuous mode, set the allframes bit. */ 1341 if (ifp->if_flags & IFF_PROMISC) { 1342 CSR_WRITE_4(sc, LGE_MODE1, 1343 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1344 } else { 1345 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1346 } 1347 1348 /* 1349 * Set the capture broadcast bit to capture broadcast frames. 1350 */ 1351 if (ifp->if_flags & IFF_BROADCAST) { 1352 CSR_WRITE_4(sc, LGE_MODE1, 1353 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1354 } else { 1355 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1356 } 1357 1358 /* Packet padding workaround? */ 1359 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1360 1361 /* No error frames */ 1362 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1363 1364 /* Receive large frames */ 1365 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1366 1367 /* Workaround: disable RX/TX flow control */ 1368 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1369 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1370 1371 /* Make sure to strip CRC from received frames */ 1372 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1373 1374 /* Turn off magic packet mode */ 1375 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1376 1377 /* Turn off all VLAN stuff */ 1378 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1379 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1380 1381 /* Workarond: FIFO overflow */ 1382 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1383 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1384 1385 /* 1386 * Load the multicast filter. 1387 */ 1388 lge_setmulti(sc); 1389 1390 /* 1391 * Enable hardware checksum validation for all received IPv4 1392 * packets, do not reject packets with bad checksums. 1393 */ 1394 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1395 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1396 LGE_MODE2_RX_ERRCSUM); 1397 1398 /* 1399 * Enable the delivery of PHY interrupts based on 1400 * link/speed/duplex status chalges. 1401 */ 1402 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1403 1404 /* Enable receiver and transmitter. */ 1405 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1406 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1407 1408 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1409 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1410 1411 /* 1412 * Enable interrupts. 1413 */ 1414 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1415 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1416 1417 lge_ifmedia_upd(ifp); 1418 1419 ifp->if_flags |= IFF_RUNNING; 1420 ifp->if_flags &= ~IFF_OACTIVE; 1421 1422 (void)splx(s); 1423 1424 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1425 1426 return; 1427 } 1428 1429 /* 1430 * Set media options. 1431 */ 1432 static int lge_ifmedia_upd(ifp) 1433 struct ifnet *ifp; 1434 { 1435 struct lge_softc *sc; 1436 struct mii_data *mii; 1437 1438 sc = ifp->if_softc; 1439 1440 mii = device_get_softc(sc->lge_miibus); 1441 sc->lge_link = 0; 1442 if (mii->mii_instance) { 1443 struct mii_softc *miisc; 1444 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1445 miisc = LIST_NEXT(miisc, mii_list)) 1446 mii_phy_reset(miisc); 1447 } 1448 mii_mediachg(mii); 1449 1450 return(0); 1451 } 1452 1453 /* 1454 * Report current media status. 1455 */ 1456 static void lge_ifmedia_sts(ifp, ifmr) 1457 struct ifnet *ifp; 1458 struct ifmediareq *ifmr; 1459 { 1460 struct lge_softc *sc; 1461 struct mii_data *mii; 1462 1463 sc = ifp->if_softc; 1464 1465 mii = device_get_softc(sc->lge_miibus); 1466 mii_pollstat(mii); 1467 ifmr->ifm_active = mii->mii_media_active; 1468 ifmr->ifm_status = mii->mii_media_status; 1469 1470 return; 1471 } 1472 1473 static int lge_ioctl(ifp, command, data) 1474 struct ifnet *ifp; 1475 u_long command; 1476 caddr_t data; 1477 { 1478 struct lge_softc *sc = ifp->if_softc; 1479 struct ifreq *ifr = (struct ifreq *) data; 1480 struct mii_data *mii; 1481 int s, error = 0; 1482 1483 s = splimp(); 1484 1485 switch(command) { 1486 case SIOCSIFADDR: 1487 case SIOCGIFADDR: 1488 error = ether_ioctl(ifp, command, data); 1489 break; 1490 case SIOCSIFMTU: 1491 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1492 error = EINVAL; 1493 else 1494 ifp->if_mtu = ifr->ifr_mtu; 1495 break; 1496 case SIOCSIFFLAGS: 1497 if (ifp->if_flags & IFF_UP) { 1498 if (ifp->if_flags & IFF_RUNNING && 1499 ifp->if_flags & IFF_PROMISC && 1500 !(sc->lge_if_flags & IFF_PROMISC)) { 1501 CSR_WRITE_4(sc, LGE_MODE1, 1502 LGE_MODE1_SETRST_CTL1| 1503 LGE_MODE1_RX_PROMISC); 1504 } else if (ifp->if_flags & IFF_RUNNING && 1505 !(ifp->if_flags & IFF_PROMISC) && 1506 sc->lge_if_flags & IFF_PROMISC) { 1507 CSR_WRITE_4(sc, LGE_MODE1, 1508 LGE_MODE1_RX_PROMISC); 1509 } else { 1510 ifp->if_flags &= ~IFF_RUNNING; 1511 lge_init(sc); 1512 } 1513 } else { 1514 if (ifp->if_flags & IFF_RUNNING) 1515 lge_stop(sc); 1516 } 1517 sc->lge_if_flags = ifp->if_flags; 1518 error = 0; 1519 break; 1520 case SIOCADDMULTI: 1521 case SIOCDELMULTI: 1522 lge_setmulti(sc); 1523 error = 0; 1524 break; 1525 case SIOCGIFMEDIA: 1526 case SIOCSIFMEDIA: 1527 mii = device_get_softc(sc->lge_miibus); 1528 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1529 break; 1530 default: 1531 error = EINVAL; 1532 break; 1533 } 1534 1535 (void)splx(s); 1536 1537 return(error); 1538 } 1539 1540 static void lge_watchdog(ifp) 1541 struct ifnet *ifp; 1542 { 1543 struct lge_softc *sc; 1544 1545 sc = ifp->if_softc; 1546 1547 ifp->if_oerrors++; 1548 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1549 1550 lge_stop(sc); 1551 lge_reset(sc); 1552 ifp->if_flags &= ~IFF_RUNNING; 1553 lge_init(sc); 1554 1555 if (ifp->if_snd.ifq_head != NULL) 1556 lge_start(ifp); 1557 1558 return; 1559 } 1560 1561 /* 1562 * Stop the adapter and free any mbufs allocated to the 1563 * RX and TX lists. 1564 */ 1565 static void lge_stop(sc) 1566 struct lge_softc *sc; 1567 { 1568 register int i; 1569 struct ifnet *ifp; 1570 1571 ifp = &sc->arpcom.ac_if; 1572 ifp->if_timer = 0; 1573 untimeout(lge_tick, sc, sc->lge_stat_ch); 1574 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1575 1576 /* Disable receiver and transmitter. */ 1577 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1578 sc->lge_link = 0; 1579 1580 /* 1581 * Free data in the RX lists. 1582 */ 1583 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1584 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1585 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1586 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1587 } 1588 } 1589 bzero((char *)&sc->lge_ldata->lge_rx_list, 1590 sizeof(sc->lge_ldata->lge_rx_list)); 1591 1592 /* 1593 * Free the TX list buffers. 1594 */ 1595 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1596 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1597 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1598 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1599 } 1600 } 1601 1602 bzero((char *)&sc->lge_ldata->lge_tx_list, 1603 sizeof(sc->lge_ldata->lge_tx_list)); 1604 1605 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1606 1607 return; 1608 } 1609 1610 /* 1611 * Stop all chip I/O so that the kernel's probe routines don't 1612 * get confused by errant DMAs when rebooting. 1613 */ 1614 static void lge_shutdown(dev) 1615 device_t dev; 1616 { 1617 struct lge_softc *sc; 1618 1619 sc = device_get_softc(dev); 1620 1621 lge_reset(sc); 1622 lge_stop(sc); 1623 1624 return; 1625 } 1626