1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 #include <sys/socket.h> 80 81 #include <net/if.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 87 #include <net/bpf.h> 88 89 #include <vm/vm.h> /* for vtophys */ 90 #include <vm/pmap.h> /* for vtophys */ 91 #include <machine/clock.h> /* for DELAY */ 92 #include <machine/bus.h> 93 #include <machine/resource.h> 94 #include <sys/bus.h> 95 #include <sys/rman.h> 96 97 #include <dev/mii/mii.h> 98 #include <dev/mii/miivar.h> 99 100 #include <dev/pci/pcireg.h> 101 #include <dev/pci/pcivar.h> 102 103 #define LGE_USEIOSPACE 104 105 #include <dev/lge/if_lgereg.h> 106 107 /* "controller miibus0" required. See GENERIC if you get errors here. */ 108 #include "miibus_if.h" 109 110 /* 111 * Various supported device vendors/types and their names. 112 */ 113 static struct lge_type lge_devs[] = { 114 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 115 { 0, 0, NULL } 116 }; 117 118 static int lge_probe(device_t); 119 static int lge_attach(device_t); 120 static int lge_detach(device_t); 121 122 static int lge_alloc_jumbo_mem(struct lge_softc *); 123 static void lge_free_jumbo_mem(struct lge_softc *); 124 static void *lge_jalloc(struct lge_softc *); 125 static void lge_jfree(void *, void *); 126 127 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 128 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 129 static void lge_rxeof(struct lge_softc *, int); 130 static void lge_rxeoc(struct lge_softc *); 131 static void lge_txeof(struct lge_softc *); 132 static void lge_intr(void *); 133 static void lge_tick(void *); 134 static void lge_start(struct ifnet *); 135 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 136 static void lge_init(void *); 137 static void lge_stop(struct lge_softc *); 138 static void lge_watchdog(struct ifnet *); 139 static void lge_shutdown(device_t); 140 static int lge_ifmedia_upd(struct ifnet *); 141 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 142 143 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 144 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 145 146 static int lge_miibus_readreg(device_t, int, int); 147 static int lge_miibus_writereg(device_t, int, int, int); 148 static void lge_miibus_statchg(device_t); 149 150 static void lge_setmulti(struct lge_softc *); 151 static void lge_reset(struct lge_softc *); 152 static int lge_list_rx_init(struct lge_softc *); 153 static int lge_list_tx_init(struct lge_softc *); 154 155 #ifdef LGE_USEIOSPACE 156 #define LGE_RES SYS_RES_IOPORT 157 #define LGE_RID LGE_PCI_LOIO 158 #else 159 #define LGE_RES SYS_RES_MEMORY 160 #define LGE_RID LGE_PCI_LOMEM 161 #endif 162 163 static device_method_t lge_methods[] = { 164 /* Device interface */ 165 DEVMETHOD(device_probe, lge_probe), 166 DEVMETHOD(device_attach, lge_attach), 167 DEVMETHOD(device_detach, lge_detach), 168 DEVMETHOD(device_shutdown, lge_shutdown), 169 170 /* bus interface */ 171 DEVMETHOD(bus_print_child, bus_generic_print_child), 172 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 173 174 /* MII interface */ 175 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 176 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 177 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 178 179 { 0, 0 } 180 }; 181 182 static driver_t lge_driver = { 183 "lge", 184 lge_methods, 185 sizeof(struct lge_softc) 186 }; 187 188 static devclass_t lge_devclass; 189 190 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 191 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 192 MODULE_DEPEND(lge, pci, 1, 1, 1); 193 MODULE_DEPEND(lge, ether, 1, 1, 1); 194 MODULE_DEPEND(lge, miibus, 1, 1, 1); 195 196 #define LGE_SETBIT(sc, reg, x) \ 197 CSR_WRITE_4(sc, reg, \ 198 CSR_READ_4(sc, reg) | (x)) 199 200 #define LGE_CLRBIT(sc, reg, x) \ 201 CSR_WRITE_4(sc, reg, \ 202 CSR_READ_4(sc, reg) & ~(x)) 203 204 #define SIO_SET(x) \ 205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 206 207 #define SIO_CLR(x) \ 208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 209 210 /* 211 * Read a word of data stored in the EEPROM at address 'addr.' 212 */ 213 static void 214 lge_eeprom_getword(sc, addr, dest) 215 struct lge_softc *sc; 216 int addr; 217 u_int16_t *dest; 218 { 219 register int i; 220 u_int32_t val; 221 222 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 223 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 224 225 for (i = 0; i < LGE_TIMEOUT; i++) 226 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 227 break; 228 229 if (i == LGE_TIMEOUT) { 230 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 231 return; 232 } 233 234 val = CSR_READ_4(sc, LGE_EEDATA); 235 236 if (addr & 1) 237 *dest = (val >> 16) & 0xFFFF; 238 else 239 *dest = val & 0xFFFF; 240 241 return; 242 } 243 244 /* 245 * Read a sequence of words from the EEPROM. 246 */ 247 static void 248 lge_read_eeprom(sc, dest, off, cnt, swap) 249 struct lge_softc *sc; 250 caddr_t dest; 251 int off; 252 int cnt; 253 int swap; 254 { 255 int i; 256 u_int16_t word = 0, *ptr; 257 258 for (i = 0; i < cnt; i++) { 259 lge_eeprom_getword(sc, off + i, &word); 260 ptr = (u_int16_t *)(dest + (i * 2)); 261 if (swap) 262 *ptr = ntohs(word); 263 else 264 *ptr = word; 265 } 266 267 return; 268 } 269 270 static int 271 lge_miibus_readreg(dev, phy, reg) 272 device_t dev; 273 int phy, reg; 274 { 275 struct lge_softc *sc; 276 int i; 277 278 sc = device_get_softc(dev); 279 280 /* 281 * If we have a non-PCS PHY, pretend that the internal 282 * autoneg stuff at PHY address 0 isn't there so that 283 * the miibus code will find only the GMII PHY. 284 */ 285 if (sc->lge_pcs == 0 && phy == 0) 286 return(0); 287 288 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 289 290 for (i = 0; i < LGE_TIMEOUT; i++) 291 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 292 break; 293 294 if (i == LGE_TIMEOUT) { 295 printf("lge%d: PHY read timed out\n", sc->lge_unit); 296 return(0); 297 } 298 299 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 300 } 301 302 static int 303 lge_miibus_writereg(dev, phy, reg, data) 304 device_t dev; 305 int phy, reg, data; 306 { 307 struct lge_softc *sc; 308 int i; 309 310 sc = device_get_softc(dev); 311 312 CSR_WRITE_4(sc, LGE_GMIICTL, 313 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 314 315 for (i = 0; i < LGE_TIMEOUT; i++) 316 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 317 break; 318 319 if (i == LGE_TIMEOUT) { 320 printf("lge%d: PHY write timed out\n", sc->lge_unit); 321 return(0); 322 } 323 324 return(0); 325 } 326 327 static void 328 lge_miibus_statchg(dev) 329 device_t dev; 330 { 331 struct lge_softc *sc; 332 struct mii_data *mii; 333 334 sc = device_get_softc(dev); 335 mii = device_get_softc(sc->lge_miibus); 336 337 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 338 switch (IFM_SUBTYPE(mii->mii_media_active)) { 339 case IFM_1000_T: 340 case IFM_1000_SX: 341 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 342 break; 343 case IFM_100_TX: 344 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 345 break; 346 case IFM_10_T: 347 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 348 break; 349 default: 350 /* 351 * Choose something, even if it's wrong. Clearing 352 * all the bits will hose autoneg on the internal 353 * PHY. 354 */ 355 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 356 break; 357 } 358 359 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 360 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 361 } else { 362 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } 364 365 return; 366 } 367 368 static void 369 lge_setmulti(sc) 370 struct lge_softc *sc; 371 { 372 struct ifnet *ifp; 373 struct ifmultiaddr *ifma; 374 u_int32_t h = 0, hashes[2] = { 0, 0 }; 375 376 ifp = &sc->arpcom.ac_if; 377 378 /* Make sure multicast hash table is enabled. */ 379 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 380 381 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 382 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 383 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 384 return; 385 } 386 387 /* first, zot all the existing hash bits */ 388 CSR_WRITE_4(sc, LGE_MAR0, 0); 389 CSR_WRITE_4(sc, LGE_MAR1, 0); 390 391 /* now program new ones */ 392 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 393 if (ifma->ifma_addr->sa_family != AF_LINK) 394 continue; 395 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 396 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 397 if (h < 32) 398 hashes[0] |= (1 << h); 399 else 400 hashes[1] |= (1 << (h - 32)); 401 } 402 403 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 404 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 405 406 return; 407 } 408 409 static void 410 lge_reset(sc) 411 struct lge_softc *sc; 412 { 413 register int i; 414 415 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 416 417 for (i = 0; i < LGE_TIMEOUT; i++) { 418 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 419 break; 420 } 421 422 if (i == LGE_TIMEOUT) 423 printf("lge%d: reset never completed\n", sc->lge_unit); 424 425 /* Wait a little while for the chip to get its brains in order. */ 426 DELAY(1000); 427 428 return; 429 } 430 431 /* 432 * Probe for a Level 1 chip. Check the PCI vendor and device 433 * IDs against our list and return a device name if we find a match. 434 */ 435 static int 436 lge_probe(dev) 437 device_t dev; 438 { 439 struct lge_type *t; 440 441 t = lge_devs; 442 443 while(t->lge_name != NULL) { 444 if ((pci_get_vendor(dev) == t->lge_vid) && 445 (pci_get_device(dev) == t->lge_did)) { 446 device_set_desc(dev, t->lge_name); 447 return(BUS_PROBE_DEFAULT); 448 } 449 t++; 450 } 451 452 return(ENXIO); 453 } 454 455 /* 456 * Attach the interface. Allocate softc structures, do ifmedia 457 * setup and ethernet/BPF attach. 458 */ 459 static int 460 lge_attach(dev) 461 device_t dev; 462 { 463 int s; 464 u_char eaddr[ETHER_ADDR_LEN]; 465 struct lge_softc *sc; 466 struct ifnet *ifp; 467 int unit, error = 0, rid; 468 469 s = splimp(); 470 471 sc = device_get_softc(dev); 472 unit = device_get_unit(dev); 473 bzero(sc, sizeof(struct lge_softc)); 474 /* 475 * Map control/status registers. 476 */ 477 pci_enable_busmaster(dev); 478 479 rid = LGE_RID; 480 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 481 482 if (sc->lge_res == NULL) { 483 printf("lge%d: couldn't map ports/memory\n", unit); 484 error = ENXIO; 485 goto fail; 486 } 487 488 sc->lge_btag = rman_get_bustag(sc->lge_res); 489 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 490 491 /* Allocate interrupt */ 492 rid = 0; 493 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 494 RF_SHAREABLE | RF_ACTIVE); 495 496 if (sc->lge_irq == NULL) { 497 printf("lge%d: couldn't map interrupt\n", unit); 498 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 499 error = ENXIO; 500 goto fail; 501 } 502 503 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 504 lge_intr, sc, &sc->lge_intrhand); 505 506 if (error) { 507 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 508 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 509 printf("lge%d: couldn't set up irq\n", unit); 510 goto fail; 511 } 512 513 /* Reset the adapter. */ 514 lge_reset(sc); 515 516 /* 517 * Get station address from the EEPROM. 518 */ 519 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 520 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 521 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 522 523 sc->lge_unit = unit; 524 callout_handle_init(&sc->lge_stat_ch); 525 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 526 527 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 528 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 529 530 if (sc->lge_ldata == NULL) { 531 printf("lge%d: no memory for list buffers!\n", unit); 532 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 534 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 535 error = ENXIO; 536 goto fail; 537 } 538 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 539 540 /* Try to allocate memory for jumbo buffers. */ 541 if (lge_alloc_jumbo_mem(sc)) { 542 printf("lge%d: jumbo buffer allocation failed\n", 543 sc->lge_unit); 544 contigfree(sc->lge_ldata, 545 sizeof(struct lge_list_data), M_DEVBUF); 546 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 547 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 548 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 549 error = ENXIO; 550 goto fail; 551 } 552 553 ifp = &sc->arpcom.ac_if; 554 ifp->if_softc = sc; 555 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 556 ifp->if_mtu = ETHERMTU; 557 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 558 IFF_NEEDSGIANT; 559 ifp->if_ioctl = lge_ioctl; 560 ifp->if_start = lge_start; 561 ifp->if_watchdog = lge_watchdog; 562 ifp->if_init = lge_init; 563 ifp->if_baudrate = 1000000000; 564 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 565 ifp->if_capabilities = IFCAP_RXCSUM; 566 ifp->if_capenable = ifp->if_capabilities; 567 568 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 569 sc->lge_pcs = 1; 570 else 571 sc->lge_pcs = 0; 572 573 /* 574 * Do MII setup. 575 */ 576 if (mii_phy_probe(dev, &sc->lge_miibus, 577 lge_ifmedia_upd, lge_ifmedia_sts)) { 578 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 579 contigfree(sc->lge_ldata, 580 sizeof(struct lge_list_data), M_DEVBUF); 581 lge_free_jumbo_mem(sc); 582 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 583 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 584 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 585 error = ENXIO; 586 goto fail; 587 } 588 589 /* 590 * Call MI attach routine. 591 */ 592 ether_ifattach(ifp, eaddr); 593 callout_handle_init(&sc->lge_stat_ch); 594 595 fail: 596 splx(s); 597 return(error); 598 } 599 600 static int 601 lge_detach(dev) 602 device_t dev; 603 { 604 struct lge_softc *sc; 605 struct ifnet *ifp; 606 int s; 607 608 s = splimp(); 609 610 sc = device_get_softc(dev); 611 ifp = &sc->arpcom.ac_if; 612 613 lge_reset(sc); 614 lge_stop(sc); 615 ether_ifdetach(ifp); 616 617 bus_generic_detach(dev); 618 device_delete_child(dev, sc->lge_miibus); 619 620 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 621 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 622 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 623 624 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 625 lge_free_jumbo_mem(sc); 626 627 splx(s); 628 629 return(0); 630 } 631 632 /* 633 * Initialize the transmit descriptors. 634 */ 635 static int 636 lge_list_tx_init(sc) 637 struct lge_softc *sc; 638 { 639 struct lge_list_data *ld; 640 struct lge_ring_data *cd; 641 int i; 642 643 cd = &sc->lge_cdata; 644 ld = sc->lge_ldata; 645 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 646 ld->lge_tx_list[i].lge_mbuf = NULL; 647 ld->lge_tx_list[i].lge_ctl = 0; 648 } 649 650 cd->lge_tx_prod = cd->lge_tx_cons = 0; 651 652 return(0); 653 } 654 655 656 /* 657 * Initialize the RX descriptors and allocate mbufs for them. Note that 658 * we arralge the descriptors in a closed ring, so that the last descriptor 659 * points back to the first. 660 */ 661 static int 662 lge_list_rx_init(sc) 663 struct lge_softc *sc; 664 { 665 struct lge_list_data *ld; 666 struct lge_ring_data *cd; 667 int i; 668 669 ld = sc->lge_ldata; 670 cd = &sc->lge_cdata; 671 672 cd->lge_rx_prod = cd->lge_rx_cons = 0; 673 674 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 675 676 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 677 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 678 break; 679 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 680 return(ENOBUFS); 681 } 682 683 /* Clear possible 'rx command queue empty' interrupt. */ 684 CSR_READ_4(sc, LGE_ISR); 685 686 return(0); 687 } 688 689 /* 690 * Initialize an RX descriptor and attach an MBUF cluster. 691 */ 692 static int 693 lge_newbuf(sc, c, m) 694 struct lge_softc *sc; 695 struct lge_rx_desc *c; 696 struct mbuf *m; 697 { 698 struct mbuf *m_new = NULL; 699 caddr_t *buf = NULL; 700 701 if (m == NULL) { 702 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 703 if (m_new == NULL) { 704 printf("lge%d: no memory for rx list " 705 "-- packet dropped!\n", sc->lge_unit); 706 return(ENOBUFS); 707 } 708 709 /* Allocate the jumbo buffer */ 710 buf = lge_jalloc(sc); 711 if (buf == NULL) { 712 #ifdef LGE_VERBOSE 713 printf("lge%d: jumbo allocation failed " 714 "-- packet dropped!\n", sc->lge_unit); 715 #endif 716 m_freem(m_new); 717 return(ENOBUFS); 718 } 719 /* Attach the buffer to the mbuf */ 720 m_new->m_data = (void *)buf; 721 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 722 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 723 (struct lge_softc *)sc, 0, EXT_NET_DRV); 724 } else { 725 m_new = m; 726 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 727 m_new->m_data = m_new->m_ext.ext_buf; 728 } 729 730 /* 731 * Adjust alignment so packet payload begins on a 732 * longword boundary. Mandatory for Alpha, useful on 733 * x86 too. 734 */ 735 m_adj(m_new, ETHER_ALIGN); 736 737 c->lge_mbuf = m_new; 738 c->lge_fragptr_hi = 0; 739 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 740 c->lge_fraglen = m_new->m_len; 741 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 742 c->lge_sts = 0; 743 744 /* 745 * Put this buffer in the RX command FIFO. To do this, 746 * we just write the physical address of the descriptor 747 * into the RX descriptor address registers. Note that 748 * there are two registers, one high DWORD and one low 749 * DWORD, which lets us specify a 64-bit address if 750 * desired. We only use a 32-bit address for now. 751 * Writing to the low DWORD register is what actually 752 * causes the command to be issued, so we do that 753 * last. 754 */ 755 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 756 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 757 758 return(0); 759 } 760 761 static int 762 lge_alloc_jumbo_mem(sc) 763 struct lge_softc *sc; 764 { 765 caddr_t ptr; 766 register int i; 767 struct lge_jpool_entry *entry; 768 769 /* Grab a big chunk o' storage. */ 770 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 771 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 772 773 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 774 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 775 return(ENOBUFS); 776 } 777 778 SLIST_INIT(&sc->lge_jfree_listhead); 779 SLIST_INIT(&sc->lge_jinuse_listhead); 780 781 /* 782 * Now divide it up into 9K pieces and save the addresses 783 * in an array. 784 */ 785 ptr = sc->lge_cdata.lge_jumbo_buf; 786 for (i = 0; i < LGE_JSLOTS; i++) { 787 sc->lge_cdata.lge_jslots[i] = ptr; 788 ptr += LGE_JLEN; 789 entry = malloc(sizeof(struct lge_jpool_entry), 790 M_DEVBUF, M_NOWAIT); 791 if (entry == NULL) { 792 printf("lge%d: no memory for jumbo " 793 "buffer queue!\n", sc->lge_unit); 794 return(ENOBUFS); 795 } 796 entry->slot = i; 797 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 798 entry, jpool_entries); 799 } 800 801 return(0); 802 } 803 804 static void 805 lge_free_jumbo_mem(sc) 806 struct lge_softc *sc; 807 { 808 int i; 809 struct lge_jpool_entry *entry; 810 811 for (i = 0; i < LGE_JSLOTS; i++) { 812 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 813 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 814 free(entry, M_DEVBUF); 815 } 816 817 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 818 819 return; 820 } 821 822 /* 823 * Allocate a jumbo buffer. 824 */ 825 static void * 826 lge_jalloc(sc) 827 struct lge_softc *sc; 828 { 829 struct lge_jpool_entry *entry; 830 831 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 832 833 if (entry == NULL) { 834 #ifdef LGE_VERBOSE 835 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 836 #endif 837 return(NULL); 838 } 839 840 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 841 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 842 return(sc->lge_cdata.lge_jslots[entry->slot]); 843 } 844 845 /* 846 * Release a jumbo buffer. 847 */ 848 static void 849 lge_jfree(buf, args) 850 void *buf; 851 void *args; 852 { 853 struct lge_softc *sc; 854 int i; 855 struct lge_jpool_entry *entry; 856 857 /* Extract the softc struct pointer. */ 858 sc = args; 859 860 if (sc == NULL) 861 panic("lge_jfree: can't find softc pointer!"); 862 863 /* calculate the slot this buffer belongs to */ 864 i = ((vm_offset_t)buf 865 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 866 867 if ((i < 0) || (i >= LGE_JSLOTS)) 868 panic("lge_jfree: asked to free buffer that we don't manage!"); 869 870 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 871 if (entry == NULL) 872 panic("lge_jfree: buffer not in use!"); 873 entry->slot = i; 874 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 875 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 876 877 return; 878 } 879 880 /* 881 * A frame has been uploaded: pass the resulting mbuf chain up to 882 * the higher level protocols. 883 */ 884 static void 885 lge_rxeof(sc, cnt) 886 struct lge_softc *sc; 887 int cnt; 888 { 889 struct mbuf *m; 890 struct ifnet *ifp; 891 struct lge_rx_desc *cur_rx; 892 int c, i, total_len = 0; 893 u_int32_t rxsts, rxctl; 894 895 ifp = &sc->arpcom.ac_if; 896 897 /* Find out how many frames were processed. */ 898 c = cnt; 899 i = sc->lge_cdata.lge_rx_cons; 900 901 /* Suck them in. */ 902 while(c) { 903 struct mbuf *m0 = NULL; 904 905 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 906 rxctl = cur_rx->lge_ctl; 907 rxsts = cur_rx->lge_sts; 908 m = cur_rx->lge_mbuf; 909 cur_rx->lge_mbuf = NULL; 910 total_len = LGE_RXBYTES(cur_rx); 911 LGE_INC(i, LGE_RX_LIST_CNT); 912 c--; 913 914 /* 915 * If an error occurs, update stats, clear the 916 * status word and leave the mbuf cluster in place: 917 * it should simply get re-used next time this descriptor 918 * comes up in the ring. 919 */ 920 if (rxctl & LGE_RXCTL_ERRMASK) { 921 ifp->if_ierrors++; 922 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 923 continue; 924 } 925 926 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 927 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 928 ifp, NULL); 929 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 930 if (m0 == NULL) { 931 printf("lge%d: no receive buffers " 932 "available -- packet dropped!\n", 933 sc->lge_unit); 934 ifp->if_ierrors++; 935 continue; 936 } 937 m = m0; 938 } else { 939 m->m_pkthdr.rcvif = ifp; 940 m->m_pkthdr.len = m->m_len = total_len; 941 } 942 943 ifp->if_ipackets++; 944 945 /* Do IP checksum checking. */ 946 if (rxsts & LGE_RXSTS_ISIP) 947 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 948 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 949 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 950 if ((rxsts & LGE_RXSTS_ISTCP && 951 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 952 (rxsts & LGE_RXSTS_ISUDP && 953 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 954 m->m_pkthdr.csum_flags |= 955 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 956 m->m_pkthdr.csum_data = 0xffff; 957 } 958 959 (*ifp->if_input)(ifp, m); 960 } 961 962 sc->lge_cdata.lge_rx_cons = i; 963 964 return; 965 } 966 967 static void 968 lge_rxeoc(sc) 969 struct lge_softc *sc; 970 { 971 struct ifnet *ifp; 972 973 ifp = &sc->arpcom.ac_if; 974 ifp->if_flags &= ~IFF_RUNNING; 975 lge_init(sc); 976 return; 977 } 978 979 /* 980 * A frame was downloaded to the chip. It's safe for us to clean up 981 * the list buffers. 982 */ 983 984 static void 985 lge_txeof(sc) 986 struct lge_softc *sc; 987 { 988 struct lge_tx_desc *cur_tx = NULL; 989 struct ifnet *ifp; 990 u_int32_t idx, txdone; 991 992 ifp = &sc->arpcom.ac_if; 993 994 /* Clear the timeout timer. */ 995 ifp->if_timer = 0; 996 997 /* 998 * Go through our tx list and free mbufs for those 999 * frames that have been transmitted. 1000 */ 1001 idx = sc->lge_cdata.lge_tx_cons; 1002 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1003 1004 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1005 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1006 1007 ifp->if_opackets++; 1008 if (cur_tx->lge_mbuf != NULL) { 1009 m_freem(cur_tx->lge_mbuf); 1010 cur_tx->lge_mbuf = NULL; 1011 } 1012 cur_tx->lge_ctl = 0; 1013 1014 txdone--; 1015 LGE_INC(idx, LGE_TX_LIST_CNT); 1016 ifp->if_timer = 0; 1017 } 1018 1019 sc->lge_cdata.lge_tx_cons = idx; 1020 1021 if (cur_tx != NULL) 1022 ifp->if_flags &= ~IFF_OACTIVE; 1023 1024 return; 1025 } 1026 1027 static void 1028 lge_tick(xsc) 1029 void *xsc; 1030 { 1031 struct lge_softc *sc; 1032 struct mii_data *mii; 1033 struct ifnet *ifp; 1034 int s; 1035 1036 s = splimp(); 1037 1038 sc = xsc; 1039 ifp = &sc->arpcom.ac_if; 1040 1041 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1042 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1043 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1044 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1045 1046 if (!sc->lge_link) { 1047 mii = device_get_softc(sc->lge_miibus); 1048 mii_tick(mii); 1049 if (mii->mii_media_status & IFM_ACTIVE && 1050 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1051 sc->lge_link++; 1052 if (bootverbose && 1053 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1054 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1055 printf("lge%d: gigabit link up\n", 1056 sc->lge_unit); 1057 if (ifp->if_snd.ifq_head != NULL) 1058 lge_start(ifp); 1059 } 1060 } 1061 1062 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1063 1064 splx(s); 1065 1066 return; 1067 } 1068 1069 static void 1070 lge_intr(arg) 1071 void *arg; 1072 { 1073 struct lge_softc *sc; 1074 struct ifnet *ifp; 1075 u_int32_t status; 1076 1077 sc = arg; 1078 ifp = &sc->arpcom.ac_if; 1079 1080 /* Supress unwanted interrupts */ 1081 if (!(ifp->if_flags & IFF_UP)) { 1082 lge_stop(sc); 1083 return; 1084 } 1085 1086 for (;;) { 1087 /* 1088 * Reading the ISR register clears all interrupts, and 1089 * clears the 'interrupts enabled' bit in the IMR 1090 * register. 1091 */ 1092 status = CSR_READ_4(sc, LGE_ISR); 1093 1094 if ((status & LGE_INTRS) == 0) 1095 break; 1096 1097 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1098 lge_txeof(sc); 1099 1100 if (status & LGE_ISR_RXDMA_DONE) 1101 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1102 1103 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1104 lge_rxeoc(sc); 1105 1106 if (status & LGE_ISR_PHY_INTR) { 1107 sc->lge_link = 0; 1108 untimeout(lge_tick, sc, sc->lge_stat_ch); 1109 lge_tick(sc); 1110 } 1111 } 1112 1113 /* Re-enable interrupts. */ 1114 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1115 1116 if (ifp->if_snd.ifq_head != NULL) 1117 lge_start(ifp); 1118 1119 return; 1120 } 1121 1122 /* 1123 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1124 * pointers to the fragment pointers. 1125 */ 1126 static int 1127 lge_encap(sc, m_head, txidx) 1128 struct lge_softc *sc; 1129 struct mbuf *m_head; 1130 u_int32_t *txidx; 1131 { 1132 struct lge_frag *f = NULL; 1133 struct lge_tx_desc *cur_tx; 1134 struct mbuf *m; 1135 int frag = 0, tot_len = 0; 1136 1137 /* 1138 * Start packing the mbufs in this chain into 1139 * the fragment pointers. Stop when we run out 1140 * of fragments or hit the end of the mbuf chain. 1141 */ 1142 m = m_head; 1143 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1144 frag = 0; 1145 1146 for (m = m_head; m != NULL; m = m->m_next) { 1147 if (m->m_len != 0) { 1148 tot_len += m->m_len; 1149 f = &cur_tx->lge_frags[frag]; 1150 f->lge_fraglen = m->m_len; 1151 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1152 f->lge_fragptr_hi = 0; 1153 frag++; 1154 } 1155 } 1156 1157 if (m != NULL) 1158 return(ENOBUFS); 1159 1160 cur_tx->lge_mbuf = m_head; 1161 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1162 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1163 1164 /* Queue for transmit */ 1165 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1166 1167 return(0); 1168 } 1169 1170 /* 1171 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1172 * to the mbuf data regions directly in the transmit lists. We also save a 1173 * copy of the pointers since the transmit list fragment pointers are 1174 * physical addresses. 1175 */ 1176 1177 static void 1178 lge_start(ifp) 1179 struct ifnet *ifp; 1180 { 1181 struct lge_softc *sc; 1182 struct mbuf *m_head = NULL; 1183 u_int32_t idx; 1184 1185 sc = ifp->if_softc; 1186 1187 if (!sc->lge_link) 1188 return; 1189 1190 idx = sc->lge_cdata.lge_tx_prod; 1191 1192 if (ifp->if_flags & IFF_OACTIVE) 1193 return; 1194 1195 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1196 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1197 break; 1198 1199 IF_DEQUEUE(&ifp->if_snd, m_head); 1200 if (m_head == NULL) 1201 break; 1202 1203 if (lge_encap(sc, m_head, &idx)) { 1204 IF_PREPEND(&ifp->if_snd, m_head); 1205 ifp->if_flags |= IFF_OACTIVE; 1206 break; 1207 } 1208 1209 /* 1210 * If there's a BPF listener, bounce a copy of this frame 1211 * to him. 1212 */ 1213 BPF_MTAP(ifp, m_head); 1214 } 1215 1216 sc->lge_cdata.lge_tx_prod = idx; 1217 1218 /* 1219 * Set a timeout in case the chip goes out to lunch. 1220 */ 1221 ifp->if_timer = 5; 1222 1223 return; 1224 } 1225 1226 static void 1227 lge_init(xsc) 1228 void *xsc; 1229 { 1230 struct lge_softc *sc = xsc; 1231 struct ifnet *ifp = &sc->arpcom.ac_if; 1232 struct mii_data *mii; 1233 int s; 1234 1235 if (ifp->if_flags & IFF_RUNNING) 1236 return; 1237 1238 s = splimp(); 1239 1240 /* 1241 * Cancel pending I/O and free all RX/TX buffers. 1242 */ 1243 lge_stop(sc); 1244 lge_reset(sc); 1245 1246 mii = device_get_softc(sc->lge_miibus); 1247 1248 /* Set MAC address */ 1249 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1250 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1251 1252 /* Init circular RX list. */ 1253 if (lge_list_rx_init(sc) == ENOBUFS) { 1254 printf("lge%d: initialization failed: no " 1255 "memory for rx buffers\n", sc->lge_unit); 1256 lge_stop(sc); 1257 (void)splx(s); 1258 return; 1259 } 1260 1261 /* 1262 * Init tx descriptors. 1263 */ 1264 lge_list_tx_init(sc); 1265 1266 /* Set initial value for MODE1 register. */ 1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1268 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1269 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1270 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1271 1272 /* If we want promiscuous mode, set the allframes bit. */ 1273 if (ifp->if_flags & IFF_PROMISC) { 1274 CSR_WRITE_4(sc, LGE_MODE1, 1275 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1276 } else { 1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1278 } 1279 1280 /* 1281 * Set the capture broadcast bit to capture broadcast frames. 1282 */ 1283 if (ifp->if_flags & IFF_BROADCAST) { 1284 CSR_WRITE_4(sc, LGE_MODE1, 1285 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1286 } else { 1287 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1288 } 1289 1290 /* Packet padding workaround? */ 1291 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1292 1293 /* No error frames */ 1294 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1295 1296 /* Receive large frames */ 1297 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1298 1299 /* Workaround: disable RX/TX flow control */ 1300 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1302 1303 /* Make sure to strip CRC from received frames */ 1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1305 1306 /* Turn off magic packet mode */ 1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1308 1309 /* Turn off all VLAN stuff */ 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1311 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1312 1313 /* Workarond: FIFO overflow */ 1314 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1315 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1316 1317 /* 1318 * Load the multicast filter. 1319 */ 1320 lge_setmulti(sc); 1321 1322 /* 1323 * Enable hardware checksum validation for all received IPv4 1324 * packets, do not reject packets with bad checksums. 1325 */ 1326 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1327 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1328 LGE_MODE2_RX_ERRCSUM); 1329 1330 /* 1331 * Enable the delivery of PHY interrupts based on 1332 * link/speed/duplex status chalges. 1333 */ 1334 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1335 1336 /* Enable receiver and transmitter. */ 1337 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1338 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1339 1340 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1341 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1342 1343 /* 1344 * Enable interrupts. 1345 */ 1346 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1347 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1348 1349 lge_ifmedia_upd(ifp); 1350 1351 ifp->if_flags |= IFF_RUNNING; 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 1354 (void)splx(s); 1355 1356 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1357 1358 return; 1359 } 1360 1361 /* 1362 * Set media options. 1363 */ 1364 static int 1365 lge_ifmedia_upd(ifp) 1366 struct ifnet *ifp; 1367 { 1368 struct lge_softc *sc; 1369 struct mii_data *mii; 1370 1371 sc = ifp->if_softc; 1372 1373 mii = device_get_softc(sc->lge_miibus); 1374 sc->lge_link = 0; 1375 if (mii->mii_instance) { 1376 struct mii_softc *miisc; 1377 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1378 miisc = LIST_NEXT(miisc, mii_list)) 1379 mii_phy_reset(miisc); 1380 } 1381 mii_mediachg(mii); 1382 1383 return(0); 1384 } 1385 1386 /* 1387 * Report current media status. 1388 */ 1389 static void 1390 lge_ifmedia_sts(ifp, ifmr) 1391 struct ifnet *ifp; 1392 struct ifmediareq *ifmr; 1393 { 1394 struct lge_softc *sc; 1395 struct mii_data *mii; 1396 1397 sc = ifp->if_softc; 1398 1399 mii = device_get_softc(sc->lge_miibus); 1400 mii_pollstat(mii); 1401 ifmr->ifm_active = mii->mii_media_active; 1402 ifmr->ifm_status = mii->mii_media_status; 1403 1404 return; 1405 } 1406 1407 static int 1408 lge_ioctl(ifp, command, data) 1409 struct ifnet *ifp; 1410 u_long command; 1411 caddr_t data; 1412 { 1413 struct lge_softc *sc = ifp->if_softc; 1414 struct ifreq *ifr = (struct ifreq *) data; 1415 struct mii_data *mii; 1416 int s, error = 0; 1417 1418 s = splimp(); 1419 1420 switch(command) { 1421 case SIOCSIFMTU: 1422 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1423 error = EINVAL; 1424 else 1425 ifp->if_mtu = ifr->ifr_mtu; 1426 break; 1427 case SIOCSIFFLAGS: 1428 if (ifp->if_flags & IFF_UP) { 1429 if (ifp->if_flags & IFF_RUNNING && 1430 ifp->if_flags & IFF_PROMISC && 1431 !(sc->lge_if_flags & IFF_PROMISC)) { 1432 CSR_WRITE_4(sc, LGE_MODE1, 1433 LGE_MODE1_SETRST_CTL1| 1434 LGE_MODE1_RX_PROMISC); 1435 } else if (ifp->if_flags & IFF_RUNNING && 1436 !(ifp->if_flags & IFF_PROMISC) && 1437 sc->lge_if_flags & IFF_PROMISC) { 1438 CSR_WRITE_4(sc, LGE_MODE1, 1439 LGE_MODE1_RX_PROMISC); 1440 } else { 1441 ifp->if_flags &= ~IFF_RUNNING; 1442 lge_init(sc); 1443 } 1444 } else { 1445 if (ifp->if_flags & IFF_RUNNING) 1446 lge_stop(sc); 1447 } 1448 sc->lge_if_flags = ifp->if_flags; 1449 error = 0; 1450 break; 1451 case SIOCADDMULTI: 1452 case SIOCDELMULTI: 1453 lge_setmulti(sc); 1454 error = 0; 1455 break; 1456 case SIOCGIFMEDIA: 1457 case SIOCSIFMEDIA: 1458 mii = device_get_softc(sc->lge_miibus); 1459 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1460 break; 1461 default: 1462 error = ether_ioctl(ifp, command, data); 1463 break; 1464 } 1465 1466 (void)splx(s); 1467 1468 return(error); 1469 } 1470 1471 static void 1472 lge_watchdog(ifp) 1473 struct ifnet *ifp; 1474 { 1475 struct lge_softc *sc; 1476 1477 sc = ifp->if_softc; 1478 1479 ifp->if_oerrors++; 1480 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1481 1482 lge_stop(sc); 1483 lge_reset(sc); 1484 ifp->if_flags &= ~IFF_RUNNING; 1485 lge_init(sc); 1486 1487 if (ifp->if_snd.ifq_head != NULL) 1488 lge_start(ifp); 1489 1490 return; 1491 } 1492 1493 /* 1494 * Stop the adapter and free any mbufs allocated to the 1495 * RX and TX lists. 1496 */ 1497 static void 1498 lge_stop(sc) 1499 struct lge_softc *sc; 1500 { 1501 register int i; 1502 struct ifnet *ifp; 1503 1504 ifp = &sc->arpcom.ac_if; 1505 ifp->if_timer = 0; 1506 untimeout(lge_tick, sc, sc->lge_stat_ch); 1507 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1508 1509 /* Disable receiver and transmitter. */ 1510 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1511 sc->lge_link = 0; 1512 1513 /* 1514 * Free data in the RX lists. 1515 */ 1516 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1517 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1518 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1519 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1520 } 1521 } 1522 bzero((char *)&sc->lge_ldata->lge_rx_list, 1523 sizeof(sc->lge_ldata->lge_rx_list)); 1524 1525 /* 1526 * Free the TX list buffers. 1527 */ 1528 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1529 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1530 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1531 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1532 } 1533 } 1534 1535 bzero((char *)&sc->lge_ldata->lge_tx_list, 1536 sizeof(sc->lge_ldata->lge_tx_list)); 1537 1538 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1539 1540 return; 1541 } 1542 1543 /* 1544 * Stop all chip I/O so that the kernel's probe routines don't 1545 * get confused by errant DMAs when rebooting. 1546 */ 1547 static void 1548 lge_shutdown(dev) 1549 device_t dev; 1550 { 1551 struct lge_softc *sc; 1552 1553 sc = device_get_softc(dev); 1554 1555 lge_reset(sc); 1556 lge_stop(sc); 1557 1558 return; 1559 } 1560