1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/cdefs.h> 73 __FBSDID("$FreeBSD$"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/sockio.h> 78 #include <sys/mbuf.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/socket.h> 82 83 #include <net/if.h> 84 #include <net/if_arp.h> 85 #include <net/ethernet.h> 86 #include <net/if_dl.h> 87 #include <net/if_media.h> 88 89 #include <net/bpf.h> 90 91 #include <vm/vm.h> /* for vtophys */ 92 #include <vm/pmap.h> /* for vtophys */ 93 #include <machine/clock.h> /* for DELAY */ 94 #include <machine/bus_pio.h> 95 #include <machine/bus_memio.h> 96 #include <machine/bus.h> 97 #include <machine/resource.h> 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 107 #define LGE_USEIOSPACE 108 109 #include <dev/lge/if_lgereg.h> 110 111 /* "controller miibus0" required. See GENERIC if you get errors here. */ 112 #include "miibus_if.h" 113 114 /* 115 * Various supported device vendors/types and their names. 116 */ 117 static struct lge_type lge_devs[] = { 118 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 119 { 0, 0, NULL } 120 }; 121 122 static int lge_probe(device_t); 123 static int lge_attach(device_t); 124 static int lge_detach(device_t); 125 126 static int lge_alloc_jumbo_mem(struct lge_softc *); 127 static void lge_free_jumbo_mem(struct lge_softc *); 128 static void *lge_jalloc(struct lge_softc *); 129 static void lge_jfree(void *, void *); 130 131 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 132 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 133 static void lge_rxeof(struct lge_softc *, int); 134 static void lge_rxeoc(struct lge_softc *); 135 static void lge_txeof(struct lge_softc *); 136 static void lge_intr(void *); 137 static void lge_tick(void *); 138 static void lge_start(struct ifnet *); 139 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 140 static void lge_init(void *); 141 static void lge_stop(struct lge_softc *); 142 static void lge_watchdog(struct ifnet *); 143 static void lge_shutdown(device_t); 144 static int lge_ifmedia_upd(struct ifnet *); 145 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146 147 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 148 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 149 150 static int lge_miibus_readreg(device_t, int, int); 151 static int lge_miibus_writereg(device_t, int, int, int); 152 static void lge_miibus_statchg(device_t); 153 154 static void lge_setmulti(struct lge_softc *); 155 static u_int32_t lge_crc(struct lge_softc *, caddr_t); 156 static void lge_reset(struct lge_softc *); 157 static int lge_list_rx_init(struct lge_softc *); 158 static int lge_list_tx_init(struct lge_softc *); 159 160 #ifdef LGE_USEIOSPACE 161 #define LGE_RES SYS_RES_IOPORT 162 #define LGE_RID LGE_PCI_LOIO 163 #else 164 #define LGE_RES SYS_RES_MEMORY 165 #define LGE_RID LGE_PCI_LOMEM 166 #endif 167 168 static device_method_t lge_methods[] = { 169 /* Device interface */ 170 DEVMETHOD(device_probe, lge_probe), 171 DEVMETHOD(device_attach, lge_attach), 172 DEVMETHOD(device_detach, lge_detach), 173 DEVMETHOD(device_shutdown, lge_shutdown), 174 175 /* bus interface */ 176 DEVMETHOD(bus_print_child, bus_generic_print_child), 177 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 178 179 /* MII interface */ 180 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 181 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 182 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 183 184 { 0, 0 } 185 }; 186 187 static driver_t lge_driver = { 188 "lge", 189 lge_methods, 190 sizeof(struct lge_softc) 191 }; 192 193 static devclass_t lge_devclass; 194 195 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 196 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 197 MODULE_DEPEND(lge, pci, 1, 1, 1); 198 MODULE_DEPEND(lge, ether, 1, 1, 1); 199 MODULE_DEPEND(lge, miibus, 1, 1, 1); 200 201 #define LGE_SETBIT(sc, reg, x) \ 202 CSR_WRITE_4(sc, reg, \ 203 CSR_READ_4(sc, reg) | (x)) 204 205 #define LGE_CLRBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) & ~(x)) 208 209 #define SIO_SET(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 211 212 #define SIO_CLR(x) \ 213 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 214 215 /* 216 * Read a word of data stored in the EEPROM at address 'addr.' 217 */ 218 static void 219 lge_eeprom_getword(sc, addr, dest) 220 struct lge_softc *sc; 221 int addr; 222 u_int16_t *dest; 223 { 224 register int i; 225 u_int32_t val; 226 227 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 228 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 229 230 for (i = 0; i < LGE_TIMEOUT; i++) 231 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 232 break; 233 234 if (i == LGE_TIMEOUT) { 235 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 236 return; 237 } 238 239 val = CSR_READ_4(sc, LGE_EEDATA); 240 241 if (addr & 1) 242 *dest = (val >> 16) & 0xFFFF; 243 else 244 *dest = val & 0xFFFF; 245 246 return; 247 } 248 249 /* 250 * Read a sequence of words from the EEPROM. 251 */ 252 static void 253 lge_read_eeprom(sc, dest, off, cnt, swap) 254 struct lge_softc *sc; 255 caddr_t dest; 256 int off; 257 int cnt; 258 int swap; 259 { 260 int i; 261 u_int16_t word = 0, *ptr; 262 263 for (i = 0; i < cnt; i++) { 264 lge_eeprom_getword(sc, off + i, &word); 265 ptr = (u_int16_t *)(dest + (i * 2)); 266 if (swap) 267 *ptr = ntohs(word); 268 else 269 *ptr = word; 270 } 271 272 return; 273 } 274 275 static int 276 lge_miibus_readreg(dev, phy, reg) 277 device_t dev; 278 int phy, reg; 279 { 280 struct lge_softc *sc; 281 int i; 282 283 sc = device_get_softc(dev); 284 285 /* 286 * If we have a non-PCS PHY, pretend that the internal 287 * autoneg stuff at PHY address 0 isn't there so that 288 * the miibus code will find only the GMII PHY. 289 */ 290 if (sc->lge_pcs == 0 && phy == 0) 291 return(0); 292 293 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 294 295 for (i = 0; i < LGE_TIMEOUT; i++) 296 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 297 break; 298 299 if (i == LGE_TIMEOUT) { 300 printf("lge%d: PHY read timed out\n", sc->lge_unit); 301 return(0); 302 } 303 304 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 305 } 306 307 static int 308 lge_miibus_writereg(dev, phy, reg, data) 309 device_t dev; 310 int phy, reg, data; 311 { 312 struct lge_softc *sc; 313 int i; 314 315 sc = device_get_softc(dev); 316 317 CSR_WRITE_4(sc, LGE_GMIICTL, 318 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 319 320 for (i = 0; i < LGE_TIMEOUT; i++) 321 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 322 break; 323 324 if (i == LGE_TIMEOUT) { 325 printf("lge%d: PHY write timed out\n", sc->lge_unit); 326 return(0); 327 } 328 329 return(0); 330 } 331 332 static void 333 lge_miibus_statchg(dev) 334 device_t dev; 335 { 336 struct lge_softc *sc; 337 struct mii_data *mii; 338 339 sc = device_get_softc(dev); 340 mii = device_get_softc(sc->lge_miibus); 341 342 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 343 switch (IFM_SUBTYPE(mii->mii_media_active)) { 344 case IFM_1000_T: 345 case IFM_1000_SX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 347 break; 348 case IFM_100_TX: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 350 break; 351 case IFM_10_T: 352 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 353 break; 354 default: 355 /* 356 * Choose something, even if it's wrong. Clearing 357 * all the bits will hose autoneg on the internal 358 * PHY. 359 */ 360 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 361 break; 362 } 363 364 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 365 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 366 } else { 367 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 368 } 369 370 return; 371 } 372 373 static u_int32_t 374 lge_crc(sc, addr) 375 struct lge_softc *sc; 376 caddr_t addr; 377 { 378 u_int32_t crc, carry; 379 int i, j; 380 u_int8_t c; 381 382 /* Compute CRC for the address value. */ 383 crc = 0xFFFFFFFF; /* initial value */ 384 385 for (i = 0; i < 6; i++) { 386 c = *(addr + i); 387 for (j = 0; j < 8; j++) { 388 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 389 crc <<= 1; 390 c >>= 1; 391 if (carry) 392 crc = (crc ^ 0x04c11db6) | carry; 393 } 394 } 395 396 /* 397 * return the filter bit position 398 */ 399 return((crc >> 26) & 0x0000003F); 400 } 401 402 static void 403 lge_setmulti(sc) 404 struct lge_softc *sc; 405 { 406 struct ifnet *ifp; 407 struct ifmultiaddr *ifma; 408 u_int32_t h = 0, hashes[2] = { 0, 0 }; 409 410 ifp = &sc->arpcom.ac_if; 411 412 /* Make sure multicast hash table is enabled. */ 413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 414 415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 416 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 417 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 418 return; 419 } 420 421 /* first, zot all the existing hash bits */ 422 CSR_WRITE_4(sc, LGE_MAR0, 0); 423 CSR_WRITE_4(sc, LGE_MAR1, 0); 424 425 /* now program new ones */ 426 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 427 if (ifma->ifma_addr->sa_family != AF_LINK) 428 continue; 429 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 430 if (h < 32) 431 hashes[0] |= (1 << h); 432 else 433 hashes[1] |= (1 << (h - 32)); 434 } 435 436 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 437 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 438 439 return; 440 } 441 442 static void 443 lge_reset(sc) 444 struct lge_softc *sc; 445 { 446 register int i; 447 448 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 449 450 for (i = 0; i < LGE_TIMEOUT; i++) { 451 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 452 break; 453 } 454 455 if (i == LGE_TIMEOUT) 456 printf("lge%d: reset never completed\n", sc->lge_unit); 457 458 /* Wait a little while for the chip to get its brains in order. */ 459 DELAY(1000); 460 461 return; 462 } 463 464 /* 465 * Probe for a Level 1 chip. Check the PCI vendor and device 466 * IDs against our list and return a device name if we find a match. 467 */ 468 static int 469 lge_probe(dev) 470 device_t dev; 471 { 472 struct lge_type *t; 473 474 t = lge_devs; 475 476 while(t->lge_name != NULL) { 477 if ((pci_get_vendor(dev) == t->lge_vid) && 478 (pci_get_device(dev) == t->lge_did)) { 479 device_set_desc(dev, t->lge_name); 480 return(0); 481 } 482 t++; 483 } 484 485 return(ENXIO); 486 } 487 488 /* 489 * Attach the interface. Allocate softc structures, do ifmedia 490 * setup and ethernet/BPF attach. 491 */ 492 static int 493 lge_attach(dev) 494 device_t dev; 495 { 496 int s; 497 u_char eaddr[ETHER_ADDR_LEN]; 498 struct lge_softc *sc; 499 struct ifnet *ifp; 500 int unit, error = 0, rid; 501 502 s = splimp(); 503 504 sc = device_get_softc(dev); 505 unit = device_get_unit(dev); 506 bzero(sc, sizeof(struct lge_softc)); 507 #ifndef BURN_BRIDGES 508 /* 509 * Handle power management nonsense. 510 */ 511 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 512 u_int32_t iobase, membase, irq; 513 514 /* Save important PCI config data. */ 515 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 516 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 517 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 518 519 /* Reset the power state. */ 520 printf("lge%d: chip is in D%d power mode " 521 "-- setting to D0\n", unit, 522 pci_get_powerstate(dev)); 523 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 524 525 /* Restore PCI config data. */ 526 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 527 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 528 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 529 } 530 #endif 531 /* 532 * Map control/status registers. 533 */ 534 pci_enable_busmaster(dev); 535 536 rid = LGE_RID; 537 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 538 0, ~0, 1, RF_ACTIVE); 539 540 if (sc->lge_res == NULL) { 541 printf("lge%d: couldn't map ports/memory\n", unit); 542 error = ENXIO; 543 goto fail; 544 } 545 546 sc->lge_btag = rman_get_bustag(sc->lge_res); 547 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 548 549 /* Allocate interrupt */ 550 rid = 0; 551 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 552 RF_SHAREABLE | RF_ACTIVE); 553 554 if (sc->lge_irq == NULL) { 555 printf("lge%d: couldn't map interrupt\n", unit); 556 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 557 error = ENXIO; 558 goto fail; 559 } 560 561 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 562 lge_intr, sc, &sc->lge_intrhand); 563 564 if (error) { 565 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 566 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 567 printf("lge%d: couldn't set up irq\n", unit); 568 goto fail; 569 } 570 571 /* Reset the adapter. */ 572 lge_reset(sc); 573 574 /* 575 * Get station address from the EEPROM. 576 */ 577 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 578 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 579 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 580 581 /* 582 * A Level 1 chip was detected. Inform the world. 583 */ 584 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 585 586 sc->lge_unit = unit; 587 callout_handle_init(&sc->lge_stat_ch); 588 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 589 590 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 591 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 592 593 if (sc->lge_ldata == NULL) { 594 printf("lge%d: no memory for list buffers!\n", unit); 595 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 596 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 597 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 598 error = ENXIO; 599 goto fail; 600 } 601 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 602 603 /* Try to allocate memory for jumbo buffers. */ 604 if (lge_alloc_jumbo_mem(sc)) { 605 printf("lge%d: jumbo buffer allocation failed\n", 606 sc->lge_unit); 607 contigfree(sc->lge_ldata, 608 sizeof(struct lge_list_data), M_DEVBUF); 609 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 610 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 611 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 612 error = ENXIO; 613 goto fail; 614 } 615 616 ifp = &sc->arpcom.ac_if; 617 ifp->if_softc = sc; 618 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 619 ifp->if_mtu = ETHERMTU; 620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 621 ifp->if_ioctl = lge_ioctl; 622 ifp->if_output = ether_output; 623 ifp->if_start = lge_start; 624 ifp->if_watchdog = lge_watchdog; 625 ifp->if_init = lge_init; 626 ifp->if_baudrate = 1000000000; 627 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 628 ifp->if_capabilities = IFCAP_RXCSUM; 629 ifp->if_capenable = ifp->if_capabilities; 630 631 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 632 sc->lge_pcs = 1; 633 else 634 sc->lge_pcs = 0; 635 636 /* 637 * Do MII setup. 638 */ 639 if (mii_phy_probe(dev, &sc->lge_miibus, 640 lge_ifmedia_upd, lge_ifmedia_sts)) { 641 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 642 contigfree(sc->lge_ldata, 643 sizeof(struct lge_list_data), M_DEVBUF); 644 lge_free_jumbo_mem(sc); 645 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 646 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 647 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 648 error = ENXIO; 649 goto fail; 650 } 651 652 /* 653 * Call MI attach routine. 654 */ 655 ether_ifattach(ifp, eaddr); 656 callout_handle_init(&sc->lge_stat_ch); 657 658 fail: 659 splx(s); 660 return(error); 661 } 662 663 static int 664 lge_detach(dev) 665 device_t dev; 666 { 667 struct lge_softc *sc; 668 struct ifnet *ifp; 669 int s; 670 671 s = splimp(); 672 673 sc = device_get_softc(dev); 674 ifp = &sc->arpcom.ac_if; 675 676 lge_reset(sc); 677 lge_stop(sc); 678 ether_ifdetach(ifp); 679 680 bus_generic_detach(dev); 681 device_delete_child(dev, sc->lge_miibus); 682 683 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 685 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 686 687 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 688 lge_free_jumbo_mem(sc); 689 690 splx(s); 691 692 return(0); 693 } 694 695 /* 696 * Initialize the transmit descriptors. 697 */ 698 static int 699 lge_list_tx_init(sc) 700 struct lge_softc *sc; 701 { 702 struct lge_list_data *ld; 703 struct lge_ring_data *cd; 704 int i; 705 706 cd = &sc->lge_cdata; 707 ld = sc->lge_ldata; 708 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 709 ld->lge_tx_list[i].lge_mbuf = NULL; 710 ld->lge_tx_list[i].lge_ctl = 0; 711 } 712 713 cd->lge_tx_prod = cd->lge_tx_cons = 0; 714 715 return(0); 716 } 717 718 719 /* 720 * Initialize the RX descriptors and allocate mbufs for them. Note that 721 * we arralge the descriptors in a closed ring, so that the last descriptor 722 * points back to the first. 723 */ 724 static int 725 lge_list_rx_init(sc) 726 struct lge_softc *sc; 727 { 728 struct lge_list_data *ld; 729 struct lge_ring_data *cd; 730 int i; 731 732 ld = sc->lge_ldata; 733 cd = &sc->lge_cdata; 734 735 cd->lge_rx_prod = cd->lge_rx_cons = 0; 736 737 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 738 739 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 740 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 741 break; 742 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 743 return(ENOBUFS); 744 } 745 746 /* Clear possible 'rx command queue empty' interrupt. */ 747 CSR_READ_4(sc, LGE_ISR); 748 749 return(0); 750 } 751 752 /* 753 * Initialize an RX descriptor and attach an MBUF cluster. 754 */ 755 static int 756 lge_newbuf(sc, c, m) 757 struct lge_softc *sc; 758 struct lge_rx_desc *c; 759 struct mbuf *m; 760 { 761 struct mbuf *m_new = NULL; 762 caddr_t *buf = NULL; 763 764 if (m == NULL) { 765 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 766 if (m_new == NULL) { 767 printf("lge%d: no memory for rx list " 768 "-- packet dropped!\n", sc->lge_unit); 769 return(ENOBUFS); 770 } 771 772 /* Allocate the jumbo buffer */ 773 buf = lge_jalloc(sc); 774 if (buf == NULL) { 775 #ifdef LGE_VERBOSE 776 printf("lge%d: jumbo allocation failed " 777 "-- packet dropped!\n", sc->lge_unit); 778 #endif 779 m_freem(m_new); 780 return(ENOBUFS); 781 } 782 /* Attach the buffer to the mbuf */ 783 m_new->m_data = (void *)buf; 784 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 785 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 786 (struct lge_softc *)sc, 0, EXT_NET_DRV); 787 } else { 788 m_new = m; 789 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 790 m_new->m_data = m_new->m_ext.ext_buf; 791 } 792 793 /* 794 * Adjust alignment so packet payload begins on a 795 * longword boundary. Mandatory for Alpha, useful on 796 * x86 too. 797 */ 798 m_adj(m_new, ETHER_ALIGN); 799 800 c->lge_mbuf = m_new; 801 c->lge_fragptr_hi = 0; 802 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 803 c->lge_fraglen = m_new->m_len; 804 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 805 c->lge_sts = 0; 806 807 /* 808 * Put this buffer in the RX command FIFO. To do this, 809 * we just write the physical address of the descriptor 810 * into the RX descriptor address registers. Note that 811 * there are two registers, one high DWORD and one low 812 * DWORD, which lets us specify a 64-bit address if 813 * desired. We only use a 32-bit address for now. 814 * Writing to the low DWORD register is what actually 815 * causes the command to be issued, so we do that 816 * last. 817 */ 818 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 819 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 820 821 return(0); 822 } 823 824 static int 825 lge_alloc_jumbo_mem(sc) 826 struct lge_softc *sc; 827 { 828 caddr_t ptr; 829 register int i; 830 struct lge_jpool_entry *entry; 831 832 /* Grab a big chunk o' storage. */ 833 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 834 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 835 836 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 837 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 838 return(ENOBUFS); 839 } 840 841 SLIST_INIT(&sc->lge_jfree_listhead); 842 SLIST_INIT(&sc->lge_jinuse_listhead); 843 844 /* 845 * Now divide it up into 9K pieces and save the addresses 846 * in an array. 847 */ 848 ptr = sc->lge_cdata.lge_jumbo_buf; 849 for (i = 0; i < LGE_JSLOTS; i++) { 850 sc->lge_cdata.lge_jslots[i] = ptr; 851 ptr += LGE_JLEN; 852 entry = malloc(sizeof(struct lge_jpool_entry), 853 M_DEVBUF, M_NOWAIT); 854 if (entry == NULL) { 855 printf("lge%d: no memory for jumbo " 856 "buffer queue!\n", sc->lge_unit); 857 return(ENOBUFS); 858 } 859 entry->slot = i; 860 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 861 entry, jpool_entries); 862 } 863 864 return(0); 865 } 866 867 static void 868 lge_free_jumbo_mem(sc) 869 struct lge_softc *sc; 870 { 871 int i; 872 struct lge_jpool_entry *entry; 873 874 for (i = 0; i < LGE_JSLOTS; i++) { 875 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 876 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 877 free(entry, M_DEVBUF); 878 } 879 880 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 881 882 return; 883 } 884 885 /* 886 * Allocate a jumbo buffer. 887 */ 888 static void * 889 lge_jalloc(sc) 890 struct lge_softc *sc; 891 { 892 struct lge_jpool_entry *entry; 893 894 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 895 896 if (entry == NULL) { 897 #ifdef LGE_VERBOSE 898 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 899 #endif 900 return(NULL); 901 } 902 903 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 904 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 905 return(sc->lge_cdata.lge_jslots[entry->slot]); 906 } 907 908 /* 909 * Release a jumbo buffer. 910 */ 911 static void 912 lge_jfree(buf, args) 913 void *buf; 914 void *args; 915 { 916 struct lge_softc *sc; 917 int i; 918 struct lge_jpool_entry *entry; 919 920 /* Extract the softc struct pointer. */ 921 sc = args; 922 923 if (sc == NULL) 924 panic("lge_jfree: can't find softc pointer!"); 925 926 /* calculate the slot this buffer belongs to */ 927 i = ((vm_offset_t)buf 928 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 929 930 if ((i < 0) || (i >= LGE_JSLOTS)) 931 panic("lge_jfree: asked to free buffer that we don't manage!"); 932 933 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 934 if (entry == NULL) 935 panic("lge_jfree: buffer not in use!"); 936 entry->slot = i; 937 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 938 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 939 940 return; 941 } 942 943 /* 944 * A frame has been uploaded: pass the resulting mbuf chain up to 945 * the higher level protocols. 946 */ 947 static void 948 lge_rxeof(sc, cnt) 949 struct lge_softc *sc; 950 int cnt; 951 { 952 struct mbuf *m; 953 struct ifnet *ifp; 954 struct lge_rx_desc *cur_rx; 955 int c, i, total_len = 0; 956 u_int32_t rxsts, rxctl; 957 958 ifp = &sc->arpcom.ac_if; 959 960 /* Find out how many frames were processed. */ 961 c = cnt; 962 i = sc->lge_cdata.lge_rx_cons; 963 964 /* Suck them in. */ 965 while(c) { 966 struct mbuf *m0 = NULL; 967 968 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 969 rxctl = cur_rx->lge_ctl; 970 rxsts = cur_rx->lge_sts; 971 m = cur_rx->lge_mbuf; 972 cur_rx->lge_mbuf = NULL; 973 total_len = LGE_RXBYTES(cur_rx); 974 LGE_INC(i, LGE_RX_LIST_CNT); 975 c--; 976 977 /* 978 * If an error occurs, update stats, clear the 979 * status word and leave the mbuf cluster in place: 980 * it should simply get re-used next time this descriptor 981 * comes up in the ring. 982 */ 983 if (rxctl & LGE_RXCTL_ERRMASK) { 984 ifp->if_ierrors++; 985 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 986 continue; 987 } 988 989 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 990 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 991 ifp, NULL); 992 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 993 if (m0 == NULL) { 994 printf("lge%d: no receive buffers " 995 "available -- packet dropped!\n", 996 sc->lge_unit); 997 ifp->if_ierrors++; 998 continue; 999 } 1000 m = m0; 1001 } else { 1002 m->m_pkthdr.rcvif = ifp; 1003 m->m_pkthdr.len = m->m_len = total_len; 1004 } 1005 1006 ifp->if_ipackets++; 1007 1008 /* Do IP checksum checking. */ 1009 if (rxsts & LGE_RXSTS_ISIP) 1010 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1011 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1012 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1013 if ((rxsts & LGE_RXSTS_ISTCP && 1014 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1015 (rxsts & LGE_RXSTS_ISUDP && 1016 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1017 m->m_pkthdr.csum_flags |= 1018 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1019 m->m_pkthdr.csum_data = 0xffff; 1020 } 1021 1022 (*ifp->if_input)(ifp, m); 1023 } 1024 1025 sc->lge_cdata.lge_rx_cons = i; 1026 1027 return; 1028 } 1029 1030 static void 1031 lge_rxeoc(sc) 1032 struct lge_softc *sc; 1033 { 1034 struct ifnet *ifp; 1035 1036 ifp = &sc->arpcom.ac_if; 1037 ifp->if_flags &= ~IFF_RUNNING; 1038 lge_init(sc); 1039 return; 1040 } 1041 1042 /* 1043 * A frame was downloaded to the chip. It's safe for us to clean up 1044 * the list buffers. 1045 */ 1046 1047 static void 1048 lge_txeof(sc) 1049 struct lge_softc *sc; 1050 { 1051 struct lge_tx_desc *cur_tx = NULL; 1052 struct ifnet *ifp; 1053 u_int32_t idx, txdone; 1054 1055 ifp = &sc->arpcom.ac_if; 1056 1057 /* Clear the timeout timer. */ 1058 ifp->if_timer = 0; 1059 1060 /* 1061 * Go through our tx list and free mbufs for those 1062 * frames that have been transmitted. 1063 */ 1064 idx = sc->lge_cdata.lge_tx_cons; 1065 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1066 1067 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1068 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1069 1070 ifp->if_opackets++; 1071 if (cur_tx->lge_mbuf != NULL) { 1072 m_freem(cur_tx->lge_mbuf); 1073 cur_tx->lge_mbuf = NULL; 1074 } 1075 cur_tx->lge_ctl = 0; 1076 1077 txdone--; 1078 LGE_INC(idx, LGE_TX_LIST_CNT); 1079 ifp->if_timer = 0; 1080 } 1081 1082 sc->lge_cdata.lge_tx_cons = idx; 1083 1084 if (cur_tx != NULL) 1085 ifp->if_flags &= ~IFF_OACTIVE; 1086 1087 return; 1088 } 1089 1090 static void 1091 lge_tick(xsc) 1092 void *xsc; 1093 { 1094 struct lge_softc *sc; 1095 struct mii_data *mii; 1096 struct ifnet *ifp; 1097 int s; 1098 1099 s = splimp(); 1100 1101 sc = xsc; 1102 ifp = &sc->arpcom.ac_if; 1103 1104 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1105 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1106 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1107 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1108 1109 if (!sc->lge_link) { 1110 mii = device_get_softc(sc->lge_miibus); 1111 mii_tick(mii); 1112 if (mii->mii_media_status & IFM_ACTIVE && 1113 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1114 sc->lge_link++; 1115 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1116 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1117 printf("lge%d: gigabit link up\n", 1118 sc->lge_unit); 1119 if (ifp->if_snd.ifq_head != NULL) 1120 lge_start(ifp); 1121 } 1122 } 1123 1124 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1125 1126 splx(s); 1127 1128 return; 1129 } 1130 1131 static void 1132 lge_intr(arg) 1133 void *arg; 1134 { 1135 struct lge_softc *sc; 1136 struct ifnet *ifp; 1137 u_int32_t status; 1138 1139 sc = arg; 1140 ifp = &sc->arpcom.ac_if; 1141 1142 /* Supress unwanted interrupts */ 1143 if (!(ifp->if_flags & IFF_UP)) { 1144 lge_stop(sc); 1145 return; 1146 } 1147 1148 for (;;) { 1149 /* 1150 * Reading the ISR register clears all interrupts, and 1151 * clears the 'interrupts enabled' bit in the IMR 1152 * register. 1153 */ 1154 status = CSR_READ_4(sc, LGE_ISR); 1155 1156 if ((status & LGE_INTRS) == 0) 1157 break; 1158 1159 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1160 lge_txeof(sc); 1161 1162 if (status & LGE_ISR_RXDMA_DONE) 1163 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1164 1165 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1166 lge_rxeoc(sc); 1167 1168 if (status & LGE_ISR_PHY_INTR) { 1169 sc->lge_link = 0; 1170 untimeout(lge_tick, sc, sc->lge_stat_ch); 1171 lge_tick(sc); 1172 } 1173 } 1174 1175 /* Re-enable interrupts. */ 1176 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1177 1178 if (ifp->if_snd.ifq_head != NULL) 1179 lge_start(ifp); 1180 1181 return; 1182 } 1183 1184 /* 1185 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1186 * pointers to the fragment pointers. 1187 */ 1188 static int 1189 lge_encap(sc, m_head, txidx) 1190 struct lge_softc *sc; 1191 struct mbuf *m_head; 1192 u_int32_t *txidx; 1193 { 1194 struct lge_frag *f = NULL; 1195 struct lge_tx_desc *cur_tx; 1196 struct mbuf *m; 1197 int frag = 0, tot_len = 0; 1198 1199 /* 1200 * Start packing the mbufs in this chain into 1201 * the fragment pointers. Stop when we run out 1202 * of fragments or hit the end of the mbuf chain. 1203 */ 1204 m = m_head; 1205 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1206 frag = 0; 1207 1208 for (m = m_head; m != NULL; m = m->m_next) { 1209 if (m->m_len != 0) { 1210 tot_len += m->m_len; 1211 f = &cur_tx->lge_frags[frag]; 1212 f->lge_fraglen = m->m_len; 1213 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1214 f->lge_fragptr_hi = 0; 1215 frag++; 1216 } 1217 } 1218 1219 if (m != NULL) 1220 return(ENOBUFS); 1221 1222 cur_tx->lge_mbuf = m_head; 1223 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1224 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1225 1226 /* Queue for transmit */ 1227 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1228 1229 return(0); 1230 } 1231 1232 /* 1233 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1234 * to the mbuf data regions directly in the transmit lists. We also save a 1235 * copy of the pointers since the transmit list fragment pointers are 1236 * physical addresses. 1237 */ 1238 1239 static void 1240 lge_start(ifp) 1241 struct ifnet *ifp; 1242 { 1243 struct lge_softc *sc; 1244 struct mbuf *m_head = NULL; 1245 u_int32_t idx; 1246 1247 sc = ifp->if_softc; 1248 1249 if (!sc->lge_link) 1250 return; 1251 1252 idx = sc->lge_cdata.lge_tx_prod; 1253 1254 if (ifp->if_flags & IFF_OACTIVE) 1255 return; 1256 1257 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1258 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1259 break; 1260 1261 IF_DEQUEUE(&ifp->if_snd, m_head); 1262 if (m_head == NULL) 1263 break; 1264 1265 if (lge_encap(sc, m_head, &idx)) { 1266 IF_PREPEND(&ifp->if_snd, m_head); 1267 ifp->if_flags |= IFF_OACTIVE; 1268 break; 1269 } 1270 1271 /* 1272 * If there's a BPF listener, bounce a copy of this frame 1273 * to him. 1274 */ 1275 BPF_MTAP(ifp, m_head); 1276 } 1277 1278 sc->lge_cdata.lge_tx_prod = idx; 1279 1280 /* 1281 * Set a timeout in case the chip goes out to lunch. 1282 */ 1283 ifp->if_timer = 5; 1284 1285 return; 1286 } 1287 1288 static void 1289 lge_init(xsc) 1290 void *xsc; 1291 { 1292 struct lge_softc *sc = xsc; 1293 struct ifnet *ifp = &sc->arpcom.ac_if; 1294 struct mii_data *mii; 1295 int s; 1296 1297 if (ifp->if_flags & IFF_RUNNING) 1298 return; 1299 1300 s = splimp(); 1301 1302 /* 1303 * Cancel pending I/O and free all RX/TX buffers. 1304 */ 1305 lge_stop(sc); 1306 lge_reset(sc); 1307 1308 mii = device_get_softc(sc->lge_miibus); 1309 1310 /* Set MAC address */ 1311 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1312 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1313 1314 /* Init circular RX list. */ 1315 if (lge_list_rx_init(sc) == ENOBUFS) { 1316 printf("lge%d: initialization failed: no " 1317 "memory for rx buffers\n", sc->lge_unit); 1318 lge_stop(sc); 1319 (void)splx(s); 1320 return; 1321 } 1322 1323 /* 1324 * Init tx descriptors. 1325 */ 1326 lge_list_tx_init(sc); 1327 1328 /* Set initial value for MODE1 register. */ 1329 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1330 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1331 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1332 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1333 1334 /* If we want promiscuous mode, set the allframes bit. */ 1335 if (ifp->if_flags & IFF_PROMISC) { 1336 CSR_WRITE_4(sc, LGE_MODE1, 1337 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1338 } else { 1339 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1340 } 1341 1342 /* 1343 * Set the capture broadcast bit to capture broadcast frames. 1344 */ 1345 if (ifp->if_flags & IFF_BROADCAST) { 1346 CSR_WRITE_4(sc, LGE_MODE1, 1347 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1348 } else { 1349 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1350 } 1351 1352 /* Packet padding workaround? */ 1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1354 1355 /* No error frames */ 1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1357 1358 /* Receive large frames */ 1359 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1360 1361 /* Workaround: disable RX/TX flow control */ 1362 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1363 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1364 1365 /* Make sure to strip CRC from received frames */ 1366 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1367 1368 /* Turn off magic packet mode */ 1369 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1370 1371 /* Turn off all VLAN stuff */ 1372 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1373 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1374 1375 /* Workarond: FIFO overflow */ 1376 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1377 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1378 1379 /* 1380 * Load the multicast filter. 1381 */ 1382 lge_setmulti(sc); 1383 1384 /* 1385 * Enable hardware checksum validation for all received IPv4 1386 * packets, do not reject packets with bad checksums. 1387 */ 1388 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1389 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1390 LGE_MODE2_RX_ERRCSUM); 1391 1392 /* 1393 * Enable the delivery of PHY interrupts based on 1394 * link/speed/duplex status chalges. 1395 */ 1396 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1397 1398 /* Enable receiver and transmitter. */ 1399 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1400 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1401 1402 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1403 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1404 1405 /* 1406 * Enable interrupts. 1407 */ 1408 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1409 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1410 1411 lge_ifmedia_upd(ifp); 1412 1413 ifp->if_flags |= IFF_RUNNING; 1414 ifp->if_flags &= ~IFF_OACTIVE; 1415 1416 (void)splx(s); 1417 1418 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1419 1420 return; 1421 } 1422 1423 /* 1424 * Set media options. 1425 */ 1426 static int 1427 lge_ifmedia_upd(ifp) 1428 struct ifnet *ifp; 1429 { 1430 struct lge_softc *sc; 1431 struct mii_data *mii; 1432 1433 sc = ifp->if_softc; 1434 1435 mii = device_get_softc(sc->lge_miibus); 1436 sc->lge_link = 0; 1437 if (mii->mii_instance) { 1438 struct mii_softc *miisc; 1439 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1440 miisc = LIST_NEXT(miisc, mii_list)) 1441 mii_phy_reset(miisc); 1442 } 1443 mii_mediachg(mii); 1444 1445 return(0); 1446 } 1447 1448 /* 1449 * Report current media status. 1450 */ 1451 static void 1452 lge_ifmedia_sts(ifp, ifmr) 1453 struct ifnet *ifp; 1454 struct ifmediareq *ifmr; 1455 { 1456 struct lge_softc *sc; 1457 struct mii_data *mii; 1458 1459 sc = ifp->if_softc; 1460 1461 mii = device_get_softc(sc->lge_miibus); 1462 mii_pollstat(mii); 1463 ifmr->ifm_active = mii->mii_media_active; 1464 ifmr->ifm_status = mii->mii_media_status; 1465 1466 return; 1467 } 1468 1469 static int 1470 lge_ioctl(ifp, command, data) 1471 struct ifnet *ifp; 1472 u_long command; 1473 caddr_t data; 1474 { 1475 struct lge_softc *sc = ifp->if_softc; 1476 struct ifreq *ifr = (struct ifreq *) data; 1477 struct mii_data *mii; 1478 int s, error = 0; 1479 1480 s = splimp(); 1481 1482 switch(command) { 1483 case SIOCSIFMTU: 1484 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1485 error = EINVAL; 1486 else 1487 ifp->if_mtu = ifr->ifr_mtu; 1488 break; 1489 case SIOCSIFFLAGS: 1490 if (ifp->if_flags & IFF_UP) { 1491 if (ifp->if_flags & IFF_RUNNING && 1492 ifp->if_flags & IFF_PROMISC && 1493 !(sc->lge_if_flags & IFF_PROMISC)) { 1494 CSR_WRITE_4(sc, LGE_MODE1, 1495 LGE_MODE1_SETRST_CTL1| 1496 LGE_MODE1_RX_PROMISC); 1497 } else if (ifp->if_flags & IFF_RUNNING && 1498 !(ifp->if_flags & IFF_PROMISC) && 1499 sc->lge_if_flags & IFF_PROMISC) { 1500 CSR_WRITE_4(sc, LGE_MODE1, 1501 LGE_MODE1_RX_PROMISC); 1502 } else { 1503 ifp->if_flags &= ~IFF_RUNNING; 1504 lge_init(sc); 1505 } 1506 } else { 1507 if (ifp->if_flags & IFF_RUNNING) 1508 lge_stop(sc); 1509 } 1510 sc->lge_if_flags = ifp->if_flags; 1511 error = 0; 1512 break; 1513 case SIOCADDMULTI: 1514 case SIOCDELMULTI: 1515 lge_setmulti(sc); 1516 error = 0; 1517 break; 1518 case SIOCGIFMEDIA: 1519 case SIOCSIFMEDIA: 1520 mii = device_get_softc(sc->lge_miibus); 1521 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1522 break; 1523 default: 1524 error = ether_ioctl(ifp, command, data); 1525 break; 1526 } 1527 1528 (void)splx(s); 1529 1530 return(error); 1531 } 1532 1533 static void 1534 lge_watchdog(ifp) 1535 struct ifnet *ifp; 1536 { 1537 struct lge_softc *sc; 1538 1539 sc = ifp->if_softc; 1540 1541 ifp->if_oerrors++; 1542 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1543 1544 lge_stop(sc); 1545 lge_reset(sc); 1546 ifp->if_flags &= ~IFF_RUNNING; 1547 lge_init(sc); 1548 1549 if (ifp->if_snd.ifq_head != NULL) 1550 lge_start(ifp); 1551 1552 return; 1553 } 1554 1555 /* 1556 * Stop the adapter and free any mbufs allocated to the 1557 * RX and TX lists. 1558 */ 1559 static void 1560 lge_stop(sc) 1561 struct lge_softc *sc; 1562 { 1563 register int i; 1564 struct ifnet *ifp; 1565 1566 ifp = &sc->arpcom.ac_if; 1567 ifp->if_timer = 0; 1568 untimeout(lge_tick, sc, sc->lge_stat_ch); 1569 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1570 1571 /* Disable receiver and transmitter. */ 1572 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1573 sc->lge_link = 0; 1574 1575 /* 1576 * Free data in the RX lists. 1577 */ 1578 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1579 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1580 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1581 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1582 } 1583 } 1584 bzero((char *)&sc->lge_ldata->lge_rx_list, 1585 sizeof(sc->lge_ldata->lge_rx_list)); 1586 1587 /* 1588 * Free the TX list buffers. 1589 */ 1590 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1591 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1592 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1593 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1594 } 1595 } 1596 1597 bzero((char *)&sc->lge_ldata->lge_tx_list, 1598 sizeof(sc->lge_ldata->lge_tx_list)); 1599 1600 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1601 1602 return; 1603 } 1604 1605 /* 1606 * Stop all chip I/O so that the kernel's probe routines don't 1607 * get confused by errant DMAs when rebooting. 1608 */ 1609 static void 1610 lge_shutdown(dev) 1611 device_t dev; 1612 { 1613 struct lge_softc *sc; 1614 1615 sc = device_get_softc(dev); 1616 1617 lge_reset(sc); 1618 lge_stop(sc); 1619 1620 return; 1621 } 1622