1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 36 * documentation not available, but ask me nicely. 37 * 38 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 39 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 40 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 41 * are three supported methods for data transfer between host and 42 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 43 * Propulsion Technology (tm) DMA. The latter mechanism is a form 44 * of double buffer DMA where the packet data is copied to a 45 * pre-allocated DMA buffer who's physical address has been loaded 46 * into a table at device initialization time. The rationale is that 47 * the virtual to physical address translation needed for normal 48 * scatter/gather DMA is more expensive than the data copy needed 49 * for double buffering. This may be true in Windows NT and the like, 50 * but it isn't true for us, at least on the x86 arch. This driver 51 * uses the scatter/gather I/O method for both TX and RX. 52 * 53 * The LXT1001 only supports TCP/IP checksum offload on receive. 54 * Also, the VLAN tagging is done using a 16-entry table which allows 55 * the chip to perform hardware filtering based on VLAN tags. Sadly, 56 * our vlan support doesn't currently play well with this kind of 57 * hardware support. 58 * 59 * Special thanks to: 60 * - Jeff James at Intel, for arranging to have the LXT1001 manual 61 * released (at long last) 62 * - Beny Chen at D-Link, for actually sending it to me 63 * - Brad Short and Keith Alexis at SMC, for sending me sample 64 * SMC9462SX and SMC9462TX adapters for testing 65 * - Paul Saab at Y!, for not killing me (though it remains to be seen 66 * if in fact he did me much of a favor) 67 */ 68 69 #include <sys/cdefs.h> 70 __FBSDID("$FreeBSD$"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 80 #include <net/if.h> 81 #include <net/if_arp.h> 82 #include <net/ethernet.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 86 #include <net/bpf.h> 87 88 #include <vm/vm.h> /* for vtophys */ 89 #include <vm/pmap.h> /* for vtophys */ 90 #include <machine/clock.h> /* for DELAY */ 91 #include <machine/bus_pio.h> 92 #include <machine/bus_memio.h> 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <pci/pcireg.h> 102 #include <pci/pcivar.h> 103 104 #define LGE_USEIOSPACE 105 106 #include <dev/lge/if_lgereg.h> 107 108 /* "controller miibus0" required. See GENERIC if you get errors here. */ 109 #include "miibus_if.h" 110 111 /* 112 * Various supported device vendors/types and their names. 113 */ 114 static struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117 }; 118 119 static int lge_probe(device_t); 120 static int lge_attach(device_t); 121 static int lge_detach(device_t); 122 123 static int lge_alloc_jumbo_mem(struct lge_softc *); 124 static void lge_free_jumbo_mem(struct lge_softc *); 125 static void *lge_jalloc(struct lge_softc *); 126 static void lge_jfree(void *, void *); 127 128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130 static void lge_rxeof(struct lge_softc *, int); 131 static void lge_rxeoc(struct lge_softc *); 132 static void lge_txeof(struct lge_softc *); 133 static void lge_intr(void *); 134 static void lge_tick(void *); 135 static void lge_start(struct ifnet *); 136 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137 static void lge_init(void *); 138 static void lge_stop(struct lge_softc *); 139 static void lge_watchdog(struct ifnet *); 140 static void lge_shutdown(device_t); 141 static int lge_ifmedia_upd(struct ifnet *); 142 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 145 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 146 147 static int lge_miibus_readreg(device_t, int, int); 148 static int lge_miibus_writereg(device_t, int, int, int); 149 static void lge_miibus_statchg(device_t); 150 151 static void lge_setmulti(struct lge_softc *); 152 static u_int32_t lge_crc(struct lge_softc *, caddr_t); 153 static void lge_reset(struct lge_softc *); 154 static int lge_list_rx_init(struct lge_softc *); 155 static int lge_list_tx_init(struct lge_softc *); 156 157 #ifdef LGE_USEIOSPACE 158 #define LGE_RES SYS_RES_IOPORT 159 #define LGE_RID LGE_PCI_LOIO 160 #else 161 #define LGE_RES SYS_RES_MEMORY 162 #define LGE_RID LGE_PCI_LOMEM 163 #endif 164 165 static device_method_t lge_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, lge_probe), 168 DEVMETHOD(device_attach, lge_attach), 169 DEVMETHOD(device_detach, lge_detach), 170 DEVMETHOD(device_shutdown, lge_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 { 0, 0 } 182 }; 183 184 static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188 }; 189 190 static devclass_t lge_devclass; 191 192 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 193 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194 195 #define LGE_SETBIT(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, \ 197 CSR_READ_4(sc, reg) | (x)) 198 199 #define LGE_CLRBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) & ~(x)) 202 203 #define SIO_SET(x) \ 204 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 205 206 #define SIO_CLR(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 208 209 /* 210 * Read a word of data stored in the EEPROM at address 'addr.' 211 */ 212 static void 213 lge_eeprom_getword(sc, addr, dest) 214 struct lge_softc *sc; 215 int addr; 216 u_int16_t *dest; 217 { 218 register int i; 219 u_int32_t val; 220 221 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 222 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 223 224 for (i = 0; i < LGE_TIMEOUT; i++) 225 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 226 break; 227 228 if (i == LGE_TIMEOUT) { 229 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 230 return; 231 } 232 233 val = CSR_READ_4(sc, LGE_EEDATA); 234 235 if (addr & 1) 236 *dest = (val >> 16) & 0xFFFF; 237 else 238 *dest = val & 0xFFFF; 239 240 return; 241 } 242 243 /* 244 * Read a sequence of words from the EEPROM. 245 */ 246 static void 247 lge_read_eeprom(sc, dest, off, cnt, swap) 248 struct lge_softc *sc; 249 caddr_t dest; 250 int off; 251 int cnt; 252 int swap; 253 { 254 int i; 255 u_int16_t word = 0, *ptr; 256 257 for (i = 0; i < cnt; i++) { 258 lge_eeprom_getword(sc, off + i, &word); 259 ptr = (u_int16_t *)(dest + (i * 2)); 260 if (swap) 261 *ptr = ntohs(word); 262 else 263 *ptr = word; 264 } 265 266 return; 267 } 268 269 static int 270 lge_miibus_readreg(dev, phy, reg) 271 device_t dev; 272 int phy, reg; 273 { 274 struct lge_softc *sc; 275 int i; 276 277 sc = device_get_softc(dev); 278 279 /* 280 * If we have a non-PCS PHY, pretend that the internal 281 * autoneg stuff at PHY address 0 isn't there so that 282 * the miibus code will find only the GMII PHY. 283 */ 284 if (sc->lge_pcs == 0 && phy == 0) 285 return(0); 286 287 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 288 289 for (i = 0; i < LGE_TIMEOUT; i++) 290 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 291 break; 292 293 if (i == LGE_TIMEOUT) { 294 printf("lge%d: PHY read timed out\n", sc->lge_unit); 295 return(0); 296 } 297 298 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 299 } 300 301 static int 302 lge_miibus_writereg(dev, phy, reg, data) 303 device_t dev; 304 int phy, reg, data; 305 { 306 struct lge_softc *sc; 307 int i; 308 309 sc = device_get_softc(dev); 310 311 CSR_WRITE_4(sc, LGE_GMIICTL, 312 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 313 314 for (i = 0; i < LGE_TIMEOUT; i++) 315 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 316 break; 317 318 if (i == LGE_TIMEOUT) { 319 printf("lge%d: PHY write timed out\n", sc->lge_unit); 320 return(0); 321 } 322 323 return(0); 324 } 325 326 static void 327 lge_miibus_statchg(dev) 328 device_t dev; 329 { 330 struct lge_softc *sc; 331 struct mii_data *mii; 332 333 sc = device_get_softc(dev); 334 mii = device_get_softc(sc->lge_miibus); 335 336 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 337 switch (IFM_SUBTYPE(mii->mii_media_active)) { 338 case IFM_1000_T: 339 case IFM_1000_SX: 340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 341 break; 342 case IFM_100_TX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 344 break; 345 case IFM_10_T: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 347 break; 348 default: 349 /* 350 * Choose something, even if it's wrong. Clearing 351 * all the bits will hose autoneg on the internal 352 * PHY. 353 */ 354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 355 break; 356 } 357 358 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 359 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 360 } else { 361 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 362 } 363 364 return; 365 } 366 367 static u_int32_t 368 lge_crc(sc, addr) 369 struct lge_softc *sc; 370 caddr_t addr; 371 { 372 u_int32_t crc, carry; 373 int i, j; 374 u_int8_t c; 375 376 /* Compute CRC for the address value. */ 377 crc = 0xFFFFFFFF; /* initial value */ 378 379 for (i = 0; i < 6; i++) { 380 c = *(addr + i); 381 for (j = 0; j < 8; j++) { 382 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 383 crc <<= 1; 384 c >>= 1; 385 if (carry) 386 crc = (crc ^ 0x04c11db6) | carry; 387 } 388 } 389 390 /* 391 * return the filter bit position 392 */ 393 return((crc >> 26) & 0x0000003F); 394 } 395 396 static void 397 lge_setmulti(sc) 398 struct lge_softc *sc; 399 { 400 struct ifnet *ifp; 401 struct ifmultiaddr *ifma; 402 u_int32_t h = 0, hashes[2] = { 0, 0 }; 403 404 ifp = &sc->arpcom.ac_if; 405 406 /* Make sure multicast hash table is enabled. */ 407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 408 409 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 410 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 411 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 412 return; 413 } 414 415 /* first, zot all the existing hash bits */ 416 CSR_WRITE_4(sc, LGE_MAR0, 0); 417 CSR_WRITE_4(sc, LGE_MAR1, 0); 418 419 /* now program new ones */ 420 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 421 if (ifma->ifma_addr->sa_family != AF_LINK) 422 continue; 423 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 424 if (h < 32) 425 hashes[0] |= (1 << h); 426 else 427 hashes[1] |= (1 << (h - 32)); 428 } 429 430 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 431 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 432 433 return; 434 } 435 436 static void 437 lge_reset(sc) 438 struct lge_softc *sc; 439 { 440 register int i; 441 442 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 443 444 for (i = 0; i < LGE_TIMEOUT; i++) { 445 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 446 break; 447 } 448 449 if (i == LGE_TIMEOUT) 450 printf("lge%d: reset never completed\n", sc->lge_unit); 451 452 /* Wait a little while for the chip to get its brains in order. */ 453 DELAY(1000); 454 455 return; 456 } 457 458 /* 459 * Probe for a Level 1 chip. Check the PCI vendor and device 460 * IDs against our list and return a device name if we find a match. 461 */ 462 static int 463 lge_probe(dev) 464 device_t dev; 465 { 466 struct lge_type *t; 467 468 t = lge_devs; 469 470 while(t->lge_name != NULL) { 471 if ((pci_get_vendor(dev) == t->lge_vid) && 472 (pci_get_device(dev) == t->lge_did)) { 473 device_set_desc(dev, t->lge_name); 474 return(0); 475 } 476 t++; 477 } 478 479 return(ENXIO); 480 } 481 482 /* 483 * Attach the interface. Allocate softc structures, do ifmedia 484 * setup and ethernet/BPF attach. 485 */ 486 static int 487 lge_attach(dev) 488 device_t dev; 489 { 490 int s; 491 u_char eaddr[ETHER_ADDR_LEN]; 492 u_int32_t command; 493 struct lge_softc *sc; 494 struct ifnet *ifp; 495 int unit, error = 0, rid; 496 497 s = splimp(); 498 499 sc = device_get_softc(dev); 500 unit = device_get_unit(dev); 501 bzero(sc, sizeof(struct lge_softc)); 502 503 /* 504 * Handle power management nonsense. 505 */ 506 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 507 u_int32_t iobase, membase, irq; 508 509 /* Save important PCI config data. */ 510 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 511 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 512 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 513 514 /* Reset the power state. */ 515 printf("lge%d: chip is in D%d power mode " 516 "-- setting to D0\n", unit, 517 pci_get_powerstate(dev)); 518 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 519 520 /* Restore PCI config data. */ 521 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 522 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 523 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 524 } 525 526 /* 527 * Map control/status registers. 528 */ 529 pci_enable_busmaster(dev); 530 pci_enable_io(dev, SYS_RES_IOPORT); 531 pci_enable_io(dev, SYS_RES_MEMORY); 532 command = pci_read_config(dev, PCIR_COMMAND, 4); 533 534 #ifdef LGE_USEIOSPACE 535 if (!(command & PCIM_CMD_PORTEN)) { 536 printf("lge%d: failed to enable I/O ports!\n", unit); 537 error = ENXIO;; 538 goto fail; 539 } 540 #else 541 if (!(command & PCIM_CMD_MEMEN)) { 542 printf("lge%d: failed to enable memory mapping!\n", unit); 543 error = ENXIO;; 544 goto fail; 545 } 546 #endif 547 548 rid = LGE_RID; 549 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 550 0, ~0, 1, RF_ACTIVE); 551 552 if (sc->lge_res == NULL) { 553 printf("lge%d: couldn't map ports/memory\n", unit); 554 error = ENXIO; 555 goto fail; 556 } 557 558 sc->lge_btag = rman_get_bustag(sc->lge_res); 559 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 560 561 /* Allocate interrupt */ 562 rid = 0; 563 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 564 RF_SHAREABLE | RF_ACTIVE); 565 566 if (sc->lge_irq == NULL) { 567 printf("lge%d: couldn't map interrupt\n", unit); 568 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 569 error = ENXIO; 570 goto fail; 571 } 572 573 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 574 lge_intr, sc, &sc->lge_intrhand); 575 576 if (error) { 577 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 578 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 579 printf("lge%d: couldn't set up irq\n", unit); 580 goto fail; 581 } 582 583 /* Reset the adapter. */ 584 lge_reset(sc); 585 586 /* 587 * Get station address from the EEPROM. 588 */ 589 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 590 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 591 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 592 593 /* 594 * A Level 1 chip was detected. Inform the world. 595 */ 596 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 597 598 sc->lge_unit = unit; 599 callout_handle_init(&sc->lge_stat_ch); 600 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 601 602 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 603 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 604 605 if (sc->lge_ldata == NULL) { 606 printf("lge%d: no memory for list buffers!\n", unit); 607 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 608 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 609 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 610 error = ENXIO; 611 goto fail; 612 } 613 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 614 615 /* Try to allocate memory for jumbo buffers. */ 616 if (lge_alloc_jumbo_mem(sc)) { 617 printf("lge%d: jumbo buffer allocation failed\n", 618 sc->lge_unit); 619 contigfree(sc->lge_ldata, 620 sizeof(struct lge_list_data), M_DEVBUF); 621 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 622 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 623 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 624 error = ENXIO; 625 goto fail; 626 } 627 628 ifp = &sc->arpcom.ac_if; 629 ifp->if_softc = sc; 630 ifp->if_unit = unit; 631 ifp->if_name = "lge"; 632 ifp->if_mtu = ETHERMTU; 633 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 634 ifp->if_ioctl = lge_ioctl; 635 ifp->if_output = ether_output; 636 ifp->if_start = lge_start; 637 ifp->if_watchdog = lge_watchdog; 638 ifp->if_init = lge_init; 639 ifp->if_baudrate = 1000000000; 640 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 641 ifp->if_capabilities = IFCAP_RXCSUM; 642 ifp->if_capenable = ifp->if_capabilities; 643 644 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 645 sc->lge_pcs = 1; 646 else 647 sc->lge_pcs = 0; 648 649 /* 650 * Do MII setup. 651 */ 652 if (mii_phy_probe(dev, &sc->lge_miibus, 653 lge_ifmedia_upd, lge_ifmedia_sts)) { 654 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 655 contigfree(sc->lge_ldata, 656 sizeof(struct lge_list_data), M_DEVBUF); 657 lge_free_jumbo_mem(sc); 658 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 659 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 660 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 661 error = ENXIO; 662 goto fail; 663 } 664 665 /* 666 * Call MI attach routine. 667 */ 668 ether_ifattach(ifp, eaddr); 669 callout_handle_init(&sc->lge_stat_ch); 670 671 fail: 672 splx(s); 673 return(error); 674 } 675 676 static int 677 lge_detach(dev) 678 device_t dev; 679 { 680 struct lge_softc *sc; 681 struct ifnet *ifp; 682 int s; 683 684 s = splimp(); 685 686 sc = device_get_softc(dev); 687 ifp = &sc->arpcom.ac_if; 688 689 lge_reset(sc); 690 lge_stop(sc); 691 ether_ifdetach(ifp); 692 693 bus_generic_detach(dev); 694 device_delete_child(dev, sc->lge_miibus); 695 696 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 697 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 698 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 699 700 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 701 lge_free_jumbo_mem(sc); 702 703 splx(s); 704 705 return(0); 706 } 707 708 /* 709 * Initialize the transmit descriptors. 710 */ 711 static int 712 lge_list_tx_init(sc) 713 struct lge_softc *sc; 714 { 715 struct lge_list_data *ld; 716 struct lge_ring_data *cd; 717 int i; 718 719 cd = &sc->lge_cdata; 720 ld = sc->lge_ldata; 721 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 722 ld->lge_tx_list[i].lge_mbuf = NULL; 723 ld->lge_tx_list[i].lge_ctl = 0; 724 } 725 726 cd->lge_tx_prod = cd->lge_tx_cons = 0; 727 728 return(0); 729 } 730 731 732 /* 733 * Initialize the RX descriptors and allocate mbufs for them. Note that 734 * we arralge the descriptors in a closed ring, so that the last descriptor 735 * points back to the first. 736 */ 737 static int 738 lge_list_rx_init(sc) 739 struct lge_softc *sc; 740 { 741 struct lge_list_data *ld; 742 struct lge_ring_data *cd; 743 int i; 744 745 ld = sc->lge_ldata; 746 cd = &sc->lge_cdata; 747 748 cd->lge_rx_prod = cd->lge_rx_cons = 0; 749 750 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 751 752 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 753 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 754 break; 755 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 756 return(ENOBUFS); 757 } 758 759 /* Clear possible 'rx command queue empty' interrupt. */ 760 CSR_READ_4(sc, LGE_ISR); 761 762 return(0); 763 } 764 765 /* 766 * Initialize an RX descriptor and attach an MBUF cluster. 767 */ 768 static int 769 lge_newbuf(sc, c, m) 770 struct lge_softc *sc; 771 struct lge_rx_desc *c; 772 struct mbuf *m; 773 { 774 struct mbuf *m_new = NULL; 775 caddr_t *buf = NULL; 776 777 if (m == NULL) { 778 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 779 if (m_new == NULL) { 780 printf("lge%d: no memory for rx list " 781 "-- packet dropped!\n", sc->lge_unit); 782 return(ENOBUFS); 783 } 784 785 /* Allocate the jumbo buffer */ 786 buf = lge_jalloc(sc); 787 if (buf == NULL) { 788 #ifdef LGE_VERBOSE 789 printf("lge%d: jumbo allocation failed " 790 "-- packet dropped!\n", sc->lge_unit); 791 #endif 792 m_freem(m_new); 793 return(ENOBUFS); 794 } 795 /* Attach the buffer to the mbuf */ 796 m_new->m_data = (void *)buf; 797 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 798 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 799 (struct lge_softc *)sc, 0, EXT_NET_DRV); 800 } else { 801 m_new = m; 802 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 803 m_new->m_data = m_new->m_ext.ext_buf; 804 } 805 806 /* 807 * Adjust alignment so packet payload begins on a 808 * longword boundary. Mandatory for Alpha, useful on 809 * x86 too. 810 */ 811 m_adj(m_new, ETHER_ALIGN); 812 813 c->lge_mbuf = m_new; 814 c->lge_fragptr_hi = 0; 815 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 816 c->lge_fraglen = m_new->m_len; 817 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 818 c->lge_sts = 0; 819 820 /* 821 * Put this buffer in the RX command FIFO. To do this, 822 * we just write the physical address of the descriptor 823 * into the RX descriptor address registers. Note that 824 * there are two registers, one high DWORD and one low 825 * DWORD, which lets us specify a 64-bit address if 826 * desired. We only use a 32-bit address for now. 827 * Writing to the low DWORD register is what actually 828 * causes the command to be issued, so we do that 829 * last. 830 */ 831 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 832 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 833 834 return(0); 835 } 836 837 static int 838 lge_alloc_jumbo_mem(sc) 839 struct lge_softc *sc; 840 { 841 caddr_t ptr; 842 register int i; 843 struct lge_jpool_entry *entry; 844 845 /* Grab a big chunk o' storage. */ 846 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 847 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 848 849 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 850 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 851 return(ENOBUFS); 852 } 853 854 SLIST_INIT(&sc->lge_jfree_listhead); 855 SLIST_INIT(&sc->lge_jinuse_listhead); 856 857 /* 858 * Now divide it up into 9K pieces and save the addresses 859 * in an array. 860 */ 861 ptr = sc->lge_cdata.lge_jumbo_buf; 862 for (i = 0; i < LGE_JSLOTS; i++) { 863 sc->lge_cdata.lge_jslots[i] = ptr; 864 ptr += LGE_JLEN; 865 entry = malloc(sizeof(struct lge_jpool_entry), 866 M_DEVBUF, M_NOWAIT); 867 if (entry == NULL) { 868 printf("lge%d: no memory for jumbo " 869 "buffer queue!\n", sc->lge_unit); 870 return(ENOBUFS); 871 } 872 entry->slot = i; 873 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 874 entry, jpool_entries); 875 } 876 877 return(0); 878 } 879 880 static void 881 lge_free_jumbo_mem(sc) 882 struct lge_softc *sc; 883 { 884 int i; 885 struct lge_jpool_entry *entry; 886 887 for (i = 0; i < LGE_JSLOTS; i++) { 888 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 889 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 890 free(entry, M_DEVBUF); 891 } 892 893 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 894 895 return; 896 } 897 898 /* 899 * Allocate a jumbo buffer. 900 */ 901 static void * 902 lge_jalloc(sc) 903 struct lge_softc *sc; 904 { 905 struct lge_jpool_entry *entry; 906 907 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 908 909 if (entry == NULL) { 910 #ifdef LGE_VERBOSE 911 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 912 #endif 913 return(NULL); 914 } 915 916 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 917 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 918 return(sc->lge_cdata.lge_jslots[entry->slot]); 919 } 920 921 /* 922 * Release a jumbo buffer. 923 */ 924 static void 925 lge_jfree(buf, args) 926 void *buf; 927 void *args; 928 { 929 struct lge_softc *sc; 930 int i; 931 struct lge_jpool_entry *entry; 932 933 /* Extract the softc struct pointer. */ 934 sc = args; 935 936 if (sc == NULL) 937 panic("lge_jfree: can't find softc pointer!"); 938 939 /* calculate the slot this buffer belongs to */ 940 i = ((vm_offset_t)buf 941 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 942 943 if ((i < 0) || (i >= LGE_JSLOTS)) 944 panic("lge_jfree: asked to free buffer that we don't manage!"); 945 946 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 947 if (entry == NULL) 948 panic("lge_jfree: buffer not in use!"); 949 entry->slot = i; 950 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 951 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 952 953 return; 954 } 955 956 /* 957 * A frame has been uploaded: pass the resulting mbuf chain up to 958 * the higher level protocols. 959 */ 960 static void 961 lge_rxeof(sc, cnt) 962 struct lge_softc *sc; 963 int cnt; 964 { 965 struct mbuf *m; 966 struct ifnet *ifp; 967 struct lge_rx_desc *cur_rx; 968 int c, i, total_len = 0; 969 u_int32_t rxsts, rxctl; 970 971 ifp = &sc->arpcom.ac_if; 972 973 /* Find out how many frames were processed. */ 974 c = cnt; 975 i = sc->lge_cdata.lge_rx_cons; 976 977 /* Suck them in. */ 978 while(c) { 979 struct mbuf *m0 = NULL; 980 981 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 982 rxctl = cur_rx->lge_ctl; 983 rxsts = cur_rx->lge_sts; 984 m = cur_rx->lge_mbuf; 985 cur_rx->lge_mbuf = NULL; 986 total_len = LGE_RXBYTES(cur_rx); 987 LGE_INC(i, LGE_RX_LIST_CNT); 988 c--; 989 990 /* 991 * If an error occurs, update stats, clear the 992 * status word and leave the mbuf cluster in place: 993 * it should simply get re-used next time this descriptor 994 * comes up in the ring. 995 */ 996 if (rxctl & LGE_RXCTL_ERRMASK) { 997 ifp->if_ierrors++; 998 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 999 continue; 1000 } 1001 1002 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 1003 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1004 ifp, NULL); 1005 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1006 if (m0 == NULL) { 1007 printf("lge%d: no receive buffers " 1008 "available -- packet dropped!\n", 1009 sc->lge_unit); 1010 ifp->if_ierrors++; 1011 continue; 1012 } 1013 m = m0; 1014 } else { 1015 m->m_pkthdr.rcvif = ifp; 1016 m->m_pkthdr.len = m->m_len = total_len; 1017 } 1018 1019 ifp->if_ipackets++; 1020 1021 /* Do IP checksum checking. */ 1022 if (rxsts & LGE_RXSTS_ISIP) 1023 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1024 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1025 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1026 if ((rxsts & LGE_RXSTS_ISTCP && 1027 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1028 (rxsts & LGE_RXSTS_ISUDP && 1029 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1030 m->m_pkthdr.csum_flags |= 1031 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1032 m->m_pkthdr.csum_data = 0xffff; 1033 } 1034 1035 (*ifp->if_input)(ifp, m); 1036 } 1037 1038 sc->lge_cdata.lge_rx_cons = i; 1039 1040 return; 1041 } 1042 1043 static void 1044 lge_rxeoc(sc) 1045 struct lge_softc *sc; 1046 { 1047 struct ifnet *ifp; 1048 1049 ifp = &sc->arpcom.ac_if; 1050 ifp->if_flags &= ~IFF_RUNNING; 1051 lge_init(sc); 1052 return; 1053 } 1054 1055 /* 1056 * A frame was downloaded to the chip. It's safe for us to clean up 1057 * the list buffers. 1058 */ 1059 1060 static void 1061 lge_txeof(sc) 1062 struct lge_softc *sc; 1063 { 1064 struct lge_tx_desc *cur_tx = NULL; 1065 struct ifnet *ifp; 1066 u_int32_t idx, txdone; 1067 1068 ifp = &sc->arpcom.ac_if; 1069 1070 /* Clear the timeout timer. */ 1071 ifp->if_timer = 0; 1072 1073 /* 1074 * Go through our tx list and free mbufs for those 1075 * frames that have been transmitted. 1076 */ 1077 idx = sc->lge_cdata.lge_tx_cons; 1078 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1079 1080 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1081 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1082 1083 ifp->if_opackets++; 1084 if (cur_tx->lge_mbuf != NULL) { 1085 m_freem(cur_tx->lge_mbuf); 1086 cur_tx->lge_mbuf = NULL; 1087 } 1088 cur_tx->lge_ctl = 0; 1089 1090 txdone--; 1091 LGE_INC(idx, LGE_TX_LIST_CNT); 1092 ifp->if_timer = 0; 1093 } 1094 1095 sc->lge_cdata.lge_tx_cons = idx; 1096 1097 if (cur_tx != NULL) 1098 ifp->if_flags &= ~IFF_OACTIVE; 1099 1100 return; 1101 } 1102 1103 static void 1104 lge_tick(xsc) 1105 void *xsc; 1106 { 1107 struct lge_softc *sc; 1108 struct mii_data *mii; 1109 struct ifnet *ifp; 1110 int s; 1111 1112 s = splimp(); 1113 1114 sc = xsc; 1115 ifp = &sc->arpcom.ac_if; 1116 1117 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1118 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1119 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1120 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1121 1122 if (!sc->lge_link) { 1123 mii = device_get_softc(sc->lge_miibus); 1124 mii_tick(mii); 1125 if (mii->mii_media_status & IFM_ACTIVE && 1126 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1127 sc->lge_link++; 1128 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1129 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1130 printf("lge%d: gigabit link up\n", 1131 sc->lge_unit); 1132 if (ifp->if_snd.ifq_head != NULL) 1133 lge_start(ifp); 1134 } 1135 } 1136 1137 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1138 1139 splx(s); 1140 1141 return; 1142 } 1143 1144 static void 1145 lge_intr(arg) 1146 void *arg; 1147 { 1148 struct lge_softc *sc; 1149 struct ifnet *ifp; 1150 u_int32_t status; 1151 1152 sc = arg; 1153 ifp = &sc->arpcom.ac_if; 1154 1155 /* Supress unwanted interrupts */ 1156 if (!(ifp->if_flags & IFF_UP)) { 1157 lge_stop(sc); 1158 return; 1159 } 1160 1161 for (;;) { 1162 /* 1163 * Reading the ISR register clears all interrupts, and 1164 * clears the 'interrupts enabled' bit in the IMR 1165 * register. 1166 */ 1167 status = CSR_READ_4(sc, LGE_ISR); 1168 1169 if ((status & LGE_INTRS) == 0) 1170 break; 1171 1172 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1173 lge_txeof(sc); 1174 1175 if (status & LGE_ISR_RXDMA_DONE) 1176 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1177 1178 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1179 lge_rxeoc(sc); 1180 1181 if (status & LGE_ISR_PHY_INTR) { 1182 sc->lge_link = 0; 1183 untimeout(lge_tick, sc, sc->lge_stat_ch); 1184 lge_tick(sc); 1185 } 1186 } 1187 1188 /* Re-enable interrupts. */ 1189 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1190 1191 if (ifp->if_snd.ifq_head != NULL) 1192 lge_start(ifp); 1193 1194 return; 1195 } 1196 1197 /* 1198 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1199 * pointers to the fragment pointers. 1200 */ 1201 static int 1202 lge_encap(sc, m_head, txidx) 1203 struct lge_softc *sc; 1204 struct mbuf *m_head; 1205 u_int32_t *txidx; 1206 { 1207 struct lge_frag *f = NULL; 1208 struct lge_tx_desc *cur_tx; 1209 struct mbuf *m; 1210 int frag = 0, tot_len = 0; 1211 1212 /* 1213 * Start packing the mbufs in this chain into 1214 * the fragment pointers. Stop when we run out 1215 * of fragments or hit the end of the mbuf chain. 1216 */ 1217 m = m_head; 1218 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1219 frag = 0; 1220 1221 for (m = m_head; m != NULL; m = m->m_next) { 1222 if (m->m_len != 0) { 1223 tot_len += m->m_len; 1224 f = &cur_tx->lge_frags[frag]; 1225 f->lge_fraglen = m->m_len; 1226 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1227 f->lge_fragptr_hi = 0; 1228 frag++; 1229 } 1230 } 1231 1232 if (m != NULL) 1233 return(ENOBUFS); 1234 1235 cur_tx->lge_mbuf = m_head; 1236 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1237 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1238 1239 /* Queue for transmit */ 1240 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1241 1242 return(0); 1243 } 1244 1245 /* 1246 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1247 * to the mbuf data regions directly in the transmit lists. We also save a 1248 * copy of the pointers since the transmit list fragment pointers are 1249 * physical addresses. 1250 */ 1251 1252 static void 1253 lge_start(ifp) 1254 struct ifnet *ifp; 1255 { 1256 struct lge_softc *sc; 1257 struct mbuf *m_head = NULL; 1258 u_int32_t idx; 1259 1260 sc = ifp->if_softc; 1261 1262 if (!sc->lge_link) 1263 return; 1264 1265 idx = sc->lge_cdata.lge_tx_prod; 1266 1267 if (ifp->if_flags & IFF_OACTIVE) 1268 return; 1269 1270 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1271 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1272 break; 1273 1274 IF_DEQUEUE(&ifp->if_snd, m_head); 1275 if (m_head == NULL) 1276 break; 1277 1278 if (lge_encap(sc, m_head, &idx)) { 1279 IF_PREPEND(&ifp->if_snd, m_head); 1280 ifp->if_flags |= IFF_OACTIVE; 1281 break; 1282 } 1283 1284 /* 1285 * If there's a BPF listener, bounce a copy of this frame 1286 * to him. 1287 */ 1288 BPF_MTAP(ifp, m_head); 1289 } 1290 1291 sc->lge_cdata.lge_tx_prod = idx; 1292 1293 /* 1294 * Set a timeout in case the chip goes out to lunch. 1295 */ 1296 ifp->if_timer = 5; 1297 1298 return; 1299 } 1300 1301 static void 1302 lge_init(xsc) 1303 void *xsc; 1304 { 1305 struct lge_softc *sc = xsc; 1306 struct ifnet *ifp = &sc->arpcom.ac_if; 1307 struct mii_data *mii; 1308 int s; 1309 1310 if (ifp->if_flags & IFF_RUNNING) 1311 return; 1312 1313 s = splimp(); 1314 1315 /* 1316 * Cancel pending I/O and free all RX/TX buffers. 1317 */ 1318 lge_stop(sc); 1319 lge_reset(sc); 1320 1321 mii = device_get_softc(sc->lge_miibus); 1322 1323 /* Set MAC address */ 1324 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1325 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1326 1327 /* Init circular RX list. */ 1328 if (lge_list_rx_init(sc) == ENOBUFS) { 1329 printf("lge%d: initialization failed: no " 1330 "memory for rx buffers\n", sc->lge_unit); 1331 lge_stop(sc); 1332 (void)splx(s); 1333 return; 1334 } 1335 1336 /* 1337 * Init tx descriptors. 1338 */ 1339 lge_list_tx_init(sc); 1340 1341 /* Set initial value for MODE1 register. */ 1342 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1343 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1344 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1345 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1346 1347 /* If we want promiscuous mode, set the allframes bit. */ 1348 if (ifp->if_flags & IFF_PROMISC) { 1349 CSR_WRITE_4(sc, LGE_MODE1, 1350 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1351 } else { 1352 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1353 } 1354 1355 /* 1356 * Set the capture broadcast bit to capture broadcast frames. 1357 */ 1358 if (ifp->if_flags & IFF_BROADCAST) { 1359 CSR_WRITE_4(sc, LGE_MODE1, 1360 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1361 } else { 1362 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1363 } 1364 1365 /* Packet padding workaround? */ 1366 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1367 1368 /* No error frames */ 1369 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1370 1371 /* Receive large frames */ 1372 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1373 1374 /* Workaround: disable RX/TX flow control */ 1375 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1376 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1377 1378 /* Make sure to strip CRC from received frames */ 1379 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1380 1381 /* Turn off magic packet mode */ 1382 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1383 1384 /* Turn off all VLAN stuff */ 1385 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1386 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1387 1388 /* Workarond: FIFO overflow */ 1389 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1390 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1391 1392 /* 1393 * Load the multicast filter. 1394 */ 1395 lge_setmulti(sc); 1396 1397 /* 1398 * Enable hardware checksum validation for all received IPv4 1399 * packets, do not reject packets with bad checksums. 1400 */ 1401 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1402 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1403 LGE_MODE2_RX_ERRCSUM); 1404 1405 /* 1406 * Enable the delivery of PHY interrupts based on 1407 * link/speed/duplex status chalges. 1408 */ 1409 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1410 1411 /* Enable receiver and transmitter. */ 1412 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1414 1415 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1416 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1417 1418 /* 1419 * Enable interrupts. 1420 */ 1421 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1422 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1423 1424 lge_ifmedia_upd(ifp); 1425 1426 ifp->if_flags |= IFF_RUNNING; 1427 ifp->if_flags &= ~IFF_OACTIVE; 1428 1429 (void)splx(s); 1430 1431 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1432 1433 return; 1434 } 1435 1436 /* 1437 * Set media options. 1438 */ 1439 static int 1440 lge_ifmedia_upd(ifp) 1441 struct ifnet *ifp; 1442 { 1443 struct lge_softc *sc; 1444 struct mii_data *mii; 1445 1446 sc = ifp->if_softc; 1447 1448 mii = device_get_softc(sc->lge_miibus); 1449 sc->lge_link = 0; 1450 if (mii->mii_instance) { 1451 struct mii_softc *miisc; 1452 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1453 miisc = LIST_NEXT(miisc, mii_list)) 1454 mii_phy_reset(miisc); 1455 } 1456 mii_mediachg(mii); 1457 1458 return(0); 1459 } 1460 1461 /* 1462 * Report current media status. 1463 */ 1464 static void 1465 lge_ifmedia_sts(ifp, ifmr) 1466 struct ifnet *ifp; 1467 struct ifmediareq *ifmr; 1468 { 1469 struct lge_softc *sc; 1470 struct mii_data *mii; 1471 1472 sc = ifp->if_softc; 1473 1474 mii = device_get_softc(sc->lge_miibus); 1475 mii_pollstat(mii); 1476 ifmr->ifm_active = mii->mii_media_active; 1477 ifmr->ifm_status = mii->mii_media_status; 1478 1479 return; 1480 } 1481 1482 static int 1483 lge_ioctl(ifp, command, data) 1484 struct ifnet *ifp; 1485 u_long command; 1486 caddr_t data; 1487 { 1488 struct lge_softc *sc = ifp->if_softc; 1489 struct ifreq *ifr = (struct ifreq *) data; 1490 struct mii_data *mii; 1491 int s, error = 0; 1492 1493 s = splimp(); 1494 1495 switch(command) { 1496 case SIOCSIFMTU: 1497 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1498 error = EINVAL; 1499 else 1500 ifp->if_mtu = ifr->ifr_mtu; 1501 break; 1502 case SIOCSIFFLAGS: 1503 if (ifp->if_flags & IFF_UP) { 1504 if (ifp->if_flags & IFF_RUNNING && 1505 ifp->if_flags & IFF_PROMISC && 1506 !(sc->lge_if_flags & IFF_PROMISC)) { 1507 CSR_WRITE_4(sc, LGE_MODE1, 1508 LGE_MODE1_SETRST_CTL1| 1509 LGE_MODE1_RX_PROMISC); 1510 } else if (ifp->if_flags & IFF_RUNNING && 1511 !(ifp->if_flags & IFF_PROMISC) && 1512 sc->lge_if_flags & IFF_PROMISC) { 1513 CSR_WRITE_4(sc, LGE_MODE1, 1514 LGE_MODE1_RX_PROMISC); 1515 } else { 1516 ifp->if_flags &= ~IFF_RUNNING; 1517 lge_init(sc); 1518 } 1519 } else { 1520 if (ifp->if_flags & IFF_RUNNING) 1521 lge_stop(sc); 1522 } 1523 sc->lge_if_flags = ifp->if_flags; 1524 error = 0; 1525 break; 1526 case SIOCADDMULTI: 1527 case SIOCDELMULTI: 1528 lge_setmulti(sc); 1529 error = 0; 1530 break; 1531 case SIOCGIFMEDIA: 1532 case SIOCSIFMEDIA: 1533 mii = device_get_softc(sc->lge_miibus); 1534 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1535 break; 1536 default: 1537 error = ether_ioctl(ifp, command, data); 1538 break; 1539 } 1540 1541 (void)splx(s); 1542 1543 return(error); 1544 } 1545 1546 static void 1547 lge_watchdog(ifp) 1548 struct ifnet *ifp; 1549 { 1550 struct lge_softc *sc; 1551 1552 sc = ifp->if_softc; 1553 1554 ifp->if_oerrors++; 1555 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1556 1557 lge_stop(sc); 1558 lge_reset(sc); 1559 ifp->if_flags &= ~IFF_RUNNING; 1560 lge_init(sc); 1561 1562 if (ifp->if_snd.ifq_head != NULL) 1563 lge_start(ifp); 1564 1565 return; 1566 } 1567 1568 /* 1569 * Stop the adapter and free any mbufs allocated to the 1570 * RX and TX lists. 1571 */ 1572 static void 1573 lge_stop(sc) 1574 struct lge_softc *sc; 1575 { 1576 register int i; 1577 struct ifnet *ifp; 1578 1579 ifp = &sc->arpcom.ac_if; 1580 ifp->if_timer = 0; 1581 untimeout(lge_tick, sc, sc->lge_stat_ch); 1582 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1583 1584 /* Disable receiver and transmitter. */ 1585 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1586 sc->lge_link = 0; 1587 1588 /* 1589 * Free data in the RX lists. 1590 */ 1591 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1592 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1593 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1594 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1595 } 1596 } 1597 bzero((char *)&sc->lge_ldata->lge_rx_list, 1598 sizeof(sc->lge_ldata->lge_rx_list)); 1599 1600 /* 1601 * Free the TX list buffers. 1602 */ 1603 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1604 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1605 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1606 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1607 } 1608 } 1609 1610 bzero((char *)&sc->lge_ldata->lge_tx_list, 1611 sizeof(sc->lge_ldata->lge_tx_list)); 1612 1613 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1614 1615 return; 1616 } 1617 1618 /* 1619 * Stop all chip I/O so that the kernel's probe routines don't 1620 * get confused by errant DMAs when rebooting. 1621 */ 1622 static void 1623 lge_shutdown(dev) 1624 device_t dev; 1625 { 1626 struct lge_softc *sc; 1627 1628 sc = device_get_softc(dev); 1629 1630 lge_reset(sc); 1631 lge_stop(sc); 1632 1633 return; 1634 } 1635