1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <william.paul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 41 * documentation not available, but ask me nicely. 42 * 43 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 44 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 45 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 46 * are three supported methods for data transfer between host and 47 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 48 * Propulsion Technology (tm) DMA. The latter mechanism is a form 49 * of double buffer DMA where the packet data is copied to a 50 * pre-allocated DMA buffer who's physical address has been loaded 51 * into a table at device initialization time. The rationale is that 52 * the virtual to physical address translation needed for normal 53 * scatter/gather DMA is more expensive than the data copy needed 54 * for double buffering. This may be true in Windows NT and the like, 55 * but it isn't true for us, at least on the x86 arch. This driver 56 * uses the scatter/gather I/O method for both TX and RX. 57 * 58 * The LXT1001 only supports TCP/IP checksum offload on receive. 59 * Also, the VLAN tagging is done using a 16-entry table which allows 60 * the chip to perform hardware filtering based on VLAN tags. Sadly, 61 * our vlan support doesn't currently play well with this kind of 62 * hardware support. 63 * 64 * Special thanks to: 65 * - Jeff James at Intel, for arranging to have the LXT1001 manual 66 * released (at long last) 67 * - Beny Chen at D-Link, for actually sending it to me 68 * - Brad Short and Keith Alexis at SMC, for sending me sample 69 * SMC9462SX and SMC9462TX adapters for testing 70 * - Paul Saab at Y!, for not killing me (though it remains to be seen 71 * if in fact he did me much of a favor) 72 */ 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 83 #include <net/if.h> 84 #include <net/if_var.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 #include <net/if_types.h> 90 91 #include <net/bpf.h> 92 93 #include <vm/vm.h> /* for vtophys */ 94 #include <vm/pmap.h> /* for vtophys */ 95 #include <machine/bus.h> 96 #include <machine/resource.h> 97 #include <sys/bus.h> 98 #include <sys/rman.h> 99 100 #include <dev/mii/mii.h> 101 #include <dev/mii/miivar.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 106 #define LGE_USEIOSPACE 107 108 #include <dev/lge/if_lgereg.h> 109 110 /* "device miibus" required. See GENERIC if you get errors here. */ 111 #include "miibus_if.h" 112 113 /* 114 * Various supported device vendors/types and their names. 115 */ 116 static const struct lge_type lge_devs[] = { 117 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 118 { 0, 0, NULL } 119 }; 120 121 static int lge_probe(device_t); 122 static int lge_attach(device_t); 123 static int lge_detach(device_t); 124 125 static int lge_alloc_jumbo_mem(struct lge_softc *); 126 static void lge_free_jumbo_mem(struct lge_softc *); 127 static void *lge_jalloc(struct lge_softc *); 128 static void lge_jfree(struct mbuf *); 129 130 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 131 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 132 static void lge_rxeof(struct lge_softc *, int); 133 static void lge_rxeoc(struct lge_softc *); 134 static void lge_txeof(struct lge_softc *); 135 static void lge_intr(void *); 136 static void lge_tick(void *); 137 static void lge_start(if_t); 138 static void lge_start_locked(if_t); 139 static int lge_ioctl(if_t, u_long, caddr_t); 140 static void lge_init(void *); 141 static void lge_init_locked(struct lge_softc *); 142 static void lge_stop(struct lge_softc *); 143 static void lge_watchdog(struct lge_softc *); 144 static int lge_shutdown(device_t); 145 static int lge_ifmedia_upd(if_t); 146 static void lge_ifmedia_upd_locked(if_t); 147 static void lge_ifmedia_sts(if_t, struct ifmediareq *); 148 149 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 150 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 151 152 static int lge_miibus_readreg(device_t, int, int); 153 static int lge_miibus_writereg(device_t, int, int, int); 154 static void lge_miibus_statchg(device_t); 155 156 static void lge_setmulti(struct lge_softc *); 157 static void lge_reset(struct lge_softc *); 158 static int lge_list_rx_init(struct lge_softc *); 159 static int lge_list_tx_init(struct lge_softc *); 160 161 #ifdef LGE_USEIOSPACE 162 #define LGE_RES SYS_RES_IOPORT 163 #define LGE_RID LGE_PCI_LOIO 164 #else 165 #define LGE_RES SYS_RES_MEMORY 166 #define LGE_RID LGE_PCI_LOMEM 167 #endif 168 169 static device_method_t lge_methods[] = { 170 /* Device interface */ 171 DEVMETHOD(device_probe, lge_probe), 172 DEVMETHOD(device_attach, lge_attach), 173 DEVMETHOD(device_detach, lge_detach), 174 DEVMETHOD(device_shutdown, lge_shutdown), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 DEVMETHOD_END 182 }; 183 184 static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188 }; 189 190 DRIVER_MODULE(lge, pci, lge_driver, 0, 0); 191 DRIVER_MODULE(miibus, lge, miibus_driver, 0, 0); 192 MODULE_DEPEND(lge, pci, 1, 1, 1); 193 MODULE_DEPEND(lge, ether, 1, 1, 1); 194 MODULE_DEPEND(lge, miibus, 1, 1, 1); 195 196 #define LGE_SETBIT(sc, reg, x) \ 197 CSR_WRITE_4(sc, reg, \ 198 CSR_READ_4(sc, reg) | (x)) 199 200 #define LGE_CLRBIT(sc, reg, x) \ 201 CSR_WRITE_4(sc, reg, \ 202 CSR_READ_4(sc, reg) & ~(x)) 203 204 #define SIO_SET(x) \ 205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 206 207 #define SIO_CLR(x) \ 208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 209 210 /* 211 * Read a word of data stored in the EEPROM at address 'addr.' 212 */ 213 static void 214 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest) 215 { 216 int i; 217 u_int32_t val; 218 219 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 220 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 221 222 for (i = 0; i < LGE_TIMEOUT; i++) 223 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 224 break; 225 226 if (i == LGE_TIMEOUT) { 227 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 228 return; 229 } 230 231 val = CSR_READ_4(sc, LGE_EEDATA); 232 233 if (addr & 1) 234 *dest = (val >> 16) & 0xFFFF; 235 else 236 *dest = val & 0xFFFF; 237 238 return; 239 } 240 241 /* 242 * Read a sequence of words from the EEPROM. 243 */ 244 static void 245 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt, int swap) 246 { 247 int i; 248 u_int16_t word = 0, *ptr; 249 250 for (i = 0; i < cnt; i++) { 251 lge_eeprom_getword(sc, off + i, &word); 252 ptr = (u_int16_t *)(dest + (i * 2)); 253 if (swap) 254 *ptr = ntohs(word); 255 else 256 *ptr = word; 257 } 258 259 return; 260 } 261 262 static int 263 lge_miibus_readreg(device_t dev, int phy, int reg) 264 { 265 struct lge_softc *sc; 266 int i; 267 268 sc = device_get_softc(dev); 269 270 /* 271 * If we have a non-PCS PHY, pretend that the internal 272 * autoneg stuff at PHY address 0 isn't there so that 273 * the miibus code will find only the GMII PHY. 274 */ 275 if (sc->lge_pcs == 0 && phy == 0) 276 return(0); 277 278 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 279 280 for (i = 0; i < LGE_TIMEOUT; i++) 281 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 282 break; 283 284 if (i == LGE_TIMEOUT) { 285 device_printf(sc->lge_dev, "PHY read timed out\n"); 286 return(0); 287 } 288 289 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 290 } 291 292 static int 293 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 294 { 295 struct lge_softc *sc; 296 int i; 297 298 sc = device_get_softc(dev); 299 300 CSR_WRITE_4(sc, LGE_GMIICTL, 301 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 302 303 for (i = 0; i < LGE_TIMEOUT; i++) 304 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 305 break; 306 307 if (i == LGE_TIMEOUT) { 308 device_printf(sc->lge_dev, "PHY write timed out\n"); 309 return(0); 310 } 311 312 return(0); 313 } 314 315 static void 316 lge_miibus_statchg(device_t dev) 317 { 318 struct lge_softc *sc; 319 struct mii_data *mii; 320 321 sc = device_get_softc(dev); 322 mii = device_get_softc(sc->lge_miibus); 323 324 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 325 switch (IFM_SUBTYPE(mii->mii_media_active)) { 326 case IFM_1000_T: 327 case IFM_1000_SX: 328 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 329 break; 330 case IFM_100_TX: 331 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 332 break; 333 case IFM_10_T: 334 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 335 break; 336 default: 337 /* 338 * Choose something, even if it's wrong. Clearing 339 * all the bits will hose autoneg on the internal 340 * PHY. 341 */ 342 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 343 break; 344 } 345 346 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 347 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 348 } else { 349 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 350 } 351 352 return; 353 } 354 355 static u_int 356 lge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int count) 357 { 358 uint32_t h, *hashes = arg; 359 360 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 361 if (h < 32) 362 hashes[0] |= (1 << h); 363 else 364 hashes[1] |= (1 << (h - 32)); 365 return (1); 366 } 367 368 static void 369 lge_setmulti(struct lge_softc *sc) 370 { 371 if_t ifp; 372 uint32_t hashes[2] = { 0, 0 }; 373 374 ifp = sc->lge_ifp; 375 LGE_LOCK_ASSERT(sc); 376 377 /* Make sure multicast hash table is enabled. */ 378 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 379 380 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 381 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 382 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 383 return; 384 } 385 386 /* first, zot all the existing hash bits */ 387 CSR_WRITE_4(sc, LGE_MAR0, 0); 388 CSR_WRITE_4(sc, LGE_MAR1, 0); 389 390 /* now program new ones */ 391 if_foreach_llmaddr(ifp, lge_hash_maddr, hashes); 392 393 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 394 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 395 396 return; 397 } 398 399 static void 400 lge_reset(struct lge_softc *sc) 401 { 402 int i; 403 404 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 405 406 for (i = 0; i < LGE_TIMEOUT; i++) { 407 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 408 break; 409 } 410 411 if (i == LGE_TIMEOUT) 412 device_printf(sc->lge_dev, "reset never completed\n"); 413 414 /* Wait a little while for the chip to get its brains in order. */ 415 DELAY(1000); 416 417 return; 418 } 419 420 /* 421 * Probe for a Level 1 chip. Check the PCI vendor and device 422 * IDs against our list and return a device name if we find a match. 423 */ 424 static int 425 lge_probe(device_t dev) 426 { 427 const struct lge_type *t; 428 429 t = lge_devs; 430 431 while(t->lge_name != NULL) { 432 if ((pci_get_vendor(dev) == t->lge_vid) && 433 (pci_get_device(dev) == t->lge_did)) { 434 device_set_desc(dev, t->lge_name); 435 return(BUS_PROBE_DEFAULT); 436 } 437 t++; 438 } 439 440 return(ENXIO); 441 } 442 443 /* 444 * Attach the interface. Allocate softc structures, do ifmedia 445 * setup and ethernet/BPF attach. 446 */ 447 static int 448 lge_attach(device_t dev) 449 { 450 u_char eaddr[ETHER_ADDR_LEN]; 451 struct lge_softc *sc; 452 if_t ifp = NULL; 453 int error = 0, rid; 454 455 sc = device_get_softc(dev); 456 sc->lge_dev = dev; 457 458 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 459 MTX_DEF); 460 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 461 462 /* 463 * Map control/status registers. 464 */ 465 pci_enable_busmaster(dev); 466 467 rid = LGE_RID; 468 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 469 470 if (sc->lge_res == NULL) { 471 device_printf(dev, "couldn't map ports/memory\n"); 472 error = ENXIO; 473 goto fail; 474 } 475 476 sc->lge_btag = rman_get_bustag(sc->lge_res); 477 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 478 479 /* Allocate interrupt */ 480 rid = 0; 481 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 482 RF_SHAREABLE | RF_ACTIVE); 483 484 if (sc->lge_irq == NULL) { 485 device_printf(dev, "couldn't map interrupt\n"); 486 error = ENXIO; 487 goto fail; 488 } 489 490 /* Reset the adapter. */ 491 lge_reset(sc); 492 493 /* 494 * Get station address from the EEPROM. 495 */ 496 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 497 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 498 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 499 500 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 501 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 502 503 if (sc->lge_ldata == NULL) { 504 device_printf(dev, "no memory for list buffers!\n"); 505 error = ENXIO; 506 goto fail; 507 } 508 509 /* Try to allocate memory for jumbo buffers. */ 510 if (lge_alloc_jumbo_mem(sc)) { 511 device_printf(dev, "jumbo buffer allocation failed\n"); 512 error = ENXIO; 513 goto fail; 514 } 515 516 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 517 if (ifp == NULL) { 518 device_printf(dev, "can not if_alloc()\n"); 519 error = ENOSPC; 520 goto fail; 521 } 522 if_setsoftc(ifp, sc); 523 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 524 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 525 if_setioctlfn(ifp, lge_ioctl); 526 if_setstartfn(ifp, lge_start); 527 if_setinitfn(ifp, lge_init); 528 if_setsendqlen(ifp, LGE_TX_LIST_CNT - 1); 529 if_setcapabilities(ifp, IFCAP_RXCSUM); 530 if_setcapenable(ifp, if_getcapabilities(ifp)); 531 532 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 533 sc->lge_pcs = 1; 534 else 535 sc->lge_pcs = 0; 536 537 /* 538 * Do MII setup. 539 */ 540 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd, 541 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 542 if (error != 0) { 543 device_printf(dev, "attaching PHYs failed\n"); 544 goto fail; 545 } 546 547 /* 548 * Call MI attach routine. 549 */ 550 ether_ifattach(ifp, eaddr); 551 552 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 553 NULL, lge_intr, sc, &sc->lge_intrhand); 554 555 if (error) { 556 ether_ifdetach(ifp); 557 device_printf(dev, "couldn't set up irq\n"); 558 goto fail; 559 } 560 return (0); 561 562 fail: 563 lge_free_jumbo_mem(sc); 564 if (sc->lge_ldata) 565 contigfree(sc->lge_ldata, 566 sizeof(struct lge_list_data), M_DEVBUF); 567 if (ifp) 568 if_free(ifp); 569 if (sc->lge_irq) 570 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 571 if (sc->lge_res) 572 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 573 mtx_destroy(&sc->lge_mtx); 574 return(error); 575 } 576 577 static int 578 lge_detach(device_t dev) 579 { 580 struct lge_softc *sc; 581 if_t ifp; 582 583 sc = device_get_softc(dev); 584 ifp = sc->lge_ifp; 585 586 LGE_LOCK(sc); 587 lge_reset(sc); 588 lge_stop(sc); 589 LGE_UNLOCK(sc); 590 callout_drain(&sc->lge_stat_callout); 591 ether_ifdetach(ifp); 592 593 bus_generic_detach(dev); 594 device_delete_child(dev, sc->lge_miibus); 595 596 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 597 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 598 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 599 600 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 601 if_free(ifp); 602 lge_free_jumbo_mem(sc); 603 mtx_destroy(&sc->lge_mtx); 604 605 return(0); 606 } 607 608 /* 609 * Initialize the transmit descriptors. 610 */ 611 static int 612 lge_list_tx_init(struct lge_softc *sc) 613 { 614 struct lge_list_data *ld; 615 struct lge_ring_data *cd; 616 int i; 617 618 cd = &sc->lge_cdata; 619 ld = sc->lge_ldata; 620 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 621 ld->lge_tx_list[i].lge_mbuf = NULL; 622 ld->lge_tx_list[i].lge_ctl = 0; 623 } 624 625 cd->lge_tx_prod = cd->lge_tx_cons = 0; 626 627 return(0); 628 } 629 630 631 /* 632 * Initialize the RX descriptors and allocate mbufs for them. Note that 633 * we arralge the descriptors in a closed ring, so that the last descriptor 634 * points back to the first. 635 */ 636 static int 637 lge_list_rx_init(struct lge_softc *sc) 638 { 639 struct lge_list_data *ld; 640 struct lge_ring_data *cd; 641 int i; 642 643 ld = sc->lge_ldata; 644 cd = &sc->lge_cdata; 645 646 cd->lge_rx_prod = cd->lge_rx_cons = 0; 647 648 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 649 650 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 651 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 652 break; 653 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 654 return(ENOBUFS); 655 } 656 657 /* Clear possible 'rx command queue empty' interrupt. */ 658 CSR_READ_4(sc, LGE_ISR); 659 660 return(0); 661 } 662 663 /* 664 * Initialize an RX descriptor and attach an MBUF cluster. 665 */ 666 static int 667 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 668 { 669 struct mbuf *m_new = NULL; 670 char *buf = NULL; 671 672 if (m == NULL) { 673 MGETHDR(m_new, M_NOWAIT, MT_DATA); 674 if (m_new == NULL) { 675 device_printf(sc->lge_dev, "no memory for rx list " 676 "-- packet dropped!\n"); 677 return(ENOBUFS); 678 } 679 680 /* Allocate the jumbo buffer */ 681 buf = lge_jalloc(sc); 682 if (buf == NULL) { 683 #ifdef LGE_VERBOSE 684 device_printf(sc->lge_dev, "jumbo allocation failed " 685 "-- packet dropped!\n"); 686 #endif 687 m_freem(m_new); 688 return(ENOBUFS); 689 } 690 /* Attach the buffer to the mbuf */ 691 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 692 m_extadd(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, sc, NULL, 693 0, EXT_NET_DRV); 694 } else { 695 m_new = m; 696 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 697 m_new->m_data = m_new->m_ext.ext_buf; 698 } 699 700 /* 701 * Adjust alignment so packet payload begins on a 702 * longword boundary. Mandatory for Alpha, useful on 703 * x86 too. 704 */ 705 m_adj(m_new, ETHER_ALIGN); 706 707 c->lge_mbuf = m_new; 708 c->lge_fragptr_hi = 0; 709 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 710 c->lge_fraglen = m_new->m_len; 711 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 712 c->lge_sts = 0; 713 714 /* 715 * Put this buffer in the RX command FIFO. To do this, 716 * we just write the physical address of the descriptor 717 * into the RX descriptor address registers. Note that 718 * there are two registers, one high DWORD and one low 719 * DWORD, which lets us specify a 64-bit address if 720 * desired. We only use a 32-bit address for now. 721 * Writing to the low DWORD register is what actually 722 * causes the command to be issued, so we do that 723 * last. 724 */ 725 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 726 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 727 728 return(0); 729 } 730 731 static int 732 lge_alloc_jumbo_mem(struct lge_softc *sc) 733 { 734 caddr_t ptr; 735 int i; 736 struct lge_jpool_entry *entry; 737 738 /* Grab a big chunk o' storage. */ 739 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 740 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 741 742 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 743 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 744 return(ENOBUFS); 745 } 746 747 SLIST_INIT(&sc->lge_jfree_listhead); 748 SLIST_INIT(&sc->lge_jinuse_listhead); 749 750 /* 751 * Now divide it up into 9K pieces and save the addresses 752 * in an array. 753 */ 754 ptr = sc->lge_cdata.lge_jumbo_buf; 755 for (i = 0; i < LGE_JSLOTS; i++) { 756 sc->lge_cdata.lge_jslots[i] = ptr; 757 ptr += LGE_JLEN; 758 entry = malloc(sizeof(struct lge_jpool_entry), 759 M_DEVBUF, M_NOWAIT); 760 if (entry == NULL) { 761 device_printf(sc->lge_dev, "no memory for jumbo " 762 "buffer queue!\n"); 763 return(ENOBUFS); 764 } 765 entry->slot = i; 766 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 767 entry, jpool_entries); 768 } 769 770 return(0); 771 } 772 773 static void 774 lge_free_jumbo_mem(struct lge_softc *sc) 775 { 776 struct lge_jpool_entry *entry; 777 778 if (sc->lge_cdata.lge_jumbo_buf == NULL) 779 return; 780 781 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) { 782 device_printf(sc->lge_dev, 783 "asked to free buffer that is in use!\n"); 784 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 785 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, 786 jpool_entries); 787 } 788 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) { 789 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 790 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 791 free(entry, M_DEVBUF); 792 } 793 794 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 795 796 return; 797 } 798 799 /* 800 * Allocate a jumbo buffer. 801 */ 802 static void * 803 lge_jalloc(struct lge_softc *sc) 804 { 805 struct lge_jpool_entry *entry; 806 807 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 808 809 if (entry == NULL) { 810 #ifdef LGE_VERBOSE 811 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 812 #endif 813 return(NULL); 814 } 815 816 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 817 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 818 return(sc->lge_cdata.lge_jslots[entry->slot]); 819 } 820 821 /* 822 * Release a jumbo buffer. 823 */ 824 static void 825 lge_jfree(struct mbuf *m) 826 { 827 struct lge_softc *sc; 828 int i; 829 struct lge_jpool_entry *entry; 830 831 /* Extract the softc struct pointer. */ 832 sc = m->m_ext.ext_arg1; 833 834 if (sc == NULL) 835 panic("lge_jfree: can't find softc pointer!"); 836 837 /* calculate the slot this buffer belongs to */ 838 i = ((vm_offset_t)m->m_ext.ext_buf 839 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 840 841 if ((i < 0) || (i >= LGE_JSLOTS)) 842 panic("lge_jfree: asked to free buffer that we don't manage!"); 843 844 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 845 if (entry == NULL) 846 panic("lge_jfree: buffer not in use!"); 847 entry->slot = i; 848 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 849 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 850 } 851 852 /* 853 * A frame has been uploaded: pass the resulting mbuf chain up to 854 * the higher level protocols. 855 */ 856 static void 857 lge_rxeof(struct lge_softc *sc, int cnt) 858 { 859 struct mbuf *m; 860 if_t ifp; 861 struct lge_rx_desc *cur_rx; 862 int c, i, total_len = 0; 863 u_int32_t rxsts, rxctl; 864 865 ifp = sc->lge_ifp; 866 867 /* Find out how many frames were processed. */ 868 c = cnt; 869 i = sc->lge_cdata.lge_rx_cons; 870 871 /* Suck them in. */ 872 while(c) { 873 struct mbuf *m0 = NULL; 874 875 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 876 rxctl = cur_rx->lge_ctl; 877 rxsts = cur_rx->lge_sts; 878 m = cur_rx->lge_mbuf; 879 cur_rx->lge_mbuf = NULL; 880 total_len = LGE_RXBYTES(cur_rx); 881 LGE_INC(i, LGE_RX_LIST_CNT); 882 c--; 883 884 /* 885 * If an error occurs, update stats, clear the 886 * status word and leave the mbuf cluster in place: 887 * it should simply get re-used next time this descriptor 888 * comes up in the ring. 889 */ 890 if (rxctl & LGE_RXCTL_ERRMASK) { 891 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 892 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 893 continue; 894 } 895 896 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 897 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 898 ifp, NULL); 899 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 900 if (m0 == NULL) { 901 device_printf(sc->lge_dev, "no receive buffers " 902 "available -- packet dropped!\n"); 903 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 904 continue; 905 } 906 m = m0; 907 } else { 908 m->m_pkthdr.rcvif = ifp; 909 m->m_pkthdr.len = m->m_len = total_len; 910 } 911 912 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 913 914 /* Do IP checksum checking. */ 915 if (rxsts & LGE_RXSTS_ISIP) 916 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 917 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 918 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 919 if ((rxsts & LGE_RXSTS_ISTCP && 920 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 921 (rxsts & LGE_RXSTS_ISUDP && 922 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 923 m->m_pkthdr.csum_flags |= 924 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 925 m->m_pkthdr.csum_data = 0xffff; 926 } 927 928 LGE_UNLOCK(sc); 929 if_input(ifp, m); 930 LGE_LOCK(sc); 931 } 932 933 sc->lge_cdata.lge_rx_cons = i; 934 935 return; 936 } 937 938 static void 939 lge_rxeoc(struct lge_softc *sc) 940 { 941 if_t ifp; 942 943 ifp = sc->lge_ifp; 944 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 945 lge_init_locked(sc); 946 return; 947 } 948 949 /* 950 * A frame was downloaded to the chip. It's safe for us to clean up 951 * the list buffers. 952 */ 953 954 static void 955 lge_txeof(struct lge_softc *sc) 956 { 957 struct lge_tx_desc *cur_tx = NULL; 958 if_t ifp; 959 u_int32_t idx, txdone; 960 961 ifp = sc->lge_ifp; 962 963 /* Clear the timeout timer. */ 964 sc->lge_timer = 0; 965 966 /* 967 * Go through our tx list and free mbufs for those 968 * frames that have been transmitted. 969 */ 970 idx = sc->lge_cdata.lge_tx_cons; 971 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 972 973 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 974 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 975 976 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 977 if (cur_tx->lge_mbuf != NULL) { 978 m_freem(cur_tx->lge_mbuf); 979 cur_tx->lge_mbuf = NULL; 980 } 981 cur_tx->lge_ctl = 0; 982 983 txdone--; 984 LGE_INC(idx, LGE_TX_LIST_CNT); 985 sc->lge_timer = 0; 986 } 987 988 sc->lge_cdata.lge_tx_cons = idx; 989 990 if (cur_tx != NULL) 991 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 992 993 return; 994 } 995 996 static void 997 lge_tick(void *xsc) 998 { 999 struct lge_softc *sc; 1000 struct mii_data *mii; 1001 if_t ifp; 1002 1003 sc = xsc; 1004 ifp = sc->lge_ifp; 1005 LGE_LOCK_ASSERT(sc); 1006 1007 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1008 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1009 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1010 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1011 1012 if (!sc->lge_link) { 1013 mii = device_get_softc(sc->lge_miibus); 1014 mii_tick(mii); 1015 if (mii->mii_media_status & IFM_ACTIVE && 1016 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1017 sc->lge_link++; 1018 if (bootverbose && 1019 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1020 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1021 device_printf(sc->lge_dev, "gigabit link up\n"); 1022 if (!if_sendq_empty(ifp)) 1023 lge_start_locked(ifp); 1024 } 1025 } 1026 1027 if (sc->lge_timer != 0 && --sc->lge_timer == 0) 1028 lge_watchdog(sc); 1029 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1030 1031 return; 1032 } 1033 1034 static void 1035 lge_intr(void *arg) 1036 { 1037 struct lge_softc *sc; 1038 if_t ifp; 1039 u_int32_t status; 1040 1041 sc = arg; 1042 ifp = sc->lge_ifp; 1043 LGE_LOCK(sc); 1044 1045 /* Suppress unwanted interrupts */ 1046 if (!(if_getflags(ifp) & IFF_UP)) { 1047 lge_stop(sc); 1048 LGE_UNLOCK(sc); 1049 return; 1050 } 1051 1052 for (;;) { 1053 /* 1054 * Reading the ISR register clears all interrupts, and 1055 * clears the 'interrupts enabled' bit in the IMR 1056 * register. 1057 */ 1058 status = CSR_READ_4(sc, LGE_ISR); 1059 1060 if ((status & LGE_INTRS) == 0) 1061 break; 1062 1063 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1064 lge_txeof(sc); 1065 1066 if (status & LGE_ISR_RXDMA_DONE) 1067 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1068 1069 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1070 lge_rxeoc(sc); 1071 1072 if (status & LGE_ISR_PHY_INTR) { 1073 sc->lge_link = 0; 1074 callout_stop(&sc->lge_stat_callout); 1075 lge_tick(sc); 1076 } 1077 } 1078 1079 /* Re-enable interrupts. */ 1080 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1081 1082 if (!if_sendq_empty(ifp)) 1083 lge_start_locked(ifp); 1084 1085 LGE_UNLOCK(sc); 1086 return; 1087 } 1088 1089 /* 1090 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1091 * pointers to the fragment pointers. 1092 */ 1093 static int 1094 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1095 { 1096 struct lge_frag *f = NULL; 1097 struct lge_tx_desc *cur_tx; 1098 struct mbuf *m; 1099 int frag = 0, tot_len = 0; 1100 1101 /* 1102 * Start packing the mbufs in this chain into 1103 * the fragment pointers. Stop when we run out 1104 * of fragments or hit the end of the mbuf chain. 1105 */ 1106 m = m_head; 1107 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1108 frag = 0; 1109 1110 for (m = m_head; m != NULL; m = m->m_next) { 1111 if (m->m_len != 0) { 1112 tot_len += m->m_len; 1113 f = &cur_tx->lge_frags[frag]; 1114 f->lge_fraglen = m->m_len; 1115 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1116 f->lge_fragptr_hi = 0; 1117 frag++; 1118 } 1119 } 1120 1121 if (m != NULL) 1122 return(ENOBUFS); 1123 1124 cur_tx->lge_mbuf = m_head; 1125 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1126 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1127 1128 /* Queue for transmit */ 1129 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1130 1131 return(0); 1132 } 1133 1134 /* 1135 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1136 * to the mbuf data regions directly in the transmit lists. We also save a 1137 * copy of the pointers since the transmit list fragment pointers are 1138 * physical addresses. 1139 */ 1140 1141 static void 1142 lge_start(if_t ifp) 1143 { 1144 struct lge_softc *sc; 1145 1146 sc = if_getsoftc(ifp); 1147 LGE_LOCK(sc); 1148 lge_start_locked(ifp); 1149 LGE_UNLOCK(sc); 1150 } 1151 1152 static void 1153 lge_start_locked(if_t ifp) 1154 { 1155 struct lge_softc *sc; 1156 struct mbuf *m_head = NULL; 1157 u_int32_t idx; 1158 1159 sc = if_getsoftc(ifp); 1160 1161 if (!sc->lge_link) 1162 return; 1163 1164 idx = sc->lge_cdata.lge_tx_prod; 1165 1166 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 1167 return; 1168 1169 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1170 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1171 break; 1172 1173 m_head = if_dequeue(ifp); 1174 if (m_head == NULL) 1175 break; 1176 1177 if (lge_encap(sc, m_head, &idx)) { 1178 if_sendq_prepend(ifp, m_head); 1179 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1180 break; 1181 } 1182 1183 /* 1184 * If there's a BPF listener, bounce a copy of this frame 1185 * to him. 1186 */ 1187 BPF_MTAP(ifp, m_head); 1188 } 1189 1190 sc->lge_cdata.lge_tx_prod = idx; 1191 1192 /* 1193 * Set a timeout in case the chip goes out to lunch. 1194 */ 1195 sc->lge_timer = 5; 1196 1197 return; 1198 } 1199 1200 static void 1201 lge_init(void *xsc) 1202 { 1203 struct lge_softc *sc = xsc; 1204 1205 LGE_LOCK(sc); 1206 lge_init_locked(sc); 1207 LGE_UNLOCK(sc); 1208 } 1209 1210 static void 1211 lge_init_locked(struct lge_softc *sc) 1212 { 1213 if_t ifp = sc->lge_ifp; 1214 1215 LGE_LOCK_ASSERT(sc); 1216 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1217 return; 1218 1219 /* 1220 * Cancel pending I/O and free all RX/TX buffers. 1221 */ 1222 lge_stop(sc); 1223 lge_reset(sc); 1224 1225 /* Set MAC address */ 1226 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[0])); 1227 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[4])); 1228 1229 /* Init circular RX list. */ 1230 if (lge_list_rx_init(sc) == ENOBUFS) { 1231 device_printf(sc->lge_dev, "initialization failed: no " 1232 "memory for rx buffers\n"); 1233 lge_stop(sc); 1234 return; 1235 } 1236 1237 /* 1238 * Init tx descriptors. 1239 */ 1240 lge_list_tx_init(sc); 1241 1242 /* Set initial value for MODE1 register. */ 1243 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1244 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1245 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1246 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1247 1248 /* If we want promiscuous mode, set the allframes bit. */ 1249 if (if_getflags(ifp) & IFF_PROMISC) { 1250 CSR_WRITE_4(sc, LGE_MODE1, 1251 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1252 } else { 1253 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1254 } 1255 1256 /* 1257 * Set the capture broadcast bit to capture broadcast frames. 1258 */ 1259 if (if_getflags(ifp) & IFF_BROADCAST) { 1260 CSR_WRITE_4(sc, LGE_MODE1, 1261 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1262 } else { 1263 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1264 } 1265 1266 /* Packet padding workaround? */ 1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1268 1269 /* No error frames */ 1270 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1271 1272 /* Receive large frames */ 1273 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1274 1275 /* Workaround: disable RX/TX flow control */ 1276 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1278 1279 /* Make sure to strip CRC from received frames */ 1280 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1281 1282 /* Turn off magic packet mode */ 1283 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1284 1285 /* Turn off all VLAN stuff */ 1286 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1287 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1288 1289 /* Workarond: FIFO overflow */ 1290 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1291 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1292 1293 /* 1294 * Load the multicast filter. 1295 */ 1296 lge_setmulti(sc); 1297 1298 /* 1299 * Enable hardware checksum validation for all received IPv4 1300 * packets, do not reject packets with bad checksums. 1301 */ 1302 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1303 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1304 LGE_MODE2_RX_ERRCSUM); 1305 1306 /* 1307 * Enable the delivery of PHY interrupts based on 1308 * link/speed/duplex status chalges. 1309 */ 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1311 1312 /* Enable receiver and transmitter. */ 1313 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1314 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1315 1316 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1318 1319 /* 1320 * Enable interrupts. 1321 */ 1322 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1323 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1324 1325 lge_ifmedia_upd_locked(ifp); 1326 1327 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1328 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1329 1330 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1331 1332 return; 1333 } 1334 1335 /* 1336 * Set media options. 1337 */ 1338 static int 1339 lge_ifmedia_upd(if_t ifp) 1340 { 1341 struct lge_softc *sc; 1342 1343 sc = if_getsoftc(ifp); 1344 LGE_LOCK(sc); 1345 lge_ifmedia_upd_locked(ifp); 1346 LGE_UNLOCK(sc); 1347 1348 return(0); 1349 } 1350 1351 static void 1352 lge_ifmedia_upd_locked(if_t ifp) 1353 { 1354 struct lge_softc *sc; 1355 struct mii_data *mii; 1356 struct mii_softc *miisc; 1357 1358 sc = if_getsoftc(ifp); 1359 1360 LGE_LOCK_ASSERT(sc); 1361 mii = device_get_softc(sc->lge_miibus); 1362 sc->lge_link = 0; 1363 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1364 PHY_RESET(miisc); 1365 mii_mediachg(mii); 1366 } 1367 1368 /* 1369 * Report current media status. 1370 */ 1371 static void 1372 lge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1373 { 1374 struct lge_softc *sc; 1375 struct mii_data *mii; 1376 1377 sc = if_getsoftc(ifp); 1378 1379 LGE_LOCK(sc); 1380 mii = device_get_softc(sc->lge_miibus); 1381 mii_pollstat(mii); 1382 ifmr->ifm_active = mii->mii_media_active; 1383 ifmr->ifm_status = mii->mii_media_status; 1384 LGE_UNLOCK(sc); 1385 1386 return; 1387 } 1388 1389 static int 1390 lge_ioctl(if_t ifp, u_long command, caddr_t data) 1391 { 1392 struct lge_softc *sc = if_getsoftc(ifp); 1393 struct ifreq *ifr = (struct ifreq *) data; 1394 struct mii_data *mii; 1395 int error = 0; 1396 1397 switch(command) { 1398 case SIOCSIFMTU: 1399 LGE_LOCK(sc); 1400 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1401 error = EINVAL; 1402 else 1403 if_setmtu(ifp, ifr->ifr_mtu); 1404 LGE_UNLOCK(sc); 1405 break; 1406 case SIOCSIFFLAGS: 1407 LGE_LOCK(sc); 1408 if (if_getflags(ifp) & IFF_UP) { 1409 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 1410 if_getflags(ifp) & IFF_PROMISC && 1411 !(sc->lge_if_flags & IFF_PROMISC)) { 1412 CSR_WRITE_4(sc, LGE_MODE1, 1413 LGE_MODE1_SETRST_CTL1| 1414 LGE_MODE1_RX_PROMISC); 1415 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 1416 !(if_getflags(ifp) & IFF_PROMISC) && 1417 sc->lge_if_flags & IFF_PROMISC) { 1418 CSR_WRITE_4(sc, LGE_MODE1, 1419 LGE_MODE1_RX_PROMISC); 1420 } else { 1421 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1422 lge_init_locked(sc); 1423 } 1424 } else { 1425 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1426 lge_stop(sc); 1427 } 1428 sc->lge_if_flags = if_getflags(ifp); 1429 LGE_UNLOCK(sc); 1430 error = 0; 1431 break; 1432 case SIOCADDMULTI: 1433 case SIOCDELMULTI: 1434 LGE_LOCK(sc); 1435 lge_setmulti(sc); 1436 LGE_UNLOCK(sc); 1437 error = 0; 1438 break; 1439 case SIOCGIFMEDIA: 1440 case SIOCSIFMEDIA: 1441 mii = device_get_softc(sc->lge_miibus); 1442 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1443 break; 1444 default: 1445 error = ether_ioctl(ifp, command, data); 1446 break; 1447 } 1448 1449 return(error); 1450 } 1451 1452 static void 1453 lge_watchdog(struct lge_softc *sc) 1454 { 1455 if_t ifp; 1456 1457 LGE_LOCK_ASSERT(sc); 1458 ifp = sc->lge_ifp; 1459 1460 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1461 if_printf(ifp, "watchdog timeout\n"); 1462 1463 lge_stop(sc); 1464 lge_reset(sc); 1465 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1466 lge_init_locked(sc); 1467 1468 if (!if_sendq_empty(ifp)) 1469 lge_start_locked(ifp); 1470 } 1471 1472 /* 1473 * Stop the adapter and free any mbufs allocated to the 1474 * RX and TX lists. 1475 */ 1476 static void 1477 lge_stop(struct lge_softc *sc) 1478 { 1479 int i; 1480 if_t ifp; 1481 1482 LGE_LOCK_ASSERT(sc); 1483 ifp = sc->lge_ifp; 1484 sc->lge_timer = 0; 1485 callout_stop(&sc->lge_stat_callout); 1486 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1487 1488 /* Disable receiver and transmitter. */ 1489 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1490 sc->lge_link = 0; 1491 1492 /* 1493 * Free data in the RX lists. 1494 */ 1495 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1496 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1497 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1498 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1499 } 1500 } 1501 bzero((char *)&sc->lge_ldata->lge_rx_list, 1502 sizeof(sc->lge_ldata->lge_rx_list)); 1503 1504 /* 1505 * Free the TX list buffers. 1506 */ 1507 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1508 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1509 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1510 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1511 } 1512 } 1513 1514 bzero((char *)&sc->lge_ldata->lge_tx_list, 1515 sizeof(sc->lge_ldata->lge_tx_list)); 1516 1517 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1518 1519 return; 1520 } 1521 1522 /* 1523 * Stop all chip I/O so that the kernel's probe routines don't 1524 * get confused by errant DMAs when rebooting. 1525 */ 1526 static int 1527 lge_shutdown(device_t dev) 1528 { 1529 struct lge_softc *sc; 1530 1531 sc = device_get_softc(dev); 1532 1533 LGE_LOCK(sc); 1534 lge_reset(sc); 1535 lge_stop(sc); 1536 LGE_UNLOCK(sc); 1537 1538 return (0); 1539 } 1540