1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 #include <sys/socket.h> 80 81 #include <net/if.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_types.h> 87 88 #include <net/bpf.h> 89 90 #include <vm/vm.h> /* for vtophys */ 91 #include <vm/pmap.h> /* for vtophys */ 92 #include <machine/clock.h> /* for DELAY */ 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 104 #define LGE_USEIOSPACE 105 106 #include <dev/lge/if_lgereg.h> 107 108 /* "controller miibus0" required. See GENERIC if you get errors here. */ 109 #include "miibus_if.h" 110 111 /* 112 * Various supported device vendors/types and their names. 113 */ 114 static struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117 }; 118 119 static int lge_probe(device_t); 120 static int lge_attach(device_t); 121 static int lge_detach(device_t); 122 123 static int lge_alloc_jumbo_mem(struct lge_softc *); 124 static void lge_free_jumbo_mem(struct lge_softc *); 125 static void *lge_jalloc(struct lge_softc *); 126 static void lge_jfree(void *, void *); 127 128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130 static void lge_rxeof(struct lge_softc *, int); 131 static void lge_rxeoc(struct lge_softc *); 132 static void lge_txeof(struct lge_softc *); 133 static void lge_intr(void *); 134 static void lge_tick(void *); 135 static void lge_start(struct ifnet *); 136 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137 static void lge_init(void *); 138 static void lge_stop(struct lge_softc *); 139 static void lge_watchdog(struct ifnet *); 140 static void lge_shutdown(device_t); 141 static int lge_ifmedia_upd(struct ifnet *); 142 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 145 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 146 147 static int lge_miibus_readreg(device_t, int, int); 148 static int lge_miibus_writereg(device_t, int, int, int); 149 static void lge_miibus_statchg(device_t); 150 151 static void lge_setmulti(struct lge_softc *); 152 static void lge_reset(struct lge_softc *); 153 static int lge_list_rx_init(struct lge_softc *); 154 static int lge_list_tx_init(struct lge_softc *); 155 156 #ifdef LGE_USEIOSPACE 157 #define LGE_RES SYS_RES_IOPORT 158 #define LGE_RID LGE_PCI_LOIO 159 #else 160 #define LGE_RES SYS_RES_MEMORY 161 #define LGE_RID LGE_PCI_LOMEM 162 #endif 163 164 static device_method_t lge_methods[] = { 165 /* Device interface */ 166 DEVMETHOD(device_probe, lge_probe), 167 DEVMETHOD(device_attach, lge_attach), 168 DEVMETHOD(device_detach, lge_detach), 169 DEVMETHOD(device_shutdown, lge_shutdown), 170 171 /* bus interface */ 172 DEVMETHOD(bus_print_child, bus_generic_print_child), 173 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 174 175 /* MII interface */ 176 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 177 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 178 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 179 180 { 0, 0 } 181 }; 182 183 static driver_t lge_driver = { 184 "lge", 185 lge_methods, 186 sizeof(struct lge_softc) 187 }; 188 189 static devclass_t lge_devclass; 190 191 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 192 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 193 MODULE_DEPEND(lge, pci, 1, 1, 1); 194 MODULE_DEPEND(lge, ether, 1, 1, 1); 195 MODULE_DEPEND(lge, miibus, 1, 1, 1); 196 197 #define LGE_SETBIT(sc, reg, x) \ 198 CSR_WRITE_4(sc, reg, \ 199 CSR_READ_4(sc, reg) | (x)) 200 201 #define LGE_CLRBIT(sc, reg, x) \ 202 CSR_WRITE_4(sc, reg, \ 203 CSR_READ_4(sc, reg) & ~(x)) 204 205 #define SIO_SET(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 207 208 #define SIO_CLR(x) \ 209 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 210 211 /* 212 * Read a word of data stored in the EEPROM at address 'addr.' 213 */ 214 static void 215 lge_eeprom_getword(sc, addr, dest) 216 struct lge_softc *sc; 217 int addr; 218 u_int16_t *dest; 219 { 220 register int i; 221 u_int32_t val; 222 223 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 224 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 225 226 for (i = 0; i < LGE_TIMEOUT; i++) 227 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 228 break; 229 230 if (i == LGE_TIMEOUT) { 231 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 232 return; 233 } 234 235 val = CSR_READ_4(sc, LGE_EEDATA); 236 237 if (addr & 1) 238 *dest = (val >> 16) & 0xFFFF; 239 else 240 *dest = val & 0xFFFF; 241 242 return; 243 } 244 245 /* 246 * Read a sequence of words from the EEPROM. 247 */ 248 static void 249 lge_read_eeprom(sc, dest, off, cnt, swap) 250 struct lge_softc *sc; 251 caddr_t dest; 252 int off; 253 int cnt; 254 int swap; 255 { 256 int i; 257 u_int16_t word = 0, *ptr; 258 259 for (i = 0; i < cnt; i++) { 260 lge_eeprom_getword(sc, off + i, &word); 261 ptr = (u_int16_t *)(dest + (i * 2)); 262 if (swap) 263 *ptr = ntohs(word); 264 else 265 *ptr = word; 266 } 267 268 return; 269 } 270 271 static int 272 lge_miibus_readreg(dev, phy, reg) 273 device_t dev; 274 int phy, reg; 275 { 276 struct lge_softc *sc; 277 int i; 278 279 sc = device_get_softc(dev); 280 281 /* 282 * If we have a non-PCS PHY, pretend that the internal 283 * autoneg stuff at PHY address 0 isn't there so that 284 * the miibus code will find only the GMII PHY. 285 */ 286 if (sc->lge_pcs == 0 && phy == 0) 287 return(0); 288 289 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 290 291 for (i = 0; i < LGE_TIMEOUT; i++) 292 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 293 break; 294 295 if (i == LGE_TIMEOUT) { 296 printf("lge%d: PHY read timed out\n", sc->lge_unit); 297 return(0); 298 } 299 300 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 301 } 302 303 static int 304 lge_miibus_writereg(dev, phy, reg, data) 305 device_t dev; 306 int phy, reg, data; 307 { 308 struct lge_softc *sc; 309 int i; 310 311 sc = device_get_softc(dev); 312 313 CSR_WRITE_4(sc, LGE_GMIICTL, 314 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 315 316 for (i = 0; i < LGE_TIMEOUT; i++) 317 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 318 break; 319 320 if (i == LGE_TIMEOUT) { 321 printf("lge%d: PHY write timed out\n", sc->lge_unit); 322 return(0); 323 } 324 325 return(0); 326 } 327 328 static void 329 lge_miibus_statchg(dev) 330 device_t dev; 331 { 332 struct lge_softc *sc; 333 struct mii_data *mii; 334 335 sc = device_get_softc(dev); 336 mii = device_get_softc(sc->lge_miibus); 337 338 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 339 switch (IFM_SUBTYPE(mii->mii_media_active)) { 340 case IFM_1000_T: 341 case IFM_1000_SX: 342 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 343 break; 344 case IFM_100_TX: 345 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 346 break; 347 case IFM_10_T: 348 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 349 break; 350 default: 351 /* 352 * Choose something, even if it's wrong. Clearing 353 * all the bits will hose autoneg on the internal 354 * PHY. 355 */ 356 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 357 break; 358 } 359 360 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 361 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 362 } else { 363 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 364 } 365 366 return; 367 } 368 369 static void 370 lge_setmulti(sc) 371 struct lge_softc *sc; 372 { 373 struct ifnet *ifp; 374 struct ifmultiaddr *ifma; 375 u_int32_t h = 0, hashes[2] = { 0, 0 }; 376 377 ifp = sc->lge_ifp; 378 379 /* Make sure multicast hash table is enabled. */ 380 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 381 382 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 383 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 384 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 385 return; 386 } 387 388 /* first, zot all the existing hash bits */ 389 CSR_WRITE_4(sc, LGE_MAR0, 0); 390 CSR_WRITE_4(sc, LGE_MAR1, 0); 391 392 /* now program new ones */ 393 IF_ADDR_LOCK(ifp); 394 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 395 if (ifma->ifma_addr->sa_family != AF_LINK) 396 continue; 397 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 398 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 399 if (h < 32) 400 hashes[0] |= (1 << h); 401 else 402 hashes[1] |= (1 << (h - 32)); 403 } 404 IF_ADDR_UNLOCK(ifp); 405 406 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 407 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 408 409 return; 410 } 411 412 static void 413 lge_reset(sc) 414 struct lge_softc *sc; 415 { 416 register int i; 417 418 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 419 420 for (i = 0; i < LGE_TIMEOUT; i++) { 421 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 422 break; 423 } 424 425 if (i == LGE_TIMEOUT) 426 printf("lge%d: reset never completed\n", sc->lge_unit); 427 428 /* Wait a little while for the chip to get its brains in order. */ 429 DELAY(1000); 430 431 return; 432 } 433 434 /* 435 * Probe for a Level 1 chip. Check the PCI vendor and device 436 * IDs against our list and return a device name if we find a match. 437 */ 438 static int 439 lge_probe(dev) 440 device_t dev; 441 { 442 struct lge_type *t; 443 444 t = lge_devs; 445 446 while(t->lge_name != NULL) { 447 if ((pci_get_vendor(dev) == t->lge_vid) && 448 (pci_get_device(dev) == t->lge_did)) { 449 device_set_desc(dev, t->lge_name); 450 return(BUS_PROBE_DEFAULT); 451 } 452 t++; 453 } 454 455 return(ENXIO); 456 } 457 458 /* 459 * Attach the interface. Allocate softc structures, do ifmedia 460 * setup and ethernet/BPF attach. 461 */ 462 static int 463 lge_attach(dev) 464 device_t dev; 465 { 466 int s; 467 u_char eaddr[ETHER_ADDR_LEN]; 468 struct lge_softc *sc; 469 struct ifnet *ifp; 470 int unit, error = 0, rid; 471 472 s = splimp(); 473 474 sc = device_get_softc(dev); 475 unit = device_get_unit(dev); 476 bzero(sc, sizeof(struct lge_softc)); 477 /* 478 * Map control/status registers. 479 */ 480 pci_enable_busmaster(dev); 481 482 rid = LGE_RID; 483 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 484 485 if (sc->lge_res == NULL) { 486 printf("lge%d: couldn't map ports/memory\n", unit); 487 error = ENXIO; 488 goto fail; 489 } 490 491 sc->lge_btag = rman_get_bustag(sc->lge_res); 492 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 493 494 /* Allocate interrupt */ 495 rid = 0; 496 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 497 RF_SHAREABLE | RF_ACTIVE); 498 499 if (sc->lge_irq == NULL) { 500 printf("lge%d: couldn't map interrupt\n", unit); 501 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 502 error = ENXIO; 503 goto fail; 504 } 505 506 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 507 lge_intr, sc, &sc->lge_intrhand); 508 509 if (error) { 510 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 511 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 512 printf("lge%d: couldn't set up irq\n", unit); 513 goto fail; 514 } 515 516 /* Reset the adapter. */ 517 lge_reset(sc); 518 519 /* 520 * Get station address from the EEPROM. 521 */ 522 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 523 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 524 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 525 526 sc->lge_unit = unit; 527 callout_handle_init(&sc->lge_stat_ch); 528 529 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 530 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 531 532 if (sc->lge_ldata == NULL) { 533 printf("lge%d: no memory for list buffers!\n", unit); 534 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 535 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 536 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 537 error = ENXIO; 538 goto fail; 539 } 540 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 541 542 /* Try to allocate memory for jumbo buffers. */ 543 if (lge_alloc_jumbo_mem(sc)) { 544 printf("lge%d: jumbo buffer allocation failed\n", 545 sc->lge_unit); 546 contigfree(sc->lge_ldata, 547 sizeof(struct lge_list_data), M_DEVBUF); 548 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 550 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 551 error = ENXIO; 552 goto fail; 553 } 554 555 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 556 if (ifp == NULL) { 557 printf("lge%d: can not if_alloc()\n", sc->lge_unit); 558 contigfree(sc->lge_ldata, 559 sizeof(struct lge_list_data), M_DEVBUF); 560 lge_free_jumbo_mem(sc); 561 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 562 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 563 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 564 error = ENOSPC; 565 goto fail; 566 } 567 ifp->if_softc = sc; 568 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 569 ifp->if_mtu = ETHERMTU; 570 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 571 IFF_NEEDSGIANT; 572 ifp->if_ioctl = lge_ioctl; 573 ifp->if_start = lge_start; 574 ifp->if_watchdog = lge_watchdog; 575 ifp->if_init = lge_init; 576 ifp->if_baudrate = 1000000000; 577 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 578 ifp->if_capabilities = IFCAP_RXCSUM; 579 ifp->if_capenable = ifp->if_capabilities; 580 581 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 582 sc->lge_pcs = 1; 583 else 584 sc->lge_pcs = 0; 585 586 /* 587 * Do MII setup. 588 */ 589 if (mii_phy_probe(dev, &sc->lge_miibus, 590 lge_ifmedia_upd, lge_ifmedia_sts)) { 591 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 592 contigfree(sc->lge_ldata, 593 sizeof(struct lge_list_data), M_DEVBUF); 594 lge_free_jumbo_mem(sc); 595 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 596 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 597 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 598 if_free(ifp); 599 error = ENXIO; 600 goto fail; 601 } 602 603 /* 604 * Call MI attach routine. 605 */ 606 ether_ifattach(ifp, eaddr); 607 callout_handle_init(&sc->lge_stat_ch); 608 609 fail: 610 splx(s); 611 return(error); 612 } 613 614 static int 615 lge_detach(dev) 616 device_t dev; 617 { 618 struct lge_softc *sc; 619 struct ifnet *ifp; 620 int s; 621 622 s = splimp(); 623 624 sc = device_get_softc(dev); 625 ifp = sc->lge_ifp; 626 627 lge_reset(sc); 628 lge_stop(sc); 629 ether_ifdetach(ifp); 630 631 bus_generic_detach(dev); 632 device_delete_child(dev, sc->lge_miibus); 633 634 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 635 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 636 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 637 638 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 639 if_free(ifp); 640 lge_free_jumbo_mem(sc); 641 642 splx(s); 643 644 return(0); 645 } 646 647 /* 648 * Initialize the transmit descriptors. 649 */ 650 static int 651 lge_list_tx_init(sc) 652 struct lge_softc *sc; 653 { 654 struct lge_list_data *ld; 655 struct lge_ring_data *cd; 656 int i; 657 658 cd = &sc->lge_cdata; 659 ld = sc->lge_ldata; 660 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 661 ld->lge_tx_list[i].lge_mbuf = NULL; 662 ld->lge_tx_list[i].lge_ctl = 0; 663 } 664 665 cd->lge_tx_prod = cd->lge_tx_cons = 0; 666 667 return(0); 668 } 669 670 671 /* 672 * Initialize the RX descriptors and allocate mbufs for them. Note that 673 * we arralge the descriptors in a closed ring, so that the last descriptor 674 * points back to the first. 675 */ 676 static int 677 lge_list_rx_init(sc) 678 struct lge_softc *sc; 679 { 680 struct lge_list_data *ld; 681 struct lge_ring_data *cd; 682 int i; 683 684 ld = sc->lge_ldata; 685 cd = &sc->lge_cdata; 686 687 cd->lge_rx_prod = cd->lge_rx_cons = 0; 688 689 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 690 691 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 692 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 693 break; 694 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 695 return(ENOBUFS); 696 } 697 698 /* Clear possible 'rx command queue empty' interrupt. */ 699 CSR_READ_4(sc, LGE_ISR); 700 701 return(0); 702 } 703 704 /* 705 * Initialize an RX descriptor and attach an MBUF cluster. 706 */ 707 static int 708 lge_newbuf(sc, c, m) 709 struct lge_softc *sc; 710 struct lge_rx_desc *c; 711 struct mbuf *m; 712 { 713 struct mbuf *m_new = NULL; 714 caddr_t *buf = NULL; 715 716 if (m == NULL) { 717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 718 if (m_new == NULL) { 719 printf("lge%d: no memory for rx list " 720 "-- packet dropped!\n", sc->lge_unit); 721 return(ENOBUFS); 722 } 723 724 /* Allocate the jumbo buffer */ 725 buf = lge_jalloc(sc); 726 if (buf == NULL) { 727 #ifdef LGE_VERBOSE 728 printf("lge%d: jumbo allocation failed " 729 "-- packet dropped!\n", sc->lge_unit); 730 #endif 731 m_freem(m_new); 732 return(ENOBUFS); 733 } 734 /* Attach the buffer to the mbuf */ 735 m_new->m_data = (void *)buf; 736 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 737 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 738 (struct lge_softc *)sc, 0, EXT_NET_DRV); 739 } else { 740 m_new = m; 741 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 742 m_new->m_data = m_new->m_ext.ext_buf; 743 } 744 745 /* 746 * Adjust alignment so packet payload begins on a 747 * longword boundary. Mandatory for Alpha, useful on 748 * x86 too. 749 */ 750 m_adj(m_new, ETHER_ALIGN); 751 752 c->lge_mbuf = m_new; 753 c->lge_fragptr_hi = 0; 754 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 755 c->lge_fraglen = m_new->m_len; 756 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 757 c->lge_sts = 0; 758 759 /* 760 * Put this buffer in the RX command FIFO. To do this, 761 * we just write the physical address of the descriptor 762 * into the RX descriptor address registers. Note that 763 * there are two registers, one high DWORD and one low 764 * DWORD, which lets us specify a 64-bit address if 765 * desired. We only use a 32-bit address for now. 766 * Writing to the low DWORD register is what actually 767 * causes the command to be issued, so we do that 768 * last. 769 */ 770 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 771 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 772 773 return(0); 774 } 775 776 static int 777 lge_alloc_jumbo_mem(sc) 778 struct lge_softc *sc; 779 { 780 caddr_t ptr; 781 register int i; 782 struct lge_jpool_entry *entry; 783 784 /* Grab a big chunk o' storage. */ 785 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 786 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 787 788 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 789 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 790 return(ENOBUFS); 791 } 792 793 SLIST_INIT(&sc->lge_jfree_listhead); 794 SLIST_INIT(&sc->lge_jinuse_listhead); 795 796 /* 797 * Now divide it up into 9K pieces and save the addresses 798 * in an array. 799 */ 800 ptr = sc->lge_cdata.lge_jumbo_buf; 801 for (i = 0; i < LGE_JSLOTS; i++) { 802 sc->lge_cdata.lge_jslots[i] = ptr; 803 ptr += LGE_JLEN; 804 entry = malloc(sizeof(struct lge_jpool_entry), 805 M_DEVBUF, M_NOWAIT); 806 if (entry == NULL) { 807 printf("lge%d: no memory for jumbo " 808 "buffer queue!\n", sc->lge_unit); 809 return(ENOBUFS); 810 } 811 entry->slot = i; 812 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 813 entry, jpool_entries); 814 } 815 816 return(0); 817 } 818 819 static void 820 lge_free_jumbo_mem(sc) 821 struct lge_softc *sc; 822 { 823 int i; 824 struct lge_jpool_entry *entry; 825 826 for (i = 0; i < LGE_JSLOTS; i++) { 827 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 828 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 829 free(entry, M_DEVBUF); 830 } 831 832 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 833 834 return; 835 } 836 837 /* 838 * Allocate a jumbo buffer. 839 */ 840 static void * 841 lge_jalloc(sc) 842 struct lge_softc *sc; 843 { 844 struct lge_jpool_entry *entry; 845 846 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 847 848 if (entry == NULL) { 849 #ifdef LGE_VERBOSE 850 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 851 #endif 852 return(NULL); 853 } 854 855 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 856 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 857 return(sc->lge_cdata.lge_jslots[entry->slot]); 858 } 859 860 /* 861 * Release a jumbo buffer. 862 */ 863 static void 864 lge_jfree(buf, args) 865 void *buf; 866 void *args; 867 { 868 struct lge_softc *sc; 869 int i; 870 struct lge_jpool_entry *entry; 871 872 /* Extract the softc struct pointer. */ 873 sc = args; 874 875 if (sc == NULL) 876 panic("lge_jfree: can't find softc pointer!"); 877 878 /* calculate the slot this buffer belongs to */ 879 i = ((vm_offset_t)buf 880 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 881 882 if ((i < 0) || (i >= LGE_JSLOTS)) 883 panic("lge_jfree: asked to free buffer that we don't manage!"); 884 885 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 886 if (entry == NULL) 887 panic("lge_jfree: buffer not in use!"); 888 entry->slot = i; 889 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 890 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 891 892 return; 893 } 894 895 /* 896 * A frame has been uploaded: pass the resulting mbuf chain up to 897 * the higher level protocols. 898 */ 899 static void 900 lge_rxeof(sc, cnt) 901 struct lge_softc *sc; 902 int cnt; 903 { 904 struct mbuf *m; 905 struct ifnet *ifp; 906 struct lge_rx_desc *cur_rx; 907 int c, i, total_len = 0; 908 u_int32_t rxsts, rxctl; 909 910 ifp = sc->lge_ifp; 911 912 /* Find out how many frames were processed. */ 913 c = cnt; 914 i = sc->lge_cdata.lge_rx_cons; 915 916 /* Suck them in. */ 917 while(c) { 918 struct mbuf *m0 = NULL; 919 920 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 921 rxctl = cur_rx->lge_ctl; 922 rxsts = cur_rx->lge_sts; 923 m = cur_rx->lge_mbuf; 924 cur_rx->lge_mbuf = NULL; 925 total_len = LGE_RXBYTES(cur_rx); 926 LGE_INC(i, LGE_RX_LIST_CNT); 927 c--; 928 929 /* 930 * If an error occurs, update stats, clear the 931 * status word and leave the mbuf cluster in place: 932 * it should simply get re-used next time this descriptor 933 * comes up in the ring. 934 */ 935 if (rxctl & LGE_RXCTL_ERRMASK) { 936 ifp->if_ierrors++; 937 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 938 continue; 939 } 940 941 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 942 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 943 ifp, NULL); 944 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 945 if (m0 == NULL) { 946 printf("lge%d: no receive buffers " 947 "available -- packet dropped!\n", 948 sc->lge_unit); 949 ifp->if_ierrors++; 950 continue; 951 } 952 m = m0; 953 } else { 954 m->m_pkthdr.rcvif = ifp; 955 m->m_pkthdr.len = m->m_len = total_len; 956 } 957 958 ifp->if_ipackets++; 959 960 /* Do IP checksum checking. */ 961 if (rxsts & LGE_RXSTS_ISIP) 962 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 963 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 964 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 965 if ((rxsts & LGE_RXSTS_ISTCP && 966 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 967 (rxsts & LGE_RXSTS_ISUDP && 968 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 969 m->m_pkthdr.csum_flags |= 970 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 971 m->m_pkthdr.csum_data = 0xffff; 972 } 973 974 (*ifp->if_input)(ifp, m); 975 } 976 977 sc->lge_cdata.lge_rx_cons = i; 978 979 return; 980 } 981 982 static void 983 lge_rxeoc(sc) 984 struct lge_softc *sc; 985 { 986 struct ifnet *ifp; 987 988 ifp = sc->lge_ifp; 989 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 990 lge_init(sc); 991 return; 992 } 993 994 /* 995 * A frame was downloaded to the chip. It's safe for us to clean up 996 * the list buffers. 997 */ 998 999 static void 1000 lge_txeof(sc) 1001 struct lge_softc *sc; 1002 { 1003 struct lge_tx_desc *cur_tx = NULL; 1004 struct ifnet *ifp; 1005 u_int32_t idx, txdone; 1006 1007 ifp = sc->lge_ifp; 1008 1009 /* Clear the timeout timer. */ 1010 ifp->if_timer = 0; 1011 1012 /* 1013 * Go through our tx list and free mbufs for those 1014 * frames that have been transmitted. 1015 */ 1016 idx = sc->lge_cdata.lge_tx_cons; 1017 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1018 1019 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1020 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1021 1022 ifp->if_opackets++; 1023 if (cur_tx->lge_mbuf != NULL) { 1024 m_freem(cur_tx->lge_mbuf); 1025 cur_tx->lge_mbuf = NULL; 1026 } 1027 cur_tx->lge_ctl = 0; 1028 1029 txdone--; 1030 LGE_INC(idx, LGE_TX_LIST_CNT); 1031 ifp->if_timer = 0; 1032 } 1033 1034 sc->lge_cdata.lge_tx_cons = idx; 1035 1036 if (cur_tx != NULL) 1037 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1038 1039 return; 1040 } 1041 1042 static void 1043 lge_tick(xsc) 1044 void *xsc; 1045 { 1046 struct lge_softc *sc; 1047 struct mii_data *mii; 1048 struct ifnet *ifp; 1049 int s; 1050 1051 s = splimp(); 1052 1053 sc = xsc; 1054 ifp = sc->lge_ifp; 1055 1056 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1057 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1058 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1059 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1060 1061 if (!sc->lge_link) { 1062 mii = device_get_softc(sc->lge_miibus); 1063 mii_tick(mii); 1064 if (mii->mii_media_status & IFM_ACTIVE && 1065 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1066 sc->lge_link++; 1067 if (bootverbose && 1068 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1069 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1070 printf("lge%d: gigabit link up\n", 1071 sc->lge_unit); 1072 if (ifp->if_snd.ifq_head != NULL) 1073 lge_start(ifp); 1074 } 1075 } 1076 1077 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1078 1079 splx(s); 1080 1081 return; 1082 } 1083 1084 static void 1085 lge_intr(arg) 1086 void *arg; 1087 { 1088 struct lge_softc *sc; 1089 struct ifnet *ifp; 1090 u_int32_t status; 1091 1092 sc = arg; 1093 ifp = sc->lge_ifp; 1094 1095 /* Supress unwanted interrupts */ 1096 if (!(ifp->if_flags & IFF_UP)) { 1097 lge_stop(sc); 1098 return; 1099 } 1100 1101 for (;;) { 1102 /* 1103 * Reading the ISR register clears all interrupts, and 1104 * clears the 'interrupts enabled' bit in the IMR 1105 * register. 1106 */ 1107 status = CSR_READ_4(sc, LGE_ISR); 1108 1109 if ((status & LGE_INTRS) == 0) 1110 break; 1111 1112 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1113 lge_txeof(sc); 1114 1115 if (status & LGE_ISR_RXDMA_DONE) 1116 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1117 1118 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1119 lge_rxeoc(sc); 1120 1121 if (status & LGE_ISR_PHY_INTR) { 1122 sc->lge_link = 0; 1123 untimeout(lge_tick, sc, sc->lge_stat_ch); 1124 lge_tick(sc); 1125 } 1126 } 1127 1128 /* Re-enable interrupts. */ 1129 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1130 1131 if (ifp->if_snd.ifq_head != NULL) 1132 lge_start(ifp); 1133 1134 return; 1135 } 1136 1137 /* 1138 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1139 * pointers to the fragment pointers. 1140 */ 1141 static int 1142 lge_encap(sc, m_head, txidx) 1143 struct lge_softc *sc; 1144 struct mbuf *m_head; 1145 u_int32_t *txidx; 1146 { 1147 struct lge_frag *f = NULL; 1148 struct lge_tx_desc *cur_tx; 1149 struct mbuf *m; 1150 int frag = 0, tot_len = 0; 1151 1152 /* 1153 * Start packing the mbufs in this chain into 1154 * the fragment pointers. Stop when we run out 1155 * of fragments or hit the end of the mbuf chain. 1156 */ 1157 m = m_head; 1158 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1159 frag = 0; 1160 1161 for (m = m_head; m != NULL; m = m->m_next) { 1162 if (m->m_len != 0) { 1163 tot_len += m->m_len; 1164 f = &cur_tx->lge_frags[frag]; 1165 f->lge_fraglen = m->m_len; 1166 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1167 f->lge_fragptr_hi = 0; 1168 frag++; 1169 } 1170 } 1171 1172 if (m != NULL) 1173 return(ENOBUFS); 1174 1175 cur_tx->lge_mbuf = m_head; 1176 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1177 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1178 1179 /* Queue for transmit */ 1180 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1181 1182 return(0); 1183 } 1184 1185 /* 1186 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1187 * to the mbuf data regions directly in the transmit lists. We also save a 1188 * copy of the pointers since the transmit list fragment pointers are 1189 * physical addresses. 1190 */ 1191 1192 static void 1193 lge_start(ifp) 1194 struct ifnet *ifp; 1195 { 1196 struct lge_softc *sc; 1197 struct mbuf *m_head = NULL; 1198 u_int32_t idx; 1199 1200 sc = ifp->if_softc; 1201 1202 if (!sc->lge_link) 1203 return; 1204 1205 idx = sc->lge_cdata.lge_tx_prod; 1206 1207 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1208 return; 1209 1210 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1211 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1212 break; 1213 1214 IF_DEQUEUE(&ifp->if_snd, m_head); 1215 if (m_head == NULL) 1216 break; 1217 1218 if (lge_encap(sc, m_head, &idx)) { 1219 IF_PREPEND(&ifp->if_snd, m_head); 1220 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1221 break; 1222 } 1223 1224 /* 1225 * If there's a BPF listener, bounce a copy of this frame 1226 * to him. 1227 */ 1228 BPF_MTAP(ifp, m_head); 1229 } 1230 1231 sc->lge_cdata.lge_tx_prod = idx; 1232 1233 /* 1234 * Set a timeout in case the chip goes out to lunch. 1235 */ 1236 ifp->if_timer = 5; 1237 1238 return; 1239 } 1240 1241 static void 1242 lge_init(xsc) 1243 void *xsc; 1244 { 1245 struct lge_softc *sc = xsc; 1246 struct ifnet *ifp = sc->lge_ifp; 1247 struct mii_data *mii; 1248 int s; 1249 1250 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1251 return; 1252 1253 s = splimp(); 1254 1255 /* 1256 * Cancel pending I/O and free all RX/TX buffers. 1257 */ 1258 lge_stop(sc); 1259 lge_reset(sc); 1260 1261 mii = device_get_softc(sc->lge_miibus); 1262 1263 /* Set MAC address */ 1264 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->lge_ifp)[0])); 1265 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->lge_ifp)[4])); 1266 1267 /* Init circular RX list. */ 1268 if (lge_list_rx_init(sc) == ENOBUFS) { 1269 printf("lge%d: initialization failed: no " 1270 "memory for rx buffers\n", sc->lge_unit); 1271 lge_stop(sc); 1272 (void)splx(s); 1273 return; 1274 } 1275 1276 /* 1277 * Init tx descriptors. 1278 */ 1279 lge_list_tx_init(sc); 1280 1281 /* Set initial value for MODE1 register. */ 1282 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1283 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1284 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1285 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1286 1287 /* If we want promiscuous mode, set the allframes bit. */ 1288 if (ifp->if_flags & IFF_PROMISC) { 1289 CSR_WRITE_4(sc, LGE_MODE1, 1290 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1291 } else { 1292 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1293 } 1294 1295 /* 1296 * Set the capture broadcast bit to capture broadcast frames. 1297 */ 1298 if (ifp->if_flags & IFF_BROADCAST) { 1299 CSR_WRITE_4(sc, LGE_MODE1, 1300 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1301 } else { 1302 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1303 } 1304 1305 /* Packet padding workaround? */ 1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1307 1308 /* No error frames */ 1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1310 1311 /* Receive large frames */ 1312 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1313 1314 /* Workaround: disable RX/TX flow control */ 1315 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1317 1318 /* Make sure to strip CRC from received frames */ 1319 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1320 1321 /* Turn off magic packet mode */ 1322 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1323 1324 /* Turn off all VLAN stuff */ 1325 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1326 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1327 1328 /* Workarond: FIFO overflow */ 1329 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1330 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1331 1332 /* 1333 * Load the multicast filter. 1334 */ 1335 lge_setmulti(sc); 1336 1337 /* 1338 * Enable hardware checksum validation for all received IPv4 1339 * packets, do not reject packets with bad checksums. 1340 */ 1341 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1342 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1343 LGE_MODE2_RX_ERRCSUM); 1344 1345 /* 1346 * Enable the delivery of PHY interrupts based on 1347 * link/speed/duplex status chalges. 1348 */ 1349 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1350 1351 /* Enable receiver and transmitter. */ 1352 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1354 1355 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1357 1358 /* 1359 * Enable interrupts. 1360 */ 1361 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1362 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1363 1364 lge_ifmedia_upd(ifp); 1365 1366 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1367 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1368 1369 (void)splx(s); 1370 1371 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1372 1373 return; 1374 } 1375 1376 /* 1377 * Set media options. 1378 */ 1379 static int 1380 lge_ifmedia_upd(ifp) 1381 struct ifnet *ifp; 1382 { 1383 struct lge_softc *sc; 1384 struct mii_data *mii; 1385 1386 sc = ifp->if_softc; 1387 1388 mii = device_get_softc(sc->lge_miibus); 1389 sc->lge_link = 0; 1390 if (mii->mii_instance) { 1391 struct mii_softc *miisc; 1392 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1393 miisc = LIST_NEXT(miisc, mii_list)) 1394 mii_phy_reset(miisc); 1395 } 1396 mii_mediachg(mii); 1397 1398 return(0); 1399 } 1400 1401 /* 1402 * Report current media status. 1403 */ 1404 static void 1405 lge_ifmedia_sts(ifp, ifmr) 1406 struct ifnet *ifp; 1407 struct ifmediareq *ifmr; 1408 { 1409 struct lge_softc *sc; 1410 struct mii_data *mii; 1411 1412 sc = ifp->if_softc; 1413 1414 mii = device_get_softc(sc->lge_miibus); 1415 mii_pollstat(mii); 1416 ifmr->ifm_active = mii->mii_media_active; 1417 ifmr->ifm_status = mii->mii_media_status; 1418 1419 return; 1420 } 1421 1422 static int 1423 lge_ioctl(ifp, command, data) 1424 struct ifnet *ifp; 1425 u_long command; 1426 caddr_t data; 1427 { 1428 struct lge_softc *sc = ifp->if_softc; 1429 struct ifreq *ifr = (struct ifreq *) data; 1430 struct mii_data *mii; 1431 int s, error = 0; 1432 1433 s = splimp(); 1434 1435 switch(command) { 1436 case SIOCSIFMTU: 1437 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1438 error = EINVAL; 1439 else 1440 ifp->if_mtu = ifr->ifr_mtu; 1441 break; 1442 case SIOCSIFFLAGS: 1443 if (ifp->if_flags & IFF_UP) { 1444 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1445 ifp->if_flags & IFF_PROMISC && 1446 !(sc->lge_if_flags & IFF_PROMISC)) { 1447 CSR_WRITE_4(sc, LGE_MODE1, 1448 LGE_MODE1_SETRST_CTL1| 1449 LGE_MODE1_RX_PROMISC); 1450 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1451 !(ifp->if_flags & IFF_PROMISC) && 1452 sc->lge_if_flags & IFF_PROMISC) { 1453 CSR_WRITE_4(sc, LGE_MODE1, 1454 LGE_MODE1_RX_PROMISC); 1455 } else { 1456 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1457 lge_init(sc); 1458 } 1459 } else { 1460 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1461 lge_stop(sc); 1462 } 1463 sc->lge_if_flags = ifp->if_flags; 1464 error = 0; 1465 break; 1466 case SIOCADDMULTI: 1467 case SIOCDELMULTI: 1468 lge_setmulti(sc); 1469 error = 0; 1470 break; 1471 case SIOCGIFMEDIA: 1472 case SIOCSIFMEDIA: 1473 mii = device_get_softc(sc->lge_miibus); 1474 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1475 break; 1476 default: 1477 error = ether_ioctl(ifp, command, data); 1478 break; 1479 } 1480 1481 (void)splx(s); 1482 1483 return(error); 1484 } 1485 1486 static void 1487 lge_watchdog(ifp) 1488 struct ifnet *ifp; 1489 { 1490 struct lge_softc *sc; 1491 1492 sc = ifp->if_softc; 1493 1494 ifp->if_oerrors++; 1495 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1496 1497 lge_stop(sc); 1498 lge_reset(sc); 1499 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1500 lge_init(sc); 1501 1502 if (ifp->if_snd.ifq_head != NULL) 1503 lge_start(ifp); 1504 1505 return; 1506 } 1507 1508 /* 1509 * Stop the adapter and free any mbufs allocated to the 1510 * RX and TX lists. 1511 */ 1512 static void 1513 lge_stop(sc) 1514 struct lge_softc *sc; 1515 { 1516 register int i; 1517 struct ifnet *ifp; 1518 1519 ifp = sc->lge_ifp; 1520 ifp->if_timer = 0; 1521 untimeout(lge_tick, sc, sc->lge_stat_ch); 1522 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1523 1524 /* Disable receiver and transmitter. */ 1525 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1526 sc->lge_link = 0; 1527 1528 /* 1529 * Free data in the RX lists. 1530 */ 1531 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1532 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1533 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1534 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1535 } 1536 } 1537 bzero((char *)&sc->lge_ldata->lge_rx_list, 1538 sizeof(sc->lge_ldata->lge_rx_list)); 1539 1540 /* 1541 * Free the TX list buffers. 1542 */ 1543 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1544 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1545 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1546 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1547 } 1548 } 1549 1550 bzero((char *)&sc->lge_ldata->lge_tx_list, 1551 sizeof(sc->lge_ldata->lge_tx_list)); 1552 1553 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1554 1555 return; 1556 } 1557 1558 /* 1559 * Stop all chip I/O so that the kernel's probe routines don't 1560 * get confused by errant DMAs when rebooting. 1561 */ 1562 static void 1563 lge_shutdown(dev) 1564 device_t dev; 1565 { 1566 struct lge_softc *sc; 1567 1568 sc = device_get_softc(dev); 1569 1570 lge_reset(sc); 1571 lge_stop(sc); 1572 1573 return; 1574 } 1575