1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/socket.h> 79 80 #include <net/if.h> 81 #include <net/if_arp.h> 82 #include <net/ethernet.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 86 #include <net/bpf.h> 87 88 #include <vm/vm.h> /* for vtophys */ 89 #include <vm/pmap.h> /* for vtophys */ 90 #include <machine/clock.h> /* for DELAY */ 91 #include <machine/bus_pio.h> 92 #include <machine/bus_memio.h> 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 104 #define LGE_USEIOSPACE 105 106 #include <dev/lge/if_lgereg.h> 107 108 /* "controller miibus0" required. See GENERIC if you get errors here. */ 109 #include "miibus_if.h" 110 111 /* 112 * Various supported device vendors/types and their names. 113 */ 114 static struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117 }; 118 119 static int lge_probe(device_t); 120 static int lge_attach(device_t); 121 static int lge_detach(device_t); 122 123 static int lge_alloc_jumbo_mem(struct lge_softc *); 124 static void lge_free_jumbo_mem(struct lge_softc *); 125 static void *lge_jalloc(struct lge_softc *); 126 static void lge_jfree(void *, void *); 127 128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130 static void lge_rxeof(struct lge_softc *, int); 131 static void lge_rxeoc(struct lge_softc *); 132 static void lge_txeof(struct lge_softc *); 133 static void lge_intr(void *); 134 static void lge_tick(void *); 135 static void lge_start(struct ifnet *); 136 static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137 static void lge_init(void *); 138 static void lge_stop(struct lge_softc *); 139 static void lge_watchdog(struct ifnet *); 140 static void lge_shutdown(device_t); 141 static int lge_ifmedia_upd(struct ifnet *); 142 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 145 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 146 147 static int lge_miibus_readreg(device_t, int, int); 148 static int lge_miibus_writereg(device_t, int, int, int); 149 static void lge_miibus_statchg(device_t); 150 151 static void lge_setmulti(struct lge_softc *); 152 static uint32_t lge_mchash(const uint8_t *); 153 static void lge_reset(struct lge_softc *); 154 static int lge_list_rx_init(struct lge_softc *); 155 static int lge_list_tx_init(struct lge_softc *); 156 157 #ifdef LGE_USEIOSPACE 158 #define LGE_RES SYS_RES_IOPORT 159 #define LGE_RID LGE_PCI_LOIO 160 #else 161 #define LGE_RES SYS_RES_MEMORY 162 #define LGE_RID LGE_PCI_LOMEM 163 #endif 164 165 static device_method_t lge_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, lge_probe), 168 DEVMETHOD(device_attach, lge_attach), 169 DEVMETHOD(device_detach, lge_detach), 170 DEVMETHOD(device_shutdown, lge_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 { 0, 0 } 182 }; 183 184 static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188 }; 189 190 static devclass_t lge_devclass; 191 192 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194 MODULE_DEPEND(lge, pci, 1, 1, 1); 195 MODULE_DEPEND(lge, ether, 1, 1, 1); 196 MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198 #define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202 #define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206 #define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209 #define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212 /* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215 static void 216 lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220 { 221 register int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244 } 245 246 /* 247 * Read a sequence of words from the EEPROM. 248 */ 249 static void 250 lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256 { 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270 } 271 272 static int 273 lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276 { 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 printf("lge%d: PHY read timed out\n", sc->lge_unit); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302 } 303 304 static int 305 lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308 { 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 printf("lge%d: PHY write timed out\n", sc->lge_unit); 323 return(0); 324 } 325 326 return(0); 327 } 328 329 static void 330 lge_miibus_statchg(dev) 331 device_t dev; 332 { 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368 } 369 370 static uint32_t 371 lge_mchash(addr) 372 const uint8_t *addr; 373 { 374 uint32_t crc, carry; 375 int idx, bit; 376 uint8_t data; 377 378 /* Compute CRC for the address value. */ 379 crc = 0xFFFFFFFF; /* initial value */ 380 381 for (idx = 0; idx < 6; idx++) { 382 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 383 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 384 crc <<= 1; 385 if (carry) 386 crc = (crc ^ 0x04c11db6) | carry; 387 } 388 } 389 390 /* 391 * return the filter bit position 392 */ 393 return((crc >> 26) & 0x0000003F); 394 } 395 396 static void 397 lge_setmulti(sc) 398 struct lge_softc *sc; 399 { 400 struct ifnet *ifp; 401 struct ifmultiaddr *ifma; 402 u_int32_t h = 0, hashes[2] = { 0, 0 }; 403 404 ifp = &sc->arpcom.ac_if; 405 406 /* Make sure multicast hash table is enabled. */ 407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 408 409 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 410 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 411 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 412 return; 413 } 414 415 /* first, zot all the existing hash bits */ 416 CSR_WRITE_4(sc, LGE_MAR0, 0); 417 CSR_WRITE_4(sc, LGE_MAR1, 0); 418 419 /* now program new ones */ 420 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 421 if (ifma->ifma_addr->sa_family != AF_LINK) 422 continue; 423 h = lge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 424 if (h < 32) 425 hashes[0] |= (1 << h); 426 else 427 hashes[1] |= (1 << (h - 32)); 428 } 429 430 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 431 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 432 433 return; 434 } 435 436 static void 437 lge_reset(sc) 438 struct lge_softc *sc; 439 { 440 register int i; 441 442 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 443 444 for (i = 0; i < LGE_TIMEOUT; i++) { 445 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 446 break; 447 } 448 449 if (i == LGE_TIMEOUT) 450 printf("lge%d: reset never completed\n", sc->lge_unit); 451 452 /* Wait a little while for the chip to get its brains in order. */ 453 DELAY(1000); 454 455 return; 456 } 457 458 /* 459 * Probe for a Level 1 chip. Check the PCI vendor and device 460 * IDs against our list and return a device name if we find a match. 461 */ 462 static int 463 lge_probe(dev) 464 device_t dev; 465 { 466 struct lge_type *t; 467 468 t = lge_devs; 469 470 while(t->lge_name != NULL) { 471 if ((pci_get_vendor(dev) == t->lge_vid) && 472 (pci_get_device(dev) == t->lge_did)) { 473 device_set_desc(dev, t->lge_name); 474 return(0); 475 } 476 t++; 477 } 478 479 return(ENXIO); 480 } 481 482 /* 483 * Attach the interface. Allocate softc structures, do ifmedia 484 * setup and ethernet/BPF attach. 485 */ 486 static int 487 lge_attach(dev) 488 device_t dev; 489 { 490 int s; 491 u_char eaddr[ETHER_ADDR_LEN]; 492 struct lge_softc *sc; 493 struct ifnet *ifp; 494 int unit, error = 0, rid; 495 496 s = splimp(); 497 498 sc = device_get_softc(dev); 499 unit = device_get_unit(dev); 500 bzero(sc, sizeof(struct lge_softc)); 501 #ifndef BURN_BRIDGES 502 /* 503 * Handle power management nonsense. 504 */ 505 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 506 u_int32_t iobase, membase, irq; 507 508 /* Save important PCI config data. */ 509 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 510 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 511 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 512 513 /* Reset the power state. */ 514 printf("lge%d: chip is in D%d power mode " 515 "-- setting to D0\n", unit, 516 pci_get_powerstate(dev)); 517 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 518 519 /* Restore PCI config data. */ 520 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 521 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 522 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 523 } 524 #endif 525 /* 526 * Map control/status registers. 527 */ 528 pci_enable_busmaster(dev); 529 530 rid = LGE_RID; 531 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 532 533 if (sc->lge_res == NULL) { 534 printf("lge%d: couldn't map ports/memory\n", unit); 535 error = ENXIO; 536 goto fail; 537 } 538 539 sc->lge_btag = rman_get_bustag(sc->lge_res); 540 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 541 542 /* Allocate interrupt */ 543 rid = 0; 544 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 545 RF_SHAREABLE | RF_ACTIVE); 546 547 if (sc->lge_irq == NULL) { 548 printf("lge%d: couldn't map interrupt\n", unit); 549 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 550 error = ENXIO; 551 goto fail; 552 } 553 554 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 555 lge_intr, sc, &sc->lge_intrhand); 556 557 if (error) { 558 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 559 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 560 printf("lge%d: couldn't set up irq\n", unit); 561 goto fail; 562 } 563 564 /* Reset the adapter. */ 565 lge_reset(sc); 566 567 /* 568 * Get station address from the EEPROM. 569 */ 570 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 571 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 572 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 573 574 sc->lge_unit = unit; 575 callout_handle_init(&sc->lge_stat_ch); 576 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 577 578 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 579 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 580 581 if (sc->lge_ldata == NULL) { 582 printf("lge%d: no memory for list buffers!\n", unit); 583 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 584 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 585 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 586 error = ENXIO; 587 goto fail; 588 } 589 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 590 591 /* Try to allocate memory for jumbo buffers. */ 592 if (lge_alloc_jumbo_mem(sc)) { 593 printf("lge%d: jumbo buffer allocation failed\n", 594 sc->lge_unit); 595 contigfree(sc->lge_ldata, 596 sizeof(struct lge_list_data), M_DEVBUF); 597 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 598 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 599 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 600 error = ENXIO; 601 goto fail; 602 } 603 604 ifp = &sc->arpcom.ac_if; 605 ifp->if_softc = sc; 606 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 607 ifp->if_mtu = ETHERMTU; 608 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 609 ifp->if_ioctl = lge_ioctl; 610 ifp->if_output = ether_output; 611 ifp->if_start = lge_start; 612 ifp->if_watchdog = lge_watchdog; 613 ifp->if_init = lge_init; 614 ifp->if_baudrate = 1000000000; 615 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 616 ifp->if_capabilities = IFCAP_RXCSUM; 617 ifp->if_capenable = ifp->if_capabilities; 618 619 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 620 sc->lge_pcs = 1; 621 else 622 sc->lge_pcs = 0; 623 624 /* 625 * Do MII setup. 626 */ 627 if (mii_phy_probe(dev, &sc->lge_miibus, 628 lge_ifmedia_upd, lge_ifmedia_sts)) { 629 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 630 contigfree(sc->lge_ldata, 631 sizeof(struct lge_list_data), M_DEVBUF); 632 lge_free_jumbo_mem(sc); 633 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 634 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 635 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 636 error = ENXIO; 637 goto fail; 638 } 639 640 /* 641 * Call MI attach routine. 642 */ 643 ether_ifattach(ifp, eaddr); 644 callout_handle_init(&sc->lge_stat_ch); 645 646 fail: 647 splx(s); 648 return(error); 649 } 650 651 static int 652 lge_detach(dev) 653 device_t dev; 654 { 655 struct lge_softc *sc; 656 struct ifnet *ifp; 657 int s; 658 659 s = splimp(); 660 661 sc = device_get_softc(dev); 662 ifp = &sc->arpcom.ac_if; 663 664 lge_reset(sc); 665 lge_stop(sc); 666 ether_ifdetach(ifp); 667 668 bus_generic_detach(dev); 669 device_delete_child(dev, sc->lge_miibus); 670 671 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 672 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 673 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 674 675 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 676 lge_free_jumbo_mem(sc); 677 678 splx(s); 679 680 return(0); 681 } 682 683 /* 684 * Initialize the transmit descriptors. 685 */ 686 static int 687 lge_list_tx_init(sc) 688 struct lge_softc *sc; 689 { 690 struct lge_list_data *ld; 691 struct lge_ring_data *cd; 692 int i; 693 694 cd = &sc->lge_cdata; 695 ld = sc->lge_ldata; 696 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 697 ld->lge_tx_list[i].lge_mbuf = NULL; 698 ld->lge_tx_list[i].lge_ctl = 0; 699 } 700 701 cd->lge_tx_prod = cd->lge_tx_cons = 0; 702 703 return(0); 704 } 705 706 707 /* 708 * Initialize the RX descriptors and allocate mbufs for them. Note that 709 * we arralge the descriptors in a closed ring, so that the last descriptor 710 * points back to the first. 711 */ 712 static int 713 lge_list_rx_init(sc) 714 struct lge_softc *sc; 715 { 716 struct lge_list_data *ld; 717 struct lge_ring_data *cd; 718 int i; 719 720 ld = sc->lge_ldata; 721 cd = &sc->lge_cdata; 722 723 cd->lge_rx_prod = cd->lge_rx_cons = 0; 724 725 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 726 727 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 728 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 729 break; 730 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 731 return(ENOBUFS); 732 } 733 734 /* Clear possible 'rx command queue empty' interrupt. */ 735 CSR_READ_4(sc, LGE_ISR); 736 737 return(0); 738 } 739 740 /* 741 * Initialize an RX descriptor and attach an MBUF cluster. 742 */ 743 static int 744 lge_newbuf(sc, c, m) 745 struct lge_softc *sc; 746 struct lge_rx_desc *c; 747 struct mbuf *m; 748 { 749 struct mbuf *m_new = NULL; 750 caddr_t *buf = NULL; 751 752 if (m == NULL) { 753 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 754 if (m_new == NULL) { 755 printf("lge%d: no memory for rx list " 756 "-- packet dropped!\n", sc->lge_unit); 757 return(ENOBUFS); 758 } 759 760 /* Allocate the jumbo buffer */ 761 buf = lge_jalloc(sc); 762 if (buf == NULL) { 763 #ifdef LGE_VERBOSE 764 printf("lge%d: jumbo allocation failed " 765 "-- packet dropped!\n", sc->lge_unit); 766 #endif 767 m_freem(m_new); 768 return(ENOBUFS); 769 } 770 /* Attach the buffer to the mbuf */ 771 m_new->m_data = (void *)buf; 772 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 773 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 774 (struct lge_softc *)sc, 0, EXT_NET_DRV); 775 } else { 776 m_new = m; 777 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 778 m_new->m_data = m_new->m_ext.ext_buf; 779 } 780 781 /* 782 * Adjust alignment so packet payload begins on a 783 * longword boundary. Mandatory for Alpha, useful on 784 * x86 too. 785 */ 786 m_adj(m_new, ETHER_ALIGN); 787 788 c->lge_mbuf = m_new; 789 c->lge_fragptr_hi = 0; 790 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 791 c->lge_fraglen = m_new->m_len; 792 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 793 c->lge_sts = 0; 794 795 /* 796 * Put this buffer in the RX command FIFO. To do this, 797 * we just write the physical address of the descriptor 798 * into the RX descriptor address registers. Note that 799 * there are two registers, one high DWORD and one low 800 * DWORD, which lets us specify a 64-bit address if 801 * desired. We only use a 32-bit address for now. 802 * Writing to the low DWORD register is what actually 803 * causes the command to be issued, so we do that 804 * last. 805 */ 806 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 807 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 808 809 return(0); 810 } 811 812 static int 813 lge_alloc_jumbo_mem(sc) 814 struct lge_softc *sc; 815 { 816 caddr_t ptr; 817 register int i; 818 struct lge_jpool_entry *entry; 819 820 /* Grab a big chunk o' storage. */ 821 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 822 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 823 824 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 825 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 826 return(ENOBUFS); 827 } 828 829 SLIST_INIT(&sc->lge_jfree_listhead); 830 SLIST_INIT(&sc->lge_jinuse_listhead); 831 832 /* 833 * Now divide it up into 9K pieces and save the addresses 834 * in an array. 835 */ 836 ptr = sc->lge_cdata.lge_jumbo_buf; 837 for (i = 0; i < LGE_JSLOTS; i++) { 838 sc->lge_cdata.lge_jslots[i] = ptr; 839 ptr += LGE_JLEN; 840 entry = malloc(sizeof(struct lge_jpool_entry), 841 M_DEVBUF, M_NOWAIT); 842 if (entry == NULL) { 843 printf("lge%d: no memory for jumbo " 844 "buffer queue!\n", sc->lge_unit); 845 return(ENOBUFS); 846 } 847 entry->slot = i; 848 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 849 entry, jpool_entries); 850 } 851 852 return(0); 853 } 854 855 static void 856 lge_free_jumbo_mem(sc) 857 struct lge_softc *sc; 858 { 859 int i; 860 struct lge_jpool_entry *entry; 861 862 for (i = 0; i < LGE_JSLOTS; i++) { 863 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 864 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 865 free(entry, M_DEVBUF); 866 } 867 868 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 869 870 return; 871 } 872 873 /* 874 * Allocate a jumbo buffer. 875 */ 876 static void * 877 lge_jalloc(sc) 878 struct lge_softc *sc; 879 { 880 struct lge_jpool_entry *entry; 881 882 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 883 884 if (entry == NULL) { 885 #ifdef LGE_VERBOSE 886 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 887 #endif 888 return(NULL); 889 } 890 891 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 892 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 893 return(sc->lge_cdata.lge_jslots[entry->slot]); 894 } 895 896 /* 897 * Release a jumbo buffer. 898 */ 899 static void 900 lge_jfree(buf, args) 901 void *buf; 902 void *args; 903 { 904 struct lge_softc *sc; 905 int i; 906 struct lge_jpool_entry *entry; 907 908 /* Extract the softc struct pointer. */ 909 sc = args; 910 911 if (sc == NULL) 912 panic("lge_jfree: can't find softc pointer!"); 913 914 /* calculate the slot this buffer belongs to */ 915 i = ((vm_offset_t)buf 916 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 917 918 if ((i < 0) || (i >= LGE_JSLOTS)) 919 panic("lge_jfree: asked to free buffer that we don't manage!"); 920 921 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 922 if (entry == NULL) 923 panic("lge_jfree: buffer not in use!"); 924 entry->slot = i; 925 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 926 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 927 928 return; 929 } 930 931 /* 932 * A frame has been uploaded: pass the resulting mbuf chain up to 933 * the higher level protocols. 934 */ 935 static void 936 lge_rxeof(sc, cnt) 937 struct lge_softc *sc; 938 int cnt; 939 { 940 struct mbuf *m; 941 struct ifnet *ifp; 942 struct lge_rx_desc *cur_rx; 943 int c, i, total_len = 0; 944 u_int32_t rxsts, rxctl; 945 946 ifp = &sc->arpcom.ac_if; 947 948 /* Find out how many frames were processed. */ 949 c = cnt; 950 i = sc->lge_cdata.lge_rx_cons; 951 952 /* Suck them in. */ 953 while(c) { 954 struct mbuf *m0 = NULL; 955 956 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 957 rxctl = cur_rx->lge_ctl; 958 rxsts = cur_rx->lge_sts; 959 m = cur_rx->lge_mbuf; 960 cur_rx->lge_mbuf = NULL; 961 total_len = LGE_RXBYTES(cur_rx); 962 LGE_INC(i, LGE_RX_LIST_CNT); 963 c--; 964 965 /* 966 * If an error occurs, update stats, clear the 967 * status word and leave the mbuf cluster in place: 968 * it should simply get re-used next time this descriptor 969 * comes up in the ring. 970 */ 971 if (rxctl & LGE_RXCTL_ERRMASK) { 972 ifp->if_ierrors++; 973 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 974 continue; 975 } 976 977 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 978 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 979 ifp, NULL); 980 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 981 if (m0 == NULL) { 982 printf("lge%d: no receive buffers " 983 "available -- packet dropped!\n", 984 sc->lge_unit); 985 ifp->if_ierrors++; 986 continue; 987 } 988 m = m0; 989 } else { 990 m->m_pkthdr.rcvif = ifp; 991 m->m_pkthdr.len = m->m_len = total_len; 992 } 993 994 ifp->if_ipackets++; 995 996 /* Do IP checksum checking. */ 997 if (rxsts & LGE_RXSTS_ISIP) 998 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 999 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1000 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1001 if ((rxsts & LGE_RXSTS_ISTCP && 1002 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1003 (rxsts & LGE_RXSTS_ISUDP && 1004 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1005 m->m_pkthdr.csum_flags |= 1006 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1007 m->m_pkthdr.csum_data = 0xffff; 1008 } 1009 1010 (*ifp->if_input)(ifp, m); 1011 } 1012 1013 sc->lge_cdata.lge_rx_cons = i; 1014 1015 return; 1016 } 1017 1018 static void 1019 lge_rxeoc(sc) 1020 struct lge_softc *sc; 1021 { 1022 struct ifnet *ifp; 1023 1024 ifp = &sc->arpcom.ac_if; 1025 ifp->if_flags &= ~IFF_RUNNING; 1026 lge_init(sc); 1027 return; 1028 } 1029 1030 /* 1031 * A frame was downloaded to the chip. It's safe for us to clean up 1032 * the list buffers. 1033 */ 1034 1035 static void 1036 lge_txeof(sc) 1037 struct lge_softc *sc; 1038 { 1039 struct lge_tx_desc *cur_tx = NULL; 1040 struct ifnet *ifp; 1041 u_int32_t idx, txdone; 1042 1043 ifp = &sc->arpcom.ac_if; 1044 1045 /* Clear the timeout timer. */ 1046 ifp->if_timer = 0; 1047 1048 /* 1049 * Go through our tx list and free mbufs for those 1050 * frames that have been transmitted. 1051 */ 1052 idx = sc->lge_cdata.lge_tx_cons; 1053 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1054 1055 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1056 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1057 1058 ifp->if_opackets++; 1059 if (cur_tx->lge_mbuf != NULL) { 1060 m_freem(cur_tx->lge_mbuf); 1061 cur_tx->lge_mbuf = NULL; 1062 } 1063 cur_tx->lge_ctl = 0; 1064 1065 txdone--; 1066 LGE_INC(idx, LGE_TX_LIST_CNT); 1067 ifp->if_timer = 0; 1068 } 1069 1070 sc->lge_cdata.lge_tx_cons = idx; 1071 1072 if (cur_tx != NULL) 1073 ifp->if_flags &= ~IFF_OACTIVE; 1074 1075 return; 1076 } 1077 1078 static void 1079 lge_tick(xsc) 1080 void *xsc; 1081 { 1082 struct lge_softc *sc; 1083 struct mii_data *mii; 1084 struct ifnet *ifp; 1085 int s; 1086 1087 s = splimp(); 1088 1089 sc = xsc; 1090 ifp = &sc->arpcom.ac_if; 1091 1092 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1093 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1094 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1095 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1096 1097 if (!sc->lge_link) { 1098 mii = device_get_softc(sc->lge_miibus); 1099 mii_tick(mii); 1100 if (mii->mii_media_status & IFM_ACTIVE && 1101 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1102 sc->lge_link++; 1103 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1104 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1105 printf("lge%d: gigabit link up\n", 1106 sc->lge_unit); 1107 if (ifp->if_snd.ifq_head != NULL) 1108 lge_start(ifp); 1109 } 1110 } 1111 1112 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1113 1114 splx(s); 1115 1116 return; 1117 } 1118 1119 static void 1120 lge_intr(arg) 1121 void *arg; 1122 { 1123 struct lge_softc *sc; 1124 struct ifnet *ifp; 1125 u_int32_t status; 1126 1127 sc = arg; 1128 ifp = &sc->arpcom.ac_if; 1129 1130 /* Supress unwanted interrupts */ 1131 if (!(ifp->if_flags & IFF_UP)) { 1132 lge_stop(sc); 1133 return; 1134 } 1135 1136 for (;;) { 1137 /* 1138 * Reading the ISR register clears all interrupts, and 1139 * clears the 'interrupts enabled' bit in the IMR 1140 * register. 1141 */ 1142 status = CSR_READ_4(sc, LGE_ISR); 1143 1144 if ((status & LGE_INTRS) == 0) 1145 break; 1146 1147 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1148 lge_txeof(sc); 1149 1150 if (status & LGE_ISR_RXDMA_DONE) 1151 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1152 1153 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1154 lge_rxeoc(sc); 1155 1156 if (status & LGE_ISR_PHY_INTR) { 1157 sc->lge_link = 0; 1158 untimeout(lge_tick, sc, sc->lge_stat_ch); 1159 lge_tick(sc); 1160 } 1161 } 1162 1163 /* Re-enable interrupts. */ 1164 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1165 1166 if (ifp->if_snd.ifq_head != NULL) 1167 lge_start(ifp); 1168 1169 return; 1170 } 1171 1172 /* 1173 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1174 * pointers to the fragment pointers. 1175 */ 1176 static int 1177 lge_encap(sc, m_head, txidx) 1178 struct lge_softc *sc; 1179 struct mbuf *m_head; 1180 u_int32_t *txidx; 1181 { 1182 struct lge_frag *f = NULL; 1183 struct lge_tx_desc *cur_tx; 1184 struct mbuf *m; 1185 int frag = 0, tot_len = 0; 1186 1187 /* 1188 * Start packing the mbufs in this chain into 1189 * the fragment pointers. Stop when we run out 1190 * of fragments or hit the end of the mbuf chain. 1191 */ 1192 m = m_head; 1193 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1194 frag = 0; 1195 1196 for (m = m_head; m != NULL; m = m->m_next) { 1197 if (m->m_len != 0) { 1198 tot_len += m->m_len; 1199 f = &cur_tx->lge_frags[frag]; 1200 f->lge_fraglen = m->m_len; 1201 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1202 f->lge_fragptr_hi = 0; 1203 frag++; 1204 } 1205 } 1206 1207 if (m != NULL) 1208 return(ENOBUFS); 1209 1210 cur_tx->lge_mbuf = m_head; 1211 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1212 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1213 1214 /* Queue for transmit */ 1215 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1216 1217 return(0); 1218 } 1219 1220 /* 1221 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1222 * to the mbuf data regions directly in the transmit lists. We also save a 1223 * copy of the pointers since the transmit list fragment pointers are 1224 * physical addresses. 1225 */ 1226 1227 static void 1228 lge_start(ifp) 1229 struct ifnet *ifp; 1230 { 1231 struct lge_softc *sc; 1232 struct mbuf *m_head = NULL; 1233 u_int32_t idx; 1234 1235 sc = ifp->if_softc; 1236 1237 if (!sc->lge_link) 1238 return; 1239 1240 idx = sc->lge_cdata.lge_tx_prod; 1241 1242 if (ifp->if_flags & IFF_OACTIVE) 1243 return; 1244 1245 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1246 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1247 break; 1248 1249 IF_DEQUEUE(&ifp->if_snd, m_head); 1250 if (m_head == NULL) 1251 break; 1252 1253 if (lge_encap(sc, m_head, &idx)) { 1254 IF_PREPEND(&ifp->if_snd, m_head); 1255 ifp->if_flags |= IFF_OACTIVE; 1256 break; 1257 } 1258 1259 /* 1260 * If there's a BPF listener, bounce a copy of this frame 1261 * to him. 1262 */ 1263 BPF_MTAP(ifp, m_head); 1264 } 1265 1266 sc->lge_cdata.lge_tx_prod = idx; 1267 1268 /* 1269 * Set a timeout in case the chip goes out to lunch. 1270 */ 1271 ifp->if_timer = 5; 1272 1273 return; 1274 } 1275 1276 static void 1277 lge_init(xsc) 1278 void *xsc; 1279 { 1280 struct lge_softc *sc = xsc; 1281 struct ifnet *ifp = &sc->arpcom.ac_if; 1282 struct mii_data *mii; 1283 int s; 1284 1285 if (ifp->if_flags & IFF_RUNNING) 1286 return; 1287 1288 s = splimp(); 1289 1290 /* 1291 * Cancel pending I/O and free all RX/TX buffers. 1292 */ 1293 lge_stop(sc); 1294 lge_reset(sc); 1295 1296 mii = device_get_softc(sc->lge_miibus); 1297 1298 /* Set MAC address */ 1299 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1300 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1301 1302 /* Init circular RX list. */ 1303 if (lge_list_rx_init(sc) == ENOBUFS) { 1304 printf("lge%d: initialization failed: no " 1305 "memory for rx buffers\n", sc->lge_unit); 1306 lge_stop(sc); 1307 (void)splx(s); 1308 return; 1309 } 1310 1311 /* 1312 * Init tx descriptors. 1313 */ 1314 lge_list_tx_init(sc); 1315 1316 /* Set initial value for MODE1 register. */ 1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1318 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1319 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1320 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1321 1322 /* If we want promiscuous mode, set the allframes bit. */ 1323 if (ifp->if_flags & IFF_PROMISC) { 1324 CSR_WRITE_4(sc, LGE_MODE1, 1325 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1326 } else { 1327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1328 } 1329 1330 /* 1331 * Set the capture broadcast bit to capture broadcast frames. 1332 */ 1333 if (ifp->if_flags & IFF_BROADCAST) { 1334 CSR_WRITE_4(sc, LGE_MODE1, 1335 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1336 } else { 1337 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1338 } 1339 1340 /* Packet padding workaround? */ 1341 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1342 1343 /* No error frames */ 1344 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1345 1346 /* Receive large frames */ 1347 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1348 1349 /* Workaround: disable RX/TX flow control */ 1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1352 1353 /* Make sure to strip CRC from received frames */ 1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1355 1356 /* Turn off magic packet mode */ 1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1358 1359 /* Turn off all VLAN stuff */ 1360 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1361 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1362 1363 /* Workarond: FIFO overflow */ 1364 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1365 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1366 1367 /* 1368 * Load the multicast filter. 1369 */ 1370 lge_setmulti(sc); 1371 1372 /* 1373 * Enable hardware checksum validation for all received IPv4 1374 * packets, do not reject packets with bad checksums. 1375 */ 1376 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1377 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1378 LGE_MODE2_RX_ERRCSUM); 1379 1380 /* 1381 * Enable the delivery of PHY interrupts based on 1382 * link/speed/duplex status chalges. 1383 */ 1384 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1385 1386 /* Enable receiver and transmitter. */ 1387 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1388 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1389 1390 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1391 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1392 1393 /* 1394 * Enable interrupts. 1395 */ 1396 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1397 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1398 1399 lge_ifmedia_upd(ifp); 1400 1401 ifp->if_flags |= IFF_RUNNING; 1402 ifp->if_flags &= ~IFF_OACTIVE; 1403 1404 (void)splx(s); 1405 1406 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1407 1408 return; 1409 } 1410 1411 /* 1412 * Set media options. 1413 */ 1414 static int 1415 lge_ifmedia_upd(ifp) 1416 struct ifnet *ifp; 1417 { 1418 struct lge_softc *sc; 1419 struct mii_data *mii; 1420 1421 sc = ifp->if_softc; 1422 1423 mii = device_get_softc(sc->lge_miibus); 1424 sc->lge_link = 0; 1425 if (mii->mii_instance) { 1426 struct mii_softc *miisc; 1427 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1428 miisc = LIST_NEXT(miisc, mii_list)) 1429 mii_phy_reset(miisc); 1430 } 1431 mii_mediachg(mii); 1432 1433 return(0); 1434 } 1435 1436 /* 1437 * Report current media status. 1438 */ 1439 static void 1440 lge_ifmedia_sts(ifp, ifmr) 1441 struct ifnet *ifp; 1442 struct ifmediareq *ifmr; 1443 { 1444 struct lge_softc *sc; 1445 struct mii_data *mii; 1446 1447 sc = ifp->if_softc; 1448 1449 mii = device_get_softc(sc->lge_miibus); 1450 mii_pollstat(mii); 1451 ifmr->ifm_active = mii->mii_media_active; 1452 ifmr->ifm_status = mii->mii_media_status; 1453 1454 return; 1455 } 1456 1457 static int 1458 lge_ioctl(ifp, command, data) 1459 struct ifnet *ifp; 1460 u_long command; 1461 caddr_t data; 1462 { 1463 struct lge_softc *sc = ifp->if_softc; 1464 struct ifreq *ifr = (struct ifreq *) data; 1465 struct mii_data *mii; 1466 int s, error = 0; 1467 1468 s = splimp(); 1469 1470 switch(command) { 1471 case SIOCSIFMTU: 1472 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1473 error = EINVAL; 1474 else 1475 ifp->if_mtu = ifr->ifr_mtu; 1476 break; 1477 case SIOCSIFFLAGS: 1478 if (ifp->if_flags & IFF_UP) { 1479 if (ifp->if_flags & IFF_RUNNING && 1480 ifp->if_flags & IFF_PROMISC && 1481 !(sc->lge_if_flags & IFF_PROMISC)) { 1482 CSR_WRITE_4(sc, LGE_MODE1, 1483 LGE_MODE1_SETRST_CTL1| 1484 LGE_MODE1_RX_PROMISC); 1485 } else if (ifp->if_flags & IFF_RUNNING && 1486 !(ifp->if_flags & IFF_PROMISC) && 1487 sc->lge_if_flags & IFF_PROMISC) { 1488 CSR_WRITE_4(sc, LGE_MODE1, 1489 LGE_MODE1_RX_PROMISC); 1490 } else { 1491 ifp->if_flags &= ~IFF_RUNNING; 1492 lge_init(sc); 1493 } 1494 } else { 1495 if (ifp->if_flags & IFF_RUNNING) 1496 lge_stop(sc); 1497 } 1498 sc->lge_if_flags = ifp->if_flags; 1499 error = 0; 1500 break; 1501 case SIOCADDMULTI: 1502 case SIOCDELMULTI: 1503 lge_setmulti(sc); 1504 error = 0; 1505 break; 1506 case SIOCGIFMEDIA: 1507 case SIOCSIFMEDIA: 1508 mii = device_get_softc(sc->lge_miibus); 1509 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1510 break; 1511 default: 1512 error = ether_ioctl(ifp, command, data); 1513 break; 1514 } 1515 1516 (void)splx(s); 1517 1518 return(error); 1519 } 1520 1521 static void 1522 lge_watchdog(ifp) 1523 struct ifnet *ifp; 1524 { 1525 struct lge_softc *sc; 1526 1527 sc = ifp->if_softc; 1528 1529 ifp->if_oerrors++; 1530 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1531 1532 lge_stop(sc); 1533 lge_reset(sc); 1534 ifp->if_flags &= ~IFF_RUNNING; 1535 lge_init(sc); 1536 1537 if (ifp->if_snd.ifq_head != NULL) 1538 lge_start(ifp); 1539 1540 return; 1541 } 1542 1543 /* 1544 * Stop the adapter and free any mbufs allocated to the 1545 * RX and TX lists. 1546 */ 1547 static void 1548 lge_stop(sc) 1549 struct lge_softc *sc; 1550 { 1551 register int i; 1552 struct ifnet *ifp; 1553 1554 ifp = &sc->arpcom.ac_if; 1555 ifp->if_timer = 0; 1556 untimeout(lge_tick, sc, sc->lge_stat_ch); 1557 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1558 1559 /* Disable receiver and transmitter. */ 1560 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1561 sc->lge_link = 0; 1562 1563 /* 1564 * Free data in the RX lists. 1565 */ 1566 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1567 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1568 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1569 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1570 } 1571 } 1572 bzero((char *)&sc->lge_ldata->lge_rx_list, 1573 sizeof(sc->lge_ldata->lge_rx_list)); 1574 1575 /* 1576 * Free the TX list buffers. 1577 */ 1578 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1579 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1580 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1581 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1582 } 1583 } 1584 1585 bzero((char *)&sc->lge_ldata->lge_tx_list, 1586 sizeof(sc->lge_ldata->lge_tx_list)); 1587 1588 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1589 1590 return; 1591 } 1592 1593 /* 1594 * Stop all chip I/O so that the kernel's probe routines don't 1595 * get confused by errant DMAs when rebooting. 1596 */ 1597 static void 1598 lge_shutdown(dev) 1599 device_t dev; 1600 { 1601 struct lge_softc *sc; 1602 1603 sc = device_get_softc(dev); 1604 1605 lge_reset(sc); 1606 lge_stop(sc); 1607 1608 return; 1609 } 1610