1 /* $NetBSD: lancereg.h,v 1.12 2005/12/11 12:21:27 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Charles M. Hannum and Jason R. Thorpe. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * Ralph Campbell and Rick Macklem. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. Neither the name of the University nor the names of its contributors 50 * may be used to endorse or promote products derived from this software 51 * without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93 66 */ 67 68 /* 69 * Register description for the following Advanced Micro Devices 70 * Ethernet chips: 71 * 72 * - Am7990 Local Area Network Controller for Ethernet (LANCE) 73 * (and its descendent Am79c90 C-LANCE). 74 * 75 * - Am79c900 Integrated Local Area Communications Controller (ILACC) 76 * 77 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA 78 * 79 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller 80 * for ISA 81 * 82 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip 83 * Ethernet Controller for ISA 84 * 85 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller 86 * (for VESA and 486 local busses) 87 * 88 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 89 * Local Bus 90 * 91 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 92 * for PCI Local Bus 93 * 94 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 95 * Ethernet Controller for PCI Local Bus 96 * 97 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 98 * with OnNow Support 99 * 100 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 101 * Ethernet Controller with Integrated PHY 102 * 103 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home 104 * Networking Controller. 105 * 106 * Initialization block, transmit descriptor, and receive descriptor 107 * formats are described in two separate files: 108 * 109 * 16-bit software model (LANCE) am7990reg.h 110 * 111 * 32-bit software model (ILACC) am79900reg.h 112 * 113 * Note that the vast majority of the registers described in this file 114 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are 115 * valid on the LANCE. 116 */ 117 118 119 #ifndef _DEV_LE_LANCEREG_H_ 120 #define _DEV_LE_LANCEREG_H_ 121 122 #define LEBLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 123 /* LEMINSIZE should be ETHER_MIN_LEN when LE_MODE_DTCR is set. */ 124 #define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN) 125 126 #define LE_INITADDR(sc) (sc->sc_initaddr) 127 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix)) 128 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix)) 129 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix)) 130 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix)) 131 132 /* 133 * The byte count fields in descriptors are in two's complement. 134 * This macro does the conversion for us on unsigned numbers. 135 */ 136 #define LE_BCNT(x) (~(x) + 1) 137 138 /* 139 * Control and Status Register addresses 140 */ 141 #define LE_CSR0 0x0000 /* Control and status register */ 142 #define LE_CSR1 0x0001 /* low address of init block */ 143 #define LE_CSR2 0x0002 /* high address of init block */ 144 #define LE_CSR3 0x0003 /* Bus master and control */ 145 #define LE_CSR4 0x0004 /* Test and features control */ 146 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */ 147 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */ 148 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */ 149 #define LE_CSR8 0x0008 /* Logical Address Filter 0 */ 150 #define LE_CSR9 0x0009 /* Logical Address Filter 1 */ 151 #define LE_CSR10 0x000a /* Logical Address Filter 2 */ 152 #define LE_CSR11 0x000b /* Logical Address Filter 3 */ 153 #define LE_CSR12 0x000c /* Physical Address 0 */ 154 #define LE_CSR13 0x000d /* Physical Address 1 */ 155 #define LE_CSR14 0x000e /* Physical Address 2 */ 156 #define LE_CSR15 0x000f /* Mode */ 157 #define LE_CSR16 0x0010 /* Initialization Block addr lower */ 158 #define LE_CSR17 0x0011 /* Initialization Block addr upper */ 159 #define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */ 160 #define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */ 161 #define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */ 162 #define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */ 163 #define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */ 164 #define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */ 165 #define LE_CSR24 0x0018 /* Base addr of Rx ring lower */ 166 #define LE_CSR25 0x0019 /* Base addr of Rx ring upper */ 167 #define LE_CSR26 0x001a /* Next Rx Desc addr lower */ 168 #define LE_CSR27 0x001b /* Next Rx Desc addr upper */ 169 #define LE_CSR28 0x001c /* Current Rx Desc addr lower */ 170 #define LE_CSR29 0x001d /* Current Rx Desc addr upper */ 171 #define LE_CSR30 0x001e /* Base addr of Tx ring lower */ 172 #define LE_CSR31 0x001f /* Base addr of Tx ring upper */ 173 #define LE_CSR32 0x0020 /* Next Tx Desc addr lower */ 174 #define LE_CSR33 0x0021 /* Next Tx Desc addr upper */ 175 #define LE_CSR34 0x0022 /* Current Tx Desc addr lower */ 176 #define LE_CSR35 0x0023 /* Current Tx Desc addr upper */ 177 #define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */ 178 #define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */ 179 #define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */ 180 #define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */ 181 #define LE_CSR40 0x0028 /* Current Rx Byte Count */ 182 #define LE_CSR41 0x0029 /* Current Rx Status */ 183 #define LE_CSR42 0x002a /* Current Tx Byte Count */ 184 #define LE_CSR43 0x002b /* Current Tx Status */ 185 #define LE_CSR44 0x002c /* Next Rx Byte Count */ 186 #define LE_CSR45 0x002d /* Next Rx Status */ 187 #define LE_CSR46 0x002e /* Tx Poll Time Counter */ 188 #define LE_CSR47 0x002f /* Tx Polling Interval */ 189 #define LE_CSR48 0x0030 /* Rx Poll Time Counter */ 190 #define LE_CSR49 0x0031 /* Rx Polling Interval */ 191 #define LE_CSR58 0x003a /* Software Style */ 192 #define LE_CSR60 0x003c /* Previous Tx Desc addr lower */ 193 #define LE_CSR61 0x003d /* Previous Tx Desc addr upper */ 194 #define LE_CSR62 0x003e /* Previous Tx Byte Count */ 195 #define LE_CSR63 0x003f /* Previous Tx Status */ 196 #define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */ 197 #define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */ 198 #define LE_CSR66 0x0042 /* Next Tx Byte Count */ 199 #define LE_CSR67 0x0043 /* Next Tx Status */ 200 #define LE_CSR72 0x0048 /* Receive Ring Counter */ 201 #define LE_CSR74 0x004a /* Transmit Ring Counter */ 202 #define LE_CSR76 0x004c /* Receive Ring Length */ 203 #define LE_CSR78 0x004e /* Transmit Ring Length */ 204 #define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO 205 Threshold Control */ 206 #define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */ 207 #define LE_CSR84 0x0054 /* DMA addr register lower */ 208 #define LE_CSR85 0x0055 /* DMA addr register upper */ 209 #define LE_CSR86 0x0056 /* Buffer Byte Counter */ 210 #define LE_CSR88 0x0058 /* Chip ID Register lower */ 211 #define LE_CSR89 0x0059 /* Chip ID Register upper */ 212 #define LE_CSR92 0x005c /* Ring Length Conversion */ 213 #define LE_CSR100 0x0064 /* Bus Timeout */ 214 #define LE_CSR112 0x0070 /* Missed Frame Count */ 215 #define LE_CSR114 0x0072 /* Receive Collision Count */ 216 #define LE_CSR116 0x0074 /* OnNow Power Mode Register */ 217 #define LE_CSR122 0x007a /* Advanced Feature Control */ 218 #define LE_CSR124 0x007c /* Test Register 1 */ 219 #define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */ 220 221 /* 222 * Bus Configuration Register addresses 223 */ 224 #define LE_BCR0 0x0000 /* Master Mode Read Active */ 225 #define LE_BCR1 0x0001 /* Master Mode Write Active */ 226 #define LE_BCR2 0x0002 /* Misc. Configuration */ 227 #define LE_BCR4 0x0004 /* LED0 Status */ 228 #define LE_BCR5 0x0005 /* LED1 Status */ 229 #define LE_BCR6 0x0006 /* LED2 Status */ 230 #define LE_BCR7 0x0007 /* LED3 Status */ 231 #define LE_BCR9 0x0009 /* Full-duplex Control */ 232 #define LE_BCR16 0x0010 /* I/O Base Address lower */ 233 #define LE_BCR17 0x0011 /* I/O Base Address upper */ 234 #define LE_BCR18 0x0012 /* Burst and Bus Control Register */ 235 #define LE_BCR19 0x0013 /* EEPROM Control and Status */ 236 #define LE_BCR20 0x0014 /* Software Style */ 237 #define LE_BCR22 0x0016 /* PCI Latency Register */ 238 #define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */ 239 #define LE_BCR24 0x0018 /* PCI Subsystem ID */ 240 #define LE_BCR25 0x0019 /* SRAM Size Register */ 241 #define LE_BCR26 0x001a /* SRAM Boundary Register */ 242 #define LE_BCR27 0x001b /* SRAM Interface Control Register */ 243 #define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */ 244 #define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */ 245 #define LE_BCR30 0x001e /* Exp. Bus Data Port */ 246 #define LE_BCR31 0x001f /* Software Timer Register */ 247 #define LE_BCR32 0x0020 /* PHY Control and Status Register */ 248 #define LE_BCR33 0x0021 /* PHY Address Register */ 249 #define LE_BCR34 0x0022 /* PHY Management Data Register */ 250 #define LE_BCR35 0x0023 /* PCI Vendor ID Register */ 251 #define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */ 252 #define LE_BCR37 0x0025 /* PCI DATA0 Alias */ 253 #define LE_BCR38 0x0026 /* PCI DATA1 Alias */ 254 #define LE_BCR39 0x0027 /* PCI DATA2 Alias */ 255 #define LE_BCR40 0x0028 /* PCI DATA3 Alias */ 256 #define LE_BCR41 0x0029 /* PCI DATA4 Alias */ 257 #define LE_BCR42 0x002a /* PCI DATA5 Alias */ 258 #define LE_BCR43 0x002b /* PCI DATA6 Alias */ 259 #define LE_BCR44 0x002c /* PCI DATA7 Alias */ 260 #define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */ 261 #define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */ 262 #define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */ 263 #define LE_BCR48 0x0030 /* LED4 Status */ 264 #define LE_BCR49 0x0031 /* PHY Select */ 265 266 /* Control and status register 0 (csr0) */ 267 #define LE_C0_ERR 0x8000 /* error summary */ 268 #define LE_C0_BABL 0x4000 /* transmitter timeout error */ 269 #define LE_C0_CERR 0x2000 /* collision */ 270 #define LE_C0_MISS 0x1000 /* missed a packet */ 271 #define LE_C0_MERR 0x0800 /* memory error */ 272 #define LE_C0_RINT 0x0400 /* receiver interrupt */ 273 #define LE_C0_TINT 0x0200 /* transmitter interrupt */ 274 #define LE_C0_IDON 0x0100 /* initialization done */ 275 #define LE_C0_INTR 0x0080 /* interrupt condition */ 276 #define LE_C0_INEA 0x0040 /* interrupt enable */ 277 #define LE_C0_RXON 0x0020 /* receiver on */ 278 #define LE_C0_TXON 0x0010 /* transmitter on */ 279 #define LE_C0_TDMD 0x0008 /* transmit demand */ 280 #define LE_C0_STOP 0x0004 /* disable all external activity */ 281 #define LE_C0_STRT 0x0002 /* enable external activity */ 282 #define LE_C0_INIT 0x0001 /* begin initialization */ 283 284 #define LE_C0_BITS \ 285 "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 286 \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 287 288 /* Control and status register 3 (csr3) */ 289 #define LE_C3_BABLM 0x4000 /* babble mask */ 290 #define LE_C3_MISSM 0x1000 /* missed frame mask */ 291 #define LE_C3_MERRM 0x0800 /* memory error mask */ 292 #define LE_C3_RINTM 0x0400 /* receive interrupt mask */ 293 #define LE_C3_TINTM 0x0200 /* transmit interrupt mask */ 294 #define LE_C3_IDONM 0x0100 /* initialization done mask */ 295 #define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */ 296 #define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */ 297 #define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */ 298 #define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */ 299 #define LE_C3_BSWP 0x0004 /* byte swap */ 300 #define LE_C3_ACON 0x0002 /* ALE control, eh? */ 301 #define LE_C3_BCON 0x0001 /* byte control */ 302 303 /* Control and status register 4 (csr4) */ 304 #define LE_C4_EN124 0x8000 /* enable CSR124 */ 305 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */ 306 #define LE_C4_TIMER 0x2000 /* enable bus activity timer */ 307 #define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */ 308 #define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */ 309 #define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */ 310 #define LE_C4_MFCO 0x0200 /* missed frame counter overflow */ 311 #define LE_C4_MFCOM 0x0100 /* missed frame coutner overflow mask */ 312 #define LE_C4_UINTCMD 0x0080 /* user interrupt command */ 313 #define LE_C4_UINT 0x0040 /* user interrupt */ 314 #define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */ 315 #define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow 316 mask */ 317 #define LE_C4_TXSTRT 0x0008 /* transmit start status */ 318 #define LE_C4_TXSTRTM 0x0004 /* transmit start mask */ 319 320 /* Control and status register 5 (csr5) */ 321 #define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */ 322 #define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */ 323 #define LE_C5_SINT 0x0800 /* system interrupt */ 324 #define LE_C5_SINTE 0x0400 /* system interrupt enable */ 325 #define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */ 326 #define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */ 327 #define LE_C5_MPPLBA 0x0020 /* magic packet physical logical 328 broadcast accept */ 329 #define LE_C5_MPINT 0x0010 /* magic packet interrupt */ 330 #define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */ 331 #define LE_C5_MPEN 0x0004 /* magic packet enable */ 332 #define LE_C5_MPMODE 0x0002 /* magic packet mode */ 333 #define LE_C5_SPND 0x0001 /* suspend */ 334 335 /* Control and status register 6 (csr6) */ 336 #define LE_C6_TLEN 0xf000 /* TLEN from init block */ 337 #define LE_C6_RLEN 0x0f00 /* RLEN from init block */ 338 339 /* Control and status register 7 (csr7) */ 340 #define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */ 341 #define LE_C7_RDMD 0x2000 /* receive demand */ 342 #define LE_C7_RDXPOLL 0x1000 /* receive disable polling */ 343 #define LE_C7_STINT 0x0800 /* software timer interrupt */ 344 #define LE_C7_STINTE 0x0400 /* software timer interrupt enable */ 345 #define LE_C7_MREINT 0x0200 /* PHY management read error intr */ 346 #define LE_C7_MREINTE 0x0100 /* PHY management read error intr 347 enable */ 348 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */ 349 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr 350 enable */ 351 #define LE_C7_MCCINT 0x0020 /* PHY management command complete 352 interrupt */ 353 #define LE_C7_MCCINTE 0x0010 /* PHY management command complete 354 interrupt enable */ 355 #define LE_C7_MCCIINT 0x0008 /* PHY management command complete 356 internal interrupt */ 357 #define LE_C7_MCCIINTE 0x0004 /* PHY management command complete 358 internal interrupt enable */ 359 #define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition 360 interrupt */ 361 #define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition 362 interrupt enable */ 363 364 /* Control and status register 15 (csr15) */ 365 #define LE_C15_PROM 0x8000 /* promiscuous mode */ 366 #define LE_C15_DRCVBC 0x4000 /* disable Rx of broadcast */ 367 #define LE_C15_DRCVPA 0x2000 /* disable Rx of physical address */ 368 #define LE_C15_DLNKTST 0x1000 /* disable link status */ 369 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */ 370 #define LE_C15_MENDECL 0x0400 /* MENDEC Loopback mode */ 371 #define LE_C15_LRT 0x0200 /* low receive threshold (TMAU) */ 372 #define LE_C15_TSEL 0x0200 /* transmit mode select (AUI) */ 373 #define LE_C15_PORTSEL(x) ((x) << 7) /* port select */ 374 #define LE_C15_INTL 0x0040 /* internal loopback */ 375 #define LE_C15_DRTY 0x0020 /* disable retry */ 376 #define LE_C15_FCOLL 0x0010 /* force collision */ 377 #define LE_C15_DXMTFCS 0x0008 /* disable Tx FCS (ADD_FCS overrides) */ 378 #define LE_C15_LOOP 0x0004 /* loopback enable */ 379 #define LE_C15_DTX 0x0002 /* disable transmit */ 380 #define LE_C15_DRX 0x0001 /* disable receiver */ 381 382 #define LE_PORTSEL_AUI 0 383 #define LE_PORTSEL_10T 1 384 #define LE_PORTSEL_GPSI 2 385 #define LE_PORTSEL_MII 3 386 #define LE_PORTSEL_MASK 3 387 388 /* control and status register 80 (csr80) */ 389 #define LE_C80_RCVFW(x) ((x) << 12) /* Receive FIFO Watermark */ 390 #define LE_C80_RCVFW_MAX 3 391 #define LE_C80_XMTSP(x) ((x) << 10) /* Transmit Start Point */ 392 #define LE_C80_XMTSP_MAX 3 393 #define LE_C80_XMTFW(x) ((x) << 8) /* Transmit FIFO Watermark */ 394 #define LE_C80_XMTFW_MAX 3 395 #define LE_C80_DMATC 0x00ff /* DMA transfer counter */ 396 397 /* control and status register 116 (csr116) */ 398 #define LE_C116_PME_EN_OVR 0x0400 /* PME_EN overwrite */ 399 #define LE_C116_LCDET 0x0200 /* link change detected */ 400 #define LE_C116_LCMODE 0x0100 /* link change wakeup mode */ 401 #define LE_C116_PMAT 0x0080 /* pattern matched */ 402 #define LE_C116_EMPPLBA 0x0040 /* magic packet physical logical 403 broadcast accept */ 404 #define LE_C116_MPMAT 0x0020 /* magic packet match */ 405 #define LE_C116_MPPEN 0x0010 /* magic packet pin enable */ 406 #define LE_C116_RST_POL 0x0001 /* PHY_RST pin polarity */ 407 408 /* control and status register 122 (csr122) */ 409 #define LE_C122_RCVALGN 0x0001 /* receive packet align */ 410 411 /* control and status register 124 (csr124) */ 412 #define LE_C124_RPA 0x0008 /* runt packet accept */ 413 414 /* control and status register 125 (csr125) */ 415 #define LE_C125_IPG 0xff00 /* inter-packet gap */ 416 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */ 417 418 /* bus configuration register 0 (bcr0) */ 419 #define LE_B0_MSRDA 0xffff /* reserved locations */ 420 421 /* bus configuration register 1 (bcr1) */ 422 #define LE_B1_MSWRA 0xffff /* reserved locations */ 423 424 /* bus configuration register 2 (bcr2) */ 425 #define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */ 426 #define LE_B2_LEDPE 0x1000 /* LED program enable */ 427 #define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */ 428 #define LE_B2_INTLEVEL 0x0080 /* 1 == edge triggered */ 429 #define LE_B2_DXCVRCTL 0x0020 /* DXCVR control */ 430 #define LE_B2_DXCVRPOL 0x0010 /* DXCVR polarity */ 431 #define LE_B2_EADISEL 0x0008 /* EADI select */ 432 #define LE_B2_AWAKE 0x0004 /* power saving mode select */ 433 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */ 434 #define LE_B2_XMAUSEL 0x0001 /* reserved location */ 435 436 /* bus configuration register 4 (bcr4) */ 437 /* bus configuration register 5 (bcr5) */ 438 /* bus configuration register 6 (bcr6) */ 439 /* bus configuration register 7 (bcr7) */ 440 /* bus configuration register 48 (bcr48) */ 441 #define LE_B4_LEDOUT 0x8000 /* LED output active */ 442 #define LE_B4_LEDPOL 0x4000 /* LED polarity */ 443 #define LE_B4_LEDDIS 0x2000 /* LED disable */ 444 #define LE_B4_100E 0x1000 /* 100Mb/s enable */ 445 #define LE_B4_MPSE 0x0200 /* magic packet status enable */ 446 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */ 447 #define LE_B4_PSE 0x0080 /* pulse stretcher enable */ 448 #define LE_B4_LNKSE 0x0040 /* link status enable */ 449 #define LE_B4_RCVME 0x0020 /* receive match status enable */ 450 #define LE_B4_XMTE 0x0010 /* transmit status enable */ 451 #define LE_B4_POWER 0x0008 /* power enable */ 452 #define LE_B4_RCVE 0x0004 /* receive status enable */ 453 #define LE_B4_SPEED 0x0002 /* high speed enable */ 454 #define LE_B4_COLE 0x0001 /* collision status enable */ 455 456 /* bus configuration register 9 (bcr9) */ 457 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept 458 disable */ 459 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */ 460 #define LE_B9_FDEN 0x0001 /* full-duplex enable */ 461 462 /* bus configuration register 18 (bcr18) */ 463 #define LE_B18_ROMTMG 0xf000 /* expansion rom timing */ 464 #define LE_B18_NOUFLO 0x0800 /* no underflow on transmit */ 465 #define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */ 466 #define LE_B18_EXTREQ 0x0100 /* extended request */ 467 #define LE_B18_DWIO 0x0080 /* double-word I/O */ 468 #define LE_B18_BREADE 0x0040 /* burst read enable */ 469 #define LE_B18_BWRITE 0x0020 /* burst write enable */ 470 #define LE_B18_PHYSEL1 0x0010 /* PHYSEL 1 */ 471 #define LE_B18_PHYSEL0 0x0008 /* PHYSEL 0 */ 472 /* 00 ex ROM/Flash */ 473 /* 01 EADI/MII snoop */ 474 /* 10 reserved */ 475 /* 11 reserved */ 476 #define LE_B18_LINBC 0x0007 /* reserved locations */ 477 478 /* bus configuration register 19 (bcr19) */ 479 #define LE_B19_PVALID 0x8000 /* EEPROM status valid */ 480 #define LE_B19_PREAD 0x4000 /* EEPROM read command */ 481 #define LE_B19_EEDET 0x2000 /* EEPROM detect */ 482 #define LE_B19_EEN 0x0010 /* EEPROM port enable */ 483 #define LE_B19_ECS 0x0004 /* EEPROM chip select */ 484 #define LE_B19_ESK 0x0002 /* EEPROM serial clock */ 485 #define LE_B19_EDI 0x0001 /* EEPROM data in */ 486 #define LE_B19_EDO 0x0001 /* EEPROM data out */ 487 488 /* bus configuration register 20 (bcr20) */ 489 #define LE_B20_APERREN 0x0400 /* Advanced parity error handling */ 490 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */ 491 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */ 492 #define LE_B20_SSTYLE 0x0007 /* Software Style */ 493 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */ 494 #define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */ 495 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */ 496 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */ 497 498 /* bus configuration register 25 (bcr25) */ 499 #define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */ 500 501 /* bus configuration register 26 (bcr26) */ 502 #define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */ 503 504 /* bus configuration register 27 (bcr27) */ 505 #define LE_B27_PTRTST 0x8000 /* reserved for manuf. tests */ 506 #define LE_B27_LOLATRX 0x4000 /* low latency receive */ 507 #define LE_B27_EBCS 0x0038 /* expansion bus clock source */ 508 /* 000 CLK pin */ 509 /* 001 time base clock */ 510 /* 010 EBCLK pin */ 511 /* 011 reserved */ 512 /* 1xx reserved */ 513 #define LE_B27_CLK_FAC 0x0007 /* clock factor */ 514 /* 000 1 */ 515 /* 001 1/2 */ 516 /* 010 reserved */ 517 /* 011 1/4 */ 518 /* 1xx reserved */ 519 520 /* bus configuration register 28 (bcr28) */ 521 #define LE_B28_EADDRL 0xffff /* expansion port address lower */ 522 523 /* bus configuration register 29 (bcr29) */ 524 #define LE_B29_FLASH 0x8000 /* flash access */ 525 #define LE_B29_LAAINC 0x4000 /* lower address auto increment */ 526 #define LE_B29_EPADDRU 0x0007 /* expansion port address upper */ 527 528 /* bus configuration register 30 (bcr30) */ 529 #define LE_B30_EBDATA 0xffff /* expansion bus data port */ 530 531 /* bus configuration register 31 (bcr31) */ 532 #define LE_B31_STVAL 0xffff /* software timer value */ 533 534 /* bus configuration register 32 (bcr32) */ 535 #define LE_B32_ANTST 0x8000 /* reserved for manuf. tests */ 536 #define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */ 537 #define LE_B32_FMDC 0x3000 /* fast management data clock */ 538 #define LE_B32_APEP 0x0800 /* auto-poll PHY */ 539 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */ 540 #define LE_B32_DANAS 0x0080 /* disable autonegotiation */ 541 #define LE_B32_XPHYRST 0x0040 /* PHY reset */ 542 #define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */ 543 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */ 544 #define LE_B32_XPHYSP 0x0008 /* PHY speed */ 545 #define LE_B32_MIIILP 0x0002 /* MII internal loopback */ 546 547 /* bus configuration register 33 (bcr33) */ 548 #define LE_B33_SHADOW 0x8000 /* shadow enable */ 549 #define LE_B33_MII_SEL 0x4000 /* MII selected */ 550 #define LE_B33_ACOMP 0x2000 /* internal PHY autonegotiation comp */ 551 #define LE_B33_LINK 0x1000 /* link status */ 552 #define LE_B33_FDX 0x0800 /* full-duplex */ 553 #define LE_B33_SPEED 0x0400 /* 1 == high speed */ 554 #define LE_B33_PHYAD 0x03e0 /* PHY address */ 555 #define PHYAD_SHIFT 5 556 #define LE_B33_REGAD 0x001f /* register address */ 557 558 /* bus configuration register 34 (bcr34) */ 559 #define LE_B34_MIIMD 0xffff /* MII data */ 560 561 /* bus configuration register 49 (bcr49) */ 562 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */ 563 #define LE_B49_PHYSEL_D 0x0300 /* PHY_SEL_Default */ 564 #define LE_B49_PHYSEL_L 0x0010 /* PHY_SEL_Lock */ 565 #define LE_B49_PHYSEL 0x0003 /* PHYSEL */ 566 /* 00 10baseT PHY */ 567 /* 01 HomePNA PHY */ 568 /* 10 external PHY */ 569 /* 11 reserved */ 570 571 /* Initialization block (mode) */ 572 #define LE_MODE_PROM 0x8000 /* promiscuous mode */ 573 /* 0x7f80 reserved, must be zero */ 574 /* 0x4000 - 0x0080 are not available on LANCE 7990. */ 575 #define LE_MODE_DRCVBC 0x4000 /* disable receive broadcast */ 576 #define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */ 577 #define LE_MODE_DLNKTST 0x1000 /* disable link status */ 578 #define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */ 579 #define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */ 580 #define LE_MODE_LRTTSEL 0x0200 /* lower receive threshold / 581 transmit mode selection */ 582 #define LE_MODE_PSEL1 0x0100 /* port selection bit1 */ 583 #define LE_MODE_PSEL0 0x0080 /* port selection bit0 */ 584 #define LE_MODE_INTL 0x0040 /* internal loopback */ 585 #define LE_MODE_DRTY 0x0020 /* disable retry */ 586 #define LE_MODE_COLL 0x0010 /* force a collision */ 587 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 588 #define LE_MODE_LOOP 0x0004 /* loopback mode */ 589 #define LE_MODE_DTX 0x0002 /* disable transmitter */ 590 #define LE_MODE_DRX 0x0001 /* disable receiver */ 591 #define LE_MODE_NORMAL 0 /* none of the above */ 592 593 /* 594 * Chip ID (CSR88 IDL, CSR89 IDU) values for various AMD PCnet parts 595 */ 596 #define CHIPID_MANFID(x) (((x) >> 1) & 0x3ff) 597 #define CHIPID_PARTID(x) (((x) >> 12) & 0xffff) 598 #define CHIPID_VER(x) (((x) >> 28) & 0x7) 599 600 #define PARTID_Am79c960 0x0003 601 #define PARTID_Am79c961 0x2260 602 #define PARTID_Am79c961A 0x2261 603 #define PARTID_Am79c965 0x2430 /* yes, these... */ 604 #define PARTID_Am79c970 0x2430 /* ...are the same */ 605 #define PARTID_Am79c970A 0x2621 606 #define PARTID_Am79c971 0x2623 607 #define PARTID_Am79c972 0x2624 608 #define PARTID_Am79c973 0x2625 609 #define PARTID_Am79c978 0x2626 610 #define PARTID_Am79c975 0x2627 611 #define PARTID_Am79c976 0x2628 612 613 #endif /* !_DEV_LE_LANCEREG_H_ */ 614