1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _IF_JMEREG_H 31 #define _IF_JMEREG_H 32 33 /* 34 * JMicron Inc. PCI vendor ID 35 */ 36 #define VENDORID_JMICRON 0x197B 37 38 /* 39 * JMC250 PCI device ID 40 */ 41 #define DEVICEID_JMC250 0x0250 42 #define DEVICEREVID_JMC250 0x10 43 44 /* 45 * JMC260 PCI device ID 46 */ 47 #define DEVICEID_JMC260 0x0260 48 #define DEVICEREVID_JMC260 0x20 49 50 /* JMC250 PCI configuration register. */ 51 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 52 53 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 54 55 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 56 57 #define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 58 59 #define JME_PCI_EROM 0x30 60 61 #define JME_PCI_DBG 0x9C 62 63 #define JME_PCI_SPI 0xB0 64 65 #define SPI_ENB 0x00000010 66 #define SPI_SO_STATUS 0x00000008 67 #define SPI_SI_CTRL 0x00000004 68 #define SPI_SCK_CTRL 0x00000002 69 #define SPI_CS_N_CTRL 0x00000001 70 71 #define JME_PCI_PHYCFG0 0xC0 72 73 #define JME_PCI_PHYCFG1 0xC4 74 75 #define JME_PCI_PHYCFG2 0xC8 76 77 #define JME_PCI_PHYCFG3 0xCC 78 79 #define JME_PCI_PIPECTL1 0xD0 80 81 #define JME_PCI_PIPECTL2 0xD4 82 83 /* PCIe link error/status. */ 84 #define JME_PCI_LES 0xD8 85 86 /* propeietary register 0. */ 87 #define JME_PCI_PE0 0xE0 88 #define PE0_SPI_EXIST 0x00200000 89 #define PE0_PME_D0 0x00100000 90 #define PE0_PME_D3H 0x00080000 91 #define PE0_PME_SPI_PAD 0x00040000 92 #define PE0_MASK_ASPM 0x00020000 93 #define PE0_EEPROM_RW_DIS 0x00008000 94 #define PE0_PCI_INTA 0x00001000 95 #define PE0_PCI_INTB 0x00002000 96 #define PE0_PCI_INTC 0x00003000 97 #define PE0_PCI_INTD 0x00004000 98 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 99 #define PE0_MSIX_SIZE_8 0x00000700 100 #define PE0_MSIX_SIZE_7 0x00000600 101 #define PE0_MSIX_SIZE_6 0x00000500 102 #define PE0_MSIX_SIZE_5 0x00000400 103 #define PE0_MSIX_SIZE_4 0x00000300 104 #define PE0_MSIX_SIZE_3 0x00000200 105 #define PE0_MSIX_SIZE_2 0x00000100 106 #define PE0_MSIX_SIZE_1 0x00000000 107 #define PE0_MSIX_SIZE_DEF 0x00000700 108 #define PE0_MSIX_CAP_DIS 0x00000080 109 #define PE0_MSI_PVMC_ENB 0x00000040 110 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 111 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 112 #define PE0_PM_AUXC_MASK 0x00000007 113 #define PE0_PM_AUXC_DEF 0x00000007 114 115 #define JME_PCI_PE1 0xE4 116 117 #define JME_PCI_PHYTEST 0xF8 118 119 #define JME_PCI_GPR 0xFC 120 121 /* 122 * JMC Register Map. 123 * ----------------------------------------------------------------------- 124 * Register Size IO space Memory space 125 * ----------------------------------------------------------------------- 126 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 127 * BAR1 + 0x7F BAR0 + 0x7F 128 * ----------------------------------------------------------------------- 129 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 130 * BAR2 + 0x7F BAR0 + 0x47F 131 * ----------------------------------------------------------------------- 132 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 133 * BAR2 + 0x7F BAR0 + 0x87F 134 * ----------------------------------------------------------------------- 135 * To simplify register access fuctions and to get better performance 136 * this driver doesn't support IO space access. It could be implemented 137 * as a function which selects appropriate BARs to access requested 138 * register. 139 */ 140 141 /* Tx control and status. */ 142 #define JME_TXCSR 0x0000 143 #define TXCSR_QWEIGHT_MASK 0x0F000000 144 #define TXCSR_QWEIGHT_SHIFT 24 145 #define TXCSR_TXQ_SEL_MASK 0x00070000 146 #define TXCSR_TXQ_SEL_SHIFT 16 147 #define TXCSR_TXQ_START 0x00000001 148 #define TXCSR_TXQ_START_SHIFT 8 149 #define TXCSR_FIFO_THRESH_4QW 0x00000000 150 #define TXCSR_FIFO_THRESH_8QW 0x00000040 151 #define TXCSR_FIFO_THRESH_12QW 0x00000080 152 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 153 #define TXCSR_DMA_SIZE_64 0x00000000 154 #define TXCSR_DMA_SIZE_128 0x00000010 155 #define TXCSR_DMA_SIZE_256 0x00000020 156 #define TXCSR_DMA_SIZE_512 0x00000030 157 #define TXCSR_DMA_BURST 0x00000004 158 #define TXCSR_TX_SUSPEND 0x00000002 159 #define TXCSR_TX_ENB 0x00000001 160 #define TXCSR_TXQ0 0 161 #define TXCSR_TXQ1 1 162 #define TXCSR_TXQ2 2 163 #define TXCSR_TXQ3 3 164 #define TXCSR_TXQ4 4 165 #define TXCSR_TXQ5 5 166 #define TXCSR_TXQ6 6 167 #define TXCSR_TXQ7 7 168 #define TXCSR_TXQ_WEIGHT(x) \ 169 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 170 #define TXCSR_TXQ_WEIGHT_MIN 0 171 #define TXCSR_TXQ_WEIGHT_MAX 15 172 #define TXCSR_TXQ_N_SEL(x) \ 173 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 174 #define TXCSR_TXQ_N_START(x) \ 175 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 176 177 /* Tx queue descriptor base address. 16bytes alignment required. */ 178 #define JME_TXDBA_LO 0x0004 179 #define JME_TXDBA_HI 0x0008 180 181 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 182 #define JME_TXQDC 0x000C 183 #define TXQDC_MASK 0x0000007F0 184 185 /* Tx queue next descriptor address. */ 186 #define JME_TXNDA 0x0010 187 #define TXNDA_ADDR_MASK 0xFFFFFFF0 188 #define TXNDA_DESC_EMPTY 0x00000008 189 #define TXNDA_DESC_VALID 0x00000004 190 #define TXNDA_DESC_WAIT 0x00000002 191 #define TXNDA_DESC_FETCH 0x00000001 192 193 /* Tx MAC control ans status. */ 194 #define JME_TXMAC 0x0014 195 #define TXMAC_IFG2_MASK 0xC0000000 196 #define TXMAC_IFG2_DEFAULT 0x40000000 197 #define TXMAC_IFG1_MASK 0x30000000 198 #define TXMAC_IFG1_DEFAULT 0x20000000 199 #define TXMAC_THRESH_1_PKT 0x00000300 200 #define TXMAC_THRESH_1_2_PKT 0x00000200 201 #define TXMAC_THRESH_1_4_PKT 0x00000100 202 #define TXMAC_THRESH_1_8_PKT 0x00000000 203 #define TXMAC_FRAME_BURST 0x00000080 204 #define TXMAC_CARRIER_EXT 0x00000040 205 #define TXMAC_IFG_ENB 0x00000020 206 #define TXMAC_BACKOFF 0x00000010 207 #define TXMAC_CARRIER_SENSE 0x00000008 208 #define TXMAC_COLL_ENB 0x00000004 209 #define TXMAC_CRC_ENB 0x00000002 210 #define TXMAC_PAD_ENB 0x00000001 211 212 /* Tx pause frame control. */ 213 #define JME_TXPFC 0x0018 214 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 215 #define TXPFC_VLAN_TAG_SHIFT 16 216 #define TXPFC_VLAN_ENB 0x00008000 217 #define TXPFC_PAUSE_ENB 0x00000001 218 219 /* Tx timer/retry at half duplex. */ 220 #define JME_TXTRHD 0x001C 221 #define TXTRHD_RT_PERIOD_ENB 0x80000000 222 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 223 #define TXTRHD_RT_PERIOD_SHIFT 8 224 #define TXTRHD_RT_LIMIT_ENB 0x00000080 225 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 226 #define TXTRHD_RT_LIMIT_SHIFT 0 227 #define TXTRHD_RT_PERIOD_DEFAULT 8192 228 #define TXTRHD_RT_LIMIT_DEFAULT 8 229 230 /* Rx control & status. */ 231 #define JME_RXCSR 0x0020 232 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 233 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 234 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 235 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 236 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 237 #define RXCSR_FIFO_THRESH_16QW 0x00000000 238 #define RXCSR_FIFO_THRESH_32QW 0x04000000 239 #define RXCSR_FIFO_THRESH_64QW 0x08000000 240 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 241 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 242 #define RXCSR_DMA_SIZE_16 0x00000000 243 #define RXCSR_DMA_SIZE_32 0x01000000 244 #define RXCSR_DMA_SIZE_64 0x02000000 245 #define RXCSR_DMA_SIZE_128 0x03000000 246 #define RXCSR_RXQ_SEL_MASK 0x00030000 247 #define RXCSR_RXQ_SEL_SHIFT 16 248 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 249 #define RXCSR_DESC_RT_GAP_SHIFT 12 250 #define RXCSR_DESC_RT_GAP_256 0x00000000 251 #define RXCSR_DESC_RT_GAP_512 0x00001000 252 #define RXCSR_DESC_RT_GAP_1024 0x00002000 253 #define RXCSR_DESC_RT_GAP_2048 0x00003000 254 #define RXCSR_DESC_RT_GAP_4096 0x00004000 255 #define RXCSR_DESC_RT_GAP_8192 0x00005000 256 #define RXCSR_DESC_RT_GAP_16384 0x00006000 257 #define RXCSR_DESC_RT_GAP_32768 0x00007000 258 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 259 #define RXCSR_DESC_RT_CNT_SHIFT 8 260 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 261 #define RXCSR_PASS_MAGIC_PKT 0x00000020 262 #define RXCSR_PASS_RUNT_PKT 0x00000010 263 #define RXCSR_PASS_BAD_PKT 0x00000008 264 #define RXCSR_RXQ_START 0x00000004 265 #define RXCSR_RX_SUSPEND 0x00000002 266 #define RXCSR_RX_ENB 0x00000001 267 268 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 269 #define RXCSR_RXQ0 0 270 #define RXCSR_RXQ1 1 271 #define RXCSR_RXQ2 2 272 #define RXCSR_RXQ3 3 273 #define RXCSR_DESC_RT_CNT(x) \ 274 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 275 #define RXCSR_DESC_RT_CNT_DEFAULT 32 276 277 /* Rx queue descriptor base address. 16bytes alignment needed. */ 278 #define JME_RXDBA_LO 0x0024 279 #define JME_RXDBA_HI 0x0028 280 281 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 282 #define JME_RXQDC 0x002C 283 #define RXQDC_MASK 0x0000007F0 284 285 /* Rx queue next descriptor address. */ 286 #define JME_RXNDA 0x0030 287 #define RXNDA_ADDR_MASK 0xFFFFFFF0 288 #define RXNDA_DESC_EMPTY 0x00000008 289 #define RXNDA_DESC_VALID 0x00000004 290 #define RXNDA_DESC_WAIT 0x00000002 291 #define RXNDA_DESC_FETCH 0x00000001 292 293 /* Rx MAC control and status. */ 294 #define JME_RXMAC 0x0034 295 #define RXMAC_RSS_UNICAST 0x00000000 296 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 297 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 298 #define RXMAC_RSS_ALLFRAME 0x00030000 299 #define RXMAC_PROMISC 0x00000800 300 #define RXMAC_BROADCAST 0x00000400 301 #define RXMAC_MULTICAST 0x00000200 302 #define RXMAC_UNICAST 0x00000100 303 #define RXMAC_ALLMULTI 0x00000080 304 #define RXMAC_MULTICAST_FILTER 0x00000040 305 #define RXMAC_COLL_DET_ENB 0x00000020 306 #define RXMAC_FC_ENB 0x00000008 307 #define RXMAC_VLAN_ENB 0x00000004 308 #define RXMAC_PAD_10BYTES 0x00000002 309 #define RXMAC_CSUM_ENB 0x00000001 310 311 /* Rx unicast MAC address. */ 312 #define JME_PAR0 0x0038 313 #define JME_PAR1 0x003C 314 315 /* Rx multicast address hash table. */ 316 #define JME_MAR0 0x0040 317 #define JME_MAR1 0x0044 318 319 /* Wakeup frame output data port. */ 320 #define JME_WFODP 0x0048 321 322 /* Wakeup frame output interface. */ 323 #define JME_WFOI 0x004C 324 #define WFOI_MASK_0_31 0x00000000 325 #define WFOI_MASK_31_63 0x00000010 326 #define WFOI_MASK_64_95 0x00000020 327 #define WFOI_MASK_96_127 0x00000030 328 #define WFOI_MASK_SEL 0x00000008 329 #define WFOI_CRC_SEL 0x00000000 330 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 331 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 332 333 /* Station management interface. */ 334 #define JME_SMI 0x0050 335 #define SMI_DATA_MASK 0xFFFF0000 336 #define SMI_DATA_SHIFT 16 337 #define SMI_REG_ADDR_MASK 0x0000F800 338 #define SMI_REG_ADDR_SHIFT 11 339 #define SMI_PHY_ADDR_MASK 0x000007C0 340 #define SMI_PHY_ADDR_SHIFT 6 341 #define SMI_OP_WRITE 0x00000020 342 #define SMI_OP_READ 0x00000000 343 #define SMI_OP_EXECUTE 0x00000010 344 #define SMI_MDIO 0x00000008 345 #define SMI_MDOE 0x00000004 346 #define SMI_MDC 0x00000002 347 #define SMI_MDEN 0x00000001 348 #define SMI_REG_ADDR(x) \ 349 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 350 #define SMI_PHY_ADDR(x) \ 351 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 352 353 /* Global host control. */ 354 #define JME_GHC 0x0054 355 #define GHC_LOOPBACK 0x80000000 356 #define GHC_RESET 0x40000000 357 #define GHC_FULL_DUPLEX 0x00000040 358 #define GHC_SPEED_UNKNOWN 0x00000000 359 #define GHC_SPEED_10 0x00000010 360 #define GHC_SPEED_100 0x00000020 361 #define GHC_SPEED_1000 0x00000030 362 #define GHC_SPEED_MASK 0x00000030 363 #define GHC_LINK_OFF 0x00000004 364 #define GHC_LINK_ON 0x00000002 365 #define GHC_LINK_STAT_POLLING 0x00000001 366 367 /* Power management control and status. */ 368 #define JME_PMCS 0x0060 369 #define PMCS_WAKEUP_FRAME_7 0x80000000 370 #define PMCS_WAKEUP_FRAME_6 0x40000000 371 #define PMCS_WAKEUP_FRAME_5 0x20000000 372 #define PMCS_WAKEUP_FRAME_4 0x10000000 373 #define PMCS_WAKEUP_FRAME_3 0x08000000 374 #define PMCS_WAKEUP_FRAME_2 0x04000000 375 #define PMCS_WAKEUP_FRAME_1 0x02000000 376 #define PMCS_WAKEUP_FRAME_0 0x01000000 377 #define PMCS_LINK_FAIL 0x00040000 378 #define PMCS_LINK_RISING 0x00020000 379 #define PMCS_MAGIC_FRAME 0x00010000 380 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 381 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 382 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 383 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 384 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 385 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 386 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 387 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 388 #define PMCS_LINK_FAIL_ENB 0x00000004 389 #define PMCS_LINK_RISING_ENB 0x00000002 390 #define PMCS_MAGIC_FRAME_ENB 0x00000001 391 #define PMCS_WOL_ENB_MASK 0x0000FFFF 392 393 /* Giga PHY & EEPROM registers. */ 394 #define JME_PHY_EEPROM_BASE_ADDR 0x0400 395 396 #define JME_GIGAR0LO 0x0400 397 #define JME_GIGAR0HI 0x0404 398 #define JME_GIGARALO 0x0408 399 #define JME_GIGARAHI 0x040C 400 #define JME_GIGARBLO 0x0410 401 #define JME_GIGARBHI 0x0414 402 #define JME_GIGARCLO 0x0418 403 #define JME_GIGARCHI 0x041C 404 #define JME_GIGARDLO 0x0420 405 #define JME_GIGARDHI 0x0424 406 407 /* BIST status and control. */ 408 #define JME_GIGACSR 0x0428 409 #define GIGACSR_STATUS 0x40000000 410 #define GIGACSR_CTRL_MASK 0x30000000 411 #define GIGACSR_CTRL_DEFAULT 0x30000000 412 #define GIGACSR_TX_CLK_MASK 0x0F000000 413 #define GIGACSR_RX_CLK_MASK 0x00F00000 414 #define GIGACSR_TX_CLK_INV 0x00080000 415 #define GIGACSR_RX_CLK_INV 0x00040000 416 #define GIGACSR_PHY_RST 0x00010000 417 #define GIGACSR_IRQ_N_O 0x00001000 418 #define GIGACSR_BIST_OK 0x00000200 419 #define GIGACSR_BIST_DONE 0x00000100 420 #define GIGACSR_BIST_LED_ENB 0x00000010 421 #define GIGACSR_BIST_MASK 0x00000003 422 423 /* PHY Link Status. */ 424 #define JME_LNKSTS 0x0430 425 #define LINKSTS_SPEED_10 0x00000000 426 #define LINKSTS_SPEED_100 0x00004000 427 #define LINKSTS_SPEED_1000 0x00008000 428 #define LINKSTS_FULL_DUPLEX 0x00002000 429 #define LINKSTS_PAGE_RCVD 0x00001000 430 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 431 #define LINKSTS_UP 0x00000400 432 #define LINKSTS_ANEG_COMP 0x00000200 433 #define LINKSTS_MDI_CROSSOVR 0x00000040 434 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 435 #define LINKSTS_LPAR_PAUSE 0x00000001 436 437 /* SMB control and status. */ 438 #define JME_SMBCSR 0x0440 439 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 440 #define SMBCSR_WR_DATA_NACK 0x00040000 441 #define SMBCSR_CMD_NACK 0x00020000 442 #define SMBCSR_RELOAD 0x00010000 443 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 444 #define SMBCSR_SCL_STAT 0x00000080 445 #define SMBCSR_SDA_STAT 0x00000040 446 #define SMBCSR_EEPROM_PRESENT 0x00000020 447 #define SMBCSR_INIT_LD_DONE 0x00000010 448 #define SMBCSR_HW_BUSY_MASK 0x0000000F 449 #define SMBCSR_HW_IDLE 0x00000000 450 451 /* SMB interface. */ 452 #define JME_SMBINTF 0x0444 453 #define SMBINTF_RD_DATA_MASK 0xFF000000 454 #define SMBINTF_RD_DATA_SHIFT 24 455 #define SMBINTF_WR_DATA_MASK 0x00FF0000 456 #define SMBINTF_WR_DATA_SHIFT 16 457 #define SMBINTF_ADDR_MASK 0x0000FF00 458 #define SMBINTF_ADDR_SHIFT 8 459 #define SMBINTF_RD 0x00000020 460 #define SMBINTF_WR 0x00000000 461 #define SMBINTF_CMD_TRIGGER 0x00000010 462 #define SMBINTF_BUSY 0x00000010 463 #define SMBINTF_FAST_MODE 0x00000008 464 #define SMBINTF_GPIO_SCL 0x00000004 465 #define SMBINTF_GPIO_SDA 0x00000002 466 #define SMBINTF_GPIO_ENB 0x00000001 467 468 #define JME_EEPROM_SIG0 0x55 469 #define JME_EEPROM_SIG1 0xAA 470 #define JME_EEPROM_DESC_BYTES 3 471 #define JME_EEPROM_DESC_END 0x80 472 #define JME_EEPROM_FUNC_MASK 0x70 473 #define JME_EEPROM_FUNC_SHIFT 4 474 #define JME_EEPROM_PAGE_MASK 0x0F 475 #define JME_EEPROM_PAGE_SHIFT 0 476 477 #define JME_EEPROM_FUNC0 0 478 /* PCI configuration space. */ 479 #define JME_EEPROM_PAGE_BAR0 0 480 /* 128 bytes I/O window. */ 481 #define JME_EEPROM_PAGE_BAR1 1 482 /* 256 bytes I/O window. */ 483 #define JME_EEPROM_PAGE_BAR2 2 484 485 #define JME_EEPROM_END 0xFF 486 487 #define JME_EEPROM_MKDESC(f, p) \ 488 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 489 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 490 491 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 492 #define JME_EEPINTF 0x0448 493 #define EEPINTF_DATA_MASK 0xFFFF0000 494 #define EEPINTF_DATA_SHIFT 16 495 #define EEPINTF_ADDR_MASK 0x0000FC00 496 #define EEPINTF_ADDR_SHIFT 10 497 #define EEPRINTF_OP_MASK 0x00000300 498 #define EEPINTF_OP_EXECUTE 0x00000080 499 #define EEPINTF_DATA_OUT 0x00000008 500 #define EEPINTF_DATA_IN 0x00000004 501 #define EEPINTF_CLK 0x00000002 502 #define EEPINTF_SEL 0x00000001 503 504 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 505 #define JME_EEPCSR 0x044C 506 #define EEPCSR_EEPROM_RELOAD 0x00000002 507 #define EEPCSR_EEPROM_PRESENT 0x00000001 508 509 /* Misc registers. */ 510 #define JME_MISC_BASE_ADDR 0x800 511 512 /* Timer control and status. */ 513 #define JME_TMCSR 0x0800 514 #define TMCSR_SW_INTR 0x80000000 515 #define TMCSR_TIMER_INTR 0x10000000 516 #define TMCSR_TIMER_ENB 0x01000000 517 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 518 519 /* GPIO control and status. */ 520 #define JME_GPIO 0x0804 521 #define GPIO_4_SPI_IN 0x80000000 522 #define GPIO_3_SPI_IN 0x40000000 523 #define GPIO_4_SPI_OUT 0x20000000 524 #define GPIO_4_SPI_OUT_ENB 0x10000000 525 #define GPIO_3_SPI_OUT 0x08000000 526 #define GPIO_3_SPI_OUT_ENB 0x04000000 527 #define GPIO_3_4_LED 0x00000000 528 #define GPIO_3_4_GPIO 0x02000000 529 #define GPIO_2_CLKREQN_IN 0x00100000 530 #define GPIO_2_CLKREQN_OUT 0x00040000 531 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 532 #define GPIO_1_LED42_IN 0x00001000 533 #define GPIO_1_LED42_OUT 0x00000400 534 #define GPIO_1_LED42_OUT_ENB 0x00000200 535 #define GPIO_1_LED42_ENB 0x00000100 536 #define GPIO_0_SDA_IN 0x00000010 537 #define GPIO_0_SDA_OUT 0x00000004 538 #define GPIO_0_SDA_OUT_ENB 0x00000002 539 #define GPIO_0_SDA_ENB 0x00000001 540 541 /* General purpose register 0. */ 542 #define JME_GPREG0 0x0808 543 #define GPREG0_SH_POST_DW7_DIS 0x80000000 544 #define GPREG0_SH_POST_DW6_DIS 0x40000000 545 #define GPREG0_SH_POST_DW5_DIS 0x20000000 546 #define GPREG0_SH_POST_DW4_DIS 0x10000000 547 #define GPREG0_SH_POST_DW3_DIS 0x08000000 548 #define GPREG0_SH_POST_DW2_DIS 0x04000000 549 #define GPREG0_SH_POST_DW1_DIS 0x02000000 550 #define GPREG0_SH_POST_DW0_DIS 0x01000000 551 #define GPREG0_DMA_RD_REQ_8 0x00000000 552 #define GPREG0_DMA_RD_REQ_6 0x00100000 553 #define GPREG0_DMA_RD_REQ_5 0x00200000 554 #define GPREG0_DMA_RD_REQ_4 0x00300000 555 #define GPREG0_POST_DW0_ENB 0x00040000 556 #define GPREG0_PCC_CLR_DIS 0x00020000 557 #define GPREG0_FORCE_SCL_OUT 0x00010000 558 #define GPREG0_DL_RSTB_DIS 0x00008000 559 #define GPREG0_STICKY_RESET 0x00004000 560 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 561 #define GPREG0_LINK_CHG_POLL 0x00001000 562 #define GPREG0_LINK_CHG_DIRECT 0x00000000 563 #define GPREG0_MSI_GEN_SEL 0x00000800 564 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 565 #define GPREG0_PCC_UNIT_16US 0x00000000 566 #define GPREG0_PCC_UNIT_256US 0x00000100 567 #define GPREG0_PCC_UNIT_US 0x00000200 568 #define GPREG0_PCC_UNIT_MS 0x00000300 569 #define GPREG0_PCC_UNIT_MASK 0x00000300 570 #define GPREG0_INTR_EVENT_ENB 0x00000080 571 #define GPREG0_PME_ENB 0x00000020 572 #define GPREG0_PHY_ADDR_MASK 0x0000001F 573 #define GPREG0_PHY_ADDR_SHIFT 0 574 #define GPREG0_PHY_ADDR 1 575 576 /* General purpose register 1. reserved for future use. */ 577 #define JME_GPREG1 0x080C 578 579 /* MSIX entry number of interrupt source. */ 580 #define JME_MSINUM_BASE 0x0810 581 #define JME_MSINUM_END 0x081F 582 #define MSINUM_MASK 0x7FFFFFFF 583 #define MSINUM_ENTRY_MASK 7 584 #define MSINUM_REG_INDEX(x) ((x) / 8) 585 #define MSINUM_INTR_SOURCE(x, y) \ 586 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 587 #define MSINUM_NUM_INTR_SOURCE 32 588 589 /* Interrupt event status. */ 590 #define JME_INTR_STATUS 0x0820 591 #define INTR_SW 0x80000000 592 #define INTR_TIMER 0x40000000 593 #define INTR_LINKCHG 0x20000000 594 #define INTR_PAUSE 0x10000000 595 #define INTR_MAGIC_PKT 0x08000000 596 #define INTR_WAKEUP_PKT 0x04000000 597 #define INTR_RXQ0_COAL_TO 0x02000000 598 #define INTR_RXQ1_COAL_TO 0x01000000 599 #define INTR_RXQ2_COAL_TO 0x00800000 600 #define INTR_RXQ3_COAL_TO 0x00400000 601 #define INTR_TXQ_COAL_TO 0x00200000 602 #define INTR_RXQ0_COAL 0x00100000 603 #define INTR_RXQ1_COAL 0x00080000 604 #define INTR_RXQ2_COAL 0x00040000 605 #define INTR_RXQ3_COAL 0x00020000 606 #define INTR_TXQ_COAL 0x00010000 607 #define INTR_RXQ3_DESC_EMPTY 0x00008000 608 #define INTR_RXQ2_DESC_EMPTY 0x00004000 609 #define INTR_RXQ1_DESC_EMPTY 0x00002000 610 #define INTR_RXQ0_DESC_EMPTY 0x00001000 611 #define INTR_RXQ3_COMP 0x00000800 612 #define INTR_RXQ2_COMP 0x00000400 613 #define INTR_RXQ1_COMP 0x00000200 614 #define INTR_RXQ0_COMP 0x00000100 615 #define INTR_TXQ7_COMP 0x00000080 616 #define INTR_TXQ6_COMP 0x00000040 617 #define INTR_TXQ5_COMP 0x00000020 618 #define INTR_TXQ4_COMP 0x00000010 619 #define INTR_TXQ3_COMP 0x00000008 620 #define INTR_TXQ2_COMP 0x00000004 621 #define INTR_TXQ1_COMP 0x00000002 622 #define INTR_TXQ0_COMP 0x00000001 623 624 #define INTR_RXQ_COAL_TO \ 625 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 626 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 627 628 #define INTR_RXQ_COAL \ 629 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 630 INTR_RXQ3_COAL) 631 632 #define INTR_RXQ_COMP \ 633 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 634 INTR_RXQ3_COMP) 635 636 #define INTR_RXQ_DESC_EMPTY \ 637 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 638 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 639 640 #define INTR_RXQ_COMP \ 641 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 642 INTR_RXQ3_COMP) 643 644 #define INTR_TXQ_COMP \ 645 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 646 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 647 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 648 649 #define JME_INTRS \ 650 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 651 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 652 653 #define N_INTR_SW 31 654 #define N_INTR_TIMER 30 655 #define N_INTR_LINKCHG 29 656 #define N_INTR_PAUSE 28 657 #define N_INTR_MAGIC_PKT 27 658 #define N_INTR_WAKEUP_PKT 26 659 #define N_INTR_RXQ0_COAL_TO 25 660 #define N_INTR_RXQ1_COAL_TO 24 661 #define N_INTR_RXQ2_COAL_TO 23 662 #define N_INTR_RXQ3_COAL_TO 22 663 #define N_INTR_TXQ_COAL_TO 21 664 #define N_INTR_RXQ0_COAL 20 665 #define N_INTR_RXQ1_COAL 19 666 #define N_INTR_RXQ2_COAL 18 667 #define N_INTR_RXQ3_COAL 17 668 #define N_INTR_TXQ_COAL 16 669 #define N_INTR_RXQ3_DESC_EMPTY 15 670 #define N_INTR_RXQ2_DESC_EMPTY 14 671 #define N_INTR_RXQ1_DESC_EMPTY 13 672 #define N_INTR_RXQ0_DESC_EMPTY 12 673 #define N_INTR_RXQ3_COMP 11 674 #define N_INTR_RXQ2_COMP 10 675 #define N_INTR_RXQ1_COMP 9 676 #define N_INTR_RXQ0_COMP 8 677 #define N_INTR_TXQ7_COMP 7 678 #define N_INTR_TXQ6_COMP 6 679 #define N_INTR_TXQ5_COMP 5 680 #define N_INTR_TXQ4_COMP 4 681 #define N_INTR_TXQ3_COMP 3 682 #define N_INTR_TXQ2_COMP 2 683 #define N_INTR_TXQ1_COMP 1 684 #define N_INTR_TXQ0_COMP 0 685 686 /* Interrupt request status. */ 687 #define JME_INTR_REQ_STATUS 0x0824 688 689 /* Interrupt enable - setting port. */ 690 #define JME_INTR_MASK_SET 0x0828 691 692 /* Interrupt enable - clearing port. */ 693 #define JME_INTR_MASK_CLR 0x082C 694 695 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 696 #define JME_PCCRX0 0x0830 697 #define JME_PCCRX1 0x0834 698 #define JME_PCCRX2 0x0838 699 #define JME_PCCRX3 0x083C 700 #define PCCRX_COAL_TO_MASK 0xFFFF0000 701 #define PCCRX_COAL_TO_SHIFT 16 702 #define PCCRX_COAL_PKT_MASK 0x0000FF00 703 #define PCCRX_COAL_PKT_SHIFT 8 704 705 #define PCCRX_COAL_TO_MIN 1 706 #define PCCRX_COAL_TO_DEFAULT 100 707 #define PCCRX_COAL_TO_MAX 65535 708 709 #define PCCRX_COAL_PKT_MIN 1 710 #define PCCRX_COAL_PKT_DEFAULT 2 711 #define PCCRX_COAL_PKT_MAX 255 712 713 /* Packet completion coalescing control of Tx queue. */ 714 #define JME_PCCTX 0x0840 715 #define PCCTX_COAL_TO_MASK 0xFFFF0000 716 #define PCCTX_COAL_TO_SHIFT 16 717 #define PCCTX_COAL_PKT_MASK 0x0000FF00 718 #define PCCTX_COAL_PKT_SHIFT 8 719 #define PCCTX_COAL_TXQ7 0x00000080 720 #define PCCTX_COAL_TXQ6 0x00000040 721 #define PCCTX_COAL_TXQ5 0x00000020 722 #define PCCTX_COAL_TXQ4 0x00000010 723 #define PCCTX_COAL_TXQ3 0x00000008 724 #define PCCTX_COAL_TXQ2 0x00000004 725 #define PCCTX_COAL_TXQ1 0x00000002 726 #define PCCTX_COAL_TXQ0 0x00000001 727 728 #define PCCTX_COAL_TO_MIN 1 729 #define PCCTX_COAL_TO_DEFAULT 100 730 #define PCCTX_COAL_TO_MAX 65535 731 732 #define PCCTX_COAL_PKT_MIN 1 733 #define PCCTX_COAL_PKT_DEFAULT 8 734 #define PCCTX_COAL_PKT_MAX 255 735 736 /* Chip mode and FPGA version. */ 737 #define JME_CHIPMODE 0x0844 738 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 739 #define CHIPMODE_FPGA_REV_SHIFT 16 740 #define CHIPMODE_NOT_FPGA 0 741 #define CHIPMODE_REV_MASK 0x0000FF00 742 #define CHIPMODE_REV_SHIFT 8 743 #define CHIPMODE_MODE_48P 0x0000000C 744 #define CHIPMODE_MODE_64P 0x00000004 745 #define CHIPMODE_MODE_128P_MAC 0x00000003 746 #define CHIPMODE_MODE_128P_DBG 0x00000002 747 #define CHIPMODE_MODE_128P_PHY 0x00000000 748 749 /* Shadow status base address high/low. */ 750 #define JME_SHBASE_ADDR_HI 0x0848 751 #define JME_SHBASE_ADDR_LO 0x084C 752 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 753 #define SHBASE_POST_FORCE 0x00000002 754 #define SHBASE_POST_ENB 0x00000001 755 756 /* Timer 1 and 2. */ 757 #define JME_TIMER1 0x0870 758 #define JME_TIMER2 0x0874 759 #define TIMER_ENB 0x01000000 760 #define TIMER_CNT_MASK 0x00FFFFFF 761 #define TIMER_CNT_SHIFT 0 762 #define TIMER_UNIT 1024 /* 1024us */ 763 764 /* Aggresive power mode control. */ 765 #define JME_APMC 0x087C 766 #define APMC_PCIE_SDOWN_STAT 0x80000000 767 #define APMC_PCIE_SDOWN_ENB 0x40000000 768 #define APMC_PSEUDO_HOT_PLUG 0x20000000 769 #define APMC_EXT_PLUGIN_ENB 0x04000000 770 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 771 #define APMC_DIS_SRAM 0x00000004 772 #define APMC_DIS_CLKPM 0x00000002 773 #define APMC_DIS_CLKTX 0x00000001 774 775 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 776 #define JME_PCCSRX_BASE 0x0880 777 #define JME_PCCSRX_END 0x088F 778 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 779 #define PCCSRX_TO_MASK 0xFFFF0000 780 #define PCCSRX_TO_SHIFT 16 781 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 782 #define PCCSRX_PKT_CNT_SHIFT 8 783 784 /* Packet completion coalesing status of Tx queue. */ 785 #define JME_PCCSTX 0x0890 786 #define PCCSTX_TO_MASK 0xFFFF0000 787 #define PCCSTX_TO_SHIFT 16 788 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 789 #define PCCSTX_PKT_CNT_SHIFT 8 790 791 /* Tx queues empty indicator. */ 792 #define JME_TXQEMPTY 0x0894 793 #define TXQEMPTY_TXQ7 0x00000080 794 #define TXQEMPTY_TXQ6 0x00000040 795 #define TXQEMPTY_TXQ5 0x00000020 796 #define TXQEMPTY_TXQ4 0x00000010 797 #define TXQEMPTY_TXQ3 0x00000008 798 #define TXQEMPTY_TXQ2 0x00000004 799 #define TXQEMPTY_TXQ1 0x00000002 800 #define TXQEMPTY_TXQ0 0x00000001 801 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 802 803 /* RSS control registers. */ 804 #define JME_RSS_BASE 0x0C00 805 806 #define JME_RSSC 0x0C00 807 #define RSSC_HASH_LEN_MASK 0x0000E000 808 #define RSSC_HASH_64_ENTRY 0x0000A000 809 #define RSSC_HASH_128_ENTRY 0x0000E000 810 #define RSSC_HASH_NONE 0x00001000 811 #define RSSC_HASH_IPV6 0x00000800 812 #define RSSC_HASH_IPV4 0x00000400 813 #define RSSC_HASH_IPV6_TCP 0x00000200 814 #define RSSC_HASH_IPV4_TCP 0x00000100 815 #define RSSC_NCPU_MASK 0x000000F8 816 #define RSSC_NCPU_SHIFT 3 817 #define RSSC_DIS_RSS 0x00000000 818 #define RSSC_2RXQ_ENB 0x00000001 819 #define RSSS_4RXQ_ENB 0x00000002 820 821 /* CPU vector. */ 822 #define JME_RSSCPU 0x0C04 823 #define RSSCPU_N_SEL(x) ((1 << (x)) 824 825 /* RSS Hash value. */ 826 #define JME_RSSHASH 0x0C10 827 828 #define JME_RSSHASH_STAT 0x0C14 829 830 #define JME_RSS_RDATA0 0x0C18 831 832 #define JME_RSS_RDATA1 0x0C1C 833 834 /* RSS secret key. */ 835 #define JME_RSSKEY_BASE 0x0C40 836 #define JME_RSSKEY_LAST 0x0C64 837 #define JME_RSSKEY_END 0x0C67 838 #define HASHKEY_NBYTES 40 839 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 840 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 841 842 /* RSS indirection table entries. */ 843 #define JME_RSSTBL_BASE 0x0C80 844 #define JME_RSSTBL_END 0x0CFF 845 #define RSSTBL_NENTRY 128 846 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 847 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 848 849 /* MSI-X table. */ 850 #define JME_MSIX_BASE_ADDR 0x2000 851 852 #define JME_MSIX_BASE 0x2000 853 #define JME_MSIX_END 0x207F 854 #define JME_MSIX_NENTRY 8 855 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 856 #define MSIX_ADDR_HI_OFF 0x00 857 #define MSIX_ADDR_LO_OFF 0x04 858 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 859 #define MSIX_DATA_OFF 0x08 860 #define MSIX_VECTOR_OFF 0x0C 861 #define MSIX_VECTOR_RSVD 0x80000000 862 #define MSIX_VECTOR_DIS 0x00000001 863 864 /* MSI-X PBA. */ 865 #define JME_MSIX_PBA_BASE_ADDR 0x3000 866 867 #define JME_MSIX_PBA 0x3000 868 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 869 #define MSIX_PBA_RSVD_SHIFT 8 870 #define MSIX_PBA_PEND_MASK 0x000000FF 871 #define MSIX_PBA_PEND_SHIFT 0 872 #define MSIX_PBA_PEND_ENTRY7 0x00000080 873 #define MSIX_PBA_PEND_ENTRY6 0x00000040 874 #define MSIX_PBA_PEND_ENTRY5 0x00000020 875 #define MSIX_PBA_PEND_ENTRY4 0x00000010 876 #define MSIX_PBA_PEND_ENTRY3 0x00000008 877 #define MSIX_PBA_PEND_ENTRY2 0x00000004 878 #define MSIX_PBA_PEND_ENTRY1 0x00000002 879 #define MSIX_PBA_PEND_ENTRY0 0x00000001 880 881 #define JME_PHY_OUI 0x001B8C 882 #define JME_PHY_MODEL 0x21 883 #define JME_PHY_REV 0x01 884 #define JME_PHY_ADDR 1 885 886 /* JMC250 shadow status block. */ 887 struct jme_ssb { 888 uint32_t dw0; 889 uint32_t dw1; 890 uint32_t dw2; 891 uint32_t dw3; 892 uint32_t dw4; 893 uint32_t dw5; 894 uint32_t dw6; 895 uint32_t dw7; 896 }; 897 898 /* JMC250 descriptor structures. */ 899 struct jme_desc { 900 uint32_t flags; 901 uint32_t buflen; 902 uint32_t addr_hi; 903 uint32_t addr_lo; 904 }; 905 906 #define JME_TD_OWN 0x80000000 907 #define JME_TD_INTR 0x40000000 908 #define JME_TD_64BIT 0x20000000 909 #define JME_TD_TCPCSUM 0x10000000 910 #define JME_TD_UDPCSUM 0x08000000 911 #define JME_TD_IPCSUM 0x04000000 912 #define JME_TD_TSO 0x02000000 913 #define JME_TD_VLAN_TAG 0x01000000 914 #define JME_TD_VLAN_MASK 0x0000FFFF 915 916 #define JME_TD_MSS_MASK 0xFFFC0000 917 #define JME_TD_MSS_SHIFT 18 918 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 919 #define JME_TD_BUF_LEN_SHIFT 0 920 921 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 922 #define JME_TD_FRAME_LEN_SHIFT 0 923 924 /* 925 * Only the first Tx descriptor of a packet is updated 926 * after packet transmission. 927 */ 928 #define JME_TD_TMOUT 0x20000000 929 #define JME_TD_RETRY_EXP 0x10000000 930 #define JME_TD_COLLISION 0x08000000 931 #define JME_TD_UNDERRUN 0x04000000 932 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 933 #define JME_TD_EHDR_SIZE_SHIFT 0 934 935 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 936 #define JME_TD_SEG_CNT_SHIFT 16 937 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 938 #define JME_TD_RETRY_CNT_SHIFT 0 939 940 #define JME_RD_OWN 0x80000000 941 #define JME_RD_INTR 0x40000000 942 #define JME_RD_64BIT 0x20000000 943 944 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 945 #define JME_RD_BUF_LEN_SHIFT 0 946 947 /* 948 * Only the first Rx descriptor of a packet is updated 949 * after packet reception. 950 */ 951 #define JME_RD_MORE_FRAG 0x20000000 952 #define JME_RD_TCP 0x10000000 953 #define JME_RD_UDP 0x08000000 954 #define JME_RD_IPCSUM 0x04000000 955 #define JME_RD_TCPCSUM 0x02000000 956 #define JME_RD_UDPCSUM 0x01000000 957 #define JME_RD_VLAN_TAG 0x00800000 958 #define JME_RD_IPV4 0x00400000 959 #define JME_RD_IPV6 0x00200000 960 #define JME_RD_PAUSE 0x00100000 961 #define JME_RD_MAGIC 0x00080000 962 #define JME_RD_WAKEUP 0x00040000 963 #define JME_RD_BCAST 0x00030000 964 #define JME_RD_MCAST 0x00020000 965 #define JME_RD_UCAST 0x00010000 966 #define JME_RD_VLAN_MASK 0x0000FFFF 967 #define JME_RD_VLAN_SHIFT 0 968 969 #define JME_RD_VALID 0x80000000 970 #define JME_RD_CNT_MASK 0x7F000000 971 #define JME_RD_CNT_SHIFT 24 972 #define JME_RD_GIANT 0x00800000 973 #define JME_RD_GMII_ERR 0x00400000 974 #define JME_RD_NBL_RCVD 0x00200000 975 #define JME_RD_COLL 0x00100000 976 #define JME_RD_ABORT 0x00080000 977 #define JME_RD_RUNT 0x00040000 978 #define JME_RD_FIFO_OVRN 0x00020000 979 #define JME_RD_CRC_ERR 0x00010000 980 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 981 982 #define JME_RX_ERR_STAT \ 983 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 984 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 985 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 986 987 #define JME_RD_ERR_MASK 0x00FF0000 988 #define JME_RD_ERR_SHIFT 16 989 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 990 #define JME_RX_ERR_BITS "\20" \ 991 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 992 "\5COLL\6NBLRCVD\7GMIIERR\10" 993 994 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 995 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 996 #define JME_RX_PAD_BYTES 10 997 998 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 999 1000 #define JME_RD_RSS_HASH_MASK 0x00003F00 1001 #define JME_RD_RSS_HASH_SHIFT 8 1002 #define JME_RD_RSS_HASH_NONE 0x00000000 1003 #define JME_RD_RSS_HASH_IPV4 0x00000100 1004 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1005 #define JME_RD_RSS_HASH_IPV6 0x00000400 1006 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1007 #define JME_RD_HASH_FN_NONE 0x00000000 1008 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1009 1010 #endif 1011