1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _IF_JMEREG_H 31 #define _IF_JMEREG_H 32 33 /* 34 * JMicron Inc. PCI vendor ID 35 */ 36 #define VENDORID_JMICRON 0x197B 37 38 /* 39 * JMC250 PCI device ID 40 */ 41 #define DEVICEID_JMC250 0x0250 42 #define DEVICEREVID_JMC250_A0 0x00 43 #define DEVICEREVID_JMC250_A2 0x11 44 45 /* 46 * JMC260 PCI device ID 47 */ 48 #define DEVICEID_JMC260 0x0260 49 #define DEVICEREVID_JMC260_A0 0x00 50 51 #define DEVICEID_JMC2XX_MASK 0x0FF0 52 53 /* JMC250 PCI configuration register. */ 54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 55 56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 57 58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 59 60 #define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 61 62 #define JME_PCI_EROM 0x30 63 64 #define JME_PCI_DBG 0x9C 65 66 #define JME_PCI_SPI 0xB0 67 68 #define SPI_ENB 0x00000010 69 #define SPI_SO_STATUS 0x00000008 70 #define SPI_SI_CTRL 0x00000004 71 #define SPI_SCK_CTRL 0x00000002 72 #define SPI_CS_N_CTRL 0x00000001 73 74 #define JME_PCI_PHYCFG0 0xC0 75 76 #define JME_PCI_PHYCFG1 0xC4 77 78 #define JME_PCI_PHYCFG2 0xC8 79 80 #define JME_PCI_PHYCFG3 0xCC 81 82 #define JME_PCI_PIPECTL1 0xD0 83 84 #define JME_PCI_PIPECTL2 0xD4 85 86 /* PCIe link error/status. */ 87 #define JME_PCI_LES 0xD8 88 89 /* propeietary register 0. */ 90 #define JME_PCI_PE0 0xE0 91 #define PE0_SPI_EXIST 0x00200000 92 #define PE0_PME_D0 0x00100000 93 #define PE0_PME_D3H 0x00080000 94 #define PE0_PME_SPI_PAD 0x00040000 95 #define PE0_MASK_ASPM 0x00020000 96 #define PE0_EEPROM_RW_DIS 0x00008000 97 #define PE0_PCI_INTA 0x00001000 98 #define PE0_PCI_INTB 0x00002000 99 #define PE0_PCI_INTC 0x00003000 100 #define PE0_PCI_INTD 0x00004000 101 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 102 #define PE0_MSIX_SIZE_8 0x00000700 103 #define PE0_MSIX_SIZE_7 0x00000600 104 #define PE0_MSIX_SIZE_6 0x00000500 105 #define PE0_MSIX_SIZE_5 0x00000400 106 #define PE0_MSIX_SIZE_4 0x00000300 107 #define PE0_MSIX_SIZE_3 0x00000200 108 #define PE0_MSIX_SIZE_2 0x00000100 109 #define PE0_MSIX_SIZE_1 0x00000000 110 #define PE0_MSIX_SIZE_DEF 0x00000700 111 #define PE0_MSIX_CAP_DIS 0x00000080 112 #define PE0_MSI_PVMC_ENB 0x00000040 113 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 114 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 115 #define PE0_PM_AUXC_MASK 0x00000007 116 #define PE0_PM_AUXC_DEF 0x00000007 117 118 #define JME_PCI_PE1 0xE4 119 120 #define JME_PCI_PHYTEST 0xF8 121 122 #define JME_PCI_GPR 0xFC 123 124 /* 125 * JMC Register Map. 126 * ----------------------------------------------------------------------- 127 * Register Size IO space Memory space 128 * ----------------------------------------------------------------------- 129 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 130 * BAR1 + 0x7F BAR0 + 0x7F 131 * ----------------------------------------------------------------------- 132 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 133 * BAR2 + 0x7F BAR0 + 0x47F 134 * ----------------------------------------------------------------------- 135 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 136 * BAR2 + 0x7F BAR0 + 0x87F 137 * ----------------------------------------------------------------------- 138 * To simplify register access fuctions and to get better performance 139 * this driver doesn't support IO space access. It could be implemented 140 * as a function which selects appropriate BARs to access requested 141 * register. 142 */ 143 144 /* Tx control and status. */ 145 #define JME_TXCSR 0x0000 146 #define TXCSR_QWEIGHT_MASK 0x0F000000 147 #define TXCSR_QWEIGHT_SHIFT 24 148 #define TXCSR_TXQ_SEL_MASK 0x00070000 149 #define TXCSR_TXQ_SEL_SHIFT 16 150 #define TXCSR_TXQ_START 0x00000001 151 #define TXCSR_TXQ_START_SHIFT 8 152 #define TXCSR_FIFO_THRESH_4QW 0x00000000 153 #define TXCSR_FIFO_THRESH_8QW 0x00000040 154 #define TXCSR_FIFO_THRESH_12QW 0x00000080 155 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 156 #define TXCSR_DMA_SIZE_64 0x00000000 157 #define TXCSR_DMA_SIZE_128 0x00000010 158 #define TXCSR_DMA_SIZE_256 0x00000020 159 #define TXCSR_DMA_SIZE_512 0x00000030 160 #define TXCSR_DMA_BURST 0x00000004 161 #define TXCSR_TX_SUSPEND 0x00000002 162 #define TXCSR_TX_ENB 0x00000001 163 #define TXCSR_TXQ0 0 164 #define TXCSR_TXQ1 1 165 #define TXCSR_TXQ2 2 166 #define TXCSR_TXQ3 3 167 #define TXCSR_TXQ4 4 168 #define TXCSR_TXQ5 5 169 #define TXCSR_TXQ6 6 170 #define TXCSR_TXQ7 7 171 #define TXCSR_TXQ_WEIGHT(x) \ 172 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 173 #define TXCSR_TXQ_WEIGHT_MIN 0 174 #define TXCSR_TXQ_WEIGHT_MAX 15 175 #define TXCSR_TXQ_N_SEL(x) \ 176 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 177 #define TXCSR_TXQ_N_START(x) \ 178 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 179 180 /* Tx queue descriptor base address. 16bytes alignment required. */ 181 #define JME_TXDBA_LO 0x0004 182 #define JME_TXDBA_HI 0x0008 183 184 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 185 #define JME_TXQDC 0x000C 186 #define TXQDC_MASK 0x0000007F0 187 188 /* Tx queue next descriptor address. */ 189 #define JME_TXNDA 0x0010 190 #define TXNDA_ADDR_MASK 0xFFFFFFF0 191 #define TXNDA_DESC_EMPTY 0x00000008 192 #define TXNDA_DESC_VALID 0x00000004 193 #define TXNDA_DESC_WAIT 0x00000002 194 #define TXNDA_DESC_FETCH 0x00000001 195 196 /* Tx MAC control ans status. */ 197 #define JME_TXMAC 0x0014 198 #define TXMAC_IFG2_MASK 0xC0000000 199 #define TXMAC_IFG2_DEFAULT 0x40000000 200 #define TXMAC_IFG1_MASK 0x30000000 201 #define TXMAC_IFG1_DEFAULT 0x20000000 202 #define TXMAC_PAUSE_CNT_MASK 0x00FF0000 203 #define TXMAC_THRESH_1_PKT 0x00000300 204 #define TXMAC_THRESH_1_2_PKT 0x00000200 205 #define TXMAC_THRESH_1_4_PKT 0x00000100 206 #define TXMAC_THRESH_1_8_PKT 0x00000000 207 #define TXMAC_FRAME_BURST 0x00000080 208 #define TXMAC_CARRIER_EXT 0x00000040 209 #define TXMAC_IFG_ENB 0x00000020 210 #define TXMAC_BACKOFF 0x00000010 211 #define TXMAC_CARRIER_SENSE 0x00000008 212 #define TXMAC_COLL_ENB 0x00000004 213 #define TXMAC_CRC_ENB 0x00000002 214 #define TXMAC_PAD_ENB 0x00000001 215 216 /* Tx pause frame control. */ 217 #define JME_TXPFC 0x0018 218 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 219 #define TXPFC_VLAN_TAG_SHIFT 16 220 #define TXPFC_VLAN_ENB 0x00008000 221 #define TXPFC_PAUSE_ENB 0x00000001 222 223 /* Tx timer/retry at half duplex. */ 224 #define JME_TXTRHD 0x001C 225 #define TXTRHD_RT_PERIOD_ENB 0x80000000 226 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 227 #define TXTRHD_RT_PERIOD_SHIFT 8 228 #define TXTRHD_RT_LIMIT_ENB 0x00000080 229 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 230 #define TXTRHD_RT_LIMIT_SHIFT 0 231 #define TXTRHD_RT_PERIOD_DEFAULT 8192 232 #define TXTRHD_RT_LIMIT_DEFAULT 8 233 234 /* Rx control & status. */ 235 #define JME_RXCSR 0x0020 236 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 237 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 238 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 239 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 240 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 241 #define RXCSR_FIFO_THRESH_16QW 0x00000000 242 #define RXCSR_FIFO_THRESH_32QW 0x04000000 243 #define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */ 244 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */ 245 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 246 #define RXCSR_DMA_SIZE_16 0x00000000 247 #define RXCSR_DMA_SIZE_32 0x01000000 248 #define RXCSR_DMA_SIZE_64 0x02000000 249 #define RXCSR_DMA_SIZE_128 0x03000000 250 #define RXCSR_RXQ_SEL_MASK 0x00030000 251 #define RXCSR_RXQ_SEL_SHIFT 16 252 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 253 #define RXCSR_DESC_RT_GAP_SHIFT 12 254 #define RXCSR_DESC_RT_GAP_256 0x00000000 255 #define RXCSR_DESC_RT_GAP_512 0x00001000 256 #define RXCSR_DESC_RT_GAP_1024 0x00002000 257 #define RXCSR_DESC_RT_GAP_2048 0x00003000 258 #define RXCSR_DESC_RT_GAP_4096 0x00004000 259 #define RXCSR_DESC_RT_GAP_8192 0x00005000 260 #define RXCSR_DESC_RT_GAP_16384 0x00006000 261 #define RXCSR_DESC_RT_GAP_32768 0x00007000 262 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 263 #define RXCSR_DESC_RT_CNT_SHIFT 8 264 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 265 #define RXCSR_PASS_MAGIC_PKT 0x00000020 266 #define RXCSR_PASS_RUNT_PKT 0x00000010 267 #define RXCSR_PASS_BAD_PKT 0x00000008 268 #define RXCSR_RXQ_START 0x00000004 269 #define RXCSR_RX_SUSPEND 0x00000002 270 #define RXCSR_RX_ENB 0x00000001 271 272 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 273 #define RXCSR_RXQ0 0 274 #define RXCSR_RXQ1 1 275 #define RXCSR_RXQ2 2 276 #define RXCSR_RXQ3 3 277 #define RXCSR_DESC_RT_CNT(x) \ 278 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 279 #define RXCSR_DESC_RT_CNT_DEFAULT 32 280 281 /* Rx queue descriptor base address. 16bytes alignment needed. */ 282 #define JME_RXDBA_LO 0x0024 283 #define JME_RXDBA_HI 0x0028 284 285 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 286 #define JME_RXQDC 0x002C 287 #define RXQDC_MASK 0x0000007F0 288 289 /* Rx queue next descriptor address. */ 290 #define JME_RXNDA 0x0030 291 #define RXNDA_ADDR_MASK 0xFFFFFFF0 292 #define RXNDA_DESC_EMPTY 0x00000008 293 #define RXNDA_DESC_VALID 0x00000004 294 #define RXNDA_DESC_WAIT 0x00000002 295 #define RXNDA_DESC_FETCH 0x00000001 296 297 /* Rx MAC control and status. */ 298 #define JME_RXMAC 0x0034 299 #define RXMAC_RSS_UNICAST 0x00000000 300 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 301 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 302 #define RXMAC_RSS_ALLFRAME 0x00030000 303 #define RXMAC_PROMISC 0x00000800 304 #define RXMAC_BROADCAST 0x00000400 305 #define RXMAC_MULTICAST 0x00000200 306 #define RXMAC_UNICAST 0x00000100 307 #define RXMAC_ALLMULTI 0x00000080 308 #define RXMAC_MULTICAST_FILTER 0x00000040 309 #define RXMAC_COLL_DET_ENB 0x00000020 310 #define RXMAC_FC_ENB 0x00000008 311 #define RXMAC_VLAN_ENB 0x00000004 312 #define RXMAC_PAD_10BYTES 0x00000002 313 #define RXMAC_CSUM_ENB 0x00000001 314 315 /* Rx unicast MAC address. */ 316 #define JME_PAR0 0x0038 317 #define JME_PAR1 0x003C 318 319 /* Rx multicast address hash table. */ 320 #define JME_MAR0 0x0040 321 #define JME_MAR1 0x0044 322 323 /* Wakeup frame output data port. */ 324 #define JME_WFODP 0x0048 325 326 /* Wakeup frame output interface. */ 327 #define JME_WFOI 0x004C 328 #define WFOI_MASK_0_31 0x00000000 329 #define WFOI_MASK_31_63 0x00000010 330 #define WFOI_MASK_64_95 0x00000020 331 #define WFOI_MASK_96_127 0x00000030 332 #define WFOI_MASK_SEL 0x00000008 333 #define WFOI_CRC_SEL 0x00000000 334 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 335 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 336 337 /* Station management interface. */ 338 #define JME_SMI 0x0050 339 #define SMI_DATA_MASK 0xFFFF0000 340 #define SMI_DATA_SHIFT 16 341 #define SMI_REG_ADDR_MASK 0x0000F800 342 #define SMI_REG_ADDR_SHIFT 11 343 #define SMI_PHY_ADDR_MASK 0x000007C0 344 #define SMI_PHY_ADDR_SHIFT 6 345 #define SMI_OP_WRITE 0x00000020 346 #define SMI_OP_READ 0x00000000 347 #define SMI_OP_EXECUTE 0x00000010 348 #define SMI_MDIO 0x00000008 349 #define SMI_MDOE 0x00000004 350 #define SMI_MDC 0x00000002 351 #define SMI_MDEN 0x00000001 352 #define SMI_REG_ADDR(x) \ 353 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 354 #define SMI_PHY_ADDR(x) \ 355 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 356 357 /* Global host control. */ 358 #define JME_GHC 0x0054 359 #define GHC_LOOPBACK 0x80000000 360 #define GHC_RESET 0x40000000 361 #define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */ 362 #define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */ 363 #define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */ 364 #define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */ 365 #define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */ 366 #define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 367 #define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */ 368 #define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */ 369 #define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 370 #define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */ 371 #define GHC_FULL_DUPLEX 0x00000040 372 #define GHC_SPEED_UNKNOWN 0x00000000 373 #define GHC_SPEED_10 0x00000010 374 #define GHC_SPEED_100 0x00000020 375 #define GHC_SPEED_1000 0x00000030 376 #define GHC_SPEED_MASK 0x00000030 377 #define GHC_LINK_OFF 0x00000004 378 #define GHC_LINK_ON 0x00000002 379 #define GHC_LINK_STAT_POLLING 0x00000001 380 381 /* Power management control and status. */ 382 #define JME_PMCS 0x0060 383 #define PMCS_WAKEUP_FRAME_7 0x80000000 384 #define PMCS_WAKEUP_FRAME_6 0x40000000 385 #define PMCS_WAKEUP_FRAME_5 0x20000000 386 #define PMCS_WAKEUP_FRAME_4 0x10000000 387 #define PMCS_WAKEUP_FRAME_3 0x08000000 388 #define PMCS_WAKEUP_FRAME_2 0x04000000 389 #define PMCS_WAKEUP_FRAME_1 0x02000000 390 #define PMCS_WAKEUP_FRAME_0 0x01000000 391 #define PMCS_LINK_FAIL 0x00040000 392 #define PMCS_LINK_RISING 0x00020000 393 #define PMCS_MAGIC_FRAME 0x00010000 394 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 395 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 396 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 397 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 398 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 399 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 400 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 401 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 402 #define PMCS_LINK_FAIL_ENB 0x00000004 403 #define PMCS_LINK_RISING_ENB 0x00000002 404 #define PMCS_MAGIC_FRAME_ENB 0x00000001 405 #define PMCS_WOL_ENB_MASK 0x0000FFFF 406 407 /* 408 * Statistic registers control and status. 409 * These statistics registers are valid only for JMC250/JMC260 REVFM >= 2. 410 */ 411 #define JME_STATCSR 0x0064 412 #define STATCSR_RXMPT_DIS 0x00000080 413 #define STATCSR_OFLOW_DIS 0x00000040 414 #define STATCSR_MIIRXER_DIS 0x00000020 415 #define STATCSR_CRCERR_DIS 0x00000010 416 #define STATCSR_RXBAD_DIS 0x00000008 417 #define STATCSR_RXGOOD_DIS 0x00000004 418 #define STATCSR_TXBAD_DIS 0x00000002 419 #define STATCSR_TXGOOD_DIS 0x00000001 420 421 #define JME_STAT_TXGOOD 0x0068 422 423 #define JME_STAT_RXGOOD 0x006C 424 425 #define JME_STAT_CRCMII 0x0070 426 #define STAT_RX_CRC_ERR_MASK 0xFFFF0000 427 #define STAT_RX_MII_ERR_MASK 0x0000FFFF 428 #define STAT_RX_CRC_ERR_SHIFT 16 429 #define STAT_RX_MII_ERR_SHIFT 0 430 431 #define JME_STAT_RXERR 0x0074 432 #define STAT_RXERR_OFLOW_MASK 0xFFFF0000 433 #define STAT_RXERR_MPTY_MASK 0x0000FFFF 434 #define STAT_RXERR_OFLOW_SHIFT 16 435 #define STAT_RXERR_MPTY_SHIFT 0 436 437 #define JME_STAT_RESERVED1 0x0078 438 439 #define JME_STAT_FAIL 0x007C 440 #define STAT_FAIL_RX_MASK 0xFFFF0000 441 #define STAT_FAIL_TX_MASK 0x0000FFFF 442 #define STAT_FAIL_RX_SHIFT 16 443 #define STAT_FAIL_TX_SHIFT 0 444 445 /* Giga PHY & EEPROM registers. */ 446 #define JME_PHY_EEPROM_BASE_ADDR 0x0400 447 448 #define JME_GIGAR0LO 0x0400 449 #define JME_GIGAR0HI 0x0404 450 #define JME_GIGARALO 0x0408 451 #define JME_GIGARAHI 0x040C 452 #define JME_GIGARBLO 0x0410 453 #define JME_GIGARBHI 0x0414 454 #define JME_GIGARCLO 0x0418 455 #define JME_GIGARCHI 0x041C 456 #define JME_GIGARDLO 0x0420 457 #define JME_GIGARDHI 0x0424 458 459 /* BIST status and control. */ 460 #define JME_GIGACSR 0x0428 461 #define GIGACSR_STATUS 0x40000000 462 #define GIGACSR_CTRL_MASK 0x30000000 463 #define GIGACSR_CTRL_DEFAULT 0x30000000 464 #define GIGACSR_TX_CLK_MASK 0x0F000000 465 #define GIGACSR_RX_CLK_MASK 0x00F00000 466 #define GIGACSR_TX_CLK_INV 0x00080000 467 #define GIGACSR_RX_CLK_INV 0x00040000 468 #define GIGACSR_PHY_RST 0x00010000 469 #define GIGACSR_IRQ_N_O 0x00001000 470 #define GIGACSR_BIST_OK 0x00000200 471 #define GIGACSR_BIST_DONE 0x00000100 472 #define GIGACSR_BIST_LED_ENB 0x00000010 473 #define GIGACSR_BIST_MASK 0x00000003 474 475 /* PHY Link Status. */ 476 #define JME_LNKSTS 0x0430 477 #define LINKSTS_SPEED_10 0x00000000 478 #define LINKSTS_SPEED_100 0x00004000 479 #define LINKSTS_SPEED_1000 0x00008000 480 #define LINKSTS_FULL_DUPLEX 0x00002000 481 #define LINKSTS_PAGE_RCVD 0x00001000 482 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 483 #define LINKSTS_UP 0x00000400 484 #define LINKSTS_ANEG_COMP 0x00000200 485 #define LINKSTS_MDI_CROSSOVR 0x00000040 486 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 487 #define LINKSTS_LPAR_PAUSE 0x00000001 488 489 /* SMB control and status. */ 490 #define JME_SMBCSR 0x0440 491 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 492 #define SMBCSR_WR_DATA_NACK 0x00040000 493 #define SMBCSR_CMD_NACK 0x00020000 494 #define SMBCSR_RELOAD 0x00010000 495 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 496 #define SMBCSR_SCL_STAT 0x00000080 497 #define SMBCSR_SDA_STAT 0x00000040 498 #define SMBCSR_EEPROM_PRESENT 0x00000020 499 #define SMBCSR_INIT_LD_DONE 0x00000010 500 #define SMBCSR_HW_BUSY_MASK 0x0000000F 501 #define SMBCSR_HW_IDLE 0x00000000 502 503 /* SMB interface. */ 504 #define JME_SMBINTF 0x0444 505 #define SMBINTF_RD_DATA_MASK 0xFF000000 506 #define SMBINTF_RD_DATA_SHIFT 24 507 #define SMBINTF_WR_DATA_MASK 0x00FF0000 508 #define SMBINTF_WR_DATA_SHIFT 16 509 #define SMBINTF_ADDR_MASK 0x0000FF00 510 #define SMBINTF_ADDR_SHIFT 8 511 #define SMBINTF_RD 0x00000020 512 #define SMBINTF_WR 0x00000000 513 #define SMBINTF_CMD_TRIGGER 0x00000010 514 #define SMBINTF_BUSY 0x00000010 515 #define SMBINTF_FAST_MODE 0x00000008 516 #define SMBINTF_GPIO_SCL 0x00000004 517 #define SMBINTF_GPIO_SDA 0x00000002 518 #define SMBINTF_GPIO_ENB 0x00000001 519 520 #define JME_EEPROM_SIG0 0x55 521 #define JME_EEPROM_SIG1 0xAA 522 #define JME_EEPROM_DESC_BYTES 3 523 #define JME_EEPROM_DESC_END 0x80 524 #define JME_EEPROM_FUNC_MASK 0x70 525 #define JME_EEPROM_FUNC_SHIFT 4 526 #define JME_EEPROM_PAGE_MASK 0x0F 527 #define JME_EEPROM_PAGE_SHIFT 0 528 529 #define JME_EEPROM_FUNC0 0 530 /* PCI configuration space. */ 531 #define JME_EEPROM_PAGE_BAR0 0 532 /* 128 bytes I/O window. */ 533 #define JME_EEPROM_PAGE_BAR1 1 534 /* 256 bytes I/O window. */ 535 #define JME_EEPROM_PAGE_BAR2 2 536 537 #define JME_EEPROM_END 0xFF 538 539 #define JME_EEPROM_MKDESC(f, p) \ 540 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 541 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 542 543 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 544 #define JME_EEPINTF 0x0448 545 #define EEPINTF_DATA_MASK 0xFFFF0000 546 #define EEPINTF_DATA_SHIFT 16 547 #define EEPINTF_ADDR_MASK 0x0000FC00 548 #define EEPINTF_ADDR_SHIFT 10 549 #define EEPRINTF_OP_MASK 0x00000300 550 #define EEPINTF_OP_EXECUTE 0x00000080 551 #define EEPINTF_DATA_OUT 0x00000008 552 #define EEPINTF_DATA_IN 0x00000004 553 #define EEPINTF_CLK 0x00000002 554 #define EEPINTF_SEL 0x00000001 555 556 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 557 #define JME_EEPCSR 0x044C 558 #define EEPCSR_EEPROM_RELOAD 0x00000002 559 #define EEPCSR_EEPROM_PRESENT 0x00000001 560 561 /* Misc registers. */ 562 #define JME_MISC_BASE_ADDR 0x800 563 564 /* Timer control and status. */ 565 #define JME_TMCSR 0x0800 566 #define TMCSR_SW_INTR 0x80000000 567 #define TMCSR_TIMER_INTR 0x10000000 568 #define TMCSR_TIMER_ENB 0x01000000 569 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 570 571 /* GPIO control and status. */ 572 #define JME_GPIO 0x0804 573 #define GPIO_4_SPI_IN 0x80000000 574 #define GPIO_3_SPI_IN 0x40000000 575 #define GPIO_4_SPI_OUT 0x20000000 576 #define GPIO_4_SPI_OUT_ENB 0x10000000 577 #define GPIO_3_SPI_OUT 0x08000000 578 #define GPIO_3_SPI_OUT_ENB 0x04000000 579 #define GPIO_3_4_LED 0x00000000 580 #define GPIO_3_4_GPIO 0x02000000 581 #define GPIO_2_CLKREQN_IN 0x00100000 582 #define GPIO_2_CLKREQN_OUT 0x00040000 583 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 584 #define GPIO_1_LED42_IN 0x00001000 585 #define GPIO_1_LED42_OUT 0x00000400 586 #define GPIO_1_LED42_OUT_ENB 0x00000200 587 #define GPIO_1_LED42_ENB 0x00000100 588 #define GPIO_0_SDA_IN 0x00000010 589 #define GPIO_0_SDA_OUT 0x00000004 590 #define GPIO_0_SDA_OUT_ENB 0x00000002 591 #define GPIO_0_SDA_ENB 0x00000001 592 593 /* General purpose register 0. */ 594 #define JME_GPREG0 0x0808 595 #define GPREG0_SH_POST_DW7_DIS 0x80000000 596 #define GPREG0_SH_POST_DW6_DIS 0x40000000 597 #define GPREG0_SH_POST_DW5_DIS 0x20000000 598 #define GPREG0_SH_POST_DW4_DIS 0x10000000 599 #define GPREG0_SH_POST_DW3_DIS 0x08000000 600 #define GPREG0_SH_POST_DW2_DIS 0x04000000 601 #define GPREG0_SH_POST_DW1_DIS 0x02000000 602 #define GPREG0_SH_POST_DW0_DIS 0x01000000 603 #define GPREG0_DMA_RD_REQ_8 0x00000000 604 #define GPREG0_DMA_RD_REQ_6 0x00100000 605 #define GPREG0_DMA_RD_REQ_5 0x00200000 606 #define GPREG0_DMA_RD_REQ_4 0x00300000 607 #define GPREG0_POST_DW0_ENB 0x00040000 608 #define GPREG0_PCC_CLR_DIS 0x00020000 609 #define GPREG0_FORCE_SCL_OUT 0x00010000 610 #define GPREG0_DL_RSTB_DIS 0x00008000 611 #define GPREG0_STICKY_RESET 0x00004000 612 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 613 #define GPREG0_LINK_CHG_POLL 0x00001000 614 #define GPREG0_LINK_CHG_DIRECT 0x00000000 615 #define GPREG0_MSI_GEN_SEL 0x00000800 616 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 617 #define GPREG0_PCC_UNIT_16US 0x00000000 618 #define GPREG0_PCC_UNIT_256US 0x00000100 619 #define GPREG0_PCC_UNIT_US 0x00000200 620 #define GPREG0_PCC_UNIT_MS 0x00000300 621 #define GPREG0_PCC_UNIT_MASK 0x00000300 622 #define GPREG0_INTR_EVENT_ENB 0x00000080 623 #define GPREG0_PME_ENB 0x00000020 624 #define GPREG0_PHY_ADDR_MASK 0x0000001F 625 #define GPREG0_PHY_ADDR_SHIFT 0 626 #define GPREG0_PHY_ADDR 1 627 628 /* General purpose register 1. */ 629 #define JME_GPREG1 0x080C 630 #define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 631 #define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 632 #define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 633 #define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 634 #define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 635 #define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 636 #define GPREG1_INTDLY_MASK 0x00000007 637 638 /* MSIX entry number of interrupt source. */ 639 #define JME_MSINUM_BASE 0x0810 640 #define JME_MSINUM_END 0x081F 641 #define MSINUM_MASK 0x7FFFFFFF 642 #define MSINUM_ENTRY_MASK 7 643 #define MSINUM_REG_INDEX(x) ((x) / 8) 644 #define MSINUM_INTR_SOURCE(x, y) \ 645 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 646 #define MSINUM_NUM_INTR_SOURCE 32 647 648 /* Interrupt event status. */ 649 #define JME_INTR_STATUS 0x0820 650 #define INTR_SW 0x80000000 651 #define INTR_TIMER 0x40000000 652 #define INTR_LINKCHG 0x20000000 653 #define INTR_PAUSE 0x10000000 654 #define INTR_MAGIC_PKT 0x08000000 655 #define INTR_WAKEUP_PKT 0x04000000 656 #define INTR_RXQ0_COAL_TO 0x02000000 657 #define INTR_RXQ1_COAL_TO 0x01000000 658 #define INTR_RXQ2_COAL_TO 0x00800000 659 #define INTR_RXQ3_COAL_TO 0x00400000 660 #define INTR_TXQ_COAL_TO 0x00200000 661 #define INTR_RXQ0_COAL 0x00100000 662 #define INTR_RXQ1_COAL 0x00080000 663 #define INTR_RXQ2_COAL 0x00040000 664 #define INTR_RXQ3_COAL 0x00020000 665 #define INTR_TXQ_COAL 0x00010000 666 #define INTR_RXQ3_DESC_EMPTY 0x00008000 667 #define INTR_RXQ2_DESC_EMPTY 0x00004000 668 #define INTR_RXQ1_DESC_EMPTY 0x00002000 669 #define INTR_RXQ0_DESC_EMPTY 0x00001000 670 #define INTR_RXQ3_COMP 0x00000800 671 #define INTR_RXQ2_COMP 0x00000400 672 #define INTR_RXQ1_COMP 0x00000200 673 #define INTR_RXQ0_COMP 0x00000100 674 #define INTR_TXQ7_COMP 0x00000080 675 #define INTR_TXQ6_COMP 0x00000040 676 #define INTR_TXQ5_COMP 0x00000020 677 #define INTR_TXQ4_COMP 0x00000010 678 #define INTR_TXQ3_COMP 0x00000008 679 #define INTR_TXQ2_COMP 0x00000004 680 #define INTR_TXQ1_COMP 0x00000002 681 #define INTR_TXQ0_COMP 0x00000001 682 683 #define INTR_RXQ_COAL_TO \ 684 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 685 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 686 687 #define INTR_RXQ_COAL \ 688 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 689 INTR_RXQ3_COAL) 690 691 #define INTR_RXQ_COMP \ 692 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 693 INTR_RXQ3_COMP) 694 695 #define INTR_RXQ_DESC_EMPTY \ 696 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 697 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 698 699 #define INTR_RXQ_COMP \ 700 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 701 INTR_RXQ3_COMP) 702 703 #define INTR_TXQ_COMP \ 704 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 705 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 706 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 707 708 #define JME_INTRS \ 709 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 710 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 711 712 #define N_INTR_SW 31 713 #define N_INTR_TIMER 30 714 #define N_INTR_LINKCHG 29 715 #define N_INTR_PAUSE 28 716 #define N_INTR_MAGIC_PKT 27 717 #define N_INTR_WAKEUP_PKT 26 718 #define N_INTR_RXQ0_COAL_TO 25 719 #define N_INTR_RXQ1_COAL_TO 24 720 #define N_INTR_RXQ2_COAL_TO 23 721 #define N_INTR_RXQ3_COAL_TO 22 722 #define N_INTR_TXQ_COAL_TO 21 723 #define N_INTR_RXQ0_COAL 20 724 #define N_INTR_RXQ1_COAL 19 725 #define N_INTR_RXQ2_COAL 18 726 #define N_INTR_RXQ3_COAL 17 727 #define N_INTR_TXQ_COAL 16 728 #define N_INTR_RXQ3_DESC_EMPTY 15 729 #define N_INTR_RXQ2_DESC_EMPTY 14 730 #define N_INTR_RXQ1_DESC_EMPTY 13 731 #define N_INTR_RXQ0_DESC_EMPTY 12 732 #define N_INTR_RXQ3_COMP 11 733 #define N_INTR_RXQ2_COMP 10 734 #define N_INTR_RXQ1_COMP 9 735 #define N_INTR_RXQ0_COMP 8 736 #define N_INTR_TXQ7_COMP 7 737 #define N_INTR_TXQ6_COMP 6 738 #define N_INTR_TXQ5_COMP 5 739 #define N_INTR_TXQ4_COMP 4 740 #define N_INTR_TXQ3_COMP 3 741 #define N_INTR_TXQ2_COMP 2 742 #define N_INTR_TXQ1_COMP 1 743 #define N_INTR_TXQ0_COMP 0 744 745 /* Interrupt request status. */ 746 #define JME_INTR_REQ_STATUS 0x0824 747 748 /* Interrupt enable - setting port. */ 749 #define JME_INTR_MASK_SET 0x0828 750 751 /* Interrupt enable - clearing port. */ 752 #define JME_INTR_MASK_CLR 0x082C 753 754 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 755 #define JME_PCCRX0 0x0830 756 #define JME_PCCRX1 0x0834 757 #define JME_PCCRX2 0x0838 758 #define JME_PCCRX3 0x083C 759 #define PCCRX_COAL_TO_MASK 0xFFFF0000 760 #define PCCRX_COAL_TO_SHIFT 16 761 #define PCCRX_COAL_PKT_MASK 0x0000FF00 762 #define PCCRX_COAL_PKT_SHIFT 8 763 764 #define PCCRX_COAL_TO_MIN 1 765 #define PCCRX_COAL_TO_DEFAULT 100 766 #define PCCRX_COAL_TO_MAX 65535 767 768 #define PCCRX_COAL_PKT_MIN 1 769 #define PCCRX_COAL_PKT_DEFAULT 2 770 #define PCCRX_COAL_PKT_MAX 255 771 772 /* Packet completion coalescing control of Tx queue. */ 773 #define JME_PCCTX 0x0840 774 #define PCCTX_COAL_TO_MASK 0xFFFF0000 775 #define PCCTX_COAL_TO_SHIFT 16 776 #define PCCTX_COAL_PKT_MASK 0x0000FF00 777 #define PCCTX_COAL_PKT_SHIFT 8 778 #define PCCTX_COAL_TXQ7 0x00000080 779 #define PCCTX_COAL_TXQ6 0x00000040 780 #define PCCTX_COAL_TXQ5 0x00000020 781 #define PCCTX_COAL_TXQ4 0x00000010 782 #define PCCTX_COAL_TXQ3 0x00000008 783 #define PCCTX_COAL_TXQ2 0x00000004 784 #define PCCTX_COAL_TXQ1 0x00000002 785 #define PCCTX_COAL_TXQ0 0x00000001 786 787 #define PCCTX_COAL_TO_MIN 1 788 #define PCCTX_COAL_TO_DEFAULT 100 789 #define PCCTX_COAL_TO_MAX 65535 790 791 #define PCCTX_COAL_PKT_MIN 1 792 #define PCCTX_COAL_PKT_DEFAULT 8 793 #define PCCTX_COAL_PKT_MAX 255 794 795 /* Chip mode and FPGA version. */ 796 #define JME_CHIPMODE 0x0844 797 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 798 #define CHIPMODE_FPGA_REV_SHIFT 16 799 #define CHIPMODE_NOT_FPGA 0 800 #define CHIPMODE_REV_MASK 0x0000FF00 801 #define CHIPMODE_REV_SHIFT 8 802 #define CHIPMODE_MODE_48P 0x0000000C 803 #define CHIPMODE_MODE_64P 0x00000004 804 #define CHIPMODE_MODE_128P_MAC 0x00000003 805 #define CHIPMODE_MODE_128P_DBG 0x00000002 806 #define CHIPMODE_MODE_128P_PHY 0x00000000 807 /* Chip full mask revision. */ 808 #define CHIPMODE_REVFM(x) ((x) & 0x0F) 809 /* Chip ECO revision. */ 810 #define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) 811 812 /* Shadow status base address high/low. */ 813 #define JME_SHBASE_ADDR_HI 0x0848 814 #define JME_SHBASE_ADDR_LO 0x084C 815 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 816 #define SHBASE_POST_FORCE 0x00000002 817 #define SHBASE_POST_ENB 0x00000001 818 819 /* Timer 1 and 2. */ 820 #define JME_TIMER1 0x0870 821 #define JME_TIMER2 0x0874 822 #define TIMER_ENB 0x01000000 823 #define TIMER_CNT_MASK 0x00FFFFFF 824 #define TIMER_CNT_SHIFT 0 825 #define TIMER_UNIT 1024 /* 1024us */ 826 827 /* Aggresive power mode control. */ 828 #define JME_APMC 0x087C 829 #define APMC_PCIE_SDOWN_STAT 0x80000000 830 #define APMC_PCIE_SDOWN_ENB 0x40000000 831 #define APMC_PSEUDO_HOT_PLUG 0x20000000 832 #define APMC_EXT_PLUGIN_ENB 0x04000000 833 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 834 #define APMC_DIS_SRAM 0x00000004 835 #define APMC_DIS_CLKPM 0x00000002 836 #define APMC_DIS_CLKTX 0x00000001 837 838 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 839 #define JME_PCCSRX_BASE 0x0880 840 #define JME_PCCSRX_END 0x088F 841 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 842 #define PCCSRX_TO_MASK 0xFFFF0000 843 #define PCCSRX_TO_SHIFT 16 844 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 845 #define PCCSRX_PKT_CNT_SHIFT 8 846 847 /* Packet completion coalesing status of Tx queue. */ 848 #define JME_PCCSTX 0x0890 849 #define PCCSTX_TO_MASK 0xFFFF0000 850 #define PCCSTX_TO_SHIFT 16 851 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 852 #define PCCSTX_PKT_CNT_SHIFT 8 853 854 /* Tx queues empty indicator. */ 855 #define JME_TXQEMPTY 0x0894 856 #define TXQEMPTY_TXQ7 0x00000080 857 #define TXQEMPTY_TXQ6 0x00000040 858 #define TXQEMPTY_TXQ5 0x00000020 859 #define TXQEMPTY_TXQ4 0x00000010 860 #define TXQEMPTY_TXQ3 0x00000008 861 #define TXQEMPTY_TXQ2 0x00000004 862 #define TXQEMPTY_TXQ1 0x00000002 863 #define TXQEMPTY_TXQ0 0x00000001 864 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 865 866 /* RSS control registers. */ 867 #define JME_RSS_BASE 0x0C00 868 869 #define JME_RSSC 0x0C00 870 #define RSSC_HASH_LEN_MASK 0x0000E000 871 #define RSSC_HASH_64_ENTRY 0x0000A000 872 #define RSSC_HASH_128_ENTRY 0x0000E000 873 #define RSSC_HASH_NONE 0x00001000 874 #define RSSC_HASH_IPV6 0x00000800 875 #define RSSC_HASH_IPV4 0x00000400 876 #define RSSC_HASH_IPV6_TCP 0x00000200 877 #define RSSC_HASH_IPV4_TCP 0x00000100 878 #define RSSC_NCPU_MASK 0x000000F8 879 #define RSSC_NCPU_SHIFT 3 880 #define RSSC_DIS_RSS 0x00000000 881 #define RSSC_2RXQ_ENB 0x00000001 882 #define RSSS_4RXQ_ENB 0x00000002 883 884 /* CPU vector. */ 885 #define JME_RSSCPU 0x0C04 886 #define RSSCPU_N_SEL(x) ((1 << (x)) 887 888 /* RSS Hash value. */ 889 #define JME_RSSHASH 0x0C10 890 891 #define JME_RSSHASH_STAT 0x0C14 892 893 #define JME_RSS_RDATA0 0x0C18 894 895 #define JME_RSS_RDATA1 0x0C1C 896 897 /* RSS secret key. */ 898 #define JME_RSSKEY_BASE 0x0C40 899 #define JME_RSSKEY_LAST 0x0C64 900 #define JME_RSSKEY_END 0x0C67 901 #define HASHKEY_NBYTES 40 902 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 903 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 904 905 /* RSS indirection table entries. */ 906 #define JME_RSSTBL_BASE 0x0C80 907 #define JME_RSSTBL_END 0x0CFF 908 #define RSSTBL_NENTRY 128 909 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 910 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 911 912 /* MSI-X table. */ 913 #define JME_MSIX_BASE_ADDR 0x2000 914 915 #define JME_MSIX_BASE 0x2000 916 #define JME_MSIX_END 0x207F 917 #define JME_MSIX_NENTRY 8 918 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 919 #define MSIX_ADDR_HI_OFF 0x00 920 #define MSIX_ADDR_LO_OFF 0x04 921 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 922 #define MSIX_DATA_OFF 0x08 923 #define MSIX_VECTOR_OFF 0x0C 924 #define MSIX_VECTOR_RSVD 0x80000000 925 #define MSIX_VECTOR_DIS 0x00000001 926 927 /* MSI-X PBA. */ 928 #define JME_MSIX_PBA_BASE_ADDR 0x3000 929 930 #define JME_MSIX_PBA 0x3000 931 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 932 #define MSIX_PBA_RSVD_SHIFT 8 933 #define MSIX_PBA_PEND_MASK 0x000000FF 934 #define MSIX_PBA_PEND_SHIFT 0 935 #define MSIX_PBA_PEND_ENTRY7 0x00000080 936 #define MSIX_PBA_PEND_ENTRY6 0x00000040 937 #define MSIX_PBA_PEND_ENTRY5 0x00000020 938 #define MSIX_PBA_PEND_ENTRY4 0x00000010 939 #define MSIX_PBA_PEND_ENTRY3 0x00000008 940 #define MSIX_PBA_PEND_ENTRY2 0x00000004 941 #define MSIX_PBA_PEND_ENTRY1 0x00000002 942 #define MSIX_PBA_PEND_ENTRY0 0x00000001 943 944 #define JME_PHY_OUI 0x001B8C 945 #define JME_PHY_MODEL 0x21 946 #define JME_PHY_REV 0x01 947 #define JME_PHY_ADDR 1 948 949 /* JMC250 shadow status block. */ 950 struct jme_ssb { 951 uint32_t dw0; 952 uint32_t dw1; 953 uint32_t dw2; 954 uint32_t dw3; 955 uint32_t dw4; 956 uint32_t dw5; 957 uint32_t dw6; 958 uint32_t dw7; 959 }; 960 961 /* JMC250 descriptor structures. */ 962 struct jme_desc { 963 uint32_t flags; 964 uint32_t buflen; 965 uint32_t addr_hi; 966 uint32_t addr_lo; 967 }; 968 969 #define JME_TD_OWN 0x80000000 970 #define JME_TD_INTR 0x40000000 971 #define JME_TD_64BIT 0x20000000 972 #define JME_TD_TCPCSUM 0x10000000 973 #define JME_TD_UDPCSUM 0x08000000 974 #define JME_TD_IPCSUM 0x04000000 975 #define JME_TD_TSO 0x02000000 976 #define JME_TD_VLAN_TAG 0x01000000 977 #define JME_TD_VLAN_MASK 0x0000FFFF 978 979 #define JME_TD_MSS_MASK 0xFFFC0000 980 #define JME_TD_MSS_SHIFT 18 981 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 982 #define JME_TD_BUF_LEN_SHIFT 0 983 984 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 985 #define JME_TD_FRAME_LEN_SHIFT 0 986 987 /* 988 * Only the first Tx descriptor of a packet is updated 989 * after packet transmission. 990 */ 991 #define JME_TD_TMOUT 0x20000000 992 #define JME_TD_RETRY_EXP 0x10000000 993 #define JME_TD_COLLISION 0x08000000 994 #define JME_TD_UNDERRUN 0x04000000 995 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 996 #define JME_TD_EHDR_SIZE_SHIFT 0 997 998 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 999 #define JME_TD_SEG_CNT_SHIFT 16 1000 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 1001 #define JME_TD_RETRY_CNT_SHIFT 0 1002 1003 #define JME_RD_OWN 0x80000000 1004 #define JME_RD_INTR 0x40000000 1005 #define JME_RD_64BIT 0x20000000 1006 1007 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 1008 #define JME_RD_BUF_LEN_SHIFT 0 1009 1010 /* 1011 * Only the first Rx descriptor of a packet is updated 1012 * after packet reception. 1013 */ 1014 #define JME_RD_MORE_FRAG 0x20000000 1015 #define JME_RD_TCP 0x10000000 1016 #define JME_RD_UDP 0x08000000 1017 #define JME_RD_IPCSUM 0x04000000 1018 #define JME_RD_TCPCSUM 0x02000000 1019 #define JME_RD_UDPCSUM 0x01000000 1020 #define JME_RD_VLAN_TAG 0x00800000 1021 #define JME_RD_IPV4 0x00400000 1022 #define JME_RD_IPV6 0x00200000 1023 #define JME_RD_PAUSE 0x00100000 1024 #define JME_RD_MAGIC 0x00080000 1025 #define JME_RD_WAKEUP 0x00040000 1026 #define JME_RD_BCAST 0x00030000 1027 #define JME_RD_MCAST 0x00020000 1028 #define JME_RD_UCAST 0x00010000 1029 #define JME_RD_VLAN_MASK 0x0000FFFF 1030 #define JME_RD_VLAN_SHIFT 0 1031 1032 #define JME_RD_VALID 0x80000000 1033 #define JME_RD_CNT_MASK 0x7F000000 1034 #define JME_RD_CNT_SHIFT 24 1035 #define JME_RD_GIANT 0x00800000 1036 #define JME_RD_GMII_ERR 0x00400000 1037 #define JME_RD_NBL_RCVD 0x00200000 1038 #define JME_RD_COLL 0x00100000 1039 #define JME_RD_ABORT 0x00080000 1040 #define JME_RD_RUNT 0x00040000 1041 #define JME_RD_FIFO_OVRN 0x00020000 1042 #define JME_RD_CRC_ERR 0x00010000 1043 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 1044 1045 #define JME_RX_ERR_STAT \ 1046 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 1047 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 1048 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 1049 1050 #define JME_RD_ERR_MASK 0x00FF0000 1051 #define JME_RD_ERR_SHIFT 16 1052 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1053 #define JME_RX_ERR_BITS "\20" \ 1054 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1055 "\5COLL\6NBLRCVD\7GMIIERR\10" 1056 1057 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1058 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1059 #define JME_RX_PAD_BYTES 10 1060 1061 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1062 1063 #define JME_RD_RSS_HASH_MASK 0x00003F00 1064 #define JME_RD_RSS_HASH_SHIFT 8 1065 #define JME_RD_RSS_HASH_NONE 0x00000000 1066 #define JME_RD_RSS_HASH_IPV4 0x00000100 1067 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1068 #define JME_RD_RSS_HASH_IPV6 0x00000400 1069 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1070 #define JME_RD_HASH_FN_NONE 0x00000000 1071 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1072 1073 #endif 1074