1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/mbuf.h> 37 #include <sys/rman.h> 38 #include <sys/module.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/taskqueue.h> 45 46 #include <net/bpf.h> 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 #include <net/if_vlan_var.h> 55 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/ip.h> 59 #include <netinet/tcp.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #include <machine/bus.h> 68 #include <machine/in_cksum.h> 69 70 #include <dev/jme/if_jmereg.h> 71 #include <dev/jme/if_jmevar.h> 72 73 /* "device miibus" required. See GENERIC if you get errors here. */ 74 #include "miibus_if.h" 75 76 /* Define the following to disable printing Rx errors. */ 77 #undef JME_SHOW_ERRORS 78 79 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 80 81 MODULE_DEPEND(jme, pci, 1, 1, 1); 82 MODULE_DEPEND(jme, ether, 1, 1, 1); 83 MODULE_DEPEND(jme, miibus, 1, 1, 1); 84 85 /* Tunables. */ 86 static int msi_disable = 0; 87 static int msix_disable = 0; 88 TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 89 TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 90 91 /* 92 * Devices supported by this driver. 93 */ 94 static struct jme_dev { 95 uint16_t jme_vendorid; 96 uint16_t jme_deviceid; 97 const char *jme_name; 98 } jme_devs[] = { 99 { VENDORID_JMICRON, DEVICEID_JMC250, 100 "JMicron Inc, JMC25x Gigabit Ethernet" }, 101 { VENDORID_JMICRON, DEVICEID_JMC260, 102 "JMicron Inc, JMC26x Fast Ethernet" }, 103 }; 104 105 static int jme_miibus_readreg(device_t, int, int); 106 static int jme_miibus_writereg(device_t, int, int, int); 107 static void jme_miibus_statchg(device_t); 108 static void jme_mediastatus(if_t, struct ifmediareq *); 109 static int jme_mediachange(if_t); 110 static int jme_probe(device_t); 111 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 112 static int jme_eeprom_macaddr(struct jme_softc *); 113 static int jme_efuse_macaddr(struct jme_softc *); 114 static void jme_reg_macaddr(struct jme_softc *); 115 static void jme_set_macaddr(struct jme_softc *, uint8_t *); 116 static void jme_map_intr_vector(struct jme_softc *); 117 static int jme_attach(device_t); 118 static int jme_detach(device_t); 119 static void jme_sysctl_node(struct jme_softc *); 120 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 121 static int jme_dma_alloc(struct jme_softc *); 122 static void jme_dma_free(struct jme_softc *); 123 static int jme_shutdown(device_t); 124 static void jme_setlinkspeed(struct jme_softc *); 125 static void jme_setwol(struct jme_softc *); 126 static int jme_suspend(device_t); 127 static int jme_resume(device_t); 128 static int jme_encap(struct jme_softc *, struct mbuf **); 129 static void jme_start(if_t); 130 static void jme_start_locked(if_t); 131 static void jme_watchdog(struct jme_softc *); 132 static int jme_ioctl(if_t, u_long, caddr_t); 133 static void jme_mac_config(struct jme_softc *); 134 static void jme_link_task(void *, int); 135 static int jme_intr(void *); 136 static void jme_int_task(void *, int); 137 static void jme_txeof(struct jme_softc *); 138 static __inline void jme_discard_rxbuf(struct jme_softc *, int); 139 static void jme_rxeof(struct jme_softc *); 140 static int jme_rxintr(struct jme_softc *, int); 141 static void jme_tick(void *); 142 static void jme_reset(struct jme_softc *); 143 static void jme_init(void *); 144 static void jme_init_locked(struct jme_softc *); 145 static void jme_stop(struct jme_softc *); 146 static void jme_stop_tx(struct jme_softc *); 147 static void jme_stop_rx(struct jme_softc *); 148 static int jme_init_rx_ring(struct jme_softc *); 149 static void jme_init_tx_ring(struct jme_softc *); 150 static void jme_init_ssb(struct jme_softc *); 151 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 152 static void jme_set_vlan(struct jme_softc *); 153 static void jme_set_filter(struct jme_softc *); 154 static void jme_stats_clear(struct jme_softc *); 155 static void jme_stats_save(struct jme_softc *); 156 static void jme_stats_update(struct jme_softc *); 157 static void jme_phy_down(struct jme_softc *); 158 static void jme_phy_up(struct jme_softc *); 159 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 160 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 161 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 162 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 163 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 164 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 165 166 167 static device_method_t jme_methods[] = { 168 /* Device interface. */ 169 DEVMETHOD(device_probe, jme_probe), 170 DEVMETHOD(device_attach, jme_attach), 171 DEVMETHOD(device_detach, jme_detach), 172 DEVMETHOD(device_shutdown, jme_shutdown), 173 DEVMETHOD(device_suspend, jme_suspend), 174 DEVMETHOD(device_resume, jme_resume), 175 176 /* MII interface. */ 177 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 178 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 179 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 180 181 { NULL, NULL } 182 }; 183 184 static driver_t jme_driver = { 185 "jme", 186 jme_methods, 187 sizeof(struct jme_softc) 188 }; 189 190 DRIVER_MODULE(jme, pci, jme_driver, 0, 0); 191 DRIVER_MODULE(miibus, jme, miibus_driver, 0, 0); 192 193 static struct resource_spec jme_res_spec_mem[] = { 194 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 195 { -1, 0, 0 } 196 }; 197 198 static struct resource_spec jme_irq_spec_legacy[] = { 199 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 200 { -1, 0, 0 } 201 }; 202 203 static struct resource_spec jme_irq_spec_msi[] = { 204 { SYS_RES_IRQ, 1, RF_ACTIVE }, 205 { -1, 0, 0 } 206 }; 207 208 /* 209 * Read a PHY register on the MII of the JMC250. 210 */ 211 static int 212 jme_miibus_readreg(device_t dev, int phy, int reg) 213 { 214 struct jme_softc *sc; 215 uint32_t val; 216 int i; 217 218 sc = device_get_softc(dev); 219 220 /* For FPGA version, PHY address 0 should be ignored. */ 221 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 222 return (0); 223 224 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 225 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 226 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 227 DELAY(1); 228 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 229 break; 230 } 231 232 if (i == 0) { 233 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 234 return (0); 235 } 236 237 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 238 } 239 240 /* 241 * Write a PHY register on the MII of the JMC250. 242 */ 243 static int 244 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 245 { 246 struct jme_softc *sc; 247 int i; 248 249 sc = device_get_softc(dev); 250 251 /* For FPGA version, PHY address 0 should be ignored. */ 252 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 253 return (0); 254 255 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 256 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 257 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 258 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 259 DELAY(1); 260 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 261 break; 262 } 263 264 if (i == 0) 265 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 266 267 return (0); 268 } 269 270 /* 271 * Callback from MII layer when media changes. 272 */ 273 static void 274 jme_miibus_statchg(device_t dev) 275 { 276 struct jme_softc *sc; 277 278 sc = device_get_softc(dev); 279 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 280 } 281 282 /* 283 * Get the current interface media status. 284 */ 285 static void 286 jme_mediastatus(if_t ifp, struct ifmediareq *ifmr) 287 { 288 struct jme_softc *sc; 289 struct mii_data *mii; 290 291 sc = if_getsoftc(ifp); 292 JME_LOCK(sc); 293 if ((if_getflags(ifp) & IFF_UP) == 0) { 294 JME_UNLOCK(sc); 295 return; 296 } 297 mii = device_get_softc(sc->jme_miibus); 298 299 mii_pollstat(mii); 300 ifmr->ifm_status = mii->mii_media_status; 301 ifmr->ifm_active = mii->mii_media_active; 302 JME_UNLOCK(sc); 303 } 304 305 /* 306 * Set hardware to newly-selected media. 307 */ 308 static int 309 jme_mediachange(if_t ifp) 310 { 311 struct jme_softc *sc; 312 struct mii_data *mii; 313 struct mii_softc *miisc; 314 int error; 315 316 sc = if_getsoftc(ifp); 317 JME_LOCK(sc); 318 mii = device_get_softc(sc->jme_miibus); 319 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 320 PHY_RESET(miisc); 321 error = mii_mediachg(mii); 322 JME_UNLOCK(sc); 323 324 return (error); 325 } 326 327 static int 328 jme_probe(device_t dev) 329 { 330 struct jme_dev *sp; 331 int i; 332 uint16_t vendor, devid; 333 334 vendor = pci_get_vendor(dev); 335 devid = pci_get_device(dev); 336 sp = jme_devs; 337 for (i = 0; i < nitems(jme_devs); i++, sp++) { 338 if (vendor == sp->jme_vendorid && 339 devid == sp->jme_deviceid) { 340 device_set_desc(dev, sp->jme_name); 341 return (BUS_PROBE_DEFAULT); 342 } 343 } 344 345 return (ENXIO); 346 } 347 348 static int 349 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 350 { 351 uint32_t reg; 352 int i; 353 354 *val = 0; 355 for (i = JME_TIMEOUT; i > 0; i--) { 356 reg = CSR_READ_4(sc, JME_SMBCSR); 357 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 358 break; 359 DELAY(1); 360 } 361 362 if (i == 0) { 363 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 364 return (ETIMEDOUT); 365 } 366 367 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 368 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 369 for (i = JME_TIMEOUT; i > 0; i--) { 370 DELAY(1); 371 reg = CSR_READ_4(sc, JME_SMBINTF); 372 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 373 break; 374 } 375 376 if (i == 0) { 377 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 378 return (ETIMEDOUT); 379 } 380 381 reg = CSR_READ_4(sc, JME_SMBINTF); 382 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 383 384 return (0); 385 } 386 387 static int 388 jme_eeprom_macaddr(struct jme_softc *sc) 389 { 390 uint8_t eaddr[ETHER_ADDR_LEN]; 391 uint8_t fup, reg, val; 392 uint32_t offset; 393 int match; 394 395 offset = 0; 396 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 397 fup != JME_EEPROM_SIG0) 398 return (ENOENT); 399 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 400 fup != JME_EEPROM_SIG1) 401 return (ENOENT); 402 match = 0; 403 do { 404 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 405 break; 406 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 407 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 408 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 409 break; 410 if (reg >= JME_PAR0 && 411 reg < JME_PAR0 + ETHER_ADDR_LEN) { 412 if (jme_eeprom_read_byte(sc, offset + 2, 413 &val) != 0) 414 break; 415 eaddr[reg - JME_PAR0] = val; 416 match++; 417 } 418 } 419 /* Check for the end of EEPROM descriptor. */ 420 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 421 break; 422 /* Try next eeprom descriptor. */ 423 offset += JME_EEPROM_DESC_BYTES; 424 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 425 426 if (match == ETHER_ADDR_LEN) { 427 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 428 return (0); 429 } 430 431 return (ENOENT); 432 } 433 434 static int 435 jme_efuse_macaddr(struct jme_softc *sc) 436 { 437 uint32_t reg; 438 int i; 439 440 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 441 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) != 442 EFUSE_CTL1_AUTOLAOD_DONE) 443 return (ENOENT); 444 /* Reset eFuse controller. */ 445 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 446 reg |= EFUSE_CTL2_RESET; 447 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 448 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 449 reg &= ~EFUSE_CTL2_RESET; 450 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 451 452 /* Have eFuse reload station address to MAC controller. */ 453 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 454 reg &= ~EFUSE_CTL1_CMD_MASK; 455 reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE; 456 pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4); 457 458 /* 459 * Verify completion of eFuse autload command. It should be 460 * completed within 108us. 461 */ 462 DELAY(110); 463 for (i = 10; i > 0; i--) { 464 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 465 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | 466 EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) { 467 DELAY(20); 468 continue; 469 } 470 if ((reg & EFUSE_CTL1_EXECUTE) == 0) 471 break; 472 /* Station address loading is still in progress. */ 473 DELAY(20); 474 } 475 if (i == 0) { 476 device_printf(sc->jme_dev, "eFuse autoload timed out.\n"); 477 return (ETIMEDOUT); 478 } 479 480 return (0); 481 } 482 483 static void 484 jme_reg_macaddr(struct jme_softc *sc) 485 { 486 uint32_t par0, par1; 487 488 /* Read station address. */ 489 par0 = CSR_READ_4(sc, JME_PAR0); 490 par1 = CSR_READ_4(sc, JME_PAR1); 491 par1 &= 0xFFFF; 492 if ((par0 == 0 && par1 == 0) || 493 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 494 device_printf(sc->jme_dev, 495 "Failed to retrieve Ethernet address.\n"); 496 } else { 497 /* 498 * For controllers that use eFuse, the station address 499 * could also be extracted from JME_PCI_PAR0 and 500 * JME_PCI_PAR1 registers in PCI configuration space. 501 * Each register holds exactly half of station address(24bits) 502 * so use JME_PAR0, JME_PAR1 registers instead. 503 */ 504 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 505 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 506 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 507 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 508 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 509 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 510 } 511 } 512 513 static void 514 jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr) 515 { 516 uint32_t val; 517 int i; 518 519 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 520 /* 521 * Avoid reprogramming station address if the address 522 * is the same as previous one. Note, reprogrammed 523 * station address is permanent as if it was written 524 * to EEPROM. So if station address was changed by 525 * admistrator it's possible to lose factory configured 526 * address when driver fails to restore its address. 527 * (e.g. reboot or system crash) 528 */ 529 if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) { 530 for (i = 0; i < ETHER_ADDR_LEN; i++) { 531 val = JME_EFUSE_EEPROM_FUNC0 << 532 JME_EFUSE_EEPROM_FUNC_SHIFT; 533 val |= JME_EFUSE_EEPROM_PAGE_BAR1 << 534 JME_EFUSE_EEPROM_PAGE_SHIFT; 535 val |= (JME_PAR0 + i) << 536 JME_EFUSE_EEPROM_ADDR_SHIFT; 537 val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT; 538 pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM, 539 val | JME_EFUSE_EEPROM_WRITE, 4); 540 } 541 } 542 } else { 543 CSR_WRITE_4(sc, JME_PAR0, 544 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 545 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 546 } 547 } 548 549 static void 550 jme_map_intr_vector(struct jme_softc *sc) 551 { 552 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 553 554 bzero(map, sizeof(map)); 555 556 /* Map Tx interrupts source to MSI/MSIX vector 2. */ 557 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 558 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 559 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 560 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 561 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 562 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 563 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 564 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 565 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 566 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 567 map[MSINUM_REG_INDEX(N_INTR_TXQ5_COMP)] |= 568 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 569 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 570 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 571 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 572 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 573 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 574 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 575 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 576 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 577 578 /* Map Rx interrupts source to MSI/MSIX vector 1. */ 579 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 580 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 581 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 582 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 583 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 584 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 585 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 586 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 587 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 588 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 589 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 590 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 591 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 592 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 593 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 594 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 595 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 596 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 597 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 598 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 599 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 600 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 601 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 602 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 603 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 604 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 605 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 606 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 607 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 608 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 609 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 610 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 611 612 /* Map all other interrupts source to MSI/MSIX vector 0. */ 613 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 614 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 615 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 616 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 617 } 618 619 static int 620 jme_attach(device_t dev) 621 { 622 struct jme_softc *sc; 623 if_t ifp; 624 struct mii_softc *miisc; 625 struct mii_data *mii; 626 uint32_t reg; 627 uint16_t burst; 628 int error, i, mii_flags, msic, msixc, pmc; 629 630 error = 0; 631 sc = device_get_softc(dev); 632 sc->jme_dev = dev; 633 634 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 635 MTX_DEF); 636 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 637 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 638 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 639 640 /* 641 * Map the device. JMC250 supports both memory mapped and I/O 642 * register space access. Because I/O register access should 643 * use different BARs to access registers it's waste of time 644 * to use I/O register spce access. JMC250 uses 16K to map 645 * entire memory space. 646 */ 647 pci_enable_busmaster(dev); 648 sc->jme_res_spec = jme_res_spec_mem; 649 sc->jme_irq_spec = jme_irq_spec_legacy; 650 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 651 if (error != 0) { 652 device_printf(dev, "cannot allocate memory resources.\n"); 653 goto fail; 654 } 655 656 /* Allocate IRQ resources. */ 657 msixc = pci_msix_count(dev); 658 msic = pci_msi_count(dev); 659 if (bootverbose) { 660 device_printf(dev, "MSIX count : %d\n", msixc); 661 device_printf(dev, "MSI count : %d\n", msic); 662 } 663 664 /* Use 1 MSI/MSI-X. */ 665 if (msixc > 1) 666 msixc = 1; 667 if (msic > 1) 668 msic = 1; 669 /* Prefer MSIX over MSI. */ 670 if (msix_disable == 0 || msi_disable == 0) { 671 if (msix_disable == 0 && msixc > 0 && 672 pci_alloc_msix(dev, &msixc) == 0) { 673 if (msixc == 1) { 674 device_printf(dev, "Using %d MSIX messages.\n", 675 msixc); 676 sc->jme_flags |= JME_FLAG_MSIX; 677 sc->jme_irq_spec = jme_irq_spec_msi; 678 } else 679 pci_release_msi(dev); 680 } 681 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 682 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 683 if (msic == 1) { 684 device_printf(dev, "Using %d MSI messages.\n", 685 msic); 686 sc->jme_flags |= JME_FLAG_MSI; 687 sc->jme_irq_spec = jme_irq_spec_msi; 688 } else 689 pci_release_msi(dev); 690 } 691 /* Map interrupt vector 0, 1 and 2. */ 692 if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 693 (sc->jme_flags & JME_FLAG_MSIX) != 0) 694 jme_map_intr_vector(sc); 695 } 696 697 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 698 if (error != 0) { 699 device_printf(dev, "cannot allocate IRQ resources.\n"); 700 goto fail; 701 } 702 703 sc->jme_rev = pci_get_device(dev); 704 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 705 sc->jme_flags |= JME_FLAG_FASTETH; 706 sc->jme_flags |= JME_FLAG_NOJUMBO; 707 } 708 reg = CSR_READ_4(sc, JME_CHIPMODE); 709 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 710 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 711 CHIPMODE_NOT_FPGA) 712 sc->jme_flags |= JME_FLAG_FPGA; 713 if (bootverbose) { 714 device_printf(dev, "PCI device revision : 0x%04x\n", 715 sc->jme_rev); 716 device_printf(dev, "Chip revision : 0x%02x\n", 717 sc->jme_chip_rev); 718 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 719 device_printf(dev, "FPGA revision : 0x%04x\n", 720 (reg & CHIPMODE_FPGA_REV_MASK) >> 721 CHIPMODE_FPGA_REV_SHIFT); 722 } 723 if (sc->jme_chip_rev == 0xFF) { 724 device_printf(dev, "Unknown chip revision : 0x%02x\n", 725 sc->jme_rev); 726 error = ENXIO; 727 goto fail; 728 } 729 730 /* Identify controller features and bugs. */ 731 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 732 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 733 CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 734 sc->jme_flags |= JME_FLAG_DMA32BIT; 735 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 736 sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD; 737 sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK; 738 sc->jme_flags |= JME_FLAG_HWMIB; 739 } 740 741 /* Reset the ethernet controller. */ 742 jme_reset(sc); 743 744 /* Get station address. */ 745 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 746 error = jme_efuse_macaddr(sc); 747 if (error == 0) 748 jme_reg_macaddr(sc); 749 } else { 750 error = ENOENT; 751 reg = CSR_READ_4(sc, JME_SMBCSR); 752 if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 753 error = jme_eeprom_macaddr(sc); 754 if (error != 0 && bootverbose) 755 device_printf(sc->jme_dev, 756 "ethernet hardware address not found in EEPROM.\n"); 757 if (error != 0) 758 jme_reg_macaddr(sc); 759 } 760 761 /* 762 * Save PHY address. 763 * Integrated JR0211 has fixed PHY address whereas FPGA version 764 * requires PHY probing to get correct PHY address. 765 */ 766 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 767 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 768 GPREG0_PHY_ADDR_MASK; 769 if (bootverbose) 770 device_printf(dev, "PHY is at address %d.\n", 771 sc->jme_phyaddr); 772 } else 773 sc->jme_phyaddr = 0; 774 775 /* Set max allowable DMA size. */ 776 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 777 sc->jme_flags |= JME_FLAG_PCIE; 778 burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 779 if (bootverbose) { 780 device_printf(dev, "Read request size : %d bytes.\n", 781 128 << ((burst >> 12) & 0x07)); 782 device_printf(dev, "TLP payload size : %d bytes.\n", 783 128 << ((burst >> 5) & 0x07)); 784 } 785 switch ((burst >> 12) & 0x07) { 786 case 0: 787 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 788 break; 789 case 1: 790 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 791 break; 792 default: 793 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 794 break; 795 } 796 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 797 } else { 798 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 799 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 800 } 801 /* Create coalescing sysctl node. */ 802 jme_sysctl_node(sc); 803 if ((error = jme_dma_alloc(sc)) != 0) 804 goto fail; 805 806 ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 807 if_setsoftc(ifp, sc); 808 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 809 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 810 if_setioctlfn(ifp, jme_ioctl); 811 if_setstartfn(ifp, jme_start); 812 if_setinitfn(ifp, jme_init); 813 if_setsendqlen(ifp, JME_TX_RING_CNT - 1); 814 if_setsendqready(ifp); 815 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 816 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 817 if_sethwassist(ifp, JME_CSUM_FEATURES | CSUM_TSO); 818 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 819 sc->jme_flags |= JME_FLAG_PMCAP; 820 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 821 } 822 if_setcapenable(ifp, if_getcapabilities(ifp)); 823 824 /* Wakeup PHY. */ 825 jme_phy_up(sc); 826 mii_flags = MIIF_DOPAUSE; 827 /* Ask PHY calibration to PHY driver. */ 828 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 829 mii_flags |= MIIF_MACPRIV0; 830 /* Set up MII bus. */ 831 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange, 832 jme_mediastatus, BMSR_DEFCAPMASK, 833 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, 834 MII_OFFSET_ANY, mii_flags); 835 if (error != 0) { 836 device_printf(dev, "attaching PHYs failed\n"); 837 goto fail; 838 } 839 840 /* 841 * Force PHY to FPGA mode. 842 */ 843 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 844 mii = device_get_softc(sc->jme_miibus); 845 if (mii->mii_instance != 0) { 846 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 847 if (miisc->mii_phy != 0) { 848 sc->jme_phyaddr = miisc->mii_phy; 849 break; 850 } 851 } 852 if (sc->jme_phyaddr != 0) { 853 device_printf(sc->jme_dev, 854 "FPGA PHY is at %d\n", sc->jme_phyaddr); 855 /* vendor magic. */ 856 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 857 0x0004); 858 } 859 } 860 } 861 862 ether_ifattach(ifp, sc->jme_eaddr); 863 864 /* VLAN capability setup */ 865 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 866 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 867 if_setcapenable(ifp, if_getcapabilities(ifp)); 868 869 /* Tell the upper layer(s) we support long frames. */ 870 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 871 872 /* Create local taskq. */ 873 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 874 taskqueue_thread_enqueue, &sc->jme_tq); 875 if (sc->jme_tq == NULL) { 876 device_printf(dev, "could not create taskqueue.\n"); 877 ether_ifdetach(ifp); 878 error = ENXIO; 879 goto fail; 880 } 881 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 882 device_get_nameunit(sc->jme_dev)); 883 884 for (i = 0; i < 1; i++) { 885 error = bus_setup_intr(dev, sc->jme_irq[i], 886 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 887 &sc->jme_intrhand[i]); 888 if (error != 0) 889 break; 890 } 891 892 if (error != 0) { 893 device_printf(dev, "could not set up interrupt handler.\n"); 894 taskqueue_free(sc->jme_tq); 895 sc->jme_tq = NULL; 896 ether_ifdetach(ifp); 897 goto fail; 898 } 899 900 fail: 901 if (error != 0) 902 jme_detach(dev); 903 904 return (error); 905 } 906 907 static int 908 jme_detach(device_t dev) 909 { 910 struct jme_softc *sc; 911 if_t ifp; 912 int i; 913 914 sc = device_get_softc(dev); 915 916 ifp = sc->jme_ifp; 917 if (device_is_attached(dev)) { 918 JME_LOCK(sc); 919 sc->jme_flags |= JME_FLAG_DETACH; 920 jme_stop(sc); 921 JME_UNLOCK(sc); 922 callout_drain(&sc->jme_tick_ch); 923 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 924 taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 925 /* Restore possibly modified station address. */ 926 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) 927 jme_set_macaddr(sc, sc->jme_eaddr); 928 ether_ifdetach(ifp); 929 } 930 931 if (sc->jme_tq != NULL) { 932 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 933 taskqueue_free(sc->jme_tq); 934 sc->jme_tq = NULL; 935 } 936 937 if (sc->jme_miibus != NULL) { 938 device_delete_child(dev, sc->jme_miibus); 939 sc->jme_miibus = NULL; 940 } 941 bus_generic_detach(dev); 942 jme_dma_free(sc); 943 944 if (ifp != NULL) { 945 if_free(ifp); 946 sc->jme_ifp = NULL; 947 } 948 949 for (i = 0; i < 1; i++) { 950 if (sc->jme_intrhand[i] != NULL) { 951 bus_teardown_intr(dev, sc->jme_irq[i], 952 sc->jme_intrhand[i]); 953 sc->jme_intrhand[i] = NULL; 954 } 955 } 956 957 if (sc->jme_irq[0] != NULL) 958 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 959 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 960 pci_release_msi(dev); 961 if (sc->jme_res[0] != NULL) 962 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 963 mtx_destroy(&sc->jme_mtx); 964 965 return (0); 966 } 967 968 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 969 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 970 971 static void 972 jme_sysctl_node(struct jme_softc *sc) 973 { 974 struct sysctl_ctx_list *ctx; 975 struct sysctl_oid_list *child, *parent; 976 struct sysctl_oid *tree; 977 struct jme_hw_stats *stats; 978 int error; 979 980 stats = &sc->jme_stats; 981 ctx = device_get_sysctl_ctx(sc->jme_dev); 982 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 983 984 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 985 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_to, 986 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 987 988 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 989 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_pkt, 990 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 991 992 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 993 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_to, 994 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 995 996 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 997 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_pkt, 998 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 999 1000 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1001 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1002 &sc->jme_process_limit, 0, sysctl_hw_jme_proc_limit, "I", 1003 "max number of Rx events to process"); 1004 1005 /* Pull in device tunables. */ 1006 sc->jme_process_limit = JME_PROC_DEFAULT; 1007 error = resource_int_value(device_get_name(sc->jme_dev), 1008 device_get_unit(sc->jme_dev), "process_limit", 1009 &sc->jme_process_limit); 1010 if (error == 0) { 1011 if (sc->jme_process_limit < JME_PROC_MIN || 1012 sc->jme_process_limit > JME_PROC_MAX) { 1013 device_printf(sc->jme_dev, 1014 "process_limit value out of range; " 1015 "using default: %d\n", JME_PROC_DEFAULT); 1016 sc->jme_process_limit = JME_PROC_DEFAULT; 1017 } 1018 } 1019 1020 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1021 error = resource_int_value(device_get_name(sc->jme_dev), 1022 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 1023 if (error == 0) { 1024 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 1025 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 1026 device_printf(sc->jme_dev, 1027 "tx_coal_to value out of range; " 1028 "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 1029 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1030 } 1031 } 1032 1033 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1034 error = resource_int_value(device_get_name(sc->jme_dev), 1035 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 1036 if (error == 0) { 1037 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 1038 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 1039 device_printf(sc->jme_dev, 1040 "tx_coal_pkt value out of range; " 1041 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 1042 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1043 } 1044 } 1045 1046 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1047 error = resource_int_value(device_get_name(sc->jme_dev), 1048 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 1049 if (error == 0) { 1050 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 1051 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 1052 device_printf(sc->jme_dev, 1053 "rx_coal_to value out of range; " 1054 "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 1055 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1056 } 1057 } 1058 1059 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1060 error = resource_int_value(device_get_name(sc->jme_dev), 1061 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 1062 if (error == 0) { 1063 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 1064 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 1065 device_printf(sc->jme_dev, 1066 "tx_coal_pkt value out of range; " 1067 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 1068 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1069 } 1070 } 1071 1072 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 1073 return; 1074 1075 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1076 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "JME statistics"); 1077 parent = SYSCTL_CHILDREN(tree); 1078 1079 /* Rx statistics. */ 1080 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1081 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1082 child = SYSCTL_CHILDREN(tree); 1083 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1084 &stats->rx_good_frames, "Good frames"); 1085 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1086 &stats->rx_crc_errs, "CRC errors"); 1087 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 1088 &stats->rx_mii_errs, "MII errors"); 1089 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1090 &stats->rx_fifo_oflows, "FIFO overflows"); 1091 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 1092 &stats->rx_desc_empty, "Descriptor empty"); 1093 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1094 &stats->rx_bad_frames, "Bad frames"); 1095 1096 /* Tx statistics. */ 1097 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1098 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1099 child = SYSCTL_CHILDREN(tree); 1100 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1101 &stats->tx_good_frames, "Good frames"); 1102 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1103 &stats->tx_bad_frames, "Bad frames"); 1104 } 1105 1106 #undef JME_SYSCTL_STAT_ADD32 1107 1108 struct jme_dmamap_arg { 1109 bus_addr_t jme_busaddr; 1110 }; 1111 1112 static void 1113 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1114 { 1115 struct jme_dmamap_arg *ctx; 1116 1117 if (error != 0) 1118 return; 1119 1120 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1121 1122 ctx = (struct jme_dmamap_arg *)arg; 1123 ctx->jme_busaddr = segs[0].ds_addr; 1124 } 1125 1126 static int 1127 jme_dma_alloc(struct jme_softc *sc) 1128 { 1129 struct jme_dmamap_arg ctx; 1130 struct jme_txdesc *txd; 1131 struct jme_rxdesc *rxd; 1132 bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1133 int error, i; 1134 1135 lowaddr = BUS_SPACE_MAXADDR; 1136 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1137 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1138 1139 again: 1140 /* Create parent ring tag. */ 1141 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1142 1, 0, /* algnmnt, boundary */ 1143 lowaddr, /* lowaddr */ 1144 BUS_SPACE_MAXADDR, /* highaddr */ 1145 NULL, NULL, /* filter, filterarg */ 1146 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1147 0, /* nsegments */ 1148 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1149 0, /* flags */ 1150 NULL, NULL, /* lockfunc, lockarg */ 1151 &sc->jme_cdata.jme_ring_tag); 1152 if (error != 0) { 1153 device_printf(sc->jme_dev, 1154 "could not create parent ring DMA tag.\n"); 1155 goto fail; 1156 } 1157 /* Create tag for Tx ring. */ 1158 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1159 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1160 BUS_SPACE_MAXADDR, /* lowaddr */ 1161 BUS_SPACE_MAXADDR, /* highaddr */ 1162 NULL, NULL, /* filter, filterarg */ 1163 JME_TX_RING_SIZE, /* maxsize */ 1164 1, /* nsegments */ 1165 JME_TX_RING_SIZE, /* maxsegsize */ 1166 0, /* flags */ 1167 NULL, NULL, /* lockfunc, lockarg */ 1168 &sc->jme_cdata.jme_tx_ring_tag); 1169 if (error != 0) { 1170 device_printf(sc->jme_dev, 1171 "could not allocate Tx ring DMA tag.\n"); 1172 goto fail; 1173 } 1174 1175 /* Create tag for Rx ring. */ 1176 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1177 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1178 lowaddr, /* lowaddr */ 1179 BUS_SPACE_MAXADDR, /* highaddr */ 1180 NULL, NULL, /* filter, filterarg */ 1181 JME_RX_RING_SIZE, /* maxsize */ 1182 1, /* nsegments */ 1183 JME_RX_RING_SIZE, /* maxsegsize */ 1184 0, /* flags */ 1185 NULL, NULL, /* lockfunc, lockarg */ 1186 &sc->jme_cdata.jme_rx_ring_tag); 1187 if (error != 0) { 1188 device_printf(sc->jme_dev, 1189 "could not allocate Rx ring DMA tag.\n"); 1190 goto fail; 1191 } 1192 1193 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1194 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1195 (void **)&sc->jme_rdata.jme_tx_ring, 1196 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1197 &sc->jme_cdata.jme_tx_ring_map); 1198 if (error != 0) { 1199 device_printf(sc->jme_dev, 1200 "could not allocate DMA'able memory for Tx ring.\n"); 1201 goto fail; 1202 } 1203 1204 ctx.jme_busaddr = 0; 1205 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1206 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1207 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1208 if (error != 0 || ctx.jme_busaddr == 0) { 1209 device_printf(sc->jme_dev, 1210 "could not load DMA'able memory for Tx ring.\n"); 1211 goto fail; 1212 } 1213 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1214 1215 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1216 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1217 (void **)&sc->jme_rdata.jme_rx_ring, 1218 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1219 &sc->jme_cdata.jme_rx_ring_map); 1220 if (error != 0) { 1221 device_printf(sc->jme_dev, 1222 "could not allocate DMA'able memory for Rx ring.\n"); 1223 goto fail; 1224 } 1225 1226 ctx.jme_busaddr = 0; 1227 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1228 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1229 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1230 if (error != 0 || ctx.jme_busaddr == 0) { 1231 device_printf(sc->jme_dev, 1232 "could not load DMA'able memory for Rx ring.\n"); 1233 goto fail; 1234 } 1235 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1236 1237 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1238 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1239 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1240 JME_TX_RING_SIZE; 1241 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1242 JME_RX_RING_SIZE; 1243 if ((JME_ADDR_HI(tx_ring_end) != 1244 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1245 (JME_ADDR_HI(rx_ring_end) != 1246 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1247 device_printf(sc->jme_dev, "4GB boundary crossed, " 1248 "switching to 32bit DMA address mode.\n"); 1249 jme_dma_free(sc); 1250 /* Limit DMA address space to 32bit and try again. */ 1251 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1252 goto again; 1253 } 1254 } 1255 1256 lowaddr = BUS_SPACE_MAXADDR; 1257 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1258 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1259 /* Create parent buffer tag. */ 1260 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1261 1, 0, /* algnmnt, boundary */ 1262 lowaddr, /* lowaddr */ 1263 BUS_SPACE_MAXADDR, /* highaddr */ 1264 NULL, NULL, /* filter, filterarg */ 1265 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1266 0, /* nsegments */ 1267 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1268 0, /* flags */ 1269 NULL, NULL, /* lockfunc, lockarg */ 1270 &sc->jme_cdata.jme_buffer_tag); 1271 if (error != 0) { 1272 device_printf(sc->jme_dev, 1273 "could not create parent buffer DMA tag.\n"); 1274 goto fail; 1275 } 1276 1277 /* Create shadow status block tag. */ 1278 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1279 JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1280 BUS_SPACE_MAXADDR, /* lowaddr */ 1281 BUS_SPACE_MAXADDR, /* highaddr */ 1282 NULL, NULL, /* filter, filterarg */ 1283 JME_SSB_SIZE, /* maxsize */ 1284 1, /* nsegments */ 1285 JME_SSB_SIZE, /* maxsegsize */ 1286 0, /* flags */ 1287 NULL, NULL, /* lockfunc, lockarg */ 1288 &sc->jme_cdata.jme_ssb_tag); 1289 if (error != 0) { 1290 device_printf(sc->jme_dev, 1291 "could not create shared status block DMA tag.\n"); 1292 goto fail; 1293 } 1294 1295 /* Create tag for Tx buffers. */ 1296 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1297 1, 0, /* algnmnt, boundary */ 1298 BUS_SPACE_MAXADDR, /* lowaddr */ 1299 BUS_SPACE_MAXADDR, /* highaddr */ 1300 NULL, NULL, /* filter, filterarg */ 1301 JME_TSO_MAXSIZE, /* maxsize */ 1302 JME_MAXTXSEGS, /* nsegments */ 1303 JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1304 0, /* flags */ 1305 NULL, NULL, /* lockfunc, lockarg */ 1306 &sc->jme_cdata.jme_tx_tag); 1307 if (error != 0) { 1308 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1309 goto fail; 1310 } 1311 1312 /* Create tag for Rx buffers. */ 1313 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1314 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1315 BUS_SPACE_MAXADDR, /* lowaddr */ 1316 BUS_SPACE_MAXADDR, /* highaddr */ 1317 NULL, NULL, /* filter, filterarg */ 1318 MCLBYTES, /* maxsize */ 1319 1, /* nsegments */ 1320 MCLBYTES, /* maxsegsize */ 1321 0, /* flags */ 1322 NULL, NULL, /* lockfunc, lockarg */ 1323 &sc->jme_cdata.jme_rx_tag); 1324 if (error != 0) { 1325 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1326 goto fail; 1327 } 1328 1329 /* 1330 * Allocate DMA'able memory and load the DMA map for shared 1331 * status block. 1332 */ 1333 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1334 (void **)&sc->jme_rdata.jme_ssb_block, 1335 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1336 &sc->jme_cdata.jme_ssb_map); 1337 if (error != 0) { 1338 device_printf(sc->jme_dev, "could not allocate DMA'able " 1339 "memory for shared status block.\n"); 1340 goto fail; 1341 } 1342 1343 ctx.jme_busaddr = 0; 1344 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1345 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1346 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1347 if (error != 0 || ctx.jme_busaddr == 0) { 1348 device_printf(sc->jme_dev, "could not load DMA'able memory " 1349 "for shared status block.\n"); 1350 goto fail; 1351 } 1352 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1353 1354 /* Create DMA maps for Tx buffers. */ 1355 for (i = 0; i < JME_TX_RING_CNT; i++) { 1356 txd = &sc->jme_cdata.jme_txdesc[i]; 1357 txd->tx_m = NULL; 1358 txd->tx_dmamap = NULL; 1359 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1360 &txd->tx_dmamap); 1361 if (error != 0) { 1362 device_printf(sc->jme_dev, 1363 "could not create Tx dmamap.\n"); 1364 goto fail; 1365 } 1366 } 1367 /* Create DMA maps for Rx buffers. */ 1368 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1369 &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1370 device_printf(sc->jme_dev, 1371 "could not create spare Rx dmamap.\n"); 1372 goto fail; 1373 } 1374 for (i = 0; i < JME_RX_RING_CNT; i++) { 1375 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1376 rxd->rx_m = NULL; 1377 rxd->rx_dmamap = NULL; 1378 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1379 &rxd->rx_dmamap); 1380 if (error != 0) { 1381 device_printf(sc->jme_dev, 1382 "could not create Rx dmamap.\n"); 1383 goto fail; 1384 } 1385 } 1386 1387 fail: 1388 return (error); 1389 } 1390 1391 static void 1392 jme_dma_free(struct jme_softc *sc) 1393 { 1394 struct jme_txdesc *txd; 1395 struct jme_rxdesc *rxd; 1396 int i; 1397 1398 /* Tx ring */ 1399 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1400 if (sc->jme_rdata.jme_tx_ring_paddr) 1401 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1402 sc->jme_cdata.jme_tx_ring_map); 1403 if (sc->jme_rdata.jme_tx_ring) 1404 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1405 sc->jme_rdata.jme_tx_ring, 1406 sc->jme_cdata.jme_tx_ring_map); 1407 sc->jme_rdata.jme_tx_ring = NULL; 1408 sc->jme_rdata.jme_tx_ring_paddr = 0; 1409 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1410 sc->jme_cdata.jme_tx_ring_tag = NULL; 1411 } 1412 /* Rx ring */ 1413 if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1414 if (sc->jme_rdata.jme_rx_ring_paddr) 1415 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1416 sc->jme_cdata.jme_rx_ring_map); 1417 if (sc->jme_rdata.jme_rx_ring) 1418 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1419 sc->jme_rdata.jme_rx_ring, 1420 sc->jme_cdata.jme_rx_ring_map); 1421 sc->jme_rdata.jme_rx_ring = NULL; 1422 sc->jme_rdata.jme_rx_ring_paddr = 0; 1423 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1424 sc->jme_cdata.jme_rx_ring_tag = NULL; 1425 } 1426 /* Tx buffers */ 1427 if (sc->jme_cdata.jme_tx_tag != NULL) { 1428 for (i = 0; i < JME_TX_RING_CNT; i++) { 1429 txd = &sc->jme_cdata.jme_txdesc[i]; 1430 if (txd->tx_dmamap != NULL) { 1431 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1432 txd->tx_dmamap); 1433 txd->tx_dmamap = NULL; 1434 } 1435 } 1436 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1437 sc->jme_cdata.jme_tx_tag = NULL; 1438 } 1439 /* Rx buffers */ 1440 if (sc->jme_cdata.jme_rx_tag != NULL) { 1441 for (i = 0; i < JME_RX_RING_CNT; i++) { 1442 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1443 if (rxd->rx_dmamap != NULL) { 1444 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1445 rxd->rx_dmamap); 1446 rxd->rx_dmamap = NULL; 1447 } 1448 } 1449 if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1450 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1451 sc->jme_cdata.jme_rx_sparemap); 1452 sc->jme_cdata.jme_rx_sparemap = NULL; 1453 } 1454 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1455 sc->jme_cdata.jme_rx_tag = NULL; 1456 } 1457 1458 /* Shared status block. */ 1459 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1460 if (sc->jme_rdata.jme_ssb_block_paddr) 1461 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1462 sc->jme_cdata.jme_ssb_map); 1463 if (sc->jme_rdata.jme_ssb_block) 1464 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1465 sc->jme_rdata.jme_ssb_block, 1466 sc->jme_cdata.jme_ssb_map); 1467 sc->jme_rdata.jme_ssb_block = NULL; 1468 sc->jme_rdata.jme_ssb_block_paddr = 0; 1469 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1470 sc->jme_cdata.jme_ssb_tag = NULL; 1471 } 1472 1473 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1474 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1475 sc->jme_cdata.jme_buffer_tag = NULL; 1476 } 1477 if (sc->jme_cdata.jme_ring_tag != NULL) { 1478 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1479 sc->jme_cdata.jme_ring_tag = NULL; 1480 } 1481 } 1482 1483 /* 1484 * Make sure the interface is stopped at reboot time. 1485 */ 1486 static int 1487 jme_shutdown(device_t dev) 1488 { 1489 1490 return (jme_suspend(dev)); 1491 } 1492 1493 /* 1494 * Unlike other ethernet controllers, JMC250 requires 1495 * explicit resetting link speed to 10/100Mbps as gigabit 1496 * link will cunsume more power than 375mA. 1497 * Note, we reset the link speed to 10/100Mbps with 1498 * auto-negotiation but we don't know whether that operation 1499 * would succeed or not as we have no control after powering 1500 * off. If the renegotiation fail WOL may not work. Running 1501 * at 1Gbps draws more power than 375mA at 3.3V which is 1502 * specified in PCI specification and that would result in 1503 * complete shutdowning power to ethernet controller. 1504 * 1505 * TODO 1506 * Save current negotiated media speed/duplex/flow-control 1507 * to softc and restore the same link again after resuming. 1508 * PHY handling such as power down/resetting to 100Mbps 1509 * may be better handled in suspend method in phy driver. 1510 */ 1511 static void 1512 jme_setlinkspeed(struct jme_softc *sc) 1513 { 1514 struct mii_data *mii; 1515 int aneg, i; 1516 1517 JME_LOCK_ASSERT(sc); 1518 1519 mii = device_get_softc(sc->jme_miibus); 1520 mii_pollstat(mii); 1521 aneg = 0; 1522 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1523 switch IFM_SUBTYPE(mii->mii_media_active) { 1524 case IFM_10_T: 1525 case IFM_100_TX: 1526 return; 1527 case IFM_1000_T: 1528 aneg++; 1529 default: 1530 break; 1531 } 1532 } 1533 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1534 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1535 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1536 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1537 BMCR_AUTOEN | BMCR_STARTNEG); 1538 DELAY(1000); 1539 if (aneg != 0) { 1540 /* Poll link state until jme(4) get a 10/100 link. */ 1541 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1542 mii_pollstat(mii); 1543 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1544 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1545 case IFM_10_T: 1546 case IFM_100_TX: 1547 jme_mac_config(sc); 1548 return; 1549 default: 1550 break; 1551 } 1552 } 1553 JME_UNLOCK(sc); 1554 pause("jmelnk", hz); 1555 JME_LOCK(sc); 1556 } 1557 if (i == MII_ANEGTICKS_GIGE) 1558 device_printf(sc->jme_dev, "establishing link failed, " 1559 "WOL may not work!"); 1560 } 1561 /* 1562 * No link, force MAC to have 100Mbps, full-duplex link. 1563 * This is the last resort and may/may not work. 1564 */ 1565 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1566 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1567 jme_mac_config(sc); 1568 } 1569 1570 static void 1571 jme_setwol(struct jme_softc *sc) 1572 { 1573 if_t ifp; 1574 uint32_t gpr, pmcs; 1575 uint16_t pmstat; 1576 int pmc; 1577 1578 JME_LOCK_ASSERT(sc); 1579 1580 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1581 /* Remove Tx MAC/offload clock to save more power. */ 1582 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1583 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1584 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1585 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1586 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 1587 CSR_WRITE_4(sc, JME_GPREG1, 1588 CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS); 1589 /* No PME capability, PHY power down. */ 1590 jme_phy_down(sc); 1591 return; 1592 } 1593 1594 ifp = sc->jme_ifp; 1595 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1596 pmcs = CSR_READ_4(sc, JME_PMCS); 1597 pmcs &= ~PMCS_WOL_ENB_MASK; 1598 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1599 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1600 /* Enable PME message. */ 1601 gpr |= GPREG0_PME_ENB; 1602 /* For gigabit controllers, reset link speed to 10/100. */ 1603 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1604 jme_setlinkspeed(sc); 1605 } 1606 1607 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1608 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1609 /* Remove Tx MAC/offload clock to save more power. */ 1610 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1611 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1612 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1613 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1614 /* Request PME. */ 1615 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1616 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1617 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1618 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1619 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1620 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1621 /* No WOL, PHY power down. */ 1622 jme_phy_down(sc); 1623 } 1624 } 1625 1626 static int 1627 jme_suspend(device_t dev) 1628 { 1629 struct jme_softc *sc; 1630 1631 sc = device_get_softc(dev); 1632 1633 JME_LOCK(sc); 1634 jme_stop(sc); 1635 jme_setwol(sc); 1636 JME_UNLOCK(sc); 1637 1638 return (0); 1639 } 1640 1641 static int 1642 jme_resume(device_t dev) 1643 { 1644 struct jme_softc *sc; 1645 if_t ifp; 1646 uint16_t pmstat; 1647 int pmc; 1648 1649 sc = device_get_softc(dev); 1650 1651 JME_LOCK(sc); 1652 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) == 0) { 1653 pmstat = pci_read_config(sc->jme_dev, 1654 pmc + PCIR_POWER_STATUS, 2); 1655 /* Disable PME clear PME status. */ 1656 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1657 pci_write_config(sc->jme_dev, 1658 pmc + PCIR_POWER_STATUS, pmstat, 2); 1659 } 1660 /* Wakeup PHY. */ 1661 jme_phy_up(sc); 1662 ifp = sc->jme_ifp; 1663 if ((if_getflags(ifp) & IFF_UP) != 0) { 1664 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1665 jme_init_locked(sc); 1666 } 1667 1668 JME_UNLOCK(sc); 1669 1670 return (0); 1671 } 1672 1673 static int 1674 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1675 { 1676 struct jme_txdesc *txd; 1677 struct jme_desc *desc; 1678 struct mbuf *m; 1679 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1680 int error, i, nsegs, prod; 1681 uint32_t cflags, tsosegsz; 1682 1683 JME_LOCK_ASSERT(sc); 1684 1685 M_ASSERTPKTHDR((*m_head)); 1686 1687 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1688 /* 1689 * Due to the adherence to NDIS specification JMC250 1690 * assumes upper stack computed TCP pseudo checksum 1691 * without including payload length. This breaks 1692 * checksum offload for TSO case so recompute TCP 1693 * pseudo checksum for JMC250. Hopefully this wouldn't 1694 * be much burden on modern CPUs. 1695 */ 1696 struct ether_header *eh; 1697 struct ip *ip; 1698 struct tcphdr *tcp; 1699 uint32_t ip_off, poff; 1700 1701 if (M_WRITABLE(*m_head) == 0) { 1702 /* Get a writable copy. */ 1703 m = m_dup(*m_head, M_NOWAIT); 1704 m_freem(*m_head); 1705 if (m == NULL) { 1706 *m_head = NULL; 1707 return (ENOBUFS); 1708 } 1709 *m_head = m; 1710 } 1711 ip_off = sizeof(struct ether_header); 1712 m = m_pullup(*m_head, ip_off); 1713 if (m == NULL) { 1714 *m_head = NULL; 1715 return (ENOBUFS); 1716 } 1717 eh = mtod(m, struct ether_header *); 1718 /* Check the existence of VLAN tag. */ 1719 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1720 ip_off = sizeof(struct ether_vlan_header); 1721 m = m_pullup(m, ip_off); 1722 if (m == NULL) { 1723 *m_head = NULL; 1724 return (ENOBUFS); 1725 } 1726 } 1727 m = m_pullup(m, ip_off + sizeof(struct ip)); 1728 if (m == NULL) { 1729 *m_head = NULL; 1730 return (ENOBUFS); 1731 } 1732 ip = (struct ip *)(mtod(m, char *) + ip_off); 1733 poff = ip_off + (ip->ip_hl << 2); 1734 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1735 if (m == NULL) { 1736 *m_head = NULL; 1737 return (ENOBUFS); 1738 } 1739 /* 1740 * Reset IP checksum and recompute TCP pseudo 1741 * checksum that NDIS specification requires. 1742 */ 1743 ip = (struct ip *)(mtod(m, char *) + ip_off); 1744 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1745 ip->ip_sum = 0; 1746 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1747 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1748 ip->ip_dst.s_addr, 1749 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1750 /* No need to TSO, force IP checksum offload. */ 1751 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1752 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1753 } else 1754 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1755 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1756 *m_head = m; 1757 } 1758 1759 prod = sc->jme_cdata.jme_tx_prod; 1760 txd = &sc->jme_cdata.jme_txdesc[prod]; 1761 1762 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1763 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1764 if (error == EFBIG) { 1765 m = m_collapse(*m_head, M_NOWAIT, JME_MAXTXSEGS); 1766 if (m == NULL) { 1767 m_freem(*m_head); 1768 *m_head = NULL; 1769 return (ENOMEM); 1770 } 1771 *m_head = m; 1772 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1773 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1774 if (error != 0) { 1775 m_freem(*m_head); 1776 *m_head = NULL; 1777 return (error); 1778 } 1779 } else if (error != 0) 1780 return (error); 1781 if (nsegs == 0) { 1782 m_freem(*m_head); 1783 *m_head = NULL; 1784 return (EIO); 1785 } 1786 1787 /* 1788 * Check descriptor overrun. Leave one free descriptor. 1789 * Since we always use 64bit address mode for transmitting, 1790 * each Tx request requires one more dummy descriptor. 1791 */ 1792 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1793 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1794 return (ENOBUFS); 1795 } 1796 1797 m = *m_head; 1798 cflags = 0; 1799 tsosegsz = 0; 1800 /* Configure checksum offload and TSO. */ 1801 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1802 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 1803 JME_TD_MSS_SHIFT; 1804 cflags |= JME_TD_TSO; 1805 } else { 1806 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1807 cflags |= JME_TD_IPCSUM; 1808 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1809 cflags |= JME_TD_TCPCSUM; 1810 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1811 cflags |= JME_TD_UDPCSUM; 1812 } 1813 /* Configure VLAN. */ 1814 if ((m->m_flags & M_VLANTAG) != 0) { 1815 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1816 cflags |= JME_TD_VLAN_TAG; 1817 } 1818 1819 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1820 desc->flags = htole32(cflags); 1821 desc->buflen = htole32(tsosegsz); 1822 desc->addr_hi = htole32(m->m_pkthdr.len); 1823 desc->addr_lo = 0; 1824 sc->jme_cdata.jme_tx_cnt++; 1825 JME_DESC_INC(prod, JME_TX_RING_CNT); 1826 for (i = 0; i < nsegs; i++) { 1827 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1828 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1829 desc->buflen = htole32(txsegs[i].ds_len); 1830 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1831 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1832 sc->jme_cdata.jme_tx_cnt++; 1833 JME_DESC_INC(prod, JME_TX_RING_CNT); 1834 } 1835 1836 /* Update producer index. */ 1837 sc->jme_cdata.jme_tx_prod = prod; 1838 /* 1839 * Finally request interrupt and give the first descriptor 1840 * owenership to hardware. 1841 */ 1842 desc = txd->tx_desc; 1843 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1844 1845 txd->tx_m = m; 1846 txd->tx_ndesc = nsegs + 1; 1847 1848 /* Sync descriptors. */ 1849 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1850 BUS_DMASYNC_PREWRITE); 1851 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1852 sc->jme_cdata.jme_tx_ring_map, 1853 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1854 1855 return (0); 1856 } 1857 1858 static void 1859 jme_start(if_t ifp) 1860 { 1861 struct jme_softc *sc; 1862 1863 sc = if_getsoftc(ifp); 1864 JME_LOCK(sc); 1865 jme_start_locked(ifp); 1866 JME_UNLOCK(sc); 1867 } 1868 1869 static void 1870 jme_start_locked(if_t ifp) 1871 { 1872 struct jme_softc *sc; 1873 struct mbuf *m_head; 1874 int enq; 1875 1876 sc = if_getsoftc(ifp); 1877 1878 JME_LOCK_ASSERT(sc); 1879 1880 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1881 jme_txeof(sc); 1882 1883 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1884 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) 1885 return; 1886 1887 for (enq = 0; !if_sendq_empty(ifp); ) { 1888 m_head = if_dequeue(ifp); 1889 if (m_head == NULL) 1890 break; 1891 /* 1892 * Pack the data into the transmit ring. If we 1893 * don't have room, set the OACTIVE flag and wait 1894 * for the NIC to drain the ring. 1895 */ 1896 if (jme_encap(sc, &m_head)) { 1897 if (m_head == NULL) 1898 break; 1899 if_sendq_prepend(ifp, m_head); 1900 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1901 break; 1902 } 1903 1904 enq++; 1905 /* 1906 * If there's a BPF listener, bounce a copy of this frame 1907 * to him. 1908 */ 1909 ETHER_BPF_MTAP(ifp, m_head); 1910 } 1911 1912 if (enq > 0) { 1913 /* 1914 * Reading TXCSR takes very long time under heavy load 1915 * so cache TXCSR value and writes the ORed value with 1916 * the kick command to the TXCSR. This saves one register 1917 * access cycle. 1918 */ 1919 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1920 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1921 /* Set a timeout in case the chip goes out to lunch. */ 1922 sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1923 } 1924 } 1925 1926 static void 1927 jme_watchdog(struct jme_softc *sc) 1928 { 1929 if_t ifp; 1930 1931 JME_LOCK_ASSERT(sc); 1932 1933 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1934 return; 1935 1936 ifp = sc->jme_ifp; 1937 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1938 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1939 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1940 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1941 jme_init_locked(sc); 1942 return; 1943 } 1944 jme_txeof(sc); 1945 if (sc->jme_cdata.jme_tx_cnt == 0) { 1946 if_printf(sc->jme_ifp, 1947 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1948 if (!if_sendq_empty(ifp)) 1949 jme_start_locked(ifp); 1950 return; 1951 } 1952 1953 if_printf(sc->jme_ifp, "watchdog timeout\n"); 1954 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1955 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1956 jme_init_locked(sc); 1957 if (!if_sendq_empty(ifp)) 1958 jme_start_locked(ifp); 1959 } 1960 1961 static int 1962 jme_ioctl(if_t ifp, u_long cmd, caddr_t data) 1963 { 1964 struct jme_softc *sc; 1965 struct ifreq *ifr; 1966 struct mii_data *mii; 1967 uint32_t reg; 1968 int error, mask; 1969 1970 sc = if_getsoftc(ifp); 1971 ifr = (struct ifreq *)data; 1972 error = 0; 1973 switch (cmd) { 1974 case SIOCSIFMTU: 1975 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1976 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1977 ifr->ifr_mtu > JME_MAX_MTU)) { 1978 error = EINVAL; 1979 break; 1980 } 1981 1982 if (if_getmtu(ifp) != ifr->ifr_mtu) { 1983 /* 1984 * No special configuration is required when interface 1985 * MTU is changed but availability of TSO/Tx checksum 1986 * offload should be chcked against new MTU size as 1987 * FIFO size is just 2K. 1988 */ 1989 JME_LOCK(sc); 1990 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1991 if_setcapenablebit(ifp, 0, 1992 IFCAP_TXCSUM | IFCAP_TSO4); 1993 if_sethwassistbits(ifp, 0, 1994 JME_CSUM_FEATURES | CSUM_TSO); 1995 VLAN_CAPABILITIES(ifp); 1996 } 1997 if_setmtu(ifp, ifr->ifr_mtu); 1998 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1999 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2000 jme_init_locked(sc); 2001 } 2002 JME_UNLOCK(sc); 2003 } 2004 break; 2005 case SIOCSIFFLAGS: 2006 JME_LOCK(sc); 2007 if ((if_getflags(ifp) & IFF_UP) != 0) { 2008 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2009 if (((if_getflags(ifp) ^ sc->jme_if_flags) 2010 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2011 jme_set_filter(sc); 2012 } else { 2013 if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 2014 jme_init_locked(sc); 2015 } 2016 } else { 2017 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2018 jme_stop(sc); 2019 } 2020 sc->jme_if_flags = if_getflags(ifp); 2021 JME_UNLOCK(sc); 2022 break; 2023 case SIOCADDMULTI: 2024 case SIOCDELMULTI: 2025 JME_LOCK(sc); 2026 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2027 jme_set_filter(sc); 2028 JME_UNLOCK(sc); 2029 break; 2030 case SIOCSIFMEDIA: 2031 case SIOCGIFMEDIA: 2032 mii = device_get_softc(sc->jme_miibus); 2033 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2034 break; 2035 case SIOCSIFCAP: 2036 JME_LOCK(sc); 2037 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2038 if ((mask & IFCAP_TXCSUM) != 0 && 2039 if_getmtu(ifp) < JME_TX_FIFO_SIZE) { 2040 if ((IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 2041 if_togglecapenable(ifp, IFCAP_TXCSUM); 2042 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 2043 if_sethwassistbits(ifp, JME_CSUM_FEATURES, 0); 2044 else 2045 if_sethwassistbits(ifp, 0, JME_CSUM_FEATURES); 2046 } 2047 } 2048 if ((mask & IFCAP_RXCSUM) != 0 && 2049 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) { 2050 if_togglecapenable(ifp, IFCAP_RXCSUM); 2051 reg = CSR_READ_4(sc, JME_RXMAC); 2052 reg &= ~RXMAC_CSUM_ENB; 2053 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2054 reg |= RXMAC_CSUM_ENB; 2055 CSR_WRITE_4(sc, JME_RXMAC, reg); 2056 } 2057 if ((mask & IFCAP_TSO4) != 0 && 2058 if_getmtu(ifp) < JME_TX_FIFO_SIZE) { 2059 if ((IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) { 2060 if_togglecapenable(ifp, IFCAP_TSO4); 2061 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 2062 if_sethwassistbits(ifp, CSUM_TSO, 0); 2063 else 2064 if_sethwassistbits(ifp, 0, CSUM_TSO); 2065 } 2066 } 2067 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2068 (IFCAP_WOL_MAGIC & if_getcapabilities(ifp)) != 0) 2069 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2070 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2071 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2072 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2073 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2074 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2075 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2076 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2077 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 2078 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2079 jme_set_vlan(sc); 2080 } 2081 JME_UNLOCK(sc); 2082 VLAN_CAPABILITIES(ifp); 2083 break; 2084 default: 2085 error = ether_ioctl(ifp, cmd, data); 2086 break; 2087 } 2088 2089 return (error); 2090 } 2091 2092 static void 2093 jme_mac_config(struct jme_softc *sc) 2094 { 2095 struct mii_data *mii; 2096 uint32_t ghc, gpreg, rxmac, txmac, txpause; 2097 uint32_t txclk; 2098 2099 JME_LOCK_ASSERT(sc); 2100 2101 mii = device_get_softc(sc->jme_miibus); 2102 2103 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2104 DELAY(10); 2105 CSR_WRITE_4(sc, JME_GHC, 0); 2106 ghc = 0; 2107 txclk = 0; 2108 rxmac = CSR_READ_4(sc, JME_RXMAC); 2109 rxmac &= ~RXMAC_FC_ENB; 2110 txmac = CSR_READ_4(sc, JME_TXMAC); 2111 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2112 txpause = CSR_READ_4(sc, JME_TXPFC); 2113 txpause &= ~TXPFC_PAUSE_ENB; 2114 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2115 ghc |= GHC_FULL_DUPLEX; 2116 rxmac &= ~RXMAC_COLL_DET_ENB; 2117 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2118 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2119 TXMAC_FRAME_BURST); 2120 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2121 txpause |= TXPFC_PAUSE_ENB; 2122 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2123 rxmac |= RXMAC_FC_ENB; 2124 /* Disable retry transmit timer/retry limit. */ 2125 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2126 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2127 } else { 2128 rxmac |= RXMAC_COLL_DET_ENB; 2129 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2130 /* Enable retry transmit timer/retry limit. */ 2131 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2132 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2133 } 2134 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2135 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2136 case IFM_10_T: 2137 ghc |= GHC_SPEED_10; 2138 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2139 break; 2140 case IFM_100_TX: 2141 ghc |= GHC_SPEED_100; 2142 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2143 break; 2144 case IFM_1000_T: 2145 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2146 break; 2147 ghc |= GHC_SPEED_1000; 2148 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2149 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2150 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2151 break; 2152 default: 2153 break; 2154 } 2155 if (sc->jme_rev == DEVICEID_JMC250 && 2156 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2157 /* 2158 * Workaround occasional packet loss issue of JMC250 A2 2159 * when it runs on half-duplex media. 2160 */ 2161 gpreg = CSR_READ_4(sc, JME_GPREG1); 2162 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2163 gpreg &= ~GPREG1_HDPX_FIX; 2164 else 2165 gpreg |= GPREG1_HDPX_FIX; 2166 CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2167 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2168 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2169 /* Extend interface FIFO depth. */ 2170 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2171 0x1B, 0x0000); 2172 } else { 2173 /* Select default interface FIFO depth. */ 2174 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2175 0x1B, 0x0004); 2176 } 2177 } 2178 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2179 ghc |= txclk; 2180 CSR_WRITE_4(sc, JME_GHC, ghc); 2181 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2182 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2183 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2184 } 2185 2186 static void 2187 jme_link_task(void *arg, int pending) 2188 { 2189 struct jme_softc *sc; 2190 struct mii_data *mii; 2191 if_t ifp; 2192 struct jme_txdesc *txd; 2193 bus_addr_t paddr; 2194 int i; 2195 2196 sc = (struct jme_softc *)arg; 2197 2198 JME_LOCK(sc); 2199 mii = device_get_softc(sc->jme_miibus); 2200 ifp = sc->jme_ifp; 2201 if (mii == NULL || ifp == NULL || 2202 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2203 JME_UNLOCK(sc); 2204 return; 2205 } 2206 2207 sc->jme_flags &= ~JME_FLAG_LINK; 2208 if ((mii->mii_media_status & IFM_AVALID) != 0) { 2209 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2210 case IFM_10_T: 2211 case IFM_100_TX: 2212 sc->jme_flags |= JME_FLAG_LINK; 2213 break; 2214 case IFM_1000_T: 2215 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2216 break; 2217 sc->jme_flags |= JME_FLAG_LINK; 2218 break; 2219 default: 2220 break; 2221 } 2222 } 2223 2224 /* 2225 * Disabling Rx/Tx MACs have a side-effect of resetting 2226 * JME_TXNDA/JME_RXNDA register to the first address of 2227 * Tx/Rx descriptor address. So driver should reset its 2228 * internal procucer/consumer pointer and reclaim any 2229 * allocated resources. Note, just saving the value of 2230 * JME_TXNDA and JME_RXNDA registers before stopping MAC 2231 * and restoring JME_TXNDA/JME_RXNDA register is not 2232 * sufficient to make sure correct MAC state because 2233 * stopping MAC operation can take a while and hardware 2234 * might have updated JME_TXNDA/JME_RXNDA registers 2235 * during the stop operation. 2236 */ 2237 /* Block execution of task. */ 2238 taskqueue_block(sc->jme_tq); 2239 /* Disable interrupts and stop driver. */ 2240 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2241 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2242 callout_stop(&sc->jme_tick_ch); 2243 sc->jme_watchdog_timer = 0; 2244 2245 /* Stop receiver/transmitter. */ 2246 jme_stop_rx(sc); 2247 jme_stop_tx(sc); 2248 2249 /* XXX Drain all queued tasks. */ 2250 JME_UNLOCK(sc); 2251 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2252 JME_LOCK(sc); 2253 2254 if (sc->jme_cdata.jme_rxhead != NULL) 2255 m_freem(sc->jme_cdata.jme_rxhead); 2256 JME_RXCHAIN_RESET(sc); 2257 jme_txeof(sc); 2258 if (sc->jme_cdata.jme_tx_cnt != 0) { 2259 /* Remove queued packets for transmit. */ 2260 for (i = 0; i < JME_TX_RING_CNT; i++) { 2261 txd = &sc->jme_cdata.jme_txdesc[i]; 2262 if (txd->tx_m != NULL) { 2263 bus_dmamap_sync( 2264 sc->jme_cdata.jme_tx_tag, 2265 txd->tx_dmamap, 2266 BUS_DMASYNC_POSTWRITE); 2267 bus_dmamap_unload( 2268 sc->jme_cdata.jme_tx_tag, 2269 txd->tx_dmamap); 2270 m_freem(txd->tx_m); 2271 txd->tx_m = NULL; 2272 txd->tx_ndesc = 0; 2273 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2274 } 2275 } 2276 } 2277 2278 /* 2279 * Reuse configured Rx descriptors and reset 2280 * producer/consumer index. 2281 */ 2282 sc->jme_cdata.jme_rx_cons = 0; 2283 sc->jme_morework = 0; 2284 jme_init_tx_ring(sc); 2285 /* Initialize shadow status block. */ 2286 jme_init_ssb(sc); 2287 2288 /* Program MAC with resolved speed/duplex/flow-control. */ 2289 if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2290 jme_mac_config(sc); 2291 jme_stats_clear(sc); 2292 2293 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2294 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2295 2296 /* Set Tx ring address to the hardware. */ 2297 paddr = JME_TX_RING_ADDR(sc, 0); 2298 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2299 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2300 2301 /* Set Rx ring address to the hardware. */ 2302 paddr = JME_RX_RING_ADDR(sc, 0); 2303 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2304 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2305 2306 /* Restart receiver/transmitter. */ 2307 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2308 RXCSR_RXQ_START); 2309 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2310 /* Lastly enable TX/RX clock. */ 2311 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2312 CSR_WRITE_4(sc, JME_GHC, 2313 CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS); 2314 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 2315 CSR_WRITE_4(sc, JME_GPREG1, 2316 CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS); 2317 } 2318 2319 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2320 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2321 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2322 /* Unblock execution of task. */ 2323 taskqueue_unblock(sc->jme_tq); 2324 /* Reenable interrupts. */ 2325 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2326 2327 JME_UNLOCK(sc); 2328 } 2329 2330 static int 2331 jme_intr(void *arg) 2332 { 2333 struct jme_softc *sc; 2334 uint32_t status; 2335 2336 sc = (struct jme_softc *)arg; 2337 2338 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2339 if (status == 0 || status == 0xFFFFFFFF) 2340 return (FILTER_STRAY); 2341 /* Disable interrupts. */ 2342 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2343 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2344 2345 return (FILTER_HANDLED); 2346 } 2347 2348 static void 2349 jme_int_task(void *arg, int pending) 2350 { 2351 struct jme_softc *sc; 2352 if_t ifp; 2353 uint32_t status; 2354 int more; 2355 2356 sc = (struct jme_softc *)arg; 2357 ifp = sc->jme_ifp; 2358 2359 JME_LOCK(sc); 2360 status = CSR_READ_4(sc, JME_INTR_STATUS); 2361 if (sc->jme_morework != 0) { 2362 sc->jme_morework = 0; 2363 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2364 } 2365 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2366 goto done; 2367 /* Reset PCC counter/timer and Ack interrupts. */ 2368 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2369 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2370 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2371 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2372 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2373 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2374 more = 0; 2375 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2376 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2377 more = jme_rxintr(sc, sc->jme_process_limit); 2378 if (more != 0) 2379 sc->jme_morework = 1; 2380 } 2381 if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2382 /* 2383 * Notify hardware availability of new Rx 2384 * buffers. 2385 * Reading RXCSR takes very long time under 2386 * heavy load so cache RXCSR value and writes 2387 * the ORed value with the kick command to 2388 * the RXCSR. This saves one register access 2389 * cycle. 2390 */ 2391 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2392 RXCSR_RX_ENB | RXCSR_RXQ_START); 2393 } 2394 if (!if_sendq_empty(ifp)) 2395 jme_start_locked(ifp); 2396 } 2397 2398 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2399 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2400 JME_UNLOCK(sc); 2401 return; 2402 } 2403 done: 2404 JME_UNLOCK(sc); 2405 2406 /* Reenable interrupts. */ 2407 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2408 } 2409 2410 static void 2411 jme_txeof(struct jme_softc *sc) 2412 { 2413 if_t ifp; 2414 struct jme_txdesc *txd; 2415 uint32_t status; 2416 int cons, nsegs; 2417 2418 JME_LOCK_ASSERT(sc); 2419 2420 ifp = sc->jme_ifp; 2421 2422 cons = sc->jme_cdata.jme_tx_cons; 2423 if (cons == sc->jme_cdata.jme_tx_prod) 2424 return; 2425 2426 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2427 sc->jme_cdata.jme_tx_ring_map, 2428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2429 2430 /* 2431 * Go through our Tx list and free mbufs for those 2432 * frames which have been transmitted. 2433 */ 2434 for (; cons != sc->jme_cdata.jme_tx_prod;) { 2435 txd = &sc->jme_cdata.jme_txdesc[cons]; 2436 status = le32toh(txd->tx_desc->flags); 2437 if ((status & JME_TD_OWN) == JME_TD_OWN) 2438 break; 2439 2440 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2441 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2442 else { 2443 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2444 if ((status & JME_TD_COLLISION) != 0) 2445 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2446 le32toh(txd->tx_desc->buflen) & 2447 JME_TD_BUF_LEN_MASK); 2448 } 2449 /* 2450 * Only the first descriptor of multi-descriptor 2451 * transmission is updated so driver have to skip entire 2452 * chained buffers for the transmiited frame. In other 2453 * words, JME_TD_OWN bit is valid only at the first 2454 * descriptor of a multi-descriptor transmission. 2455 */ 2456 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2457 sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2458 JME_DESC_INC(cons, JME_TX_RING_CNT); 2459 } 2460 2461 /* Reclaim transferred mbufs. */ 2462 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2463 BUS_DMASYNC_POSTWRITE); 2464 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2465 2466 KASSERT(txd->tx_m != NULL, 2467 ("%s: freeing NULL mbuf!\n", __func__)); 2468 m_freem(txd->tx_m); 2469 txd->tx_m = NULL; 2470 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2471 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2472 ("%s: Active Tx desc counter was garbled\n", __func__)); 2473 txd->tx_ndesc = 0; 2474 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2475 } 2476 sc->jme_cdata.jme_tx_cons = cons; 2477 /* Unarm watchdog timer when there is no pending descriptors in queue. */ 2478 if (sc->jme_cdata.jme_tx_cnt == 0) 2479 sc->jme_watchdog_timer = 0; 2480 2481 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2482 sc->jme_cdata.jme_tx_ring_map, 2483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2484 } 2485 2486 static __inline void 2487 jme_discard_rxbuf(struct jme_softc *sc, int cons) 2488 { 2489 struct jme_desc *desc; 2490 2491 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2492 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2493 desc->buflen = htole32(MCLBYTES); 2494 } 2495 2496 /* Receive a frame. */ 2497 static void 2498 jme_rxeof(struct jme_softc *sc) 2499 { 2500 if_t ifp; 2501 struct jme_desc *desc; 2502 struct jme_rxdesc *rxd; 2503 struct mbuf *mp, *m; 2504 uint32_t flags, status; 2505 int cons, count, nsegs; 2506 2507 JME_LOCK_ASSERT(sc); 2508 2509 ifp = sc->jme_ifp; 2510 2511 cons = sc->jme_cdata.jme_rx_cons; 2512 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2513 flags = le32toh(desc->flags); 2514 status = le32toh(desc->buflen); 2515 nsegs = JME_RX_NSEGS(status); 2516 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2517 if ((status & JME_RX_ERR_STAT) != 0) { 2518 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2519 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2520 #ifdef JME_SHOW_ERRORS 2521 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2522 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2523 #endif 2524 sc->jme_cdata.jme_rx_cons += nsegs; 2525 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2526 return; 2527 } 2528 2529 for (count = 0; count < nsegs; count++, 2530 JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2531 rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2532 mp = rxd->rx_m; 2533 /* Add a new receive buffer to the ring. */ 2534 if (jme_newbuf(sc, rxd) != 0) { 2535 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2536 /* Reuse buffer. */ 2537 for (; count < nsegs; count++) { 2538 jme_discard_rxbuf(sc, cons); 2539 JME_DESC_INC(cons, JME_RX_RING_CNT); 2540 } 2541 if (sc->jme_cdata.jme_rxhead != NULL) { 2542 m_freem(sc->jme_cdata.jme_rxhead); 2543 JME_RXCHAIN_RESET(sc); 2544 } 2545 break; 2546 } 2547 2548 /* 2549 * Assume we've received a full sized frame. 2550 * Actual size is fixed when we encounter the end of 2551 * multi-segmented frame. 2552 */ 2553 mp->m_len = MCLBYTES; 2554 2555 /* Chain received mbufs. */ 2556 if (sc->jme_cdata.jme_rxhead == NULL) { 2557 sc->jme_cdata.jme_rxhead = mp; 2558 sc->jme_cdata.jme_rxtail = mp; 2559 } else { 2560 /* 2561 * Receive processor can receive a maximum frame 2562 * size of 65535 bytes. 2563 */ 2564 mp->m_flags &= ~M_PKTHDR; 2565 sc->jme_cdata.jme_rxtail->m_next = mp; 2566 sc->jme_cdata.jme_rxtail = mp; 2567 } 2568 2569 if (count == nsegs - 1) { 2570 /* Last desc. for this frame. */ 2571 m = sc->jme_cdata.jme_rxhead; 2572 m->m_flags |= M_PKTHDR; 2573 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2574 if (nsegs > 1) { 2575 /* Set first mbuf size. */ 2576 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2577 /* Set last mbuf size. */ 2578 mp->m_len = sc->jme_cdata.jme_rxlen - 2579 ((MCLBYTES - JME_RX_PAD_BYTES) + 2580 (MCLBYTES * (nsegs - 2))); 2581 } else 2582 m->m_len = sc->jme_cdata.jme_rxlen; 2583 m->m_pkthdr.rcvif = ifp; 2584 2585 /* 2586 * Account for 10bytes auto padding which is used 2587 * to align IP header on 32bit boundary. Also note, 2588 * CRC bytes is automatically removed by the 2589 * hardware. 2590 */ 2591 m->m_data += JME_RX_PAD_BYTES; 2592 2593 /* Set checksum information. */ 2594 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2595 (flags & JME_RD_IPV4) != 0) { 2596 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2597 if ((flags & JME_RD_IPCSUM) != 0) 2598 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2599 if (((flags & JME_RD_MORE_FRAG) == 0) && 2600 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2601 (JME_RD_TCP | JME_RD_TCPCSUM) || 2602 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2603 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2604 m->m_pkthdr.csum_flags |= 2605 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2606 m->m_pkthdr.csum_data = 0xffff; 2607 } 2608 } 2609 2610 /* Check for VLAN tagged packets. */ 2611 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2612 (flags & JME_RD_VLAN_TAG) != 0) { 2613 m->m_pkthdr.ether_vtag = 2614 flags & JME_RD_VLAN_MASK; 2615 m->m_flags |= M_VLANTAG; 2616 } 2617 2618 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2619 /* Pass it on. */ 2620 JME_UNLOCK(sc); 2621 if_input(ifp, m); 2622 JME_LOCK(sc); 2623 2624 /* Reset mbuf chains. */ 2625 JME_RXCHAIN_RESET(sc); 2626 } 2627 } 2628 2629 sc->jme_cdata.jme_rx_cons += nsegs; 2630 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2631 } 2632 2633 static int 2634 jme_rxintr(struct jme_softc *sc, int count) 2635 { 2636 struct jme_desc *desc; 2637 int nsegs, prog, pktlen; 2638 2639 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2640 sc->jme_cdata.jme_rx_ring_map, 2641 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2642 2643 for (prog = 0; count > 0; prog++) { 2644 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2645 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2646 break; 2647 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2648 break; 2649 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2650 /* 2651 * Check number of segments against received bytes. 2652 * Non-matching value would indicate that hardware 2653 * is still trying to update Rx descriptors. I'm not 2654 * sure whether this check is needed. 2655 */ 2656 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2657 if (nsegs != howmany(pktlen, MCLBYTES)) 2658 break; 2659 prog++; 2660 /* Received a frame. */ 2661 jme_rxeof(sc); 2662 count -= nsegs; 2663 } 2664 2665 if (prog > 0) 2666 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2667 sc->jme_cdata.jme_rx_ring_map, 2668 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2669 2670 return (count > 0 ? 0 : EAGAIN); 2671 } 2672 2673 static void 2674 jme_tick(void *arg) 2675 { 2676 struct jme_softc *sc; 2677 struct mii_data *mii; 2678 2679 sc = (struct jme_softc *)arg; 2680 2681 JME_LOCK_ASSERT(sc); 2682 2683 mii = device_get_softc(sc->jme_miibus); 2684 mii_tick(mii); 2685 /* 2686 * Reclaim Tx buffers that have been completed. It's not 2687 * needed here but it would release allocated mbuf chains 2688 * faster and limit the maximum delay to a hz. 2689 */ 2690 jme_txeof(sc); 2691 jme_stats_update(sc); 2692 jme_watchdog(sc); 2693 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2694 } 2695 2696 static void 2697 jme_reset(struct jme_softc *sc) 2698 { 2699 uint32_t ghc, gpreg; 2700 2701 /* Stop receiver, transmitter. */ 2702 jme_stop_rx(sc); 2703 jme_stop_tx(sc); 2704 2705 /* Reset controller. */ 2706 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2707 CSR_READ_4(sc, JME_GHC); 2708 DELAY(10); 2709 /* 2710 * Workaround Rx FIFO overruns seen under certain conditions. 2711 * Explicitly synchorize TX/RX clock. TX/RX clock should be 2712 * enabled only after enabling TX/RX MACs. 2713 */ 2714 if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) { 2715 /* Disable TX clock. */ 2716 CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS); 2717 /* Disable RX clock. */ 2718 gpreg = CSR_READ_4(sc, JME_GPREG1); 2719 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2720 gpreg = CSR_READ_4(sc, JME_GPREG1); 2721 /* De-assert RESET but still disable TX clock. */ 2722 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2723 ghc = CSR_READ_4(sc, JME_GHC); 2724 2725 /* Enable TX clock. */ 2726 CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS); 2727 /* Enable RX clock. */ 2728 CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS); 2729 CSR_READ_4(sc, JME_GPREG1); 2730 2731 /* Disable TX/RX clock again. */ 2732 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2733 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2734 } else 2735 CSR_WRITE_4(sc, JME_GHC, 0); 2736 CSR_READ_4(sc, JME_GHC); 2737 DELAY(10); 2738 } 2739 2740 static void 2741 jme_init(void *xsc) 2742 { 2743 struct jme_softc *sc; 2744 2745 sc = (struct jme_softc *)xsc; 2746 JME_LOCK(sc); 2747 jme_init_locked(sc); 2748 JME_UNLOCK(sc); 2749 } 2750 2751 static void 2752 jme_init_locked(struct jme_softc *sc) 2753 { 2754 if_t ifp; 2755 struct mii_data *mii; 2756 bus_addr_t paddr; 2757 uint32_t reg; 2758 int error; 2759 2760 JME_LOCK_ASSERT(sc); 2761 2762 ifp = sc->jme_ifp; 2763 mii = device_get_softc(sc->jme_miibus); 2764 2765 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2766 return; 2767 /* 2768 * Cancel any pending I/O. 2769 */ 2770 jme_stop(sc); 2771 2772 /* 2773 * Reset the chip to a known state. 2774 */ 2775 jme_reset(sc); 2776 2777 /* Init descriptors. */ 2778 error = jme_init_rx_ring(sc); 2779 if (error != 0) { 2780 device_printf(sc->jme_dev, 2781 "%s: initialization failed: no memory for Rx buffers.\n", 2782 __func__); 2783 jme_stop(sc); 2784 return; 2785 } 2786 jme_init_tx_ring(sc); 2787 /* Initialize shadow status block. */ 2788 jme_init_ssb(sc); 2789 2790 /* Reprogram the station address. */ 2791 jme_set_macaddr(sc, if_getlladdr(sc->jme_ifp)); 2792 2793 /* 2794 * Configure Tx queue. 2795 * Tx priority queue weight value : 0 2796 * Tx FIFO threshold for processing next packet : 16QW 2797 * Maximum Tx DMA length : 512 2798 * Allow Tx DMA burst. 2799 */ 2800 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2801 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2802 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2803 sc->jme_txcsr |= sc->jme_tx_dma_size; 2804 sc->jme_txcsr |= TXCSR_DMA_BURST; 2805 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2806 2807 /* Set Tx descriptor counter. */ 2808 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2809 2810 /* Set Tx ring address to the hardware. */ 2811 paddr = JME_TX_RING_ADDR(sc, 0); 2812 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2813 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2814 2815 /* Configure TxMAC parameters. */ 2816 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2817 reg |= TXMAC_THRESH_1_PKT; 2818 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2819 CSR_WRITE_4(sc, JME_TXMAC, reg); 2820 2821 /* 2822 * Configure Rx queue. 2823 * FIFO full threshold for transmitting Tx pause packet : 128T 2824 * FIFO threshold for processing next packet : 128QW 2825 * Rx queue 0 select 2826 * Max Rx DMA length : 128 2827 * Rx descriptor retry : 32 2828 * Rx descriptor retry time gap : 256ns 2829 * Don't receive runt/bad frame. 2830 */ 2831 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2832 /* 2833 * Since Rx FIFO size is 4K bytes, receiving frames larger 2834 * than 4K bytes will suffer from Rx FIFO overruns. So 2835 * decrease FIFO threshold to reduce the FIFO overruns for 2836 * frames larger than 4000 bytes. 2837 * For best performance of standard MTU sized frames use 2838 * maximum allowable FIFO threshold, 128QW. Note these do 2839 * not hold on chip full mask version >=2. For these 2840 * controllers 64QW and 128QW are not valid value. 2841 */ 2842 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2843 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2844 else { 2845 if ((if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2846 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2847 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2848 else 2849 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2850 } 2851 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2852 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2853 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2854 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2855 2856 /* Set Rx descriptor counter. */ 2857 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2858 2859 /* Set Rx ring address to the hardware. */ 2860 paddr = JME_RX_RING_ADDR(sc, 0); 2861 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2862 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2863 2864 /* Clear receive filter. */ 2865 CSR_WRITE_4(sc, JME_RXMAC, 0); 2866 /* Set up the receive filter. */ 2867 jme_set_filter(sc); 2868 jme_set_vlan(sc); 2869 2870 /* 2871 * Disable all WOL bits as WOL can interfere normal Rx 2872 * operation. Also clear WOL detection status bits. 2873 */ 2874 reg = CSR_READ_4(sc, JME_PMCS); 2875 reg &= ~PMCS_WOL_ENB_MASK; 2876 CSR_WRITE_4(sc, JME_PMCS, reg); 2877 2878 reg = CSR_READ_4(sc, JME_RXMAC); 2879 /* 2880 * Pad 10bytes right before received frame. This will greatly 2881 * help Rx performance on strict-alignment architectures as 2882 * it does not need to copy the frame to align the payload. 2883 */ 2884 reg |= RXMAC_PAD_10BYTES; 2885 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2886 reg |= RXMAC_CSUM_ENB; 2887 CSR_WRITE_4(sc, JME_RXMAC, reg); 2888 2889 /* Configure general purpose reg0 */ 2890 reg = CSR_READ_4(sc, JME_GPREG0); 2891 reg &= ~GPREG0_PCC_UNIT_MASK; 2892 /* Set PCC timer resolution to micro-seconds unit. */ 2893 reg |= GPREG0_PCC_UNIT_US; 2894 /* 2895 * Disable all shadow register posting as we have to read 2896 * JME_INTR_STATUS register in jme_int_task. Also it seems 2897 * that it's hard to synchronize interrupt status between 2898 * hardware and software with shadow posting due to 2899 * requirements of bus_dmamap_sync(9). 2900 */ 2901 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2902 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2903 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2904 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2905 /* Disable posting of DW0. */ 2906 reg &= ~GPREG0_POST_DW0_ENB; 2907 /* Clear PME message. */ 2908 reg &= ~GPREG0_PME_ENB; 2909 /* Set PHY address. */ 2910 reg &= ~GPREG0_PHY_ADDR_MASK; 2911 reg |= sc->jme_phyaddr; 2912 CSR_WRITE_4(sc, JME_GPREG0, reg); 2913 2914 /* Configure Tx queue 0 packet completion coalescing. */ 2915 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2916 PCCTX_COAL_TO_MASK; 2917 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2918 PCCTX_COAL_PKT_MASK; 2919 reg |= PCCTX_COAL_TXQ0; 2920 CSR_WRITE_4(sc, JME_PCCTX, reg); 2921 2922 /* Configure Rx queue 0 packet completion coalescing. */ 2923 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2924 PCCRX_COAL_TO_MASK; 2925 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2926 PCCRX_COAL_PKT_MASK; 2927 CSR_WRITE_4(sc, JME_PCCRX0, reg); 2928 2929 /* 2930 * Configure PCD(Packet Completion Deferring). It seems PCD 2931 * generates an interrupt when the time interval between two 2932 * back-to-back incoming/outgoing packet is long enough for 2933 * it to reach its timer value 0. The arrival of new packets 2934 * after timer has started causes the PCD timer to restart. 2935 * Unfortunately, it's not clear how PCD is useful at this 2936 * moment, so just use the same of PCC parameters. 2937 */ 2938 if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) { 2939 sc->jme_rx_pcd_to = sc->jme_rx_coal_to; 2940 if (sc->jme_rx_coal_to > PCDRX_TO_MAX) 2941 sc->jme_rx_pcd_to = PCDRX_TO_MAX; 2942 sc->jme_tx_pcd_to = sc->jme_tx_coal_to; 2943 if (sc->jme_tx_coal_to > PCDTX_TO_MAX) 2944 sc->jme_tx_pcd_to = PCDTX_TO_MAX; 2945 reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT; 2946 reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT; 2947 CSR_WRITE_4(sc, PCDRX_REG(0), reg); 2948 reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT; 2949 reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT; 2950 CSR_WRITE_4(sc, JME_PCDTX, reg); 2951 } 2952 2953 /* Configure shadow status block but don't enable posting. */ 2954 paddr = sc->jme_rdata.jme_ssb_block_paddr; 2955 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2956 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2957 2958 /* Disable Timer 1 and Timer 2. */ 2959 CSR_WRITE_4(sc, JME_TIMER1, 0); 2960 CSR_WRITE_4(sc, JME_TIMER2, 0); 2961 2962 /* Configure retry transmit period, retry limit value. */ 2963 CSR_WRITE_4(sc, JME_TXTRHD, 2964 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2965 TXTRHD_RT_PERIOD_MASK) | 2966 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2967 TXTRHD_RT_LIMIT_SHIFT)); 2968 2969 /* Disable RSS. */ 2970 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2971 2972 /* Initialize the interrupt mask. */ 2973 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2974 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2975 2976 /* 2977 * Enabling Tx/Rx DMA engines and Rx queue processing is 2978 * done after detection of valid link in jme_link_task. 2979 */ 2980 2981 sc->jme_flags &= ~JME_FLAG_LINK; 2982 /* Set the current media. */ 2983 mii_mediachg(mii); 2984 2985 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2986 2987 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2988 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2989 } 2990 2991 static void 2992 jme_stop(struct jme_softc *sc) 2993 { 2994 if_t ifp; 2995 struct jme_txdesc *txd; 2996 struct jme_rxdesc *rxd; 2997 int i; 2998 2999 JME_LOCK_ASSERT(sc); 3000 /* 3001 * Mark the interface down and cancel the watchdog timer. 3002 */ 3003 ifp = sc->jme_ifp; 3004 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3005 sc->jme_flags &= ~JME_FLAG_LINK; 3006 callout_stop(&sc->jme_tick_ch); 3007 sc->jme_watchdog_timer = 0; 3008 3009 /* 3010 * Disable interrupts. 3011 */ 3012 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 3013 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 3014 3015 /* Disable updating shadow status block. */ 3016 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 3017 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 3018 3019 /* Stop receiver, transmitter. */ 3020 jme_stop_rx(sc); 3021 jme_stop_tx(sc); 3022 3023 /* Reclaim Rx/Tx buffers that have been completed. */ 3024 jme_rxintr(sc, JME_RX_RING_CNT); 3025 if (sc->jme_cdata.jme_rxhead != NULL) 3026 m_freem(sc->jme_cdata.jme_rxhead); 3027 JME_RXCHAIN_RESET(sc); 3028 jme_txeof(sc); 3029 /* 3030 * Free RX and TX mbufs still in the queues. 3031 */ 3032 for (i = 0; i < JME_RX_RING_CNT; i++) { 3033 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3034 if (rxd->rx_m != NULL) { 3035 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 3036 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3037 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 3038 rxd->rx_dmamap); 3039 m_freem(rxd->rx_m); 3040 rxd->rx_m = NULL; 3041 } 3042 } 3043 for (i = 0; i < JME_TX_RING_CNT; i++) { 3044 txd = &sc->jme_cdata.jme_txdesc[i]; 3045 if (txd->tx_m != NULL) { 3046 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 3047 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3048 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 3049 txd->tx_dmamap); 3050 m_freem(txd->tx_m); 3051 txd->tx_m = NULL; 3052 txd->tx_ndesc = 0; 3053 } 3054 } 3055 jme_stats_update(sc); 3056 jme_stats_save(sc); 3057 } 3058 3059 static void 3060 jme_stop_tx(struct jme_softc *sc) 3061 { 3062 uint32_t reg; 3063 int i; 3064 3065 reg = CSR_READ_4(sc, JME_TXCSR); 3066 if ((reg & TXCSR_TX_ENB) == 0) 3067 return; 3068 reg &= ~TXCSR_TX_ENB; 3069 CSR_WRITE_4(sc, JME_TXCSR, reg); 3070 for (i = JME_TIMEOUT; i > 0; i--) { 3071 DELAY(1); 3072 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 3073 break; 3074 } 3075 if (i == 0) 3076 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 3077 } 3078 3079 static void 3080 jme_stop_rx(struct jme_softc *sc) 3081 { 3082 uint32_t reg; 3083 int i; 3084 3085 reg = CSR_READ_4(sc, JME_RXCSR); 3086 if ((reg & RXCSR_RX_ENB) == 0) 3087 return; 3088 reg &= ~RXCSR_RX_ENB; 3089 CSR_WRITE_4(sc, JME_RXCSR, reg); 3090 for (i = JME_TIMEOUT; i > 0; i--) { 3091 DELAY(1); 3092 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 3093 break; 3094 } 3095 if (i == 0) 3096 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 3097 } 3098 3099 static void 3100 jme_init_tx_ring(struct jme_softc *sc) 3101 { 3102 struct jme_ring_data *rd; 3103 struct jme_txdesc *txd; 3104 int i; 3105 3106 sc->jme_cdata.jme_tx_prod = 0; 3107 sc->jme_cdata.jme_tx_cons = 0; 3108 sc->jme_cdata.jme_tx_cnt = 0; 3109 3110 rd = &sc->jme_rdata; 3111 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 3112 for (i = 0; i < JME_TX_RING_CNT; i++) { 3113 txd = &sc->jme_cdata.jme_txdesc[i]; 3114 txd->tx_m = NULL; 3115 txd->tx_desc = &rd->jme_tx_ring[i]; 3116 txd->tx_ndesc = 0; 3117 } 3118 3119 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 3120 sc->jme_cdata.jme_tx_ring_map, 3121 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3122 } 3123 3124 static void 3125 jme_init_ssb(struct jme_softc *sc) 3126 { 3127 struct jme_ring_data *rd; 3128 3129 rd = &sc->jme_rdata; 3130 bzero(rd->jme_ssb_block, JME_SSB_SIZE); 3131 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 3132 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3133 } 3134 3135 static int 3136 jme_init_rx_ring(struct jme_softc *sc) 3137 { 3138 struct jme_ring_data *rd; 3139 struct jme_rxdesc *rxd; 3140 int i; 3141 3142 sc->jme_cdata.jme_rx_cons = 0; 3143 JME_RXCHAIN_RESET(sc); 3144 sc->jme_morework = 0; 3145 3146 rd = &sc->jme_rdata; 3147 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 3148 for (i = 0; i < JME_RX_RING_CNT; i++) { 3149 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3150 rxd->rx_m = NULL; 3151 rxd->rx_desc = &rd->jme_rx_ring[i]; 3152 if (jme_newbuf(sc, rxd) != 0) 3153 return (ENOBUFS); 3154 } 3155 3156 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 3157 sc->jme_cdata.jme_rx_ring_map, 3158 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3159 3160 return (0); 3161 } 3162 3163 static int 3164 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3165 { 3166 struct jme_desc *desc; 3167 struct mbuf *m; 3168 bus_dma_segment_t segs[1]; 3169 bus_dmamap_t map; 3170 int nsegs; 3171 3172 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3173 if (m == NULL) 3174 return (ENOBUFS); 3175 /* 3176 * JMC250 has 64bit boundary alignment limitation so jme(4) 3177 * takes advantage of 10 bytes padding feature of hardware 3178 * in order not to copy entire frame to align IP header on 3179 * 32bit boundary. 3180 */ 3181 m->m_len = m->m_pkthdr.len = MCLBYTES; 3182 3183 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3184 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3185 m_freem(m); 3186 return (ENOBUFS); 3187 } 3188 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3189 3190 if (rxd->rx_m != NULL) { 3191 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3192 BUS_DMASYNC_POSTREAD); 3193 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3194 } 3195 map = rxd->rx_dmamap; 3196 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3197 sc->jme_cdata.jme_rx_sparemap = map; 3198 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3199 BUS_DMASYNC_PREREAD); 3200 rxd->rx_m = m; 3201 3202 desc = rxd->rx_desc; 3203 desc->buflen = htole32(segs[0].ds_len); 3204 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3205 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3206 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3207 3208 return (0); 3209 } 3210 3211 static void 3212 jme_set_vlan(struct jme_softc *sc) 3213 { 3214 if_t ifp; 3215 uint32_t reg; 3216 3217 JME_LOCK_ASSERT(sc); 3218 3219 ifp = sc->jme_ifp; 3220 reg = CSR_READ_4(sc, JME_RXMAC); 3221 reg &= ~RXMAC_VLAN_ENB; 3222 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3223 reg |= RXMAC_VLAN_ENB; 3224 CSR_WRITE_4(sc, JME_RXMAC, reg); 3225 } 3226 3227 static u_int 3228 jme_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3229 { 3230 uint32_t crc, *mchash = arg; 3231 3232 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3233 3234 /* Just want the 6 least significant bits. */ 3235 crc &= 0x3f; 3236 3237 /* Set the corresponding bit in the hash table. */ 3238 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3239 3240 return (1); 3241 } 3242 3243 static void 3244 jme_set_filter(struct jme_softc *sc) 3245 { 3246 if_t ifp; 3247 uint32_t mchash[2]; 3248 uint32_t rxcfg; 3249 3250 JME_LOCK_ASSERT(sc); 3251 3252 ifp = sc->jme_ifp; 3253 3254 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3255 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3256 RXMAC_ALLMULTI); 3257 /* Always accept frames destined to our station address. */ 3258 rxcfg |= RXMAC_UNICAST; 3259 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3260 rxcfg |= RXMAC_BROADCAST; 3261 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3262 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3263 rxcfg |= RXMAC_PROMISC; 3264 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3265 rxcfg |= RXMAC_ALLMULTI; 3266 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3267 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3268 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3269 return; 3270 } 3271 3272 /* 3273 * Set up the multicast address filter by passing all multicast 3274 * addresses through a CRC generator, and then using the low-order 3275 * 6 bits as an index into the 64 bit multicast hash table. The 3276 * high order bits select the register, while the rest of the bits 3277 * select the bit within the register. 3278 */ 3279 rxcfg |= RXMAC_MULTICAST; 3280 bzero(mchash, sizeof(mchash)); 3281 if_foreach_llmaddr(ifp, jme_hash_maddr, &mchash); 3282 3283 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3284 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3285 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3286 } 3287 3288 static void 3289 jme_stats_clear(struct jme_softc *sc) 3290 { 3291 3292 JME_LOCK_ASSERT(sc); 3293 3294 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3295 return; 3296 3297 /* Disable and clear counters. */ 3298 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3299 /* Activate hw counters. */ 3300 CSR_WRITE_4(sc, JME_STATCSR, 0); 3301 CSR_READ_4(sc, JME_STATCSR); 3302 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3303 } 3304 3305 static void 3306 jme_stats_save(struct jme_softc *sc) 3307 { 3308 3309 JME_LOCK_ASSERT(sc); 3310 3311 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3312 return; 3313 /* Save current counters. */ 3314 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3315 /* Disable and clear counters. */ 3316 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3317 } 3318 3319 static void 3320 jme_stats_update(struct jme_softc *sc) 3321 { 3322 struct jme_hw_stats *stat, *ostat; 3323 uint32_t reg; 3324 3325 JME_LOCK_ASSERT(sc); 3326 3327 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3328 return; 3329 stat = &sc->jme_stats; 3330 ostat = &sc->jme_ostats; 3331 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3332 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3333 reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3334 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3335 STAT_RX_CRC_ERR_SHIFT; 3336 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3337 STAT_RX_MII_ERR_SHIFT; 3338 reg = CSR_READ_4(sc, JME_STAT_RXERR); 3339 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3340 STAT_RXERR_OFLOW_SHIFT; 3341 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3342 STAT_RXERR_MPTY_SHIFT; 3343 reg = CSR_READ_4(sc, JME_STAT_FAIL); 3344 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3345 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3346 3347 /* Account for previous counters. */ 3348 stat->rx_good_frames += ostat->rx_good_frames; 3349 stat->rx_crc_errs += ostat->rx_crc_errs; 3350 stat->rx_mii_errs += ostat->rx_mii_errs; 3351 stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3352 stat->rx_desc_empty += ostat->rx_desc_empty; 3353 stat->rx_bad_frames += ostat->rx_bad_frames; 3354 stat->tx_good_frames += ostat->tx_good_frames; 3355 stat->tx_bad_frames += ostat->tx_bad_frames; 3356 } 3357 3358 static void 3359 jme_phy_down(struct jme_softc *sc) 3360 { 3361 uint32_t reg; 3362 3363 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN); 3364 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3365 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3366 reg |= 0x0000000F; 3367 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3368 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3369 reg &= ~PE1_GIGA_PDOWN_MASK; 3370 reg |= PE1_GIGA_PDOWN_D3; 3371 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3372 } 3373 } 3374 3375 static void 3376 jme_phy_up(struct jme_softc *sc) 3377 { 3378 uint32_t reg; 3379 uint16_t bmcr; 3380 3381 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); 3382 bmcr &= ~BMCR_PDOWN; 3383 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); 3384 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3385 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3386 reg &= ~0x0000000F; 3387 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3388 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3389 reg &= ~PE1_GIGA_PDOWN_MASK; 3390 reg |= PE1_GIGA_PDOWN_DIS; 3391 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3392 } 3393 } 3394 3395 static int 3396 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3397 { 3398 int error, value; 3399 3400 if (arg1 == NULL) 3401 return (EINVAL); 3402 value = *(int *)arg1; 3403 error = sysctl_handle_int(oidp, &value, 0, req); 3404 if (error || req->newptr == NULL) 3405 return (error); 3406 if (value < low || value > high) 3407 return (EINVAL); 3408 *(int *)arg1 = value; 3409 3410 return (0); 3411 } 3412 3413 static int 3414 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3415 { 3416 return (sysctl_int_range(oidp, arg1, arg2, req, 3417 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3418 } 3419 3420 static int 3421 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3422 { 3423 return (sysctl_int_range(oidp, arg1, arg2, req, 3424 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3425 } 3426 3427 static int 3428 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3429 { 3430 return (sysctl_int_range(oidp, arg1, arg2, req, 3431 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3432 } 3433 3434 static int 3435 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3436 { 3437 return (sysctl_int_range(oidp, arg1, arg2, req, 3438 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3439 } 3440 3441 static int 3442 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3443 { 3444 return (sysctl_int_range(oidp, arg1, arg2, req, 3445 JME_PROC_MIN, JME_PROC_MAX)); 3446 } 3447