1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/proc.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/ip.h> 62 #include <netinet/tcp.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/jme/if_jmereg.h> 74 #include <dev/jme/if_jmevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* Define the following to disable printing Rx errors. */ 80 #undef JME_SHOW_ERRORS 81 82 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 83 84 MODULE_DEPEND(jme, pci, 1, 1, 1); 85 MODULE_DEPEND(jme, ether, 1, 1, 1); 86 MODULE_DEPEND(jme, miibus, 1, 1, 1); 87 88 /* Tunables. */ 89 static int msi_disable = 0; 90 static int msix_disable = 0; 91 TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 92 TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 93 94 /* 95 * Devices supported by this driver. 96 */ 97 static struct jme_dev { 98 uint16_t jme_vendorid; 99 uint16_t jme_deviceid; 100 const char *jme_name; 101 } jme_devs[] = { 102 { VENDORID_JMICRON, DEVICEID_JMC250, 103 "JMicron Inc, JMC25x Gigabit Ethernet" }, 104 { VENDORID_JMICRON, DEVICEID_JMC260, 105 "JMicron Inc, JMC26x Fast Ethernet" }, 106 }; 107 108 static int jme_miibus_readreg(device_t, int, int); 109 static int jme_miibus_writereg(device_t, int, int, int); 110 static void jme_miibus_statchg(device_t); 111 static void jme_mediastatus(if_t, struct ifmediareq *); 112 static int jme_mediachange(if_t); 113 static int jme_probe(device_t); 114 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 115 static int jme_eeprom_macaddr(struct jme_softc *); 116 static int jme_efuse_macaddr(struct jme_softc *); 117 static void jme_reg_macaddr(struct jme_softc *); 118 static void jme_set_macaddr(struct jme_softc *, uint8_t *); 119 static void jme_map_intr_vector(struct jme_softc *); 120 static int jme_attach(device_t); 121 static int jme_detach(device_t); 122 static void jme_sysctl_node(struct jme_softc *); 123 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 124 static int jme_dma_alloc(struct jme_softc *); 125 static void jme_dma_free(struct jme_softc *); 126 static int jme_shutdown(device_t); 127 static void jme_setlinkspeed(struct jme_softc *); 128 static void jme_setwol(struct jme_softc *); 129 static int jme_suspend(device_t); 130 static int jme_resume(device_t); 131 static int jme_encap(struct jme_softc *, struct mbuf **); 132 static void jme_start(if_t); 133 static void jme_start_locked(if_t); 134 static void jme_watchdog(struct jme_softc *); 135 static int jme_ioctl(if_t, u_long, caddr_t); 136 static void jme_mac_config(struct jme_softc *); 137 static void jme_link_task(void *, int); 138 static int jme_intr(void *); 139 static void jme_int_task(void *, int); 140 static void jme_txeof(struct jme_softc *); 141 static __inline void jme_discard_rxbuf(struct jme_softc *, int); 142 static void jme_rxeof(struct jme_softc *); 143 static int jme_rxintr(struct jme_softc *, int); 144 static void jme_tick(void *); 145 static void jme_reset(struct jme_softc *); 146 static void jme_init(void *); 147 static void jme_init_locked(struct jme_softc *); 148 static void jme_stop(struct jme_softc *); 149 static void jme_stop_tx(struct jme_softc *); 150 static void jme_stop_rx(struct jme_softc *); 151 static int jme_init_rx_ring(struct jme_softc *); 152 static void jme_init_tx_ring(struct jme_softc *); 153 static void jme_init_ssb(struct jme_softc *); 154 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 155 static void jme_set_vlan(struct jme_softc *); 156 static void jme_set_filter(struct jme_softc *); 157 static void jme_stats_clear(struct jme_softc *); 158 static void jme_stats_save(struct jme_softc *); 159 static void jme_stats_update(struct jme_softc *); 160 static void jme_phy_down(struct jme_softc *); 161 static void jme_phy_up(struct jme_softc *); 162 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 163 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 164 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 165 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 166 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 167 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 168 169 170 static device_method_t jme_methods[] = { 171 /* Device interface. */ 172 DEVMETHOD(device_probe, jme_probe), 173 DEVMETHOD(device_attach, jme_attach), 174 DEVMETHOD(device_detach, jme_detach), 175 DEVMETHOD(device_shutdown, jme_shutdown), 176 DEVMETHOD(device_suspend, jme_suspend), 177 DEVMETHOD(device_resume, jme_resume), 178 179 /* MII interface. */ 180 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 181 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 182 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 183 184 { NULL, NULL } 185 }; 186 187 static driver_t jme_driver = { 188 "jme", 189 jme_methods, 190 sizeof(struct jme_softc) 191 }; 192 193 DRIVER_MODULE(jme, pci, jme_driver, 0, 0); 194 DRIVER_MODULE(miibus, jme, miibus_driver, 0, 0); 195 196 static struct resource_spec jme_res_spec_mem[] = { 197 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static struct resource_spec jme_irq_spec_legacy[] = { 202 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 203 { -1, 0, 0 } 204 }; 205 206 static struct resource_spec jme_irq_spec_msi[] = { 207 { SYS_RES_IRQ, 1, RF_ACTIVE }, 208 { -1, 0, 0 } 209 }; 210 211 /* 212 * Read a PHY register on the MII of the JMC250. 213 */ 214 static int 215 jme_miibus_readreg(device_t dev, int phy, int reg) 216 { 217 struct jme_softc *sc; 218 uint32_t val; 219 int i; 220 221 sc = device_get_softc(dev); 222 223 /* For FPGA version, PHY address 0 should be ignored. */ 224 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 225 return (0); 226 227 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 228 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 229 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 230 DELAY(1); 231 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 232 break; 233 } 234 235 if (i == 0) { 236 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 237 return (0); 238 } 239 240 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 241 } 242 243 /* 244 * Write a PHY register on the MII of the JMC250. 245 */ 246 static int 247 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 248 { 249 struct jme_softc *sc; 250 int i; 251 252 sc = device_get_softc(dev); 253 254 /* For FPGA version, PHY address 0 should be ignored. */ 255 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 256 return (0); 257 258 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 259 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 260 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 261 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 262 DELAY(1); 263 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 264 break; 265 } 266 267 if (i == 0) 268 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 269 270 return (0); 271 } 272 273 /* 274 * Callback from MII layer when media changes. 275 */ 276 static void 277 jme_miibus_statchg(device_t dev) 278 { 279 struct jme_softc *sc; 280 281 sc = device_get_softc(dev); 282 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 283 } 284 285 /* 286 * Get the current interface media status. 287 */ 288 static void 289 jme_mediastatus(if_t ifp, struct ifmediareq *ifmr) 290 { 291 struct jme_softc *sc; 292 struct mii_data *mii; 293 294 sc = if_getsoftc(ifp); 295 JME_LOCK(sc); 296 if ((if_getflags(ifp) & IFF_UP) == 0) { 297 JME_UNLOCK(sc); 298 return; 299 } 300 mii = device_get_softc(sc->jme_miibus); 301 302 mii_pollstat(mii); 303 ifmr->ifm_status = mii->mii_media_status; 304 ifmr->ifm_active = mii->mii_media_active; 305 JME_UNLOCK(sc); 306 } 307 308 /* 309 * Set hardware to newly-selected media. 310 */ 311 static int 312 jme_mediachange(if_t ifp) 313 { 314 struct jme_softc *sc; 315 struct mii_data *mii; 316 struct mii_softc *miisc; 317 int error; 318 319 sc = if_getsoftc(ifp); 320 JME_LOCK(sc); 321 mii = device_get_softc(sc->jme_miibus); 322 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 323 PHY_RESET(miisc); 324 error = mii_mediachg(mii); 325 JME_UNLOCK(sc); 326 327 return (error); 328 } 329 330 static int 331 jme_probe(device_t dev) 332 { 333 struct jme_dev *sp; 334 int i; 335 uint16_t vendor, devid; 336 337 vendor = pci_get_vendor(dev); 338 devid = pci_get_device(dev); 339 sp = jme_devs; 340 for (i = 0; i < nitems(jme_devs); i++, sp++) { 341 if (vendor == sp->jme_vendorid && 342 devid == sp->jme_deviceid) { 343 device_set_desc(dev, sp->jme_name); 344 return (BUS_PROBE_DEFAULT); 345 } 346 } 347 348 return (ENXIO); 349 } 350 351 static int 352 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 353 { 354 uint32_t reg; 355 int i; 356 357 *val = 0; 358 for (i = JME_TIMEOUT; i > 0; i--) { 359 reg = CSR_READ_4(sc, JME_SMBCSR); 360 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 361 break; 362 DELAY(1); 363 } 364 365 if (i == 0) { 366 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 367 return (ETIMEDOUT); 368 } 369 370 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 371 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 372 for (i = JME_TIMEOUT; i > 0; i--) { 373 DELAY(1); 374 reg = CSR_READ_4(sc, JME_SMBINTF); 375 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 376 break; 377 } 378 379 if (i == 0) { 380 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 381 return (ETIMEDOUT); 382 } 383 384 reg = CSR_READ_4(sc, JME_SMBINTF); 385 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 386 387 return (0); 388 } 389 390 static int 391 jme_eeprom_macaddr(struct jme_softc *sc) 392 { 393 uint8_t eaddr[ETHER_ADDR_LEN]; 394 uint8_t fup, reg, val; 395 uint32_t offset; 396 int match; 397 398 offset = 0; 399 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 400 fup != JME_EEPROM_SIG0) 401 return (ENOENT); 402 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 403 fup != JME_EEPROM_SIG1) 404 return (ENOENT); 405 match = 0; 406 do { 407 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 408 break; 409 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 410 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 411 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 412 break; 413 if (reg >= JME_PAR0 && 414 reg < JME_PAR0 + ETHER_ADDR_LEN) { 415 if (jme_eeprom_read_byte(sc, offset + 2, 416 &val) != 0) 417 break; 418 eaddr[reg - JME_PAR0] = val; 419 match++; 420 } 421 } 422 /* Check for the end of EEPROM descriptor. */ 423 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 424 break; 425 /* Try next eeprom descriptor. */ 426 offset += JME_EEPROM_DESC_BYTES; 427 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 428 429 if (match == ETHER_ADDR_LEN) { 430 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 431 return (0); 432 } 433 434 return (ENOENT); 435 } 436 437 static int 438 jme_efuse_macaddr(struct jme_softc *sc) 439 { 440 uint32_t reg; 441 int i; 442 443 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 444 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) != 445 EFUSE_CTL1_AUTOLAOD_DONE) 446 return (ENOENT); 447 /* Reset eFuse controller. */ 448 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 449 reg |= EFUSE_CTL2_RESET; 450 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 451 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 452 reg &= ~EFUSE_CTL2_RESET; 453 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 454 455 /* Have eFuse reload station address to MAC controller. */ 456 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 457 reg &= ~EFUSE_CTL1_CMD_MASK; 458 reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE; 459 pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4); 460 461 /* 462 * Verify completion of eFuse autload command. It should be 463 * completed within 108us. 464 */ 465 DELAY(110); 466 for (i = 10; i > 0; i--) { 467 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 468 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | 469 EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) { 470 DELAY(20); 471 continue; 472 } 473 if ((reg & EFUSE_CTL1_EXECUTE) == 0) 474 break; 475 /* Station address loading is still in progress. */ 476 DELAY(20); 477 } 478 if (i == 0) { 479 device_printf(sc->jme_dev, "eFuse autoload timed out.\n"); 480 return (ETIMEDOUT); 481 } 482 483 return (0); 484 } 485 486 static void 487 jme_reg_macaddr(struct jme_softc *sc) 488 { 489 uint32_t par0, par1; 490 491 /* Read station address. */ 492 par0 = CSR_READ_4(sc, JME_PAR0); 493 par1 = CSR_READ_4(sc, JME_PAR1); 494 par1 &= 0xFFFF; 495 if ((par0 == 0 && par1 == 0) || 496 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 497 device_printf(sc->jme_dev, 498 "Failed to retrieve Ethernet address.\n"); 499 } else { 500 /* 501 * For controllers that use eFuse, the station address 502 * could also be extracted from JME_PCI_PAR0 and 503 * JME_PCI_PAR1 registers in PCI configuration space. 504 * Each register holds exactly half of station address(24bits) 505 * so use JME_PAR0, JME_PAR1 registers instead. 506 */ 507 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 508 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 509 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 510 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 511 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 512 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 513 } 514 } 515 516 static void 517 jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr) 518 { 519 uint32_t val; 520 int i; 521 522 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 523 /* 524 * Avoid reprogramming station address if the address 525 * is the same as previous one. Note, reprogrammed 526 * station address is permanent as if it was written 527 * to EEPROM. So if station address was changed by 528 * admistrator it's possible to lose factory configured 529 * address when driver fails to restore its address. 530 * (e.g. reboot or system crash) 531 */ 532 if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) { 533 for (i = 0; i < ETHER_ADDR_LEN; i++) { 534 val = JME_EFUSE_EEPROM_FUNC0 << 535 JME_EFUSE_EEPROM_FUNC_SHIFT; 536 val |= JME_EFUSE_EEPROM_PAGE_BAR1 << 537 JME_EFUSE_EEPROM_PAGE_SHIFT; 538 val |= (JME_PAR0 + i) << 539 JME_EFUSE_EEPROM_ADDR_SHIFT; 540 val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT; 541 pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM, 542 val | JME_EFUSE_EEPROM_WRITE, 4); 543 } 544 } 545 } else { 546 CSR_WRITE_4(sc, JME_PAR0, 547 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 548 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 549 } 550 } 551 552 static void 553 jme_map_intr_vector(struct jme_softc *sc) 554 { 555 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 556 557 bzero(map, sizeof(map)); 558 559 /* Map Tx interrupts source to MSI/MSIX vector 2. */ 560 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 561 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 562 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 563 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 564 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 565 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 566 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 567 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 568 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 569 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 570 map[MSINUM_REG_INDEX(N_INTR_TXQ5_COMP)] |= 571 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 572 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 573 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 574 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 575 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 576 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 577 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 578 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 579 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 580 581 /* Map Rx interrupts source to MSI/MSIX vector 1. */ 582 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 583 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 584 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 585 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 586 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 587 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 588 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 589 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 590 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 591 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 592 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 593 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 594 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 595 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 596 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 597 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 598 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 599 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 600 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 601 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 602 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 603 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 604 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 605 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 606 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 607 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 608 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 609 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 610 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 611 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 612 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 613 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 614 615 /* Map all other interrupts source to MSI/MSIX vector 0. */ 616 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 617 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 618 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 619 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 620 } 621 622 static int 623 jme_attach(device_t dev) 624 { 625 struct jme_softc *sc; 626 if_t ifp; 627 struct mii_softc *miisc; 628 struct mii_data *mii; 629 uint32_t reg; 630 uint16_t burst; 631 int error, i, mii_flags, msic, msixc, pmc; 632 633 error = 0; 634 sc = device_get_softc(dev); 635 sc->jme_dev = dev; 636 637 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 638 MTX_DEF); 639 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 640 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 641 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 642 643 /* 644 * Map the device. JMC250 supports both memory mapped and I/O 645 * register space access. Because I/O register access should 646 * use different BARs to access registers it's waste of time 647 * to use I/O register spce access. JMC250 uses 16K to map 648 * entire memory space. 649 */ 650 pci_enable_busmaster(dev); 651 sc->jme_res_spec = jme_res_spec_mem; 652 sc->jme_irq_spec = jme_irq_spec_legacy; 653 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 654 if (error != 0) { 655 device_printf(dev, "cannot allocate memory resources.\n"); 656 goto fail; 657 } 658 659 /* Allocate IRQ resources. */ 660 msixc = pci_msix_count(dev); 661 msic = pci_msi_count(dev); 662 if (bootverbose) { 663 device_printf(dev, "MSIX count : %d\n", msixc); 664 device_printf(dev, "MSI count : %d\n", msic); 665 } 666 667 /* Use 1 MSI/MSI-X. */ 668 if (msixc > 1) 669 msixc = 1; 670 if (msic > 1) 671 msic = 1; 672 /* Prefer MSIX over MSI. */ 673 if (msix_disable == 0 || msi_disable == 0) { 674 if (msix_disable == 0 && msixc > 0 && 675 pci_alloc_msix(dev, &msixc) == 0) { 676 if (msixc == 1) { 677 device_printf(dev, "Using %d MSIX messages.\n", 678 msixc); 679 sc->jme_flags |= JME_FLAG_MSIX; 680 sc->jme_irq_spec = jme_irq_spec_msi; 681 } else 682 pci_release_msi(dev); 683 } 684 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 685 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 686 if (msic == 1) { 687 device_printf(dev, "Using %d MSI messages.\n", 688 msic); 689 sc->jme_flags |= JME_FLAG_MSI; 690 sc->jme_irq_spec = jme_irq_spec_msi; 691 } else 692 pci_release_msi(dev); 693 } 694 /* Map interrupt vector 0, 1 and 2. */ 695 if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 696 (sc->jme_flags & JME_FLAG_MSIX) != 0) 697 jme_map_intr_vector(sc); 698 } 699 700 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 701 if (error != 0) { 702 device_printf(dev, "cannot allocate IRQ resources.\n"); 703 goto fail; 704 } 705 706 sc->jme_rev = pci_get_device(dev); 707 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 708 sc->jme_flags |= JME_FLAG_FASTETH; 709 sc->jme_flags |= JME_FLAG_NOJUMBO; 710 } 711 reg = CSR_READ_4(sc, JME_CHIPMODE); 712 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 713 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 714 CHIPMODE_NOT_FPGA) 715 sc->jme_flags |= JME_FLAG_FPGA; 716 if (bootverbose) { 717 device_printf(dev, "PCI device revision : 0x%04x\n", 718 sc->jme_rev); 719 device_printf(dev, "Chip revision : 0x%02x\n", 720 sc->jme_chip_rev); 721 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 722 device_printf(dev, "FPGA revision : 0x%04x\n", 723 (reg & CHIPMODE_FPGA_REV_MASK) >> 724 CHIPMODE_FPGA_REV_SHIFT); 725 } 726 if (sc->jme_chip_rev == 0xFF) { 727 device_printf(dev, "Unknown chip revision : 0x%02x\n", 728 sc->jme_rev); 729 error = ENXIO; 730 goto fail; 731 } 732 733 /* Identify controller features and bugs. */ 734 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 735 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 736 CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 737 sc->jme_flags |= JME_FLAG_DMA32BIT; 738 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 739 sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD; 740 sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK; 741 sc->jme_flags |= JME_FLAG_HWMIB; 742 } 743 744 /* Reset the ethernet controller. */ 745 jme_reset(sc); 746 747 /* Get station address. */ 748 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 749 error = jme_efuse_macaddr(sc); 750 if (error == 0) 751 jme_reg_macaddr(sc); 752 } else { 753 error = ENOENT; 754 reg = CSR_READ_4(sc, JME_SMBCSR); 755 if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 756 error = jme_eeprom_macaddr(sc); 757 if (error != 0 && bootverbose) 758 device_printf(sc->jme_dev, 759 "ethernet hardware address not found in EEPROM.\n"); 760 if (error != 0) 761 jme_reg_macaddr(sc); 762 } 763 764 /* 765 * Save PHY address. 766 * Integrated JR0211 has fixed PHY address whereas FPGA version 767 * requires PHY probing to get correct PHY address. 768 */ 769 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 770 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 771 GPREG0_PHY_ADDR_MASK; 772 if (bootverbose) 773 device_printf(dev, "PHY is at address %d.\n", 774 sc->jme_phyaddr); 775 } else 776 sc->jme_phyaddr = 0; 777 778 /* Set max allowable DMA size. */ 779 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 780 sc->jme_flags |= JME_FLAG_PCIE; 781 burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 782 if (bootverbose) { 783 device_printf(dev, "Read request size : %d bytes.\n", 784 128 << ((burst >> 12) & 0x07)); 785 device_printf(dev, "TLP payload size : %d bytes.\n", 786 128 << ((burst >> 5) & 0x07)); 787 } 788 switch ((burst >> 12) & 0x07) { 789 case 0: 790 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 791 break; 792 case 1: 793 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 794 break; 795 default: 796 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 797 break; 798 } 799 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 800 } else { 801 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 802 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 803 } 804 /* Create coalescing sysctl node. */ 805 jme_sysctl_node(sc); 806 if ((error = jme_dma_alloc(sc)) != 0) 807 goto fail; 808 809 ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 810 if (ifp == NULL) { 811 device_printf(dev, "cannot allocate ifnet structure.\n"); 812 error = ENXIO; 813 goto fail; 814 } 815 816 if_setsoftc(ifp, sc); 817 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 818 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 819 if_setioctlfn(ifp, jme_ioctl); 820 if_setstartfn(ifp, jme_start); 821 if_setinitfn(ifp, jme_init); 822 if_setsendqlen(ifp, JME_TX_RING_CNT - 1); 823 if_setsendqready(ifp); 824 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 825 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 826 if_sethwassist(ifp, JME_CSUM_FEATURES | CSUM_TSO); 827 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 828 sc->jme_flags |= JME_FLAG_PMCAP; 829 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 830 } 831 if_setcapenable(ifp, if_getcapabilities(ifp)); 832 833 /* Wakeup PHY. */ 834 jme_phy_up(sc); 835 mii_flags = MIIF_DOPAUSE; 836 /* Ask PHY calibration to PHY driver. */ 837 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 838 mii_flags |= MIIF_MACPRIV0; 839 /* Set up MII bus. */ 840 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange, 841 jme_mediastatus, BMSR_DEFCAPMASK, 842 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, 843 MII_OFFSET_ANY, mii_flags); 844 if (error != 0) { 845 device_printf(dev, "attaching PHYs failed\n"); 846 goto fail; 847 } 848 849 /* 850 * Force PHY to FPGA mode. 851 */ 852 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 853 mii = device_get_softc(sc->jme_miibus); 854 if (mii->mii_instance != 0) { 855 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 856 if (miisc->mii_phy != 0) { 857 sc->jme_phyaddr = miisc->mii_phy; 858 break; 859 } 860 } 861 if (sc->jme_phyaddr != 0) { 862 device_printf(sc->jme_dev, 863 "FPGA PHY is at %d\n", sc->jme_phyaddr); 864 /* vendor magic. */ 865 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 866 0x0004); 867 } 868 } 869 } 870 871 ether_ifattach(ifp, sc->jme_eaddr); 872 873 /* VLAN capability setup */ 874 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 875 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 876 if_setcapenable(ifp, if_getcapabilities(ifp)); 877 878 /* Tell the upper layer(s) we support long frames. */ 879 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 880 881 /* Create local taskq. */ 882 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 883 taskqueue_thread_enqueue, &sc->jme_tq); 884 if (sc->jme_tq == NULL) { 885 device_printf(dev, "could not create taskqueue.\n"); 886 ether_ifdetach(ifp); 887 error = ENXIO; 888 goto fail; 889 } 890 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 891 device_get_nameunit(sc->jme_dev)); 892 893 for (i = 0; i < 1; i++) { 894 error = bus_setup_intr(dev, sc->jme_irq[i], 895 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 896 &sc->jme_intrhand[i]); 897 if (error != 0) 898 break; 899 } 900 901 if (error != 0) { 902 device_printf(dev, "could not set up interrupt handler.\n"); 903 taskqueue_free(sc->jme_tq); 904 sc->jme_tq = NULL; 905 ether_ifdetach(ifp); 906 goto fail; 907 } 908 909 fail: 910 if (error != 0) 911 jme_detach(dev); 912 913 return (error); 914 } 915 916 static int 917 jme_detach(device_t dev) 918 { 919 struct jme_softc *sc; 920 if_t ifp; 921 int i; 922 923 sc = device_get_softc(dev); 924 925 ifp = sc->jme_ifp; 926 if (device_is_attached(dev)) { 927 JME_LOCK(sc); 928 sc->jme_flags |= JME_FLAG_DETACH; 929 jme_stop(sc); 930 JME_UNLOCK(sc); 931 callout_drain(&sc->jme_tick_ch); 932 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 933 taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 934 /* Restore possibly modified station address. */ 935 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) 936 jme_set_macaddr(sc, sc->jme_eaddr); 937 ether_ifdetach(ifp); 938 } 939 940 if (sc->jme_tq != NULL) { 941 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 942 taskqueue_free(sc->jme_tq); 943 sc->jme_tq = NULL; 944 } 945 946 if (sc->jme_miibus != NULL) { 947 device_delete_child(dev, sc->jme_miibus); 948 sc->jme_miibus = NULL; 949 } 950 bus_generic_detach(dev); 951 jme_dma_free(sc); 952 953 if (ifp != NULL) { 954 if_free(ifp); 955 sc->jme_ifp = NULL; 956 } 957 958 for (i = 0; i < 1; i++) { 959 if (sc->jme_intrhand[i] != NULL) { 960 bus_teardown_intr(dev, sc->jme_irq[i], 961 sc->jme_intrhand[i]); 962 sc->jme_intrhand[i] = NULL; 963 } 964 } 965 966 if (sc->jme_irq[0] != NULL) 967 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 968 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 969 pci_release_msi(dev); 970 if (sc->jme_res[0] != NULL) 971 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 972 mtx_destroy(&sc->jme_mtx); 973 974 return (0); 975 } 976 977 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 978 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 979 980 static void 981 jme_sysctl_node(struct jme_softc *sc) 982 { 983 struct sysctl_ctx_list *ctx; 984 struct sysctl_oid_list *child, *parent; 985 struct sysctl_oid *tree; 986 struct jme_hw_stats *stats; 987 int error; 988 989 stats = &sc->jme_stats; 990 ctx = device_get_sysctl_ctx(sc->jme_dev); 991 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 992 993 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 994 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_to, 995 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 996 997 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 998 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_pkt, 999 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 1000 1001 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 1002 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_to, 1003 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 1004 1005 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 1006 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_pkt, 1007 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 1008 1009 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1010 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1011 &sc->jme_process_limit, 0, sysctl_hw_jme_proc_limit, "I", 1012 "max number of Rx events to process"); 1013 1014 /* Pull in device tunables. */ 1015 sc->jme_process_limit = JME_PROC_DEFAULT; 1016 error = resource_int_value(device_get_name(sc->jme_dev), 1017 device_get_unit(sc->jme_dev), "process_limit", 1018 &sc->jme_process_limit); 1019 if (error == 0) { 1020 if (sc->jme_process_limit < JME_PROC_MIN || 1021 sc->jme_process_limit > JME_PROC_MAX) { 1022 device_printf(sc->jme_dev, 1023 "process_limit value out of range; " 1024 "using default: %d\n", JME_PROC_DEFAULT); 1025 sc->jme_process_limit = JME_PROC_DEFAULT; 1026 } 1027 } 1028 1029 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1030 error = resource_int_value(device_get_name(sc->jme_dev), 1031 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 1032 if (error == 0) { 1033 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 1034 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 1035 device_printf(sc->jme_dev, 1036 "tx_coal_to value out of range; " 1037 "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 1038 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1039 } 1040 } 1041 1042 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1043 error = resource_int_value(device_get_name(sc->jme_dev), 1044 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 1045 if (error == 0) { 1046 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 1047 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 1048 device_printf(sc->jme_dev, 1049 "tx_coal_pkt value out of range; " 1050 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 1051 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1052 } 1053 } 1054 1055 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1056 error = resource_int_value(device_get_name(sc->jme_dev), 1057 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 1058 if (error == 0) { 1059 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 1060 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 1061 device_printf(sc->jme_dev, 1062 "rx_coal_to value out of range; " 1063 "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 1064 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1065 } 1066 } 1067 1068 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1069 error = resource_int_value(device_get_name(sc->jme_dev), 1070 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 1071 if (error == 0) { 1072 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 1073 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 1074 device_printf(sc->jme_dev, 1075 "tx_coal_pkt value out of range; " 1076 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 1077 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1078 } 1079 } 1080 1081 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 1082 return; 1083 1084 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1085 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "JME statistics"); 1086 parent = SYSCTL_CHILDREN(tree); 1087 1088 /* Rx statistics. */ 1089 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1090 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1091 child = SYSCTL_CHILDREN(tree); 1092 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1093 &stats->rx_good_frames, "Good frames"); 1094 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1095 &stats->rx_crc_errs, "CRC errors"); 1096 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 1097 &stats->rx_mii_errs, "MII errors"); 1098 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1099 &stats->rx_fifo_oflows, "FIFO overflows"); 1100 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 1101 &stats->rx_desc_empty, "Descriptor empty"); 1102 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1103 &stats->rx_bad_frames, "Bad frames"); 1104 1105 /* Tx statistics. */ 1106 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1107 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1108 child = SYSCTL_CHILDREN(tree); 1109 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1110 &stats->tx_good_frames, "Good frames"); 1111 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1112 &stats->tx_bad_frames, "Bad frames"); 1113 } 1114 1115 #undef JME_SYSCTL_STAT_ADD32 1116 1117 struct jme_dmamap_arg { 1118 bus_addr_t jme_busaddr; 1119 }; 1120 1121 static void 1122 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1123 { 1124 struct jme_dmamap_arg *ctx; 1125 1126 if (error != 0) 1127 return; 1128 1129 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1130 1131 ctx = (struct jme_dmamap_arg *)arg; 1132 ctx->jme_busaddr = segs[0].ds_addr; 1133 } 1134 1135 static int 1136 jme_dma_alloc(struct jme_softc *sc) 1137 { 1138 struct jme_dmamap_arg ctx; 1139 struct jme_txdesc *txd; 1140 struct jme_rxdesc *rxd; 1141 bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1142 int error, i; 1143 1144 lowaddr = BUS_SPACE_MAXADDR; 1145 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1146 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1147 1148 again: 1149 /* Create parent ring tag. */ 1150 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1151 1, 0, /* algnmnt, boundary */ 1152 lowaddr, /* lowaddr */ 1153 BUS_SPACE_MAXADDR, /* highaddr */ 1154 NULL, NULL, /* filter, filterarg */ 1155 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1156 0, /* nsegments */ 1157 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1158 0, /* flags */ 1159 NULL, NULL, /* lockfunc, lockarg */ 1160 &sc->jme_cdata.jme_ring_tag); 1161 if (error != 0) { 1162 device_printf(sc->jme_dev, 1163 "could not create parent ring DMA tag.\n"); 1164 goto fail; 1165 } 1166 /* Create tag for Tx ring. */ 1167 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1168 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1169 BUS_SPACE_MAXADDR, /* lowaddr */ 1170 BUS_SPACE_MAXADDR, /* highaddr */ 1171 NULL, NULL, /* filter, filterarg */ 1172 JME_TX_RING_SIZE, /* maxsize */ 1173 1, /* nsegments */ 1174 JME_TX_RING_SIZE, /* maxsegsize */ 1175 0, /* flags */ 1176 NULL, NULL, /* lockfunc, lockarg */ 1177 &sc->jme_cdata.jme_tx_ring_tag); 1178 if (error != 0) { 1179 device_printf(sc->jme_dev, 1180 "could not allocate Tx ring DMA tag.\n"); 1181 goto fail; 1182 } 1183 1184 /* Create tag for Rx ring. */ 1185 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1186 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1187 lowaddr, /* lowaddr */ 1188 BUS_SPACE_MAXADDR, /* highaddr */ 1189 NULL, NULL, /* filter, filterarg */ 1190 JME_RX_RING_SIZE, /* maxsize */ 1191 1, /* nsegments */ 1192 JME_RX_RING_SIZE, /* maxsegsize */ 1193 0, /* flags */ 1194 NULL, NULL, /* lockfunc, lockarg */ 1195 &sc->jme_cdata.jme_rx_ring_tag); 1196 if (error != 0) { 1197 device_printf(sc->jme_dev, 1198 "could not allocate Rx ring DMA tag.\n"); 1199 goto fail; 1200 } 1201 1202 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1203 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1204 (void **)&sc->jme_rdata.jme_tx_ring, 1205 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1206 &sc->jme_cdata.jme_tx_ring_map); 1207 if (error != 0) { 1208 device_printf(sc->jme_dev, 1209 "could not allocate DMA'able memory for Tx ring.\n"); 1210 goto fail; 1211 } 1212 1213 ctx.jme_busaddr = 0; 1214 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1215 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1216 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1217 if (error != 0 || ctx.jme_busaddr == 0) { 1218 device_printf(sc->jme_dev, 1219 "could not load DMA'able memory for Tx ring.\n"); 1220 goto fail; 1221 } 1222 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1223 1224 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1225 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1226 (void **)&sc->jme_rdata.jme_rx_ring, 1227 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1228 &sc->jme_cdata.jme_rx_ring_map); 1229 if (error != 0) { 1230 device_printf(sc->jme_dev, 1231 "could not allocate DMA'able memory for Rx ring.\n"); 1232 goto fail; 1233 } 1234 1235 ctx.jme_busaddr = 0; 1236 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1237 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1238 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1239 if (error != 0 || ctx.jme_busaddr == 0) { 1240 device_printf(sc->jme_dev, 1241 "could not load DMA'able memory for Rx ring.\n"); 1242 goto fail; 1243 } 1244 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1245 1246 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1247 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1248 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1249 JME_TX_RING_SIZE; 1250 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1251 JME_RX_RING_SIZE; 1252 if ((JME_ADDR_HI(tx_ring_end) != 1253 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1254 (JME_ADDR_HI(rx_ring_end) != 1255 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1256 device_printf(sc->jme_dev, "4GB boundary crossed, " 1257 "switching to 32bit DMA address mode.\n"); 1258 jme_dma_free(sc); 1259 /* Limit DMA address space to 32bit and try again. */ 1260 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1261 goto again; 1262 } 1263 } 1264 1265 lowaddr = BUS_SPACE_MAXADDR; 1266 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1267 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1268 /* Create parent buffer tag. */ 1269 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1270 1, 0, /* algnmnt, boundary */ 1271 lowaddr, /* lowaddr */ 1272 BUS_SPACE_MAXADDR, /* highaddr */ 1273 NULL, NULL, /* filter, filterarg */ 1274 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1275 0, /* nsegments */ 1276 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1277 0, /* flags */ 1278 NULL, NULL, /* lockfunc, lockarg */ 1279 &sc->jme_cdata.jme_buffer_tag); 1280 if (error != 0) { 1281 device_printf(sc->jme_dev, 1282 "could not create parent buffer DMA tag.\n"); 1283 goto fail; 1284 } 1285 1286 /* Create shadow status block tag. */ 1287 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1288 JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1289 BUS_SPACE_MAXADDR, /* lowaddr */ 1290 BUS_SPACE_MAXADDR, /* highaddr */ 1291 NULL, NULL, /* filter, filterarg */ 1292 JME_SSB_SIZE, /* maxsize */ 1293 1, /* nsegments */ 1294 JME_SSB_SIZE, /* maxsegsize */ 1295 0, /* flags */ 1296 NULL, NULL, /* lockfunc, lockarg */ 1297 &sc->jme_cdata.jme_ssb_tag); 1298 if (error != 0) { 1299 device_printf(sc->jme_dev, 1300 "could not create shared status block DMA tag.\n"); 1301 goto fail; 1302 } 1303 1304 /* Create tag for Tx buffers. */ 1305 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1306 1, 0, /* algnmnt, boundary */ 1307 BUS_SPACE_MAXADDR, /* lowaddr */ 1308 BUS_SPACE_MAXADDR, /* highaddr */ 1309 NULL, NULL, /* filter, filterarg */ 1310 JME_TSO_MAXSIZE, /* maxsize */ 1311 JME_MAXTXSEGS, /* nsegments */ 1312 JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1313 0, /* flags */ 1314 NULL, NULL, /* lockfunc, lockarg */ 1315 &sc->jme_cdata.jme_tx_tag); 1316 if (error != 0) { 1317 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1318 goto fail; 1319 } 1320 1321 /* Create tag for Rx buffers. */ 1322 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1323 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1324 BUS_SPACE_MAXADDR, /* lowaddr */ 1325 BUS_SPACE_MAXADDR, /* highaddr */ 1326 NULL, NULL, /* filter, filterarg */ 1327 MCLBYTES, /* maxsize */ 1328 1, /* nsegments */ 1329 MCLBYTES, /* maxsegsize */ 1330 0, /* flags */ 1331 NULL, NULL, /* lockfunc, lockarg */ 1332 &sc->jme_cdata.jme_rx_tag); 1333 if (error != 0) { 1334 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1335 goto fail; 1336 } 1337 1338 /* 1339 * Allocate DMA'able memory and load the DMA map for shared 1340 * status block. 1341 */ 1342 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1343 (void **)&sc->jme_rdata.jme_ssb_block, 1344 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1345 &sc->jme_cdata.jme_ssb_map); 1346 if (error != 0) { 1347 device_printf(sc->jme_dev, "could not allocate DMA'able " 1348 "memory for shared status block.\n"); 1349 goto fail; 1350 } 1351 1352 ctx.jme_busaddr = 0; 1353 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1354 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1355 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1356 if (error != 0 || ctx.jme_busaddr == 0) { 1357 device_printf(sc->jme_dev, "could not load DMA'able memory " 1358 "for shared status block.\n"); 1359 goto fail; 1360 } 1361 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1362 1363 /* Create DMA maps for Tx buffers. */ 1364 for (i = 0; i < JME_TX_RING_CNT; i++) { 1365 txd = &sc->jme_cdata.jme_txdesc[i]; 1366 txd->tx_m = NULL; 1367 txd->tx_dmamap = NULL; 1368 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1369 &txd->tx_dmamap); 1370 if (error != 0) { 1371 device_printf(sc->jme_dev, 1372 "could not create Tx dmamap.\n"); 1373 goto fail; 1374 } 1375 } 1376 /* Create DMA maps for Rx buffers. */ 1377 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1378 &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1379 device_printf(sc->jme_dev, 1380 "could not create spare Rx dmamap.\n"); 1381 goto fail; 1382 } 1383 for (i = 0; i < JME_RX_RING_CNT; i++) { 1384 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1385 rxd->rx_m = NULL; 1386 rxd->rx_dmamap = NULL; 1387 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1388 &rxd->rx_dmamap); 1389 if (error != 0) { 1390 device_printf(sc->jme_dev, 1391 "could not create Rx dmamap.\n"); 1392 goto fail; 1393 } 1394 } 1395 1396 fail: 1397 return (error); 1398 } 1399 1400 static void 1401 jme_dma_free(struct jme_softc *sc) 1402 { 1403 struct jme_txdesc *txd; 1404 struct jme_rxdesc *rxd; 1405 int i; 1406 1407 /* Tx ring */ 1408 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1409 if (sc->jme_rdata.jme_tx_ring_paddr) 1410 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1411 sc->jme_cdata.jme_tx_ring_map); 1412 if (sc->jme_rdata.jme_tx_ring) 1413 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1414 sc->jme_rdata.jme_tx_ring, 1415 sc->jme_cdata.jme_tx_ring_map); 1416 sc->jme_rdata.jme_tx_ring = NULL; 1417 sc->jme_rdata.jme_tx_ring_paddr = 0; 1418 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1419 sc->jme_cdata.jme_tx_ring_tag = NULL; 1420 } 1421 /* Rx ring */ 1422 if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1423 if (sc->jme_rdata.jme_rx_ring_paddr) 1424 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1425 sc->jme_cdata.jme_rx_ring_map); 1426 if (sc->jme_rdata.jme_rx_ring) 1427 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1428 sc->jme_rdata.jme_rx_ring, 1429 sc->jme_cdata.jme_rx_ring_map); 1430 sc->jme_rdata.jme_rx_ring = NULL; 1431 sc->jme_rdata.jme_rx_ring_paddr = 0; 1432 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1433 sc->jme_cdata.jme_rx_ring_tag = NULL; 1434 } 1435 /* Tx buffers */ 1436 if (sc->jme_cdata.jme_tx_tag != NULL) { 1437 for (i = 0; i < JME_TX_RING_CNT; i++) { 1438 txd = &sc->jme_cdata.jme_txdesc[i]; 1439 if (txd->tx_dmamap != NULL) { 1440 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1441 txd->tx_dmamap); 1442 txd->tx_dmamap = NULL; 1443 } 1444 } 1445 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1446 sc->jme_cdata.jme_tx_tag = NULL; 1447 } 1448 /* Rx buffers */ 1449 if (sc->jme_cdata.jme_rx_tag != NULL) { 1450 for (i = 0; i < JME_RX_RING_CNT; i++) { 1451 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1452 if (rxd->rx_dmamap != NULL) { 1453 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1454 rxd->rx_dmamap); 1455 rxd->rx_dmamap = NULL; 1456 } 1457 } 1458 if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1459 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1460 sc->jme_cdata.jme_rx_sparemap); 1461 sc->jme_cdata.jme_rx_sparemap = NULL; 1462 } 1463 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1464 sc->jme_cdata.jme_rx_tag = NULL; 1465 } 1466 1467 /* Shared status block. */ 1468 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1469 if (sc->jme_rdata.jme_ssb_block_paddr) 1470 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1471 sc->jme_cdata.jme_ssb_map); 1472 if (sc->jme_rdata.jme_ssb_block) 1473 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1474 sc->jme_rdata.jme_ssb_block, 1475 sc->jme_cdata.jme_ssb_map); 1476 sc->jme_rdata.jme_ssb_block = NULL; 1477 sc->jme_rdata.jme_ssb_block_paddr = 0; 1478 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1479 sc->jme_cdata.jme_ssb_tag = NULL; 1480 } 1481 1482 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1483 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1484 sc->jme_cdata.jme_buffer_tag = NULL; 1485 } 1486 if (sc->jme_cdata.jme_ring_tag != NULL) { 1487 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1488 sc->jme_cdata.jme_ring_tag = NULL; 1489 } 1490 } 1491 1492 /* 1493 * Make sure the interface is stopped at reboot time. 1494 */ 1495 static int 1496 jme_shutdown(device_t dev) 1497 { 1498 1499 return (jme_suspend(dev)); 1500 } 1501 1502 /* 1503 * Unlike other ethernet controllers, JMC250 requires 1504 * explicit resetting link speed to 10/100Mbps as gigabit 1505 * link will cunsume more power than 375mA. 1506 * Note, we reset the link speed to 10/100Mbps with 1507 * auto-negotiation but we don't know whether that operation 1508 * would succeed or not as we have no control after powering 1509 * off. If the renegotiation fail WOL may not work. Running 1510 * at 1Gbps draws more power than 375mA at 3.3V which is 1511 * specified in PCI specification and that would result in 1512 * complete shutdowning power to ethernet controller. 1513 * 1514 * TODO 1515 * Save current negotiated media speed/duplex/flow-control 1516 * to softc and restore the same link again after resuming. 1517 * PHY handling such as power down/resetting to 100Mbps 1518 * may be better handled in suspend method in phy driver. 1519 */ 1520 static void 1521 jme_setlinkspeed(struct jme_softc *sc) 1522 { 1523 struct mii_data *mii; 1524 int aneg, i; 1525 1526 JME_LOCK_ASSERT(sc); 1527 1528 mii = device_get_softc(sc->jme_miibus); 1529 mii_pollstat(mii); 1530 aneg = 0; 1531 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1532 switch IFM_SUBTYPE(mii->mii_media_active) { 1533 case IFM_10_T: 1534 case IFM_100_TX: 1535 return; 1536 case IFM_1000_T: 1537 aneg++; 1538 default: 1539 break; 1540 } 1541 } 1542 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1543 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1544 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1545 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1546 BMCR_AUTOEN | BMCR_STARTNEG); 1547 DELAY(1000); 1548 if (aneg != 0) { 1549 /* Poll link state until jme(4) get a 10/100 link. */ 1550 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1551 mii_pollstat(mii); 1552 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1553 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1554 case IFM_10_T: 1555 case IFM_100_TX: 1556 jme_mac_config(sc); 1557 return; 1558 default: 1559 break; 1560 } 1561 } 1562 JME_UNLOCK(sc); 1563 pause("jmelnk", hz); 1564 JME_LOCK(sc); 1565 } 1566 if (i == MII_ANEGTICKS_GIGE) 1567 device_printf(sc->jme_dev, "establishing link failed, " 1568 "WOL may not work!"); 1569 } 1570 /* 1571 * No link, force MAC to have 100Mbps, full-duplex link. 1572 * This is the last resort and may/may not work. 1573 */ 1574 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1575 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1576 jme_mac_config(sc); 1577 } 1578 1579 static void 1580 jme_setwol(struct jme_softc *sc) 1581 { 1582 if_t ifp; 1583 uint32_t gpr, pmcs; 1584 uint16_t pmstat; 1585 int pmc; 1586 1587 JME_LOCK_ASSERT(sc); 1588 1589 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1590 /* Remove Tx MAC/offload clock to save more power. */ 1591 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1592 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1593 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1594 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1595 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 1596 CSR_WRITE_4(sc, JME_GPREG1, 1597 CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS); 1598 /* No PME capability, PHY power down. */ 1599 jme_phy_down(sc); 1600 return; 1601 } 1602 1603 ifp = sc->jme_ifp; 1604 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1605 pmcs = CSR_READ_4(sc, JME_PMCS); 1606 pmcs &= ~PMCS_WOL_ENB_MASK; 1607 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 1608 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1609 /* Enable PME message. */ 1610 gpr |= GPREG0_PME_ENB; 1611 /* For gigabit controllers, reset link speed to 10/100. */ 1612 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1613 jme_setlinkspeed(sc); 1614 } 1615 1616 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1617 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1618 /* Remove Tx MAC/offload clock to save more power. */ 1619 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1620 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1621 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1622 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1623 /* Request PME. */ 1624 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1625 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1626 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1627 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1628 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1629 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1630 /* No WOL, PHY power down. */ 1631 jme_phy_down(sc); 1632 } 1633 } 1634 1635 static int 1636 jme_suspend(device_t dev) 1637 { 1638 struct jme_softc *sc; 1639 1640 sc = device_get_softc(dev); 1641 1642 JME_LOCK(sc); 1643 jme_stop(sc); 1644 jme_setwol(sc); 1645 JME_UNLOCK(sc); 1646 1647 return (0); 1648 } 1649 1650 static int 1651 jme_resume(device_t dev) 1652 { 1653 struct jme_softc *sc; 1654 if_t ifp; 1655 uint16_t pmstat; 1656 int pmc; 1657 1658 sc = device_get_softc(dev); 1659 1660 JME_LOCK(sc); 1661 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) == 0) { 1662 pmstat = pci_read_config(sc->jme_dev, 1663 pmc + PCIR_POWER_STATUS, 2); 1664 /* Disable PME clear PME status. */ 1665 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1666 pci_write_config(sc->jme_dev, 1667 pmc + PCIR_POWER_STATUS, pmstat, 2); 1668 } 1669 /* Wakeup PHY. */ 1670 jme_phy_up(sc); 1671 ifp = sc->jme_ifp; 1672 if ((if_getflags(ifp) & IFF_UP) != 0) { 1673 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1674 jme_init_locked(sc); 1675 } 1676 1677 JME_UNLOCK(sc); 1678 1679 return (0); 1680 } 1681 1682 static int 1683 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1684 { 1685 struct jme_txdesc *txd; 1686 struct jme_desc *desc; 1687 struct mbuf *m; 1688 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1689 int error, i, nsegs, prod; 1690 uint32_t cflags, tsosegsz; 1691 1692 JME_LOCK_ASSERT(sc); 1693 1694 M_ASSERTPKTHDR((*m_head)); 1695 1696 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1697 /* 1698 * Due to the adherence to NDIS specification JMC250 1699 * assumes upper stack computed TCP pseudo checksum 1700 * without including payload length. This breaks 1701 * checksum offload for TSO case so recompute TCP 1702 * pseudo checksum for JMC250. Hopefully this wouldn't 1703 * be much burden on modern CPUs. 1704 */ 1705 struct ether_header *eh; 1706 struct ip *ip; 1707 struct tcphdr *tcp; 1708 uint32_t ip_off, poff; 1709 1710 if (M_WRITABLE(*m_head) == 0) { 1711 /* Get a writable copy. */ 1712 m = m_dup(*m_head, M_NOWAIT); 1713 m_freem(*m_head); 1714 if (m == NULL) { 1715 *m_head = NULL; 1716 return (ENOBUFS); 1717 } 1718 *m_head = m; 1719 } 1720 ip_off = sizeof(struct ether_header); 1721 m = m_pullup(*m_head, ip_off); 1722 if (m == NULL) { 1723 *m_head = NULL; 1724 return (ENOBUFS); 1725 } 1726 eh = mtod(m, struct ether_header *); 1727 /* Check the existence of VLAN tag. */ 1728 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1729 ip_off = sizeof(struct ether_vlan_header); 1730 m = m_pullup(m, ip_off); 1731 if (m == NULL) { 1732 *m_head = NULL; 1733 return (ENOBUFS); 1734 } 1735 } 1736 m = m_pullup(m, ip_off + sizeof(struct ip)); 1737 if (m == NULL) { 1738 *m_head = NULL; 1739 return (ENOBUFS); 1740 } 1741 ip = (struct ip *)(mtod(m, char *) + ip_off); 1742 poff = ip_off + (ip->ip_hl << 2); 1743 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1744 if (m == NULL) { 1745 *m_head = NULL; 1746 return (ENOBUFS); 1747 } 1748 /* 1749 * Reset IP checksum and recompute TCP pseudo 1750 * checksum that NDIS specification requires. 1751 */ 1752 ip = (struct ip *)(mtod(m, char *) + ip_off); 1753 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1754 ip->ip_sum = 0; 1755 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1756 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1757 ip->ip_dst.s_addr, 1758 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1759 /* No need to TSO, force IP checksum offload. */ 1760 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1761 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1762 } else 1763 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1764 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1765 *m_head = m; 1766 } 1767 1768 prod = sc->jme_cdata.jme_tx_prod; 1769 txd = &sc->jme_cdata.jme_txdesc[prod]; 1770 1771 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1772 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1773 if (error == EFBIG) { 1774 m = m_collapse(*m_head, M_NOWAIT, JME_MAXTXSEGS); 1775 if (m == NULL) { 1776 m_freem(*m_head); 1777 *m_head = NULL; 1778 return (ENOMEM); 1779 } 1780 *m_head = m; 1781 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1782 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1783 if (error != 0) { 1784 m_freem(*m_head); 1785 *m_head = NULL; 1786 return (error); 1787 } 1788 } else if (error != 0) 1789 return (error); 1790 if (nsegs == 0) { 1791 m_freem(*m_head); 1792 *m_head = NULL; 1793 return (EIO); 1794 } 1795 1796 /* 1797 * Check descriptor overrun. Leave one free descriptor. 1798 * Since we always use 64bit address mode for transmitting, 1799 * each Tx request requires one more dummy descriptor. 1800 */ 1801 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1802 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1803 return (ENOBUFS); 1804 } 1805 1806 m = *m_head; 1807 cflags = 0; 1808 tsosegsz = 0; 1809 /* Configure checksum offload and TSO. */ 1810 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1811 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 1812 JME_TD_MSS_SHIFT; 1813 cflags |= JME_TD_TSO; 1814 } else { 1815 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1816 cflags |= JME_TD_IPCSUM; 1817 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1818 cflags |= JME_TD_TCPCSUM; 1819 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1820 cflags |= JME_TD_UDPCSUM; 1821 } 1822 /* Configure VLAN. */ 1823 if ((m->m_flags & M_VLANTAG) != 0) { 1824 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1825 cflags |= JME_TD_VLAN_TAG; 1826 } 1827 1828 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1829 desc->flags = htole32(cflags); 1830 desc->buflen = htole32(tsosegsz); 1831 desc->addr_hi = htole32(m->m_pkthdr.len); 1832 desc->addr_lo = 0; 1833 sc->jme_cdata.jme_tx_cnt++; 1834 JME_DESC_INC(prod, JME_TX_RING_CNT); 1835 for (i = 0; i < nsegs; i++) { 1836 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1837 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1838 desc->buflen = htole32(txsegs[i].ds_len); 1839 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1840 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1841 sc->jme_cdata.jme_tx_cnt++; 1842 JME_DESC_INC(prod, JME_TX_RING_CNT); 1843 } 1844 1845 /* Update producer index. */ 1846 sc->jme_cdata.jme_tx_prod = prod; 1847 /* 1848 * Finally request interrupt and give the first descriptor 1849 * owenership to hardware. 1850 */ 1851 desc = txd->tx_desc; 1852 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1853 1854 txd->tx_m = m; 1855 txd->tx_ndesc = nsegs + 1; 1856 1857 /* Sync descriptors. */ 1858 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1859 BUS_DMASYNC_PREWRITE); 1860 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1861 sc->jme_cdata.jme_tx_ring_map, 1862 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1863 1864 return (0); 1865 } 1866 1867 static void 1868 jme_start(if_t ifp) 1869 { 1870 struct jme_softc *sc; 1871 1872 sc = if_getsoftc(ifp); 1873 JME_LOCK(sc); 1874 jme_start_locked(ifp); 1875 JME_UNLOCK(sc); 1876 } 1877 1878 static void 1879 jme_start_locked(if_t ifp) 1880 { 1881 struct jme_softc *sc; 1882 struct mbuf *m_head; 1883 int enq; 1884 1885 sc = if_getsoftc(ifp); 1886 1887 JME_LOCK_ASSERT(sc); 1888 1889 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1890 jme_txeof(sc); 1891 1892 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1893 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) 1894 return; 1895 1896 for (enq = 0; !if_sendq_empty(ifp); ) { 1897 m_head = if_dequeue(ifp); 1898 if (m_head == NULL) 1899 break; 1900 /* 1901 * Pack the data into the transmit ring. If we 1902 * don't have room, set the OACTIVE flag and wait 1903 * for the NIC to drain the ring. 1904 */ 1905 if (jme_encap(sc, &m_head)) { 1906 if (m_head == NULL) 1907 break; 1908 if_sendq_prepend(ifp, m_head); 1909 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1910 break; 1911 } 1912 1913 enq++; 1914 /* 1915 * If there's a BPF listener, bounce a copy of this frame 1916 * to him. 1917 */ 1918 ETHER_BPF_MTAP(ifp, m_head); 1919 } 1920 1921 if (enq > 0) { 1922 /* 1923 * Reading TXCSR takes very long time under heavy load 1924 * so cache TXCSR value and writes the ORed value with 1925 * the kick command to the TXCSR. This saves one register 1926 * access cycle. 1927 */ 1928 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1929 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1930 /* Set a timeout in case the chip goes out to lunch. */ 1931 sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1932 } 1933 } 1934 1935 static void 1936 jme_watchdog(struct jme_softc *sc) 1937 { 1938 if_t ifp; 1939 1940 JME_LOCK_ASSERT(sc); 1941 1942 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1943 return; 1944 1945 ifp = sc->jme_ifp; 1946 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1947 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1948 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1949 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1950 jme_init_locked(sc); 1951 return; 1952 } 1953 jme_txeof(sc); 1954 if (sc->jme_cdata.jme_tx_cnt == 0) { 1955 if_printf(sc->jme_ifp, 1956 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1957 if (!if_sendq_empty(ifp)) 1958 jme_start_locked(ifp); 1959 return; 1960 } 1961 1962 if_printf(sc->jme_ifp, "watchdog timeout\n"); 1963 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1964 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1965 jme_init_locked(sc); 1966 if (!if_sendq_empty(ifp)) 1967 jme_start_locked(ifp); 1968 } 1969 1970 static int 1971 jme_ioctl(if_t ifp, u_long cmd, caddr_t data) 1972 { 1973 struct jme_softc *sc; 1974 struct ifreq *ifr; 1975 struct mii_data *mii; 1976 uint32_t reg; 1977 int error, mask; 1978 1979 sc = if_getsoftc(ifp); 1980 ifr = (struct ifreq *)data; 1981 error = 0; 1982 switch (cmd) { 1983 case SIOCSIFMTU: 1984 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1985 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1986 ifr->ifr_mtu > JME_MAX_MTU)) { 1987 error = EINVAL; 1988 break; 1989 } 1990 1991 if (if_getmtu(ifp) != ifr->ifr_mtu) { 1992 /* 1993 * No special configuration is required when interface 1994 * MTU is changed but availability of TSO/Tx checksum 1995 * offload should be chcked against new MTU size as 1996 * FIFO size is just 2K. 1997 */ 1998 JME_LOCK(sc); 1999 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 2000 if_setcapenablebit(ifp, 0, 2001 IFCAP_TXCSUM | IFCAP_TSO4); 2002 if_sethwassistbits(ifp, 0, 2003 JME_CSUM_FEATURES | CSUM_TSO); 2004 VLAN_CAPABILITIES(ifp); 2005 } 2006 if_setmtu(ifp, ifr->ifr_mtu); 2007 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2008 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2009 jme_init_locked(sc); 2010 } 2011 JME_UNLOCK(sc); 2012 } 2013 break; 2014 case SIOCSIFFLAGS: 2015 JME_LOCK(sc); 2016 if ((if_getflags(ifp) & IFF_UP) != 0) { 2017 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2018 if (((if_getflags(ifp) ^ sc->jme_if_flags) 2019 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2020 jme_set_filter(sc); 2021 } else { 2022 if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 2023 jme_init_locked(sc); 2024 } 2025 } else { 2026 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2027 jme_stop(sc); 2028 } 2029 sc->jme_if_flags = if_getflags(ifp); 2030 JME_UNLOCK(sc); 2031 break; 2032 case SIOCADDMULTI: 2033 case SIOCDELMULTI: 2034 JME_LOCK(sc); 2035 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2036 jme_set_filter(sc); 2037 JME_UNLOCK(sc); 2038 break; 2039 case SIOCSIFMEDIA: 2040 case SIOCGIFMEDIA: 2041 mii = device_get_softc(sc->jme_miibus); 2042 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2043 break; 2044 case SIOCSIFCAP: 2045 JME_LOCK(sc); 2046 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2047 if ((mask & IFCAP_TXCSUM) != 0 && 2048 if_getmtu(ifp) < JME_TX_FIFO_SIZE) { 2049 if ((IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 2050 if_togglecapenable(ifp, IFCAP_TXCSUM); 2051 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 2052 if_sethwassistbits(ifp, JME_CSUM_FEATURES, 0); 2053 else 2054 if_sethwassistbits(ifp, 0, JME_CSUM_FEATURES); 2055 } 2056 } 2057 if ((mask & IFCAP_RXCSUM) != 0 && 2058 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) { 2059 if_togglecapenable(ifp, IFCAP_RXCSUM); 2060 reg = CSR_READ_4(sc, JME_RXMAC); 2061 reg &= ~RXMAC_CSUM_ENB; 2062 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2063 reg |= RXMAC_CSUM_ENB; 2064 CSR_WRITE_4(sc, JME_RXMAC, reg); 2065 } 2066 if ((mask & IFCAP_TSO4) != 0 && 2067 if_getmtu(ifp) < JME_TX_FIFO_SIZE) { 2068 if ((IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) { 2069 if_togglecapenable(ifp, IFCAP_TSO4); 2070 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 2071 if_sethwassistbits(ifp, CSUM_TSO, 0); 2072 else 2073 if_sethwassistbits(ifp, 0, CSUM_TSO); 2074 } 2075 } 2076 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2077 (IFCAP_WOL_MAGIC & if_getcapabilities(ifp)) != 0) 2078 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2079 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2080 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2081 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2082 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2083 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2084 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2085 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2086 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 2087 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2088 jme_set_vlan(sc); 2089 } 2090 JME_UNLOCK(sc); 2091 VLAN_CAPABILITIES(ifp); 2092 break; 2093 default: 2094 error = ether_ioctl(ifp, cmd, data); 2095 break; 2096 } 2097 2098 return (error); 2099 } 2100 2101 static void 2102 jme_mac_config(struct jme_softc *sc) 2103 { 2104 struct mii_data *mii; 2105 uint32_t ghc, gpreg, rxmac, txmac, txpause; 2106 uint32_t txclk; 2107 2108 JME_LOCK_ASSERT(sc); 2109 2110 mii = device_get_softc(sc->jme_miibus); 2111 2112 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2113 DELAY(10); 2114 CSR_WRITE_4(sc, JME_GHC, 0); 2115 ghc = 0; 2116 txclk = 0; 2117 rxmac = CSR_READ_4(sc, JME_RXMAC); 2118 rxmac &= ~RXMAC_FC_ENB; 2119 txmac = CSR_READ_4(sc, JME_TXMAC); 2120 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2121 txpause = CSR_READ_4(sc, JME_TXPFC); 2122 txpause &= ~TXPFC_PAUSE_ENB; 2123 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2124 ghc |= GHC_FULL_DUPLEX; 2125 rxmac &= ~RXMAC_COLL_DET_ENB; 2126 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2127 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2128 TXMAC_FRAME_BURST); 2129 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2130 txpause |= TXPFC_PAUSE_ENB; 2131 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2132 rxmac |= RXMAC_FC_ENB; 2133 /* Disable retry transmit timer/retry limit. */ 2134 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2135 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2136 } else { 2137 rxmac |= RXMAC_COLL_DET_ENB; 2138 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2139 /* Enable retry transmit timer/retry limit. */ 2140 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2141 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2142 } 2143 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2144 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2145 case IFM_10_T: 2146 ghc |= GHC_SPEED_10; 2147 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2148 break; 2149 case IFM_100_TX: 2150 ghc |= GHC_SPEED_100; 2151 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2152 break; 2153 case IFM_1000_T: 2154 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2155 break; 2156 ghc |= GHC_SPEED_1000; 2157 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2158 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2159 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2160 break; 2161 default: 2162 break; 2163 } 2164 if (sc->jme_rev == DEVICEID_JMC250 && 2165 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2166 /* 2167 * Workaround occasional packet loss issue of JMC250 A2 2168 * when it runs on half-duplex media. 2169 */ 2170 gpreg = CSR_READ_4(sc, JME_GPREG1); 2171 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2172 gpreg &= ~GPREG1_HDPX_FIX; 2173 else 2174 gpreg |= GPREG1_HDPX_FIX; 2175 CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2176 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2177 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2178 /* Extend interface FIFO depth. */ 2179 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2180 0x1B, 0x0000); 2181 } else { 2182 /* Select default interface FIFO depth. */ 2183 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2184 0x1B, 0x0004); 2185 } 2186 } 2187 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2188 ghc |= txclk; 2189 CSR_WRITE_4(sc, JME_GHC, ghc); 2190 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2191 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2192 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2193 } 2194 2195 static void 2196 jme_link_task(void *arg, int pending) 2197 { 2198 struct jme_softc *sc; 2199 struct mii_data *mii; 2200 if_t ifp; 2201 struct jme_txdesc *txd; 2202 bus_addr_t paddr; 2203 int i; 2204 2205 sc = (struct jme_softc *)arg; 2206 2207 JME_LOCK(sc); 2208 mii = device_get_softc(sc->jme_miibus); 2209 ifp = sc->jme_ifp; 2210 if (mii == NULL || ifp == NULL || 2211 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2212 JME_UNLOCK(sc); 2213 return; 2214 } 2215 2216 sc->jme_flags &= ~JME_FLAG_LINK; 2217 if ((mii->mii_media_status & IFM_AVALID) != 0) { 2218 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2219 case IFM_10_T: 2220 case IFM_100_TX: 2221 sc->jme_flags |= JME_FLAG_LINK; 2222 break; 2223 case IFM_1000_T: 2224 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2225 break; 2226 sc->jme_flags |= JME_FLAG_LINK; 2227 break; 2228 default: 2229 break; 2230 } 2231 } 2232 2233 /* 2234 * Disabling Rx/Tx MACs have a side-effect of resetting 2235 * JME_TXNDA/JME_RXNDA register to the first address of 2236 * Tx/Rx descriptor address. So driver should reset its 2237 * internal procucer/consumer pointer and reclaim any 2238 * allocated resources. Note, just saving the value of 2239 * JME_TXNDA and JME_RXNDA registers before stopping MAC 2240 * and restoring JME_TXNDA/JME_RXNDA register is not 2241 * sufficient to make sure correct MAC state because 2242 * stopping MAC operation can take a while and hardware 2243 * might have updated JME_TXNDA/JME_RXNDA registers 2244 * during the stop operation. 2245 */ 2246 /* Block execution of task. */ 2247 taskqueue_block(sc->jme_tq); 2248 /* Disable interrupts and stop driver. */ 2249 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2250 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2251 callout_stop(&sc->jme_tick_ch); 2252 sc->jme_watchdog_timer = 0; 2253 2254 /* Stop receiver/transmitter. */ 2255 jme_stop_rx(sc); 2256 jme_stop_tx(sc); 2257 2258 /* XXX Drain all queued tasks. */ 2259 JME_UNLOCK(sc); 2260 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2261 JME_LOCK(sc); 2262 2263 if (sc->jme_cdata.jme_rxhead != NULL) 2264 m_freem(sc->jme_cdata.jme_rxhead); 2265 JME_RXCHAIN_RESET(sc); 2266 jme_txeof(sc); 2267 if (sc->jme_cdata.jme_tx_cnt != 0) { 2268 /* Remove queued packets for transmit. */ 2269 for (i = 0; i < JME_TX_RING_CNT; i++) { 2270 txd = &sc->jme_cdata.jme_txdesc[i]; 2271 if (txd->tx_m != NULL) { 2272 bus_dmamap_sync( 2273 sc->jme_cdata.jme_tx_tag, 2274 txd->tx_dmamap, 2275 BUS_DMASYNC_POSTWRITE); 2276 bus_dmamap_unload( 2277 sc->jme_cdata.jme_tx_tag, 2278 txd->tx_dmamap); 2279 m_freem(txd->tx_m); 2280 txd->tx_m = NULL; 2281 txd->tx_ndesc = 0; 2282 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2283 } 2284 } 2285 } 2286 2287 /* 2288 * Reuse configured Rx descriptors and reset 2289 * producer/consumer index. 2290 */ 2291 sc->jme_cdata.jme_rx_cons = 0; 2292 sc->jme_morework = 0; 2293 jme_init_tx_ring(sc); 2294 /* Initialize shadow status block. */ 2295 jme_init_ssb(sc); 2296 2297 /* Program MAC with resolved speed/duplex/flow-control. */ 2298 if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2299 jme_mac_config(sc); 2300 jme_stats_clear(sc); 2301 2302 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2303 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2304 2305 /* Set Tx ring address to the hardware. */ 2306 paddr = JME_TX_RING_ADDR(sc, 0); 2307 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2308 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2309 2310 /* Set Rx ring address to the hardware. */ 2311 paddr = JME_RX_RING_ADDR(sc, 0); 2312 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2313 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2314 2315 /* Restart receiver/transmitter. */ 2316 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2317 RXCSR_RXQ_START); 2318 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2319 /* Lastly enable TX/RX clock. */ 2320 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2321 CSR_WRITE_4(sc, JME_GHC, 2322 CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS); 2323 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 2324 CSR_WRITE_4(sc, JME_GPREG1, 2325 CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS); 2326 } 2327 2328 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2329 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2330 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2331 /* Unblock execution of task. */ 2332 taskqueue_unblock(sc->jme_tq); 2333 /* Reenable interrupts. */ 2334 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2335 2336 JME_UNLOCK(sc); 2337 } 2338 2339 static int 2340 jme_intr(void *arg) 2341 { 2342 struct jme_softc *sc; 2343 uint32_t status; 2344 2345 sc = (struct jme_softc *)arg; 2346 2347 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2348 if (status == 0 || status == 0xFFFFFFFF) 2349 return (FILTER_STRAY); 2350 /* Disable interrupts. */ 2351 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2352 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2353 2354 return (FILTER_HANDLED); 2355 } 2356 2357 static void 2358 jme_int_task(void *arg, int pending) 2359 { 2360 struct jme_softc *sc; 2361 if_t ifp; 2362 uint32_t status; 2363 int more; 2364 2365 sc = (struct jme_softc *)arg; 2366 ifp = sc->jme_ifp; 2367 2368 JME_LOCK(sc); 2369 status = CSR_READ_4(sc, JME_INTR_STATUS); 2370 if (sc->jme_morework != 0) { 2371 sc->jme_morework = 0; 2372 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2373 } 2374 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2375 goto done; 2376 /* Reset PCC counter/timer and Ack interrupts. */ 2377 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2378 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2379 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2380 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2381 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2382 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2383 more = 0; 2384 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2385 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2386 more = jme_rxintr(sc, sc->jme_process_limit); 2387 if (more != 0) 2388 sc->jme_morework = 1; 2389 } 2390 if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2391 /* 2392 * Notify hardware availability of new Rx 2393 * buffers. 2394 * Reading RXCSR takes very long time under 2395 * heavy load so cache RXCSR value and writes 2396 * the ORed value with the kick command to 2397 * the RXCSR. This saves one register access 2398 * cycle. 2399 */ 2400 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2401 RXCSR_RX_ENB | RXCSR_RXQ_START); 2402 } 2403 if (!if_sendq_empty(ifp)) 2404 jme_start_locked(ifp); 2405 } 2406 2407 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2408 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2409 JME_UNLOCK(sc); 2410 return; 2411 } 2412 done: 2413 JME_UNLOCK(sc); 2414 2415 /* Reenable interrupts. */ 2416 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2417 } 2418 2419 static void 2420 jme_txeof(struct jme_softc *sc) 2421 { 2422 if_t ifp; 2423 struct jme_txdesc *txd; 2424 uint32_t status; 2425 int cons, nsegs; 2426 2427 JME_LOCK_ASSERT(sc); 2428 2429 ifp = sc->jme_ifp; 2430 2431 cons = sc->jme_cdata.jme_tx_cons; 2432 if (cons == sc->jme_cdata.jme_tx_prod) 2433 return; 2434 2435 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2436 sc->jme_cdata.jme_tx_ring_map, 2437 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2438 2439 /* 2440 * Go through our Tx list and free mbufs for those 2441 * frames which have been transmitted. 2442 */ 2443 for (; cons != sc->jme_cdata.jme_tx_prod;) { 2444 txd = &sc->jme_cdata.jme_txdesc[cons]; 2445 status = le32toh(txd->tx_desc->flags); 2446 if ((status & JME_TD_OWN) == JME_TD_OWN) 2447 break; 2448 2449 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2450 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2451 else { 2452 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2453 if ((status & JME_TD_COLLISION) != 0) 2454 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2455 le32toh(txd->tx_desc->buflen) & 2456 JME_TD_BUF_LEN_MASK); 2457 } 2458 /* 2459 * Only the first descriptor of multi-descriptor 2460 * transmission is updated so driver have to skip entire 2461 * chained buffers for the transmiited frame. In other 2462 * words, JME_TD_OWN bit is valid only at the first 2463 * descriptor of a multi-descriptor transmission. 2464 */ 2465 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2466 sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2467 JME_DESC_INC(cons, JME_TX_RING_CNT); 2468 } 2469 2470 /* Reclaim transferred mbufs. */ 2471 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2472 BUS_DMASYNC_POSTWRITE); 2473 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2474 2475 KASSERT(txd->tx_m != NULL, 2476 ("%s: freeing NULL mbuf!\n", __func__)); 2477 m_freem(txd->tx_m); 2478 txd->tx_m = NULL; 2479 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2480 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2481 ("%s: Active Tx desc counter was garbled\n", __func__)); 2482 txd->tx_ndesc = 0; 2483 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2484 } 2485 sc->jme_cdata.jme_tx_cons = cons; 2486 /* Unarm watchdog timer when there is no pending descriptors in queue. */ 2487 if (sc->jme_cdata.jme_tx_cnt == 0) 2488 sc->jme_watchdog_timer = 0; 2489 2490 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2491 sc->jme_cdata.jme_tx_ring_map, 2492 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2493 } 2494 2495 static __inline void 2496 jme_discard_rxbuf(struct jme_softc *sc, int cons) 2497 { 2498 struct jme_desc *desc; 2499 2500 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2501 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2502 desc->buflen = htole32(MCLBYTES); 2503 } 2504 2505 /* Receive a frame. */ 2506 static void 2507 jme_rxeof(struct jme_softc *sc) 2508 { 2509 if_t ifp; 2510 struct jme_desc *desc; 2511 struct jme_rxdesc *rxd; 2512 struct mbuf *mp, *m; 2513 uint32_t flags, status; 2514 int cons, count, nsegs; 2515 2516 JME_LOCK_ASSERT(sc); 2517 2518 ifp = sc->jme_ifp; 2519 2520 cons = sc->jme_cdata.jme_rx_cons; 2521 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2522 flags = le32toh(desc->flags); 2523 status = le32toh(desc->buflen); 2524 nsegs = JME_RX_NSEGS(status); 2525 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2526 if ((status & JME_RX_ERR_STAT) != 0) { 2527 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2528 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2529 #ifdef JME_SHOW_ERRORS 2530 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2531 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2532 #endif 2533 sc->jme_cdata.jme_rx_cons += nsegs; 2534 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2535 return; 2536 } 2537 2538 for (count = 0; count < nsegs; count++, 2539 JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2540 rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2541 mp = rxd->rx_m; 2542 /* Add a new receive buffer to the ring. */ 2543 if (jme_newbuf(sc, rxd) != 0) { 2544 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2545 /* Reuse buffer. */ 2546 for (; count < nsegs; count++) { 2547 jme_discard_rxbuf(sc, cons); 2548 JME_DESC_INC(cons, JME_RX_RING_CNT); 2549 } 2550 if (sc->jme_cdata.jme_rxhead != NULL) { 2551 m_freem(sc->jme_cdata.jme_rxhead); 2552 JME_RXCHAIN_RESET(sc); 2553 } 2554 break; 2555 } 2556 2557 /* 2558 * Assume we've received a full sized frame. 2559 * Actual size is fixed when we encounter the end of 2560 * multi-segmented frame. 2561 */ 2562 mp->m_len = MCLBYTES; 2563 2564 /* Chain received mbufs. */ 2565 if (sc->jme_cdata.jme_rxhead == NULL) { 2566 sc->jme_cdata.jme_rxhead = mp; 2567 sc->jme_cdata.jme_rxtail = mp; 2568 } else { 2569 /* 2570 * Receive processor can receive a maximum frame 2571 * size of 65535 bytes. 2572 */ 2573 mp->m_flags &= ~M_PKTHDR; 2574 sc->jme_cdata.jme_rxtail->m_next = mp; 2575 sc->jme_cdata.jme_rxtail = mp; 2576 } 2577 2578 if (count == nsegs - 1) { 2579 /* Last desc. for this frame. */ 2580 m = sc->jme_cdata.jme_rxhead; 2581 m->m_flags |= M_PKTHDR; 2582 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2583 if (nsegs > 1) { 2584 /* Set first mbuf size. */ 2585 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2586 /* Set last mbuf size. */ 2587 mp->m_len = sc->jme_cdata.jme_rxlen - 2588 ((MCLBYTES - JME_RX_PAD_BYTES) + 2589 (MCLBYTES * (nsegs - 2))); 2590 } else 2591 m->m_len = sc->jme_cdata.jme_rxlen; 2592 m->m_pkthdr.rcvif = ifp; 2593 2594 /* 2595 * Account for 10bytes auto padding which is used 2596 * to align IP header on 32bit boundary. Also note, 2597 * CRC bytes is automatically removed by the 2598 * hardware. 2599 */ 2600 m->m_data += JME_RX_PAD_BYTES; 2601 2602 /* Set checksum information. */ 2603 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2604 (flags & JME_RD_IPV4) != 0) { 2605 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2606 if ((flags & JME_RD_IPCSUM) != 0) 2607 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2608 if (((flags & JME_RD_MORE_FRAG) == 0) && 2609 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2610 (JME_RD_TCP | JME_RD_TCPCSUM) || 2611 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2612 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2613 m->m_pkthdr.csum_flags |= 2614 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2615 m->m_pkthdr.csum_data = 0xffff; 2616 } 2617 } 2618 2619 /* Check for VLAN tagged packets. */ 2620 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2621 (flags & JME_RD_VLAN_TAG) != 0) { 2622 m->m_pkthdr.ether_vtag = 2623 flags & JME_RD_VLAN_MASK; 2624 m->m_flags |= M_VLANTAG; 2625 } 2626 2627 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2628 /* Pass it on. */ 2629 JME_UNLOCK(sc); 2630 if_input(ifp, m); 2631 JME_LOCK(sc); 2632 2633 /* Reset mbuf chains. */ 2634 JME_RXCHAIN_RESET(sc); 2635 } 2636 } 2637 2638 sc->jme_cdata.jme_rx_cons += nsegs; 2639 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2640 } 2641 2642 static int 2643 jme_rxintr(struct jme_softc *sc, int count) 2644 { 2645 struct jme_desc *desc; 2646 int nsegs, prog, pktlen; 2647 2648 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2649 sc->jme_cdata.jme_rx_ring_map, 2650 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2651 2652 for (prog = 0; count > 0; prog++) { 2653 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2654 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2655 break; 2656 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2657 break; 2658 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2659 /* 2660 * Check number of segments against received bytes. 2661 * Non-matching value would indicate that hardware 2662 * is still trying to update Rx descriptors. I'm not 2663 * sure whether this check is needed. 2664 */ 2665 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2666 if (nsegs != howmany(pktlen, MCLBYTES)) 2667 break; 2668 prog++; 2669 /* Received a frame. */ 2670 jme_rxeof(sc); 2671 count -= nsegs; 2672 } 2673 2674 if (prog > 0) 2675 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2676 sc->jme_cdata.jme_rx_ring_map, 2677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2678 2679 return (count > 0 ? 0 : EAGAIN); 2680 } 2681 2682 static void 2683 jme_tick(void *arg) 2684 { 2685 struct jme_softc *sc; 2686 struct mii_data *mii; 2687 2688 sc = (struct jme_softc *)arg; 2689 2690 JME_LOCK_ASSERT(sc); 2691 2692 mii = device_get_softc(sc->jme_miibus); 2693 mii_tick(mii); 2694 /* 2695 * Reclaim Tx buffers that have been completed. It's not 2696 * needed here but it would release allocated mbuf chains 2697 * faster and limit the maximum delay to a hz. 2698 */ 2699 jme_txeof(sc); 2700 jme_stats_update(sc); 2701 jme_watchdog(sc); 2702 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2703 } 2704 2705 static void 2706 jme_reset(struct jme_softc *sc) 2707 { 2708 uint32_t ghc, gpreg; 2709 2710 /* Stop receiver, transmitter. */ 2711 jme_stop_rx(sc); 2712 jme_stop_tx(sc); 2713 2714 /* Reset controller. */ 2715 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2716 CSR_READ_4(sc, JME_GHC); 2717 DELAY(10); 2718 /* 2719 * Workaround Rx FIFO overruns seen under certain conditions. 2720 * Explicitly synchorize TX/RX clock. TX/RX clock should be 2721 * enabled only after enabling TX/RX MACs. 2722 */ 2723 if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) { 2724 /* Disable TX clock. */ 2725 CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS); 2726 /* Disable RX clock. */ 2727 gpreg = CSR_READ_4(sc, JME_GPREG1); 2728 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2729 gpreg = CSR_READ_4(sc, JME_GPREG1); 2730 /* De-assert RESET but still disable TX clock. */ 2731 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2732 ghc = CSR_READ_4(sc, JME_GHC); 2733 2734 /* Enable TX clock. */ 2735 CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS); 2736 /* Enable RX clock. */ 2737 CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS); 2738 CSR_READ_4(sc, JME_GPREG1); 2739 2740 /* Disable TX/RX clock again. */ 2741 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2742 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2743 } else 2744 CSR_WRITE_4(sc, JME_GHC, 0); 2745 CSR_READ_4(sc, JME_GHC); 2746 DELAY(10); 2747 } 2748 2749 static void 2750 jme_init(void *xsc) 2751 { 2752 struct jme_softc *sc; 2753 2754 sc = (struct jme_softc *)xsc; 2755 JME_LOCK(sc); 2756 jme_init_locked(sc); 2757 JME_UNLOCK(sc); 2758 } 2759 2760 static void 2761 jme_init_locked(struct jme_softc *sc) 2762 { 2763 if_t ifp; 2764 struct mii_data *mii; 2765 bus_addr_t paddr; 2766 uint32_t reg; 2767 int error; 2768 2769 JME_LOCK_ASSERT(sc); 2770 2771 ifp = sc->jme_ifp; 2772 mii = device_get_softc(sc->jme_miibus); 2773 2774 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2775 return; 2776 /* 2777 * Cancel any pending I/O. 2778 */ 2779 jme_stop(sc); 2780 2781 /* 2782 * Reset the chip to a known state. 2783 */ 2784 jme_reset(sc); 2785 2786 /* Init descriptors. */ 2787 error = jme_init_rx_ring(sc); 2788 if (error != 0) { 2789 device_printf(sc->jme_dev, 2790 "%s: initialization failed: no memory for Rx buffers.\n", 2791 __func__); 2792 jme_stop(sc); 2793 return; 2794 } 2795 jme_init_tx_ring(sc); 2796 /* Initialize shadow status block. */ 2797 jme_init_ssb(sc); 2798 2799 /* Reprogram the station address. */ 2800 jme_set_macaddr(sc, if_getlladdr(sc->jme_ifp)); 2801 2802 /* 2803 * Configure Tx queue. 2804 * Tx priority queue weight value : 0 2805 * Tx FIFO threshold for processing next packet : 16QW 2806 * Maximum Tx DMA length : 512 2807 * Allow Tx DMA burst. 2808 */ 2809 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2810 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2811 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2812 sc->jme_txcsr |= sc->jme_tx_dma_size; 2813 sc->jme_txcsr |= TXCSR_DMA_BURST; 2814 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2815 2816 /* Set Tx descriptor counter. */ 2817 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2818 2819 /* Set Tx ring address to the hardware. */ 2820 paddr = JME_TX_RING_ADDR(sc, 0); 2821 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2822 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2823 2824 /* Configure TxMAC parameters. */ 2825 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2826 reg |= TXMAC_THRESH_1_PKT; 2827 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2828 CSR_WRITE_4(sc, JME_TXMAC, reg); 2829 2830 /* 2831 * Configure Rx queue. 2832 * FIFO full threshold for transmitting Tx pause packet : 128T 2833 * FIFO threshold for processing next packet : 128QW 2834 * Rx queue 0 select 2835 * Max Rx DMA length : 128 2836 * Rx descriptor retry : 32 2837 * Rx descriptor retry time gap : 256ns 2838 * Don't receive runt/bad frame. 2839 */ 2840 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2841 /* 2842 * Since Rx FIFO size is 4K bytes, receiving frames larger 2843 * than 4K bytes will suffer from Rx FIFO overruns. So 2844 * decrease FIFO threshold to reduce the FIFO overruns for 2845 * frames larger than 4000 bytes. 2846 * For best performance of standard MTU sized frames use 2847 * maximum allowable FIFO threshold, 128QW. Note these do 2848 * not hold on chip full mask version >=2. For these 2849 * controllers 64QW and 128QW are not valid value. 2850 */ 2851 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2852 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2853 else { 2854 if ((if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2855 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2856 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2857 else 2858 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2859 } 2860 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2861 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2862 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2863 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2864 2865 /* Set Rx descriptor counter. */ 2866 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2867 2868 /* Set Rx ring address to the hardware. */ 2869 paddr = JME_RX_RING_ADDR(sc, 0); 2870 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2871 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2872 2873 /* Clear receive filter. */ 2874 CSR_WRITE_4(sc, JME_RXMAC, 0); 2875 /* Set up the receive filter. */ 2876 jme_set_filter(sc); 2877 jme_set_vlan(sc); 2878 2879 /* 2880 * Disable all WOL bits as WOL can interfere normal Rx 2881 * operation. Also clear WOL detection status bits. 2882 */ 2883 reg = CSR_READ_4(sc, JME_PMCS); 2884 reg &= ~PMCS_WOL_ENB_MASK; 2885 CSR_WRITE_4(sc, JME_PMCS, reg); 2886 2887 reg = CSR_READ_4(sc, JME_RXMAC); 2888 /* 2889 * Pad 10bytes right before received frame. This will greatly 2890 * help Rx performance on strict-alignment architectures as 2891 * it does not need to copy the frame to align the payload. 2892 */ 2893 reg |= RXMAC_PAD_10BYTES; 2894 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2895 reg |= RXMAC_CSUM_ENB; 2896 CSR_WRITE_4(sc, JME_RXMAC, reg); 2897 2898 /* Configure general purpose reg0 */ 2899 reg = CSR_READ_4(sc, JME_GPREG0); 2900 reg &= ~GPREG0_PCC_UNIT_MASK; 2901 /* Set PCC timer resolution to micro-seconds unit. */ 2902 reg |= GPREG0_PCC_UNIT_US; 2903 /* 2904 * Disable all shadow register posting as we have to read 2905 * JME_INTR_STATUS register in jme_int_task. Also it seems 2906 * that it's hard to synchronize interrupt status between 2907 * hardware and software with shadow posting due to 2908 * requirements of bus_dmamap_sync(9). 2909 */ 2910 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2911 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2912 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2913 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2914 /* Disable posting of DW0. */ 2915 reg &= ~GPREG0_POST_DW0_ENB; 2916 /* Clear PME message. */ 2917 reg &= ~GPREG0_PME_ENB; 2918 /* Set PHY address. */ 2919 reg &= ~GPREG0_PHY_ADDR_MASK; 2920 reg |= sc->jme_phyaddr; 2921 CSR_WRITE_4(sc, JME_GPREG0, reg); 2922 2923 /* Configure Tx queue 0 packet completion coalescing. */ 2924 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2925 PCCTX_COAL_TO_MASK; 2926 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2927 PCCTX_COAL_PKT_MASK; 2928 reg |= PCCTX_COAL_TXQ0; 2929 CSR_WRITE_4(sc, JME_PCCTX, reg); 2930 2931 /* Configure Rx queue 0 packet completion coalescing. */ 2932 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2933 PCCRX_COAL_TO_MASK; 2934 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2935 PCCRX_COAL_PKT_MASK; 2936 CSR_WRITE_4(sc, JME_PCCRX0, reg); 2937 2938 /* 2939 * Configure PCD(Packet Completion Deferring). It seems PCD 2940 * generates an interrupt when the time interval between two 2941 * back-to-back incoming/outgoing packet is long enough for 2942 * it to reach its timer value 0. The arrival of new packets 2943 * after timer has started causes the PCD timer to restart. 2944 * Unfortunately, it's not clear how PCD is useful at this 2945 * moment, so just use the same of PCC parameters. 2946 */ 2947 if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) { 2948 sc->jme_rx_pcd_to = sc->jme_rx_coal_to; 2949 if (sc->jme_rx_coal_to > PCDRX_TO_MAX) 2950 sc->jme_rx_pcd_to = PCDRX_TO_MAX; 2951 sc->jme_tx_pcd_to = sc->jme_tx_coal_to; 2952 if (sc->jme_tx_coal_to > PCDTX_TO_MAX) 2953 sc->jme_tx_pcd_to = PCDTX_TO_MAX; 2954 reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT; 2955 reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT; 2956 CSR_WRITE_4(sc, PCDRX_REG(0), reg); 2957 reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT; 2958 reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT; 2959 CSR_WRITE_4(sc, JME_PCDTX, reg); 2960 } 2961 2962 /* Configure shadow status block but don't enable posting. */ 2963 paddr = sc->jme_rdata.jme_ssb_block_paddr; 2964 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2965 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2966 2967 /* Disable Timer 1 and Timer 2. */ 2968 CSR_WRITE_4(sc, JME_TIMER1, 0); 2969 CSR_WRITE_4(sc, JME_TIMER2, 0); 2970 2971 /* Configure retry transmit period, retry limit value. */ 2972 CSR_WRITE_4(sc, JME_TXTRHD, 2973 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2974 TXTRHD_RT_PERIOD_MASK) | 2975 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2976 TXTRHD_RT_LIMIT_SHIFT)); 2977 2978 /* Disable RSS. */ 2979 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2980 2981 /* Initialize the interrupt mask. */ 2982 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2983 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2984 2985 /* 2986 * Enabling Tx/Rx DMA engines and Rx queue processing is 2987 * done after detection of valid link in jme_link_task. 2988 */ 2989 2990 sc->jme_flags &= ~JME_FLAG_LINK; 2991 /* Set the current media. */ 2992 mii_mediachg(mii); 2993 2994 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2995 2996 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2997 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2998 } 2999 3000 static void 3001 jme_stop(struct jme_softc *sc) 3002 { 3003 if_t ifp; 3004 struct jme_txdesc *txd; 3005 struct jme_rxdesc *rxd; 3006 int i; 3007 3008 JME_LOCK_ASSERT(sc); 3009 /* 3010 * Mark the interface down and cancel the watchdog timer. 3011 */ 3012 ifp = sc->jme_ifp; 3013 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3014 sc->jme_flags &= ~JME_FLAG_LINK; 3015 callout_stop(&sc->jme_tick_ch); 3016 sc->jme_watchdog_timer = 0; 3017 3018 /* 3019 * Disable interrupts. 3020 */ 3021 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 3022 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 3023 3024 /* Disable updating shadow status block. */ 3025 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 3026 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 3027 3028 /* Stop receiver, transmitter. */ 3029 jme_stop_rx(sc); 3030 jme_stop_tx(sc); 3031 3032 /* Reclaim Rx/Tx buffers that have been completed. */ 3033 jme_rxintr(sc, JME_RX_RING_CNT); 3034 if (sc->jme_cdata.jme_rxhead != NULL) 3035 m_freem(sc->jme_cdata.jme_rxhead); 3036 JME_RXCHAIN_RESET(sc); 3037 jme_txeof(sc); 3038 /* 3039 * Free RX and TX mbufs still in the queues. 3040 */ 3041 for (i = 0; i < JME_RX_RING_CNT; i++) { 3042 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3043 if (rxd->rx_m != NULL) { 3044 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 3045 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3046 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 3047 rxd->rx_dmamap); 3048 m_freem(rxd->rx_m); 3049 rxd->rx_m = NULL; 3050 } 3051 } 3052 for (i = 0; i < JME_TX_RING_CNT; i++) { 3053 txd = &sc->jme_cdata.jme_txdesc[i]; 3054 if (txd->tx_m != NULL) { 3055 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 3056 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3057 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 3058 txd->tx_dmamap); 3059 m_freem(txd->tx_m); 3060 txd->tx_m = NULL; 3061 txd->tx_ndesc = 0; 3062 } 3063 } 3064 jme_stats_update(sc); 3065 jme_stats_save(sc); 3066 } 3067 3068 static void 3069 jme_stop_tx(struct jme_softc *sc) 3070 { 3071 uint32_t reg; 3072 int i; 3073 3074 reg = CSR_READ_4(sc, JME_TXCSR); 3075 if ((reg & TXCSR_TX_ENB) == 0) 3076 return; 3077 reg &= ~TXCSR_TX_ENB; 3078 CSR_WRITE_4(sc, JME_TXCSR, reg); 3079 for (i = JME_TIMEOUT; i > 0; i--) { 3080 DELAY(1); 3081 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 3082 break; 3083 } 3084 if (i == 0) 3085 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 3086 } 3087 3088 static void 3089 jme_stop_rx(struct jme_softc *sc) 3090 { 3091 uint32_t reg; 3092 int i; 3093 3094 reg = CSR_READ_4(sc, JME_RXCSR); 3095 if ((reg & RXCSR_RX_ENB) == 0) 3096 return; 3097 reg &= ~RXCSR_RX_ENB; 3098 CSR_WRITE_4(sc, JME_RXCSR, reg); 3099 for (i = JME_TIMEOUT; i > 0; i--) { 3100 DELAY(1); 3101 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 3102 break; 3103 } 3104 if (i == 0) 3105 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 3106 } 3107 3108 static void 3109 jme_init_tx_ring(struct jme_softc *sc) 3110 { 3111 struct jme_ring_data *rd; 3112 struct jme_txdesc *txd; 3113 int i; 3114 3115 sc->jme_cdata.jme_tx_prod = 0; 3116 sc->jme_cdata.jme_tx_cons = 0; 3117 sc->jme_cdata.jme_tx_cnt = 0; 3118 3119 rd = &sc->jme_rdata; 3120 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 3121 for (i = 0; i < JME_TX_RING_CNT; i++) { 3122 txd = &sc->jme_cdata.jme_txdesc[i]; 3123 txd->tx_m = NULL; 3124 txd->tx_desc = &rd->jme_tx_ring[i]; 3125 txd->tx_ndesc = 0; 3126 } 3127 3128 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 3129 sc->jme_cdata.jme_tx_ring_map, 3130 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3131 } 3132 3133 static void 3134 jme_init_ssb(struct jme_softc *sc) 3135 { 3136 struct jme_ring_data *rd; 3137 3138 rd = &sc->jme_rdata; 3139 bzero(rd->jme_ssb_block, JME_SSB_SIZE); 3140 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 3141 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3142 } 3143 3144 static int 3145 jme_init_rx_ring(struct jme_softc *sc) 3146 { 3147 struct jme_ring_data *rd; 3148 struct jme_rxdesc *rxd; 3149 int i; 3150 3151 sc->jme_cdata.jme_rx_cons = 0; 3152 JME_RXCHAIN_RESET(sc); 3153 sc->jme_morework = 0; 3154 3155 rd = &sc->jme_rdata; 3156 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 3157 for (i = 0; i < JME_RX_RING_CNT; i++) { 3158 rxd = &sc->jme_cdata.jme_rxdesc[i]; 3159 rxd->rx_m = NULL; 3160 rxd->rx_desc = &rd->jme_rx_ring[i]; 3161 if (jme_newbuf(sc, rxd) != 0) 3162 return (ENOBUFS); 3163 } 3164 3165 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 3166 sc->jme_cdata.jme_rx_ring_map, 3167 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3168 3169 return (0); 3170 } 3171 3172 static int 3173 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3174 { 3175 struct jme_desc *desc; 3176 struct mbuf *m; 3177 bus_dma_segment_t segs[1]; 3178 bus_dmamap_t map; 3179 int nsegs; 3180 3181 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3182 if (m == NULL) 3183 return (ENOBUFS); 3184 /* 3185 * JMC250 has 64bit boundary alignment limitation so jme(4) 3186 * takes advantage of 10 bytes padding feature of hardware 3187 * in order not to copy entire frame to align IP header on 3188 * 32bit boundary. 3189 */ 3190 m->m_len = m->m_pkthdr.len = MCLBYTES; 3191 3192 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3193 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3194 m_freem(m); 3195 return (ENOBUFS); 3196 } 3197 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3198 3199 if (rxd->rx_m != NULL) { 3200 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3201 BUS_DMASYNC_POSTREAD); 3202 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3203 } 3204 map = rxd->rx_dmamap; 3205 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3206 sc->jme_cdata.jme_rx_sparemap = map; 3207 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3208 BUS_DMASYNC_PREREAD); 3209 rxd->rx_m = m; 3210 3211 desc = rxd->rx_desc; 3212 desc->buflen = htole32(segs[0].ds_len); 3213 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3214 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3215 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3216 3217 return (0); 3218 } 3219 3220 static void 3221 jme_set_vlan(struct jme_softc *sc) 3222 { 3223 if_t ifp; 3224 uint32_t reg; 3225 3226 JME_LOCK_ASSERT(sc); 3227 3228 ifp = sc->jme_ifp; 3229 reg = CSR_READ_4(sc, JME_RXMAC); 3230 reg &= ~RXMAC_VLAN_ENB; 3231 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3232 reg |= RXMAC_VLAN_ENB; 3233 CSR_WRITE_4(sc, JME_RXMAC, reg); 3234 } 3235 3236 static u_int 3237 jme_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3238 { 3239 uint32_t crc, *mchash = arg; 3240 3241 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3242 3243 /* Just want the 6 least significant bits. */ 3244 crc &= 0x3f; 3245 3246 /* Set the corresponding bit in the hash table. */ 3247 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3248 3249 return (1); 3250 } 3251 3252 static void 3253 jme_set_filter(struct jme_softc *sc) 3254 { 3255 if_t ifp; 3256 uint32_t mchash[2]; 3257 uint32_t rxcfg; 3258 3259 JME_LOCK_ASSERT(sc); 3260 3261 ifp = sc->jme_ifp; 3262 3263 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3264 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3265 RXMAC_ALLMULTI); 3266 /* Always accept frames destined to our station address. */ 3267 rxcfg |= RXMAC_UNICAST; 3268 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3269 rxcfg |= RXMAC_BROADCAST; 3270 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3271 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3272 rxcfg |= RXMAC_PROMISC; 3273 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3274 rxcfg |= RXMAC_ALLMULTI; 3275 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3276 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3277 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3278 return; 3279 } 3280 3281 /* 3282 * Set up the multicast address filter by passing all multicast 3283 * addresses through a CRC generator, and then using the low-order 3284 * 6 bits as an index into the 64 bit multicast hash table. The 3285 * high order bits select the register, while the rest of the bits 3286 * select the bit within the register. 3287 */ 3288 rxcfg |= RXMAC_MULTICAST; 3289 bzero(mchash, sizeof(mchash)); 3290 if_foreach_llmaddr(ifp, jme_hash_maddr, &mchash); 3291 3292 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3293 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3294 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3295 } 3296 3297 static void 3298 jme_stats_clear(struct jme_softc *sc) 3299 { 3300 3301 JME_LOCK_ASSERT(sc); 3302 3303 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3304 return; 3305 3306 /* Disable and clear counters. */ 3307 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3308 /* Activate hw counters. */ 3309 CSR_WRITE_4(sc, JME_STATCSR, 0); 3310 CSR_READ_4(sc, JME_STATCSR); 3311 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3312 } 3313 3314 static void 3315 jme_stats_save(struct jme_softc *sc) 3316 { 3317 3318 JME_LOCK_ASSERT(sc); 3319 3320 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3321 return; 3322 /* Save current counters. */ 3323 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3324 /* Disable and clear counters. */ 3325 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3326 } 3327 3328 static void 3329 jme_stats_update(struct jme_softc *sc) 3330 { 3331 struct jme_hw_stats *stat, *ostat; 3332 uint32_t reg; 3333 3334 JME_LOCK_ASSERT(sc); 3335 3336 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3337 return; 3338 stat = &sc->jme_stats; 3339 ostat = &sc->jme_ostats; 3340 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3341 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3342 reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3343 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3344 STAT_RX_CRC_ERR_SHIFT; 3345 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3346 STAT_RX_MII_ERR_SHIFT; 3347 reg = CSR_READ_4(sc, JME_STAT_RXERR); 3348 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3349 STAT_RXERR_OFLOW_SHIFT; 3350 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3351 STAT_RXERR_MPTY_SHIFT; 3352 reg = CSR_READ_4(sc, JME_STAT_FAIL); 3353 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3354 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3355 3356 /* Account for previous counters. */ 3357 stat->rx_good_frames += ostat->rx_good_frames; 3358 stat->rx_crc_errs += ostat->rx_crc_errs; 3359 stat->rx_mii_errs += ostat->rx_mii_errs; 3360 stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3361 stat->rx_desc_empty += ostat->rx_desc_empty; 3362 stat->rx_bad_frames += ostat->rx_bad_frames; 3363 stat->tx_good_frames += ostat->tx_good_frames; 3364 stat->tx_bad_frames += ostat->tx_bad_frames; 3365 } 3366 3367 static void 3368 jme_phy_down(struct jme_softc *sc) 3369 { 3370 uint32_t reg; 3371 3372 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN); 3373 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3374 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3375 reg |= 0x0000000F; 3376 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3377 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3378 reg &= ~PE1_GIGA_PDOWN_MASK; 3379 reg |= PE1_GIGA_PDOWN_D3; 3380 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3381 } 3382 } 3383 3384 static void 3385 jme_phy_up(struct jme_softc *sc) 3386 { 3387 uint32_t reg; 3388 uint16_t bmcr; 3389 3390 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); 3391 bmcr &= ~BMCR_PDOWN; 3392 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); 3393 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3394 reg = CSR_READ_4(sc, JME_PHYPOWDN); 3395 reg &= ~0x0000000F; 3396 CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3397 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3398 reg &= ~PE1_GIGA_PDOWN_MASK; 3399 reg |= PE1_GIGA_PDOWN_DIS; 3400 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3401 } 3402 } 3403 3404 static int 3405 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3406 { 3407 int error, value; 3408 3409 if (arg1 == NULL) 3410 return (EINVAL); 3411 value = *(int *)arg1; 3412 error = sysctl_handle_int(oidp, &value, 0, req); 3413 if (error || req->newptr == NULL) 3414 return (error); 3415 if (value < low || value > high) 3416 return (EINVAL); 3417 *(int *)arg1 = value; 3418 3419 return (0); 3420 } 3421 3422 static int 3423 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3424 { 3425 return (sysctl_int_range(oidp, arg1, arg2, req, 3426 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3427 } 3428 3429 static int 3430 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3431 { 3432 return (sysctl_int_range(oidp, arg1, arg2, req, 3433 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3434 } 3435 3436 static int 3437 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3438 { 3439 return (sysctl_int_range(oidp, arg1, arg2, req, 3440 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3441 } 3442 3443 static int 3444 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3445 { 3446 return (sysctl_int_range(oidp, arg1, arg2, req, 3447 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3448 } 3449 3450 static int 3451 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3452 { 3453 return (sysctl_int_range(oidp, arg1, arg2, req, 3454 JME_PROC_MIN, JME_PROC_MAX)); 3455 } 3456