xref: /freebsd/sys/dev/jme/if_jme.c (revision a3cf0ef5a295c885c895fabfd56470c0d1db322d)
1 /*-
2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/mbuf.h>
38 #include <sys/rman.h>
39 #include <sys/module.h>
40 #include <sys/proc.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46 
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_vlan_var.h>
55 
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/ip.h>
59 #include <netinet/tcp.h>
60 
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
63 
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66 
67 #include <machine/atomic.h>
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
70 
71 #include <dev/jme/if_jmereg.h>
72 #include <dev/jme/if_jmevar.h>
73 
74 /* "device miibus" required.  See GENERIC if you get errors here. */
75 #include "miibus_if.h"
76 
77 /* Define the following to disable printing Rx errors. */
78 #undef	JME_SHOW_ERRORS
79 
80 #define	JME_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
81 
82 MODULE_DEPEND(jme, pci, 1, 1, 1);
83 MODULE_DEPEND(jme, ether, 1, 1, 1);
84 MODULE_DEPEND(jme, miibus, 1, 1, 1);
85 
86 /* Tunables. */
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable);
91 
92 /*
93  * Devices supported by this driver.
94  */
95 static struct jme_dev {
96 	uint16_t	jme_vendorid;
97 	uint16_t	jme_deviceid;
98 	const char	*jme_name;
99 } jme_devs[] = {
100 	{ VENDORID_JMICRON, DEVICEID_JMC250,
101 	    "JMicron Inc, JMC250 Gigabit Ethernet" },
102 	{ VENDORID_JMICRON, DEVICEID_JMC260,
103 	    "JMicron Inc, JMC260 Fast Ethernet" },
104 };
105 
106 static int jme_miibus_readreg(device_t, int, int);
107 static int jme_miibus_writereg(device_t, int, int, int);
108 static void jme_miibus_statchg(device_t);
109 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
110 static int jme_mediachange(struct ifnet *);
111 static int jme_probe(device_t);
112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
113 static int jme_eeprom_macaddr(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *);
115 static void jme_map_intr_vector(struct jme_softc *);
116 static int jme_attach(device_t);
117 static int jme_detach(device_t);
118 static void jme_sysctl_node(struct jme_softc *);
119 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
120 static int jme_dma_alloc(struct jme_softc *);
121 static void jme_dma_free(struct jme_softc *);
122 static int jme_shutdown(device_t);
123 static void jme_setlinkspeed(struct jme_softc *);
124 static void jme_setwol(struct jme_softc *);
125 static int jme_suspend(device_t);
126 static int jme_resume(device_t);
127 static int jme_encap(struct jme_softc *, struct mbuf **);
128 static void jme_tx_task(void *, int);
129 static void jme_start(struct ifnet *);
130 static void jme_watchdog(struct jme_softc *);
131 static int jme_ioctl(struct ifnet *, u_long, caddr_t);
132 static void jme_mac_config(struct jme_softc *);
133 static void jme_link_task(void *, int);
134 static int jme_intr(void *);
135 static void jme_int_task(void *, int);
136 static void jme_txeof(struct jme_softc *);
137 static __inline void jme_discard_rxbuf(struct jme_softc *, int);
138 static void jme_rxeof(struct jme_softc *);
139 static int jme_rxintr(struct jme_softc *, int);
140 static void jme_tick(void *);
141 static void jme_reset(struct jme_softc *);
142 static void jme_init(void *);
143 static void jme_init_locked(struct jme_softc *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_stop_tx(struct jme_softc *);
146 static void jme_stop_rx(struct jme_softc *);
147 static int jme_init_rx_ring(struct jme_softc *);
148 static void jme_init_tx_ring(struct jme_softc *);
149 static void jme_init_ssb(struct jme_softc *);
150 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
151 static void jme_set_vlan(struct jme_softc *);
152 static void jme_set_filter(struct jme_softc *);
153 static void jme_stats_clear(struct jme_softc *);
154 static void jme_stats_save(struct jme_softc *);
155 static void jme_stats_update(struct jme_softc *);
156 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
157 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
158 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
159 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
160 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
161 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
162 
163 
164 static device_method_t jme_methods[] = {
165 	/* Device interface. */
166 	DEVMETHOD(device_probe,		jme_probe),
167 	DEVMETHOD(device_attach,	jme_attach),
168 	DEVMETHOD(device_detach,	jme_detach),
169 	DEVMETHOD(device_shutdown,	jme_shutdown),
170 	DEVMETHOD(device_suspend,	jme_suspend),
171 	DEVMETHOD(device_resume,	jme_resume),
172 
173 	/* MII interface. */
174 	DEVMETHOD(miibus_readreg,	jme_miibus_readreg),
175 	DEVMETHOD(miibus_writereg,	jme_miibus_writereg),
176 	DEVMETHOD(miibus_statchg,	jme_miibus_statchg),
177 
178 	{ NULL, NULL }
179 };
180 
181 static driver_t jme_driver = {
182 	"jme",
183 	jme_methods,
184 	sizeof(struct jme_softc)
185 };
186 
187 static devclass_t jme_devclass;
188 
189 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0);
190 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
191 
192 static struct resource_spec jme_res_spec_mem[] = {
193 	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
194 	{ -1,			0,		0 }
195 };
196 
197 static struct resource_spec jme_irq_spec_legacy[] = {
198 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
199 	{ -1,			0,		0 }
200 };
201 
202 static struct resource_spec jme_irq_spec_msi[] = {
203 	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
204 	{ SYS_RES_IRQ,		2,		RF_ACTIVE },
205 	{ SYS_RES_IRQ,		3,		RF_ACTIVE },
206 	{ SYS_RES_IRQ,		4,		RF_ACTIVE },
207 	{ SYS_RES_IRQ,		5,		RF_ACTIVE },
208 	{ SYS_RES_IRQ,		6,		RF_ACTIVE },
209 	{ SYS_RES_IRQ,		7,		RF_ACTIVE },
210 	{ SYS_RES_IRQ,		8,		RF_ACTIVE },
211 	{ -1,			0,		0 }
212 };
213 
214 /*
215  *	Read a PHY register on the MII of the JMC250.
216  */
217 static int
218 jme_miibus_readreg(device_t dev, int phy, int reg)
219 {
220 	struct jme_softc *sc;
221 	uint32_t val;
222 	int i;
223 
224 	sc = device_get_softc(dev);
225 
226 	/* For FPGA version, PHY address 0 should be ignored. */
227 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
228 		return (0);
229 
230 	CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
231 	    SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
232 	for (i = JME_PHY_TIMEOUT; i > 0; i--) {
233 		DELAY(1);
234 		if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
235 			break;
236 	}
237 
238 	if (i == 0) {
239 		device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
240 		return (0);
241 	}
242 
243 	return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
244 }
245 
246 /*
247  *	Write a PHY register on the MII of the JMC250.
248  */
249 static int
250 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
251 {
252 	struct jme_softc *sc;
253 	int i;
254 
255 	sc = device_get_softc(dev);
256 
257 	/* For FPGA version, PHY address 0 should be ignored. */
258 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
259 		return (0);
260 
261 	CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
262 	    ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
263 	    SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
264 	for (i = JME_PHY_TIMEOUT; i > 0; i--) {
265 		DELAY(1);
266 		if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
267 			break;
268 	}
269 
270 	if (i == 0)
271 		device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
272 
273 	return (0);
274 }
275 
276 /*
277  *	Callback from MII layer when media changes.
278  */
279 static void
280 jme_miibus_statchg(device_t dev)
281 {
282 	struct jme_softc *sc;
283 
284 	sc = device_get_softc(dev);
285 	taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task);
286 }
287 
288 /*
289  *	Get the current interface media status.
290  */
291 static void
292 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
293 {
294 	struct jme_softc *sc;
295 	struct mii_data *mii;
296 
297 	sc = ifp->if_softc;
298 	JME_LOCK(sc);
299 	if ((ifp->if_flags & IFF_UP) == 0) {
300 		JME_UNLOCK(sc);
301 		return;
302 	}
303 	mii = device_get_softc(sc->jme_miibus);
304 
305 	mii_pollstat(mii);
306 	ifmr->ifm_status = mii->mii_media_status;
307 	ifmr->ifm_active = mii->mii_media_active;
308 	JME_UNLOCK(sc);
309 }
310 
311 /*
312  *	Set hardware to newly-selected media.
313  */
314 static int
315 jme_mediachange(struct ifnet *ifp)
316 {
317 	struct jme_softc *sc;
318 	struct mii_data *mii;
319 	struct mii_softc *miisc;
320 	int error;
321 
322 	sc = ifp->if_softc;
323 	JME_LOCK(sc);
324 	mii = device_get_softc(sc->jme_miibus);
325 	if (mii->mii_instance != 0) {
326 		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
327 			mii_phy_reset(miisc);
328 	}
329 	error = mii_mediachg(mii);
330 	JME_UNLOCK(sc);
331 
332 	return (error);
333 }
334 
335 static int
336 jme_probe(device_t dev)
337 {
338 	struct jme_dev *sp;
339 	int i;
340 	uint16_t vendor, devid;
341 
342 	vendor = pci_get_vendor(dev);
343 	devid = pci_get_device(dev);
344 	sp = jme_devs;
345 	for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]);
346 	    i++, sp++) {
347 		if (vendor == sp->jme_vendorid &&
348 		    devid == sp->jme_deviceid) {
349 			device_set_desc(dev, sp->jme_name);
350 			return (BUS_PROBE_DEFAULT);
351 		}
352 	}
353 
354 	return (ENXIO);
355 }
356 
357 static int
358 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
359 {
360 	uint32_t reg;
361 	int i;
362 
363 	*val = 0;
364 	for (i = JME_TIMEOUT; i > 0; i--) {
365 		reg = CSR_READ_4(sc, JME_SMBCSR);
366 		if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
367 			break;
368 		DELAY(1);
369 	}
370 
371 	if (i == 0) {
372 		device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
373 		return (ETIMEDOUT);
374 	}
375 
376 	reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
377 	CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
378 	for (i = JME_TIMEOUT; i > 0; i--) {
379 		DELAY(1);
380 		reg = CSR_READ_4(sc, JME_SMBINTF);
381 		if ((reg & SMBINTF_CMD_TRIGGER) == 0)
382 			break;
383 	}
384 
385 	if (i == 0) {
386 		device_printf(sc->jme_dev, "EEPROM read timeout!\n");
387 		return (ETIMEDOUT);
388 	}
389 
390 	reg = CSR_READ_4(sc, JME_SMBINTF);
391 	*val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
392 
393 	return (0);
394 }
395 
396 static int
397 jme_eeprom_macaddr(struct jme_softc *sc)
398 {
399 	uint8_t eaddr[ETHER_ADDR_LEN];
400 	uint8_t fup, reg, val;
401 	uint32_t offset;
402 	int match;
403 
404 	offset = 0;
405 	if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
406 	    fup != JME_EEPROM_SIG0)
407 		return (ENOENT);
408 	if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
409 	    fup != JME_EEPROM_SIG1)
410 		return (ENOENT);
411 	match = 0;
412 	do {
413 		if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
414 			break;
415 		if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
416 		    (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
417 			if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
418 				break;
419 			if (reg >= JME_PAR0 &&
420 			    reg < JME_PAR0 + ETHER_ADDR_LEN) {
421 				if (jme_eeprom_read_byte(sc, offset + 2,
422 				    &val) != 0)
423 					break;
424 				eaddr[reg - JME_PAR0] = val;
425 				match++;
426 			}
427 		}
428 		/* Check for the end of EEPROM descriptor. */
429 		if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
430 			break;
431 		/* Try next eeprom descriptor. */
432 		offset += JME_EEPROM_DESC_BYTES;
433 	} while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
434 
435 	if (match == ETHER_ADDR_LEN) {
436 		bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
437 		return (0);
438 	}
439 
440 	return (ENOENT);
441 }
442 
443 static void
444 jme_reg_macaddr(struct jme_softc *sc)
445 {
446 	uint32_t par0, par1;
447 
448 	/* Read station address. */
449 	par0 = CSR_READ_4(sc, JME_PAR0);
450 	par1 = CSR_READ_4(sc, JME_PAR1);
451 	par1 &= 0xFFFF;
452 	if ((par0 == 0 && par1 == 0) ||
453 	    (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
454 		device_printf(sc->jme_dev,
455 		    "Failed to retrieve Ethernet address.\n");
456 	} else {
457 		sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
458 		sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
459 		sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
460 		sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
461 		sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
462 		sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
463 	}
464 }
465 
466 static void
467 jme_map_intr_vector(struct jme_softc *sc)
468 {
469 	uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
470 
471 	bzero(map, sizeof(map));
472 
473 	/* Map Tx interrupts source to MSI/MSIX vector 2. */
474 	map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
475 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
476 	map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
477 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
478 	map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |=
479 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP);
480 	map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |=
481 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP);
482 	map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
483 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP);
484 	map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
485 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP);
486 	map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |=
487 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP);
488 	map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |=
489 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP);
490 	map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |=
491 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL);
492 	map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |=
493 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
494 
495 	/* Map Rx interrupts source to MSI/MSIX vector 1. */
496 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
497 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
498 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
499 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
500 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
501 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
502 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
503 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
504 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
505 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
506 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
507 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
508 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
509 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
510 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
511 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
512 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
513 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
514 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
515 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
516 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
517 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
518 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
519 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
520 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
521 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
522 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
523 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
524 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
525 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
526 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
527 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
528 
529 	/* Map all other interrupts source to MSI/MSIX vector 0. */
530 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);
531 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);
532 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);
533 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);
534 }
535 
536 static int
537 jme_attach(device_t dev)
538 {
539 	struct jme_softc *sc;
540 	struct ifnet *ifp;
541 	struct mii_softc *miisc;
542 	struct mii_data *mii;
543 	uint32_t reg;
544 	uint16_t burst;
545 	int error, i, msic, msixc, pmc;
546 
547 	error = 0;
548 	sc = device_get_softc(dev);
549 	sc->jme_dev = dev;
550 
551 	mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
552 	    MTX_DEF);
553 	callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);
554 	TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc);
555 	TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc);
556 
557 	/*
558 	 * Map the device. JMC250 supports both memory mapped and I/O
559 	 * register space access. Because I/O register access should
560 	 * use different BARs to access registers it's waste of time
561 	 * to use I/O register spce access. JMC250 uses 16K to map
562 	 * entire memory space.
563 	 */
564 	pci_enable_busmaster(dev);
565 	sc->jme_res_spec = jme_res_spec_mem;
566 	sc->jme_irq_spec = jme_irq_spec_legacy;
567 	error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res);
568 	if (error != 0) {
569 		device_printf(dev, "cannot allocate memory resources.\n");
570 		goto fail;
571 	}
572 
573 	/* Allocate IRQ resources. */
574 	msixc = pci_msix_count(dev);
575 	msic = pci_msi_count(dev);
576 	if (bootverbose) {
577 		device_printf(dev, "MSIX count : %d\n", msixc);
578 		device_printf(dev, "MSI count : %d\n", msic);
579 	}
580 
581 	/* Prefer MSIX over MSI. */
582 	if (msix_disable == 0 || msi_disable == 0) {
583 		if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES &&
584 		    pci_alloc_msix(dev, &msixc) == 0) {
585 			if (msic == JME_MSIX_MESSAGES) {
586 				device_printf(dev, "Using %d MSIX messages.\n",
587 				    msixc);
588 				sc->jme_flags |= JME_FLAG_MSIX;
589 				sc->jme_irq_spec = jme_irq_spec_msi;
590 			} else
591 				pci_release_msi(dev);
592 		}
593 		if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
594 		    msic == JME_MSI_MESSAGES &&
595 		    pci_alloc_msi(dev, &msic) == 0) {
596 			if (msic == JME_MSI_MESSAGES) {
597 				device_printf(dev, "Using %d MSI messages.\n",
598 				    msic);
599 				sc->jme_flags |= JME_FLAG_MSI;
600 				sc->jme_irq_spec = jme_irq_spec_msi;
601 			} else
602 				pci_release_msi(dev);
603 		}
604 		/* Map interrupt vector 0, 1 and 2. */
605 		if ((sc->jme_flags & JME_FLAG_MSI) != 0 ||
606 		    (sc->jme_flags & JME_FLAG_MSIX) != 0)
607 			jme_map_intr_vector(sc);
608 	}
609 
610 	error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq);
611 	if (error != 0) {
612 		device_printf(dev, "cannot allocate IRQ resources.\n");
613 		goto fail;
614 	}
615 
616 	sc->jme_rev = pci_get_device(dev);
617 	if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) {
618 		sc->jme_flags |= JME_FLAG_FASTETH;
619 		sc->jme_flags |= JME_FLAG_NOJUMBO;
620 	}
621 	reg = CSR_READ_4(sc, JME_CHIPMODE);
622 	sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
623 	if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
624 	    CHIPMODE_NOT_FPGA)
625 		sc->jme_flags |= JME_FLAG_FPGA;
626 	if (bootverbose) {
627 		device_printf(dev, "PCI device revision : 0x%04x\n",
628 		    sc->jme_rev);
629 		device_printf(dev, "Chip revision : 0x%02x\n",
630 		    sc->jme_chip_rev);
631 		if ((sc->jme_flags & JME_FLAG_FPGA) != 0)
632 			device_printf(dev, "FPGA revision : 0x%04x\n",
633 			    (reg & CHIPMODE_FPGA_REV_MASK) >>
634 			    CHIPMODE_FPGA_REV_SHIFT);
635 	}
636 	if (sc->jme_chip_rev == 0xFF) {
637 		device_printf(dev, "Unknown chip revision : 0x%02x\n",
638 		    sc->jme_rev);
639 		error = ENXIO;
640 		goto fail;
641 	}
642 
643 	if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
644 		if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
645 		    CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
646 			sc->jme_flags |= JME_FLAG_DMA32BIT;
647 		sc->jme_flags |= JME_FLAG_TXCLK;
648 		sc->jme_flags |= JME_FLAG_HWMIB;
649 	}
650 
651 	/* Reset the ethernet controller. */
652 	jme_reset(sc);
653 
654 	/* Get station address. */
655 	reg = CSR_READ_4(sc, JME_SMBCSR);
656 	if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
657 		error = jme_eeprom_macaddr(sc);
658 	if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
659 		if (error != 0 && (bootverbose))
660 			device_printf(sc->jme_dev,
661 			    "ethernet hardware address not found in EEPROM.\n");
662 		jme_reg_macaddr(sc);
663 	}
664 
665 	/*
666 	 * Save PHY address.
667 	 * Integrated JR0211 has fixed PHY address whereas FPGA version
668 	 * requires PHY probing to get correct PHY address.
669 	 */
670 	if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
671 		sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
672 		    GPREG0_PHY_ADDR_MASK;
673 		if (bootverbose)
674 			device_printf(dev, "PHY is at address %d.\n",
675 			    sc->jme_phyaddr);
676 	} else
677 		sc->jme_phyaddr = 0;
678 
679 	/* Set max allowable DMA size. */
680 	if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
681 		sc->jme_flags |= JME_FLAG_PCIE;
682 		burst = pci_read_config(dev, i + 0x08, 2);
683 		if (bootverbose) {
684 			device_printf(dev, "Read request size : %d bytes.\n",
685 			    128 << ((burst >> 12) & 0x07));
686 			device_printf(dev, "TLP payload size : %d bytes.\n",
687 			    128 << ((burst >> 5) & 0x07));
688 		}
689 		switch ((burst >> 12) & 0x07) {
690 		case 0:
691 			sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
692 			break;
693 		case 1:
694 			sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
695 			break;
696 		default:
697 			sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
698 			break;
699 		}
700 		sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
701 	} else {
702 		sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
703 		sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
704 	}
705 	/* Create coalescing sysctl node. */
706 	jme_sysctl_node(sc);
707 	if ((error = jme_dma_alloc(sc) != 0))
708 		goto fail;
709 
710 	ifp = sc->jme_ifp = if_alloc(IFT_ETHER);
711 	if (ifp == NULL) {
712 		device_printf(dev, "cannot allocate ifnet structure.\n");
713 		error = ENXIO;
714 		goto fail;
715 	}
716 
717 	ifp->if_softc = sc;
718 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
719 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
720 	ifp->if_ioctl = jme_ioctl;
721 	ifp->if_start = jme_start;
722 	ifp->if_init = jme_init;
723 	ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1;
724 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
725 	IFQ_SET_READY(&ifp->if_snd);
726 	/* JMC250 supports Tx/Rx checksum offload as well as TSO. */
727 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
728 	ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
729 	if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
730 		sc->jme_flags |= JME_FLAG_PMCAP;
731 		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
732 	}
733 	ifp->if_capenable = ifp->if_capabilities;
734 
735 	/* Set up MII bus. */
736 	error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
737 	    jme_mediastatus, BMSR_DEFCAPMASK, sc->jme_phyaddr, MII_OFFSET_ANY,
738 	    0);
739 	if (error != 0) {
740 		device_printf(dev, "attaching PHYs failed\n");
741 		goto fail;
742 	}
743 
744 	/*
745 	 * Force PHY to FPGA mode.
746 	 */
747 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
748 		mii = device_get_softc(sc->jme_miibus);
749 		if (mii->mii_instance != 0) {
750 			LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
751 				if (miisc->mii_phy != 0) {
752 					sc->jme_phyaddr = miisc->mii_phy;
753 					break;
754 				}
755 			}
756 			if (sc->jme_phyaddr != 0) {
757 				device_printf(sc->jme_dev,
758 				    "FPGA PHY is at %d\n", sc->jme_phyaddr);
759 				/* vendor magic. */
760 				jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
761 				    0x0004);
762 			}
763 		}
764 	}
765 
766 	ether_ifattach(ifp, sc->jme_eaddr);
767 
768 	/* VLAN capability setup */
769 	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
770 	    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
771 	ifp->if_capenable = ifp->if_capabilities;
772 
773 	/* Tell the upper layer(s) we support long frames. */
774 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
775 
776 	/* Create local taskq. */
777 	TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp);
778 	sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK,
779 	    taskqueue_thread_enqueue, &sc->jme_tq);
780 	if (sc->jme_tq == NULL) {
781 		device_printf(dev, "could not create taskqueue.\n");
782 		ether_ifdetach(ifp);
783 		error = ENXIO;
784 		goto fail;
785 	}
786 	taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
787 	    device_get_nameunit(sc->jme_dev));
788 
789 	if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
790 		msic = JME_MSIX_MESSAGES;
791 	else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
792 		msic = JME_MSI_MESSAGES;
793 	else
794 		msic = 1;
795 	for (i = 0; i < msic; i++) {
796 		error = bus_setup_intr(dev, sc->jme_irq[i],
797 		    INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
798 		    &sc->jme_intrhand[i]);
799 		if (error != 0)
800 			break;
801 	}
802 
803 	if (error != 0) {
804 		device_printf(dev, "could not set up interrupt handler.\n");
805 		taskqueue_free(sc->jme_tq);
806 		sc->jme_tq = NULL;
807 		ether_ifdetach(ifp);
808 		goto fail;
809 	}
810 
811 fail:
812 	if (error != 0)
813 		jme_detach(dev);
814 
815 	return (error);
816 }
817 
818 static int
819 jme_detach(device_t dev)
820 {
821 	struct jme_softc *sc;
822 	struct ifnet *ifp;
823 	int i, msic;
824 
825 	sc = device_get_softc(dev);
826 
827 	ifp = sc->jme_ifp;
828 	if (device_is_attached(dev)) {
829 		JME_LOCK(sc);
830 		sc->jme_flags |= JME_FLAG_DETACH;
831 		jme_stop(sc);
832 		JME_UNLOCK(sc);
833 		callout_drain(&sc->jme_tick_ch);
834 		taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
835 		taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
836 		taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
837 		ether_ifdetach(ifp);
838 	}
839 
840 	if (sc->jme_tq != NULL) {
841 		taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
842 		taskqueue_free(sc->jme_tq);
843 		sc->jme_tq = NULL;
844 	}
845 
846 	if (sc->jme_miibus != NULL) {
847 		device_delete_child(dev, sc->jme_miibus);
848 		sc->jme_miibus = NULL;
849 	}
850 	bus_generic_detach(dev);
851 	jme_dma_free(sc);
852 
853 	if (ifp != NULL) {
854 		if_free(ifp);
855 		sc->jme_ifp = NULL;
856 	}
857 
858 	msic = 1;
859 	if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
860 		msic = JME_MSIX_MESSAGES;
861 	else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
862 		msic = JME_MSI_MESSAGES;
863 	else
864 		msic = 1;
865 	for (i = 0; i < msic; i++) {
866 		if (sc->jme_intrhand[i] != NULL) {
867 			bus_teardown_intr(dev, sc->jme_irq[i],
868 			    sc->jme_intrhand[i]);
869 			sc->jme_intrhand[i] = NULL;
870 		}
871 	}
872 
873 	bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq);
874 	if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0)
875 		pci_release_msi(dev);
876 	bus_release_resources(dev, sc->jme_res_spec, sc->jme_res);
877 	mtx_destroy(&sc->jme_mtx);
878 
879 	return (0);
880 }
881 
882 #define	JME_SYSCTL_STAT_ADD32(c, h, n, p, d)	\
883 	    SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
884 
885 static void
886 jme_sysctl_node(struct jme_softc *sc)
887 {
888 	struct sysctl_ctx_list *ctx;
889 	struct sysctl_oid_list *child, *parent;
890 	struct sysctl_oid *tree;
891 	struct jme_hw_stats *stats;
892 	int error;
893 
894 	stats = &sc->jme_stats;
895 	ctx = device_get_sysctl_ctx(sc->jme_dev);
896 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
897 
898 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
899 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0,
900 	    sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
901 
902 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
903 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0,
904 	    sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
905 
906 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
907 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0,
908 	    sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
909 
910 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
911 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0,
912 	    sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
913 
914 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
915 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0,
916 	    sysctl_hw_jme_proc_limit, "I",
917 	    "max number of Rx events to process");
918 
919 	/* Pull in device tunables. */
920 	sc->jme_process_limit = JME_PROC_DEFAULT;
921 	error = resource_int_value(device_get_name(sc->jme_dev),
922 	    device_get_unit(sc->jme_dev), "process_limit",
923 	    &sc->jme_process_limit);
924 	if (error == 0) {
925 		if (sc->jme_process_limit < JME_PROC_MIN ||
926 		    sc->jme_process_limit > JME_PROC_MAX) {
927 			device_printf(sc->jme_dev,
928 			    "process_limit value out of range; "
929 			    "using default: %d\n", JME_PROC_DEFAULT);
930 			sc->jme_process_limit = JME_PROC_DEFAULT;
931 		}
932 	}
933 
934 	sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
935 	error = resource_int_value(device_get_name(sc->jme_dev),
936 	    device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
937 	if (error == 0) {
938 		if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
939 		    sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
940 			device_printf(sc->jme_dev,
941 			    "tx_coal_to value out of range; "
942 			    "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
943 			sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
944 		}
945 	}
946 
947 	sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
948 	error = resource_int_value(device_get_name(sc->jme_dev),
949 	    device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
950 	if (error == 0) {
951 		if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
952 		    sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
953 			device_printf(sc->jme_dev,
954 			    "tx_coal_pkt value out of range; "
955 			    "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
956 			sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
957 		}
958 	}
959 
960 	sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
961 	error = resource_int_value(device_get_name(sc->jme_dev),
962 	    device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
963 	if (error == 0) {
964 		if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
965 		    sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
966 			device_printf(sc->jme_dev,
967 			    "rx_coal_to value out of range; "
968 			    "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
969 			sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
970 		}
971 	}
972 
973 	sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
974 	error = resource_int_value(device_get_name(sc->jme_dev),
975 	    device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
976 	if (error == 0) {
977 		if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
978 		    sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
979 			device_printf(sc->jme_dev,
980 			    "tx_coal_pkt value out of range; "
981 			    "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
982 			sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
983 		}
984 	}
985 
986 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
987 		return;
988 
989 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
990 	    NULL, "JME statistics");
991 	parent = SYSCTL_CHILDREN(tree);
992 
993 	/* Rx statistics. */
994 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
995 	    NULL, "Rx MAC statistics");
996 	child = SYSCTL_CHILDREN(tree);
997 	JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
998 	    &stats->rx_good_frames, "Good frames");
999 	JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1000 	    &stats->rx_crc_errs, "CRC errors");
1001 	JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
1002 	    &stats->rx_mii_errs, "MII errors");
1003 	JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1004 	    &stats->rx_fifo_oflows, "FIFO overflows");
1005 	JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
1006 	    &stats->rx_desc_empty, "Descriptor empty");
1007 	JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1008 	    &stats->rx_bad_frames, "Bad frames");
1009 
1010 	/* Tx statistics. */
1011 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1012 	    NULL, "Tx MAC statistics");
1013 	child = SYSCTL_CHILDREN(tree);
1014 	JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1015 	    &stats->tx_good_frames, "Good frames");
1016 	JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1017 	    &stats->tx_bad_frames, "Bad frames");
1018 }
1019 
1020 #undef	JME_SYSCTL_STAT_ADD32
1021 
1022 struct jme_dmamap_arg {
1023 	bus_addr_t	jme_busaddr;
1024 };
1025 
1026 static void
1027 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1028 {
1029 	struct jme_dmamap_arg *ctx;
1030 
1031 	if (error != 0)
1032 		return;
1033 
1034 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1035 
1036 	ctx = (struct jme_dmamap_arg *)arg;
1037 	ctx->jme_busaddr = segs[0].ds_addr;
1038 }
1039 
1040 static int
1041 jme_dma_alloc(struct jme_softc *sc)
1042 {
1043 	struct jme_dmamap_arg ctx;
1044 	struct jme_txdesc *txd;
1045 	struct jme_rxdesc *rxd;
1046 	bus_addr_t lowaddr, rx_ring_end, tx_ring_end;
1047 	int error, i;
1048 
1049 	lowaddr = BUS_SPACE_MAXADDR;
1050 	if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1051 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1052 
1053 again:
1054 	/* Create parent ring tag. */
1055 	error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1056 	    1, 0,			/* algnmnt, boundary */
1057 	    lowaddr,			/* lowaddr */
1058 	    BUS_SPACE_MAXADDR,		/* highaddr */
1059 	    NULL, NULL,			/* filter, filterarg */
1060 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1061 	    0,				/* nsegments */
1062 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1063 	    0,				/* flags */
1064 	    NULL, NULL,			/* lockfunc, lockarg */
1065 	    &sc->jme_cdata.jme_ring_tag);
1066 	if (error != 0) {
1067 		device_printf(sc->jme_dev,
1068 		    "could not create parent ring DMA tag.\n");
1069 		goto fail;
1070 	}
1071 	/* Create tag for Tx ring. */
1072 	error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1073 	    JME_TX_RING_ALIGN, 0,	/* algnmnt, boundary */
1074 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1075 	    BUS_SPACE_MAXADDR,		/* highaddr */
1076 	    NULL, NULL,			/* filter, filterarg */
1077 	    JME_TX_RING_SIZE,		/* maxsize */
1078 	    1,				/* nsegments */
1079 	    JME_TX_RING_SIZE,		/* maxsegsize */
1080 	    0,				/* flags */
1081 	    NULL, NULL,			/* lockfunc, lockarg */
1082 	    &sc->jme_cdata.jme_tx_ring_tag);
1083 	if (error != 0) {
1084 		device_printf(sc->jme_dev,
1085 		    "could not allocate Tx ring DMA tag.\n");
1086 		goto fail;
1087 	}
1088 
1089 	/* Create tag for Rx ring. */
1090 	error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1091 	    JME_RX_RING_ALIGN, 0,	/* algnmnt, boundary */
1092 	    lowaddr,			/* lowaddr */
1093 	    BUS_SPACE_MAXADDR,		/* highaddr */
1094 	    NULL, NULL,			/* filter, filterarg */
1095 	    JME_RX_RING_SIZE,		/* maxsize */
1096 	    1,				/* nsegments */
1097 	    JME_RX_RING_SIZE,		/* maxsegsize */
1098 	    0,				/* flags */
1099 	    NULL, NULL,			/* lockfunc, lockarg */
1100 	    &sc->jme_cdata.jme_rx_ring_tag);
1101 	if (error != 0) {
1102 		device_printf(sc->jme_dev,
1103 		    "could not allocate Rx ring DMA tag.\n");
1104 		goto fail;
1105 	}
1106 
1107 	/* Allocate DMA'able memory and load the DMA map for Tx ring. */
1108 	error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1109 	    (void **)&sc->jme_rdata.jme_tx_ring,
1110 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1111 	    &sc->jme_cdata.jme_tx_ring_map);
1112 	if (error != 0) {
1113 		device_printf(sc->jme_dev,
1114 		    "could not allocate DMA'able memory for Tx ring.\n");
1115 		goto fail;
1116 	}
1117 
1118 	ctx.jme_busaddr = 0;
1119 	error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1120 	    sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1121 	    JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1122 	if (error != 0 || ctx.jme_busaddr == 0) {
1123 		device_printf(sc->jme_dev,
1124 		    "could not load DMA'able memory for Tx ring.\n");
1125 		goto fail;
1126 	}
1127 	sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr;
1128 
1129 	/* Allocate DMA'able memory and load the DMA map for Rx ring. */
1130 	error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1131 	    (void **)&sc->jme_rdata.jme_rx_ring,
1132 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1133 	    &sc->jme_cdata.jme_rx_ring_map);
1134 	if (error != 0) {
1135 		device_printf(sc->jme_dev,
1136 		    "could not allocate DMA'able memory for Rx ring.\n");
1137 		goto fail;
1138 	}
1139 
1140 	ctx.jme_busaddr = 0;
1141 	error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1142 	    sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1143 	    JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1144 	if (error != 0 || ctx.jme_busaddr == 0) {
1145 		device_printf(sc->jme_dev,
1146 		    "could not load DMA'able memory for Rx ring.\n");
1147 		goto fail;
1148 	}
1149 	sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
1150 
1151 	if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1152 		/* Tx/Rx descriptor queue should reside within 4GB boundary. */
1153 		tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1154 		    JME_TX_RING_SIZE;
1155 		rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1156 		    JME_RX_RING_SIZE;
1157 		if ((JME_ADDR_HI(tx_ring_end) !=
1158 		    JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1159 		    (JME_ADDR_HI(rx_ring_end) !=
1160 		     JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1161 			device_printf(sc->jme_dev, "4GB boundary crossed, "
1162 			    "switching to 32bit DMA address mode.\n");
1163 			jme_dma_free(sc);
1164 			/* Limit DMA address space to 32bit and try again. */
1165 			lowaddr = BUS_SPACE_MAXADDR_32BIT;
1166 			goto again;
1167 		}
1168 	}
1169 
1170 	lowaddr = BUS_SPACE_MAXADDR;
1171 	if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1172 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1173 	/* Create parent buffer tag. */
1174 	error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1175 	    1, 0,			/* algnmnt, boundary */
1176 	    lowaddr,			/* lowaddr */
1177 	    BUS_SPACE_MAXADDR,		/* highaddr */
1178 	    NULL, NULL,			/* filter, filterarg */
1179 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1180 	    0,				/* nsegments */
1181 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1182 	    0,				/* flags */
1183 	    NULL, NULL,			/* lockfunc, lockarg */
1184 	    &sc->jme_cdata.jme_buffer_tag);
1185 	if (error != 0) {
1186 		device_printf(sc->jme_dev,
1187 		    "could not create parent buffer DMA tag.\n");
1188 		goto fail;
1189 	}
1190 
1191 	/* Create shadow status block tag. */
1192 	error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1193 	    JME_SSB_ALIGN, 0,		/* algnmnt, boundary */
1194 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1195 	    BUS_SPACE_MAXADDR,		/* highaddr */
1196 	    NULL, NULL,			/* filter, filterarg */
1197 	    JME_SSB_SIZE,		/* maxsize */
1198 	    1,				/* nsegments */
1199 	    JME_SSB_SIZE,		/* maxsegsize */
1200 	    0,				/* flags */
1201 	    NULL, NULL,			/* lockfunc, lockarg */
1202 	    &sc->jme_cdata.jme_ssb_tag);
1203 	if (error != 0) {
1204 		device_printf(sc->jme_dev,
1205 		    "could not create shared status block DMA tag.\n");
1206 		goto fail;
1207 	}
1208 
1209 	/* Create tag for Tx buffers. */
1210 	error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1211 	    1, 0,			/* algnmnt, boundary */
1212 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1213 	    BUS_SPACE_MAXADDR,		/* highaddr */
1214 	    NULL, NULL,			/* filter, filterarg */
1215 	    JME_TSO_MAXSIZE,		/* maxsize */
1216 	    JME_MAXTXSEGS,		/* nsegments */
1217 	    JME_TSO_MAXSEGSIZE,		/* maxsegsize */
1218 	    0,				/* flags */
1219 	    NULL, NULL,			/* lockfunc, lockarg */
1220 	    &sc->jme_cdata.jme_tx_tag);
1221 	if (error != 0) {
1222 		device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1223 		goto fail;
1224 	}
1225 
1226 	/* Create tag for Rx buffers. */
1227 	error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1228 	    JME_RX_BUF_ALIGN, 0,	/* algnmnt, boundary */
1229 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1230 	    BUS_SPACE_MAXADDR,		/* highaddr */
1231 	    NULL, NULL,			/* filter, filterarg */
1232 	    MCLBYTES,			/* maxsize */
1233 	    1,				/* nsegments */
1234 	    MCLBYTES,			/* maxsegsize */
1235 	    0,				/* flags */
1236 	    NULL, NULL,			/* lockfunc, lockarg */
1237 	    &sc->jme_cdata.jme_rx_tag);
1238 	if (error != 0) {
1239 		device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1240 		goto fail;
1241 	}
1242 
1243 	/*
1244 	 * Allocate DMA'able memory and load the DMA map for shared
1245 	 * status block.
1246 	 */
1247 	error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1248 	    (void **)&sc->jme_rdata.jme_ssb_block,
1249 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1250 	    &sc->jme_cdata.jme_ssb_map);
1251 	if (error != 0) {
1252 		device_printf(sc->jme_dev, "could not allocate DMA'able "
1253 		    "memory for shared status block.\n");
1254 		goto fail;
1255 	}
1256 
1257 	ctx.jme_busaddr = 0;
1258 	error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1259 	    sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1260 	    JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1261 	if (error != 0 || ctx.jme_busaddr == 0) {
1262 		device_printf(sc->jme_dev, "could not load DMA'able memory "
1263 		    "for shared status block.\n");
1264 		goto fail;
1265 	}
1266 	sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr;
1267 
1268 	/* Create DMA maps for Tx buffers. */
1269 	for (i = 0; i < JME_TX_RING_CNT; i++) {
1270 		txd = &sc->jme_cdata.jme_txdesc[i];
1271 		txd->tx_m = NULL;
1272 		txd->tx_dmamap = NULL;
1273 		error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1274 		    &txd->tx_dmamap);
1275 		if (error != 0) {
1276 			device_printf(sc->jme_dev,
1277 			    "could not create Tx dmamap.\n");
1278 			goto fail;
1279 		}
1280 	}
1281 	/* Create DMA maps for Rx buffers. */
1282 	if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1283 	    &sc->jme_cdata.jme_rx_sparemap)) != 0) {
1284 		device_printf(sc->jme_dev,
1285 		    "could not create spare Rx dmamap.\n");
1286 		goto fail;
1287 	}
1288 	for (i = 0; i < JME_RX_RING_CNT; i++) {
1289 		rxd = &sc->jme_cdata.jme_rxdesc[i];
1290 		rxd->rx_m = NULL;
1291 		rxd->rx_dmamap = NULL;
1292 		error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1293 		    &rxd->rx_dmamap);
1294 		if (error != 0) {
1295 			device_printf(sc->jme_dev,
1296 			    "could not create Rx dmamap.\n");
1297 			goto fail;
1298 		}
1299 	}
1300 
1301 fail:
1302 	return (error);
1303 }
1304 
1305 static void
1306 jme_dma_free(struct jme_softc *sc)
1307 {
1308 	struct jme_txdesc *txd;
1309 	struct jme_rxdesc *rxd;
1310 	int i;
1311 
1312 	/* Tx ring */
1313 	if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1314 		if (sc->jme_cdata.jme_tx_ring_map)
1315 			bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1316 			    sc->jme_cdata.jme_tx_ring_map);
1317 		if (sc->jme_cdata.jme_tx_ring_map &&
1318 		    sc->jme_rdata.jme_tx_ring)
1319 			bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1320 			    sc->jme_rdata.jme_tx_ring,
1321 			    sc->jme_cdata.jme_tx_ring_map);
1322 		sc->jme_rdata.jme_tx_ring = NULL;
1323 		sc->jme_cdata.jme_tx_ring_map = NULL;
1324 		bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1325 		sc->jme_cdata.jme_tx_ring_tag = NULL;
1326 	}
1327 	/* Rx ring */
1328 	if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1329 		if (sc->jme_cdata.jme_rx_ring_map)
1330 			bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1331 			    sc->jme_cdata.jme_rx_ring_map);
1332 		if (sc->jme_cdata.jme_rx_ring_map &&
1333 		    sc->jme_rdata.jme_rx_ring)
1334 			bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1335 			    sc->jme_rdata.jme_rx_ring,
1336 			    sc->jme_cdata.jme_rx_ring_map);
1337 		sc->jme_rdata.jme_rx_ring = NULL;
1338 		sc->jme_cdata.jme_rx_ring_map = NULL;
1339 		bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1340 		sc->jme_cdata.jme_rx_ring_tag = NULL;
1341 	}
1342 	/* Tx buffers */
1343 	if (sc->jme_cdata.jme_tx_tag != NULL) {
1344 		for (i = 0; i < JME_TX_RING_CNT; i++) {
1345 			txd = &sc->jme_cdata.jme_txdesc[i];
1346 			if (txd->tx_dmamap != NULL) {
1347 				bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1348 				    txd->tx_dmamap);
1349 				txd->tx_dmamap = NULL;
1350 			}
1351 		}
1352 		bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1353 		sc->jme_cdata.jme_tx_tag = NULL;
1354 	}
1355 	/* Rx buffers */
1356 	if (sc->jme_cdata.jme_rx_tag != NULL) {
1357 		for (i = 0; i < JME_RX_RING_CNT; i++) {
1358 			rxd = &sc->jme_cdata.jme_rxdesc[i];
1359 			if (rxd->rx_dmamap != NULL) {
1360 				bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1361 				    rxd->rx_dmamap);
1362 				rxd->rx_dmamap = NULL;
1363 			}
1364 		}
1365 		if (sc->jme_cdata.jme_rx_sparemap != NULL) {
1366 			bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1367 			    sc->jme_cdata.jme_rx_sparemap);
1368 			sc->jme_cdata.jme_rx_sparemap = NULL;
1369 		}
1370 		bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1371 		sc->jme_cdata.jme_rx_tag = NULL;
1372 	}
1373 
1374 	/* Shared status block. */
1375 	if (sc->jme_cdata.jme_ssb_tag != NULL) {
1376 		if (sc->jme_cdata.jme_ssb_map)
1377 			bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1378 			    sc->jme_cdata.jme_ssb_map);
1379 		if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block)
1380 			bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1381 			    sc->jme_rdata.jme_ssb_block,
1382 			    sc->jme_cdata.jme_ssb_map);
1383 		sc->jme_rdata.jme_ssb_block = NULL;
1384 		sc->jme_cdata.jme_ssb_map = NULL;
1385 		bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1386 		sc->jme_cdata.jme_ssb_tag = NULL;
1387 	}
1388 
1389 	if (sc->jme_cdata.jme_buffer_tag != NULL) {
1390 		bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1391 		sc->jme_cdata.jme_buffer_tag = NULL;
1392 	}
1393 	if (sc->jme_cdata.jme_ring_tag != NULL) {
1394 		bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1395 		sc->jme_cdata.jme_ring_tag = NULL;
1396 	}
1397 }
1398 
1399 /*
1400  *	Make sure the interface is stopped at reboot time.
1401  */
1402 static int
1403 jme_shutdown(device_t dev)
1404 {
1405 
1406 	return (jme_suspend(dev));
1407 }
1408 
1409 /*
1410  * Unlike other ethernet controllers, JMC250 requires
1411  * explicit resetting link speed to 10/100Mbps as gigabit
1412  * link will cunsume more power than 375mA.
1413  * Note, we reset the link speed to 10/100Mbps with
1414  * auto-negotiation but we don't know whether that operation
1415  * would succeed or not as we have no control after powering
1416  * off. If the renegotiation fail WOL may not work. Running
1417  * at 1Gbps draws more power than 375mA at 3.3V which is
1418  * specified in PCI specification and that would result in
1419  * complete shutdowning power to ethernet controller.
1420  *
1421  * TODO
1422  *  Save current negotiated media speed/duplex/flow-control
1423  *  to softc and restore the same link again after resuming.
1424  *  PHY handling such as power down/resetting to 100Mbps
1425  *  may be better handled in suspend method in phy driver.
1426  */
1427 static void
1428 jme_setlinkspeed(struct jme_softc *sc)
1429 {
1430 	struct mii_data *mii;
1431 	int aneg, i;
1432 
1433 	JME_LOCK_ASSERT(sc);
1434 
1435 	mii = device_get_softc(sc->jme_miibus);
1436 	mii_pollstat(mii);
1437 	aneg = 0;
1438 	if ((mii->mii_media_status & IFM_AVALID) != 0) {
1439 		switch IFM_SUBTYPE(mii->mii_media_active) {
1440 		case IFM_10_T:
1441 		case IFM_100_TX:
1442 			return;
1443 		case IFM_1000_T:
1444 			aneg++;
1445 		default:
1446 			break;
1447 		}
1448 	}
1449 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1450 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1451 	    ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1452 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1453 	    BMCR_AUTOEN | BMCR_STARTNEG);
1454 	DELAY(1000);
1455 	if (aneg != 0) {
1456 		/* Poll link state until jme(4) get a 10/100 link. */
1457 		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1458 			mii_pollstat(mii);
1459 			if ((mii->mii_media_status & IFM_AVALID) != 0) {
1460 				switch (IFM_SUBTYPE(mii->mii_media_active)) {
1461 				case IFM_10_T:
1462 				case IFM_100_TX:
1463 					jme_mac_config(sc);
1464 					return;
1465 				default:
1466 					break;
1467 				}
1468 			}
1469 			JME_UNLOCK(sc);
1470 			pause("jmelnk", hz);
1471 			JME_LOCK(sc);
1472 		}
1473 		if (i == MII_ANEGTICKS_GIGE)
1474 			device_printf(sc->jme_dev, "establishing link failed, "
1475 			    "WOL may not work!");
1476 	}
1477 	/*
1478 	 * No link, force MAC to have 100Mbps, full-duplex link.
1479 	 * This is the last resort and may/may not work.
1480 	 */
1481 	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1482 	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1483 	jme_mac_config(sc);
1484 }
1485 
1486 static void
1487 jme_setwol(struct jme_softc *sc)
1488 {
1489 	struct ifnet *ifp;
1490 	uint32_t gpr, pmcs;
1491 	uint16_t pmstat;
1492 	int pmc;
1493 
1494 	JME_LOCK_ASSERT(sc);
1495 
1496 	if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1497 		/* Remove Tx MAC/offload clock to save more power. */
1498 		if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1499 			CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1500 			    ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1501 			    GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1502 		/* No PME capability, PHY power down. */
1503 		jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1504 		    MII_BMCR, BMCR_PDOWN);
1505 		return;
1506 	}
1507 
1508 	ifp = sc->jme_ifp;
1509 	gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1510 	pmcs = CSR_READ_4(sc, JME_PMCS);
1511 	pmcs &= ~PMCS_WOL_ENB_MASK;
1512 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1513 		pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1514 		/* Enable PME message. */
1515 		gpr |= GPREG0_PME_ENB;
1516 		/* For gigabit controllers, reset link speed to 10/100. */
1517 		if ((sc->jme_flags & JME_FLAG_FASTETH) == 0)
1518 			jme_setlinkspeed(sc);
1519 	}
1520 
1521 	CSR_WRITE_4(sc, JME_PMCS, pmcs);
1522 	CSR_WRITE_4(sc, JME_GPREG0, gpr);
1523 	/* Remove Tx MAC/offload clock to save more power. */
1524 	if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1525 		CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1526 		    ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1527 		    GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1528 	/* Request PME. */
1529 	pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1530 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1531 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1532 		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1533 	pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1534 	if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1535 		/* No WOL, PHY power down. */
1536 		jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1537 		    MII_BMCR, BMCR_PDOWN);
1538 	}
1539 }
1540 
1541 static int
1542 jme_suspend(device_t dev)
1543 {
1544 	struct jme_softc *sc;
1545 
1546 	sc = device_get_softc(dev);
1547 
1548 	JME_LOCK(sc);
1549 	jme_stop(sc);
1550 	jme_setwol(sc);
1551 	JME_UNLOCK(sc);
1552 
1553 	return (0);
1554 }
1555 
1556 static int
1557 jme_resume(device_t dev)
1558 {
1559 	struct jme_softc *sc;
1560 	struct ifnet *ifp;
1561 	uint16_t pmstat;
1562 	int pmc;
1563 
1564 	sc = device_get_softc(dev);
1565 
1566 	JME_LOCK(sc);
1567 	if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1568 		pmstat = pci_read_config(sc->jme_dev,
1569 		    pmc + PCIR_POWER_STATUS, 2);
1570 		/* Disable PME clear PME status. */
1571 		pmstat &= ~PCIM_PSTAT_PMEENABLE;
1572 		pci_write_config(sc->jme_dev,
1573 		    pmc + PCIR_POWER_STATUS, pmstat, 2);
1574 	}
1575 	ifp = sc->jme_ifp;
1576 	if ((ifp->if_flags & IFF_UP) != 0) {
1577 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1578 		jme_init_locked(sc);
1579 	}
1580 
1581 	JME_UNLOCK(sc);
1582 
1583 	return (0);
1584 }
1585 
1586 static int
1587 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1588 {
1589 	struct jme_txdesc *txd;
1590 	struct jme_desc *desc;
1591 	struct mbuf *m;
1592 	bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1593 	int error, i, nsegs, prod;
1594 	uint32_t cflags, tso_segsz;
1595 
1596 	JME_LOCK_ASSERT(sc);
1597 
1598 	M_ASSERTPKTHDR((*m_head));
1599 
1600 	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1601 		/*
1602 		 * Due to the adherence to NDIS specification JMC250
1603 		 * assumes upper stack computed TCP pseudo checksum
1604 		 * without including payload length. This breaks
1605 		 * checksum offload for TSO case so recompute TCP
1606 		 * pseudo checksum for JMC250. Hopefully this wouldn't
1607 		 * be much burden on modern CPUs.
1608 		 */
1609 		struct ether_header *eh;
1610 		struct ip *ip;
1611 		struct tcphdr *tcp;
1612 		uint32_t ip_off, poff;
1613 
1614 		if (M_WRITABLE(*m_head) == 0) {
1615 			/* Get a writable copy. */
1616 			m = m_dup(*m_head, M_DONTWAIT);
1617 			m_freem(*m_head);
1618 			if (m == NULL) {
1619 				*m_head = NULL;
1620 				return (ENOBUFS);
1621 			}
1622 			*m_head = m;
1623 		}
1624 		ip_off = sizeof(struct ether_header);
1625 		m = m_pullup(*m_head, ip_off);
1626 		if (m == NULL) {
1627 			*m_head = NULL;
1628 			return (ENOBUFS);
1629 		}
1630 		eh = mtod(m, struct ether_header *);
1631 		/* Check the existence of VLAN tag. */
1632 		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1633 			ip_off = sizeof(struct ether_vlan_header);
1634 			m = m_pullup(m, ip_off);
1635 			if (m == NULL) {
1636 				*m_head = NULL;
1637 				return (ENOBUFS);
1638 			}
1639 		}
1640 		m = m_pullup(m, ip_off + sizeof(struct ip));
1641 		if (m == NULL) {
1642 			*m_head = NULL;
1643 			return (ENOBUFS);
1644 		}
1645 		ip = (struct ip *)(mtod(m, char *) + ip_off);
1646 		poff = ip_off + (ip->ip_hl << 2);
1647 		m = m_pullup(m, poff + sizeof(struct tcphdr));
1648 		if (m == NULL) {
1649 			*m_head = NULL;
1650 			return (ENOBUFS);
1651 		}
1652 		/*
1653 		 * Reset IP checksum and recompute TCP pseudo
1654 		 * checksum that NDIS specification requires.
1655 		 */
1656 		ip = (struct ip *)(mtod(m, char *) + ip_off);
1657 		tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1658 		ip->ip_sum = 0;
1659 		if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1660 			tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1661 			    ip->ip_dst.s_addr,
1662 			    htons((tcp->th_off << 2) + IPPROTO_TCP));
1663 			/* No need to TSO, force IP checksum offload. */
1664 			(*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO;
1665 			(*m_head)->m_pkthdr.csum_flags |= CSUM_IP;
1666 		} else
1667 			tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1668 			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1669 		*m_head = m;
1670 	}
1671 
1672 	prod = sc->jme_cdata.jme_tx_prod;
1673 	txd = &sc->jme_cdata.jme_txdesc[prod];
1674 
1675 	error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1676 	    txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1677 	if (error == EFBIG) {
1678 		m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS);
1679 		if (m == NULL) {
1680 			m_freem(*m_head);
1681 			*m_head = NULL;
1682 			return (ENOMEM);
1683 		}
1684 		*m_head = m;
1685 		error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1686 		    txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1687 		if (error != 0) {
1688 			m_freem(*m_head);
1689 			*m_head = NULL;
1690 			return (error);
1691 		}
1692 	} else if (error != 0)
1693 		return (error);
1694 	if (nsegs == 0) {
1695 		m_freem(*m_head);
1696 		*m_head = NULL;
1697 		return (EIO);
1698 	}
1699 
1700 	/*
1701 	 * Check descriptor overrun. Leave one free descriptor.
1702 	 * Since we always use 64bit address mode for transmitting,
1703 	 * each Tx request requires one more dummy descriptor.
1704 	 */
1705 	if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) {
1706 		bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1707 		return (ENOBUFS);
1708 	}
1709 
1710 	m = *m_head;
1711 	cflags = 0;
1712 	tso_segsz = 0;
1713 	/* Configure checksum offload and TSO. */
1714 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1715 		tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz <<
1716 		    JME_TD_MSS_SHIFT;
1717 		cflags |= JME_TD_TSO;
1718 	} else {
1719 		if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1720 			cflags |= JME_TD_IPCSUM;
1721 		if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1722 			cflags |= JME_TD_TCPCSUM;
1723 		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1724 			cflags |= JME_TD_UDPCSUM;
1725 	}
1726 	/* Configure VLAN. */
1727 	if ((m->m_flags & M_VLANTAG) != 0) {
1728 		cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK);
1729 		cflags |= JME_TD_VLAN_TAG;
1730 	}
1731 
1732 	desc = &sc->jme_rdata.jme_tx_ring[prod];
1733 	desc->flags = htole32(cflags);
1734 	desc->buflen = htole32(tso_segsz);
1735 	desc->addr_hi = htole32(m->m_pkthdr.len);
1736 	desc->addr_lo = 0;
1737 	sc->jme_cdata.jme_tx_cnt++;
1738 	JME_DESC_INC(prod, JME_TX_RING_CNT);
1739 	for (i = 0; i < nsegs; i++) {
1740 		desc = &sc->jme_rdata.jme_tx_ring[prod];
1741 		desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1742 		desc->buflen = htole32(txsegs[i].ds_len);
1743 		desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1744 		desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1745 		sc->jme_cdata.jme_tx_cnt++;
1746 		JME_DESC_INC(prod, JME_TX_RING_CNT);
1747 	}
1748 
1749 	/* Update producer index. */
1750 	sc->jme_cdata.jme_tx_prod = prod;
1751 	/*
1752 	 * Finally request interrupt and give the first descriptor
1753 	 * owenership to hardware.
1754 	 */
1755 	desc = txd->tx_desc;
1756 	desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1757 
1758 	txd->tx_m = m;
1759 	txd->tx_ndesc = nsegs + 1;
1760 
1761 	/* Sync descriptors. */
1762 	bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1763 	    BUS_DMASYNC_PREWRITE);
1764 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1765 	    sc->jme_cdata.jme_tx_ring_map,
1766 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1767 
1768 	return (0);
1769 }
1770 
1771 static void
1772 jme_tx_task(void *arg, int pending)
1773 {
1774 	struct ifnet *ifp;
1775 
1776 	ifp = (struct ifnet *)arg;
1777 	jme_start(ifp);
1778 }
1779 
1780 static void
1781 jme_start(struct ifnet *ifp)
1782 {
1783         struct jme_softc *sc;
1784         struct mbuf *m_head;
1785 	int enq;
1786 
1787 	sc = ifp->if_softc;
1788 
1789 	JME_LOCK(sc);
1790 
1791 	if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1792 		jme_txeof(sc);
1793 
1794 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1795 	    IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) {
1796 		JME_UNLOCK(sc);
1797 		return;
1798 	}
1799 
1800 	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1801 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1802 		if (m_head == NULL)
1803 			break;
1804 		/*
1805 		 * Pack the data into the transmit ring. If we
1806 		 * don't have room, set the OACTIVE flag and wait
1807 		 * for the NIC to drain the ring.
1808 		 */
1809 		if (jme_encap(sc, &m_head)) {
1810 			if (m_head == NULL)
1811 				break;
1812 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1813 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1814 			break;
1815 		}
1816 
1817 		enq++;
1818 		/*
1819 		 * If there's a BPF listener, bounce a copy of this frame
1820 		 * to him.
1821 		 */
1822 		ETHER_BPF_MTAP(ifp, m_head);
1823 	}
1824 
1825 	if (enq > 0) {
1826 		/*
1827 		 * Reading TXCSR takes very long time under heavy load
1828 		 * so cache TXCSR value and writes the ORed value with
1829 		 * the kick command to the TXCSR. This saves one register
1830 		 * access cycle.
1831 		 */
1832 		CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1833 		    TXCSR_TXQ_N_START(TXCSR_TXQ0));
1834 		/* Set a timeout in case the chip goes out to lunch. */
1835 		sc->jme_watchdog_timer = JME_TX_TIMEOUT;
1836 	}
1837 
1838 	JME_UNLOCK(sc);
1839 }
1840 
1841 static void
1842 jme_watchdog(struct jme_softc *sc)
1843 {
1844 	struct ifnet *ifp;
1845 
1846 	JME_LOCK_ASSERT(sc);
1847 
1848 	if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer)
1849 		return;
1850 
1851 	ifp = sc->jme_ifp;
1852 	if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1853 		if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
1854 		ifp->if_oerrors++;
1855 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1856 		jme_init_locked(sc);
1857 		return;
1858 	}
1859 	jme_txeof(sc);
1860 	if (sc->jme_cdata.jme_tx_cnt == 0) {
1861 		if_printf(sc->jme_ifp,
1862 		    "watchdog timeout (missed Tx interrupts) -- recovering\n");
1863 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1864 			taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1865 		return;
1866 	}
1867 
1868 	if_printf(sc->jme_ifp, "watchdog timeout\n");
1869 	ifp->if_oerrors++;
1870 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1871 	jme_init_locked(sc);
1872 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1873 		taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1874 }
1875 
1876 static int
1877 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1878 {
1879 	struct jme_softc *sc;
1880 	struct ifreq *ifr;
1881 	struct mii_data *mii;
1882 	uint32_t reg;
1883 	int error, mask;
1884 
1885 	sc = ifp->if_softc;
1886 	ifr = (struct ifreq *)data;
1887 	error = 0;
1888 	switch (cmd) {
1889 	case SIOCSIFMTU:
1890 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1891 		    ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 &&
1892 		    ifr->ifr_mtu > JME_MAX_MTU)) {
1893 			error = EINVAL;
1894 			break;
1895 		}
1896 
1897 		if (ifp->if_mtu != ifr->ifr_mtu) {
1898 			/*
1899 			 * No special configuration is required when interface
1900 			 * MTU is changed but availability of TSO/Tx checksum
1901 			 * offload should be chcked against new MTU size as
1902 			 * FIFO size is just 2K.
1903 			 */
1904 			JME_LOCK(sc);
1905 			if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1906 				ifp->if_capenable &=
1907 				    ~(IFCAP_TXCSUM | IFCAP_TSO4);
1908 				ifp->if_hwassist &=
1909 				    ~(JME_CSUM_FEATURES | CSUM_TSO);
1910 				VLAN_CAPABILITIES(ifp);
1911 			}
1912 			ifp->if_mtu = ifr->ifr_mtu;
1913 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1914 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1915 				jme_init_locked(sc);
1916 			}
1917 			JME_UNLOCK(sc);
1918 		}
1919 		break;
1920 	case SIOCSIFFLAGS:
1921 		JME_LOCK(sc);
1922 		if ((ifp->if_flags & IFF_UP) != 0) {
1923 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1924 				if (((ifp->if_flags ^ sc->jme_if_flags)
1925 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1926 					jme_set_filter(sc);
1927 			} else {
1928 				if ((sc->jme_flags & JME_FLAG_DETACH) == 0)
1929 					jme_init_locked(sc);
1930 			}
1931 		} else {
1932 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1933 				jme_stop(sc);
1934 		}
1935 		sc->jme_if_flags = ifp->if_flags;
1936 		JME_UNLOCK(sc);
1937 		break;
1938 	case SIOCADDMULTI:
1939 	case SIOCDELMULTI:
1940 		JME_LOCK(sc);
1941 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1942 			jme_set_filter(sc);
1943 		JME_UNLOCK(sc);
1944 		break;
1945 	case SIOCSIFMEDIA:
1946 	case SIOCGIFMEDIA:
1947 		mii = device_get_softc(sc->jme_miibus);
1948 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1949 		break;
1950 	case SIOCSIFCAP:
1951 		JME_LOCK(sc);
1952 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1953 		if ((mask & IFCAP_TXCSUM) != 0 &&
1954 		    ifp->if_mtu < JME_TX_FIFO_SIZE) {
1955 			if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1956 				ifp->if_capenable ^= IFCAP_TXCSUM;
1957 				if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1958 					ifp->if_hwassist |= JME_CSUM_FEATURES;
1959 				else
1960 					ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1961 			}
1962 		}
1963 		if ((mask & IFCAP_RXCSUM) != 0 &&
1964 		    (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1965 			ifp->if_capenable ^= IFCAP_RXCSUM;
1966 			reg = CSR_READ_4(sc, JME_RXMAC);
1967 			reg &= ~RXMAC_CSUM_ENB;
1968 			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1969 				reg |= RXMAC_CSUM_ENB;
1970 			CSR_WRITE_4(sc, JME_RXMAC, reg);
1971 		}
1972 		if ((mask & IFCAP_TSO4) != 0 &&
1973 		    ifp->if_mtu < JME_TX_FIFO_SIZE) {
1974 			if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) {
1975 				ifp->if_capenable ^= IFCAP_TSO4;
1976 				if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1977 					ifp->if_hwassist |= CSUM_TSO;
1978 				else
1979 					ifp->if_hwassist &= ~CSUM_TSO;
1980 			}
1981 		}
1982 		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1983 		    (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0)
1984 			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1985 		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1986 		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1987 			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1988 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1989 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1990 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1991 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1992 		    (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
1993 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1994 			jme_set_vlan(sc);
1995 		}
1996 		JME_UNLOCK(sc);
1997 		VLAN_CAPABILITIES(ifp);
1998 		break;
1999 	default:
2000 		error = ether_ioctl(ifp, cmd, data);
2001 		break;
2002 	}
2003 
2004 	return (error);
2005 }
2006 
2007 static void
2008 jme_mac_config(struct jme_softc *sc)
2009 {
2010 	struct mii_data *mii;
2011 	uint32_t ghc, gpreg, rxmac, txmac, txpause;
2012 	uint32_t txclk;
2013 
2014 	JME_LOCK_ASSERT(sc);
2015 
2016 	mii = device_get_softc(sc->jme_miibus);
2017 
2018 	CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2019 	DELAY(10);
2020 	CSR_WRITE_4(sc, JME_GHC, 0);
2021 	ghc = 0;
2022 	txclk = 0;
2023 	rxmac = CSR_READ_4(sc, JME_RXMAC);
2024 	rxmac &= ~RXMAC_FC_ENB;
2025 	txmac = CSR_READ_4(sc, JME_TXMAC);
2026 	txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2027 	txpause = CSR_READ_4(sc, JME_TXPFC);
2028 	txpause &= ~TXPFC_PAUSE_ENB;
2029 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2030 		ghc |= GHC_FULL_DUPLEX;
2031 		rxmac &= ~RXMAC_COLL_DET_ENB;
2032 		txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2033 		    TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2034 		    TXMAC_FRAME_BURST);
2035 #ifdef notyet
2036 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2037 			txpause |= TXPFC_PAUSE_ENB;
2038 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2039 			rxmac |= RXMAC_FC_ENB;
2040 #endif
2041 		/* Disable retry transmit timer/retry limit. */
2042 		CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2043 		    ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2044 	} else {
2045 		rxmac |= RXMAC_COLL_DET_ENB;
2046 		txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2047 		/* Enable retry transmit timer/retry limit. */
2048 		CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2049 		    TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2050 	}
2051 		/* Reprogram Tx/Rx MACs with resolved speed/duplex. */
2052 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
2053 	case IFM_10_T:
2054 		ghc |= GHC_SPEED_10;
2055 		txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2056 		break;
2057 	case IFM_100_TX:
2058 		ghc |= GHC_SPEED_100;
2059 		txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2060 		break;
2061 	case IFM_1000_T:
2062 		if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2063 			break;
2064 		ghc |= GHC_SPEED_1000;
2065 		txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
2066 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2067 			txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2068 		break;
2069 	default:
2070 		break;
2071 	}
2072 	if (sc->jme_rev == DEVICEID_JMC250 &&
2073 	    sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
2074 		/*
2075 		 * Workaround occasional packet loss issue of JMC250 A2
2076 		 * when it runs on half-duplex media.
2077 		 */
2078 		gpreg = CSR_READ_4(sc, JME_GPREG1);
2079 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
2080 			gpreg &= ~GPREG1_HDPX_FIX;
2081 		else
2082 			gpreg |= GPREG1_HDPX_FIX;
2083 		CSR_WRITE_4(sc, JME_GPREG1, gpreg);
2084 		/* Workaround CRC errors at 100Mbps on JMC250 A2. */
2085 		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2086 			/* Extend interface FIFO depth. */
2087 			jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2088 			    0x1B, 0x0000);
2089 		} else {
2090 			/* Select default interface FIFO depth. */
2091 			jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2092 			    0x1B, 0x0004);
2093 		}
2094 	}
2095 	if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2096 		ghc |= txclk;
2097 	CSR_WRITE_4(sc, JME_GHC, ghc);
2098 	CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2099 	CSR_WRITE_4(sc, JME_TXMAC, txmac);
2100 	CSR_WRITE_4(sc, JME_TXPFC, txpause);
2101 }
2102 
2103 static void
2104 jme_link_task(void *arg, int pending)
2105 {
2106 	struct jme_softc *sc;
2107 	struct mii_data *mii;
2108 	struct ifnet *ifp;
2109 	struct jme_txdesc *txd;
2110 	bus_addr_t paddr;
2111 	int i;
2112 
2113 	sc = (struct jme_softc *)arg;
2114 
2115 	JME_LOCK(sc);
2116 	mii = device_get_softc(sc->jme_miibus);
2117 	ifp = sc->jme_ifp;
2118 	if (mii == NULL || ifp == NULL ||
2119 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2120 		JME_UNLOCK(sc);
2121 		return;
2122 	}
2123 
2124 	sc->jme_flags &= ~JME_FLAG_LINK;
2125 	if ((mii->mii_media_status & IFM_AVALID) != 0) {
2126 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
2127 		case IFM_10_T:
2128 		case IFM_100_TX:
2129 			sc->jme_flags |= JME_FLAG_LINK;
2130 			break;
2131 		case IFM_1000_T:
2132 			if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2133 				break;
2134 			sc->jme_flags |= JME_FLAG_LINK;
2135 			break;
2136 		default:
2137 			break;
2138 		}
2139 	}
2140 
2141 	/*
2142 	 * Disabling Rx/Tx MACs have a side-effect of resetting
2143 	 * JME_TXNDA/JME_RXNDA register to the first address of
2144 	 * Tx/Rx descriptor address. So driver should reset its
2145 	 * internal procucer/consumer pointer and reclaim any
2146 	 * allocated resources. Note, just saving the value of
2147 	 * JME_TXNDA and JME_RXNDA registers before stopping MAC
2148 	 * and restoring JME_TXNDA/JME_RXNDA register is not
2149 	 * sufficient to make sure correct MAC state because
2150 	 * stopping MAC operation can take a while and hardware
2151 	 * might have updated JME_TXNDA/JME_RXNDA registers
2152 	 * during the stop operation.
2153 	 */
2154 	/* Block execution of task. */
2155 	taskqueue_block(sc->jme_tq);
2156 	/* Disable interrupts and stop driver. */
2157 	CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2158 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2159 	callout_stop(&sc->jme_tick_ch);
2160 	sc->jme_watchdog_timer = 0;
2161 
2162 	/* Stop receiver/transmitter. */
2163 	jme_stop_rx(sc);
2164 	jme_stop_tx(sc);
2165 
2166 	/* XXX Drain all queued tasks. */
2167 	JME_UNLOCK(sc);
2168 	taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
2169 	taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
2170 	JME_LOCK(sc);
2171 
2172 	jme_rxintr(sc, JME_RX_RING_CNT);
2173 	if (sc->jme_cdata.jme_rxhead != NULL)
2174 		m_freem(sc->jme_cdata.jme_rxhead);
2175 	JME_RXCHAIN_RESET(sc);
2176 	jme_txeof(sc);
2177 	if (sc->jme_cdata.jme_tx_cnt != 0) {
2178 		/* Remove queued packets for transmit. */
2179 		for (i = 0; i < JME_TX_RING_CNT; i++) {
2180 			txd = &sc->jme_cdata.jme_txdesc[i];
2181 			if (txd->tx_m != NULL) {
2182 				bus_dmamap_sync(
2183 				    sc->jme_cdata.jme_tx_tag,
2184 				    txd->tx_dmamap,
2185 				    BUS_DMASYNC_POSTWRITE);
2186 				bus_dmamap_unload(
2187 				    sc->jme_cdata.jme_tx_tag,
2188 				    txd->tx_dmamap);
2189 				m_freem(txd->tx_m);
2190 				txd->tx_m = NULL;
2191 				txd->tx_ndesc = 0;
2192 				ifp->if_oerrors++;
2193 			}
2194 		}
2195 	}
2196 
2197 	/*
2198 	 * Reuse configured Rx descriptors and reset
2199 	 * procuder/consumer index.
2200 	 */
2201 	sc->jme_cdata.jme_rx_cons = 0;
2202 	atomic_set_int(&sc->jme_morework, 0);
2203 	jme_init_tx_ring(sc);
2204 	/* Initialize shadow status block. */
2205 	jme_init_ssb(sc);
2206 
2207 	/* Program MAC with resolved speed/duplex/flow-control. */
2208 	if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
2209 		jme_mac_config(sc);
2210 		jme_stats_clear(sc);
2211 
2212 		CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2213 		CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2214 
2215 		/* Set Tx ring address to the hardware. */
2216 		paddr = JME_TX_RING_ADDR(sc, 0);
2217 		CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2218 		CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2219 
2220 		/* Set Rx ring address to the hardware. */
2221 		paddr = JME_RX_RING_ADDR(sc, 0);
2222 		CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2223 		CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2224 
2225 		/* Restart receiver/transmitter. */
2226 		CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2227 		    RXCSR_RXQ_START);
2228 		CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2229 	}
2230 
2231 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2232 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2233 	callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2234 	/* Unblock execution of task. */
2235 	taskqueue_unblock(sc->jme_tq);
2236 	/* Reenable interrupts. */
2237 	CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2238 
2239 	JME_UNLOCK(sc);
2240 }
2241 
2242 static int
2243 jme_intr(void *arg)
2244 {
2245 	struct jme_softc *sc;
2246 	uint32_t status;
2247 
2248 	sc = (struct jme_softc *)arg;
2249 
2250 	status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2251 	if (status == 0 || status == 0xFFFFFFFF)
2252 		return (FILTER_STRAY);
2253 	/* Disable interrupts. */
2254 	CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2255 	taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2256 
2257 	return (FILTER_HANDLED);
2258 }
2259 
2260 static void
2261 jme_int_task(void *arg, int pending)
2262 {
2263 	struct jme_softc *sc;
2264 	struct ifnet *ifp;
2265 	uint32_t status;
2266 	int more;
2267 
2268 	sc = (struct jme_softc *)arg;
2269 	ifp = sc->jme_ifp;
2270 
2271 	status = CSR_READ_4(sc, JME_INTR_STATUS);
2272 	more = atomic_readandclear_int(&sc->jme_morework);
2273 	if (more != 0) {
2274 		status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO;
2275 		more = 0;
2276 	}
2277 	if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2278 		goto done;
2279 	/* Reset PCC counter/timer and Ack interrupts. */
2280 	status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2281 	if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
2282 		status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2283 	if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
2284 		status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2285 	CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2286 	more = 0;
2287 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2288 		if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) {
2289 			more = jme_rxintr(sc, sc->jme_process_limit);
2290 			if (more != 0)
2291 				atomic_set_int(&sc->jme_morework, 1);
2292 		}
2293 		if ((status & INTR_RXQ_DESC_EMPTY) != 0) {
2294 			/*
2295 			 * Notify hardware availability of new Rx
2296 			 * buffers.
2297 			 * Reading RXCSR takes very long time under
2298 			 * heavy load so cache RXCSR value and writes
2299 			 * the ORed value with the kick command to
2300 			 * the RXCSR. This saves one register access
2301 			 * cycle.
2302 			 */
2303 			CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2304 			    RXCSR_RX_ENB | RXCSR_RXQ_START);
2305 		}
2306 		/*
2307 		 * Reclaiming Tx buffers are deferred to make jme(4) run
2308 		 * without locks held.
2309 		 */
2310 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2311 			taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
2312 	}
2313 
2314 	if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {
2315 		taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2316 		return;
2317 	}
2318 done:
2319 	/* Reenable interrupts. */
2320 	CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2321 }
2322 
2323 static void
2324 jme_txeof(struct jme_softc *sc)
2325 {
2326 	struct ifnet *ifp;
2327 	struct jme_txdesc *txd;
2328 	uint32_t status;
2329 	int cons, nsegs;
2330 
2331 	JME_LOCK_ASSERT(sc);
2332 
2333 	ifp = sc->jme_ifp;
2334 
2335 	cons = sc->jme_cdata.jme_tx_cons;
2336 	if (cons == sc->jme_cdata.jme_tx_prod)
2337 		return;
2338 
2339 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2340 	    sc->jme_cdata.jme_tx_ring_map,
2341 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2342 
2343 	/*
2344 	 * Go through our Tx list and free mbufs for those
2345 	 * frames which have been transmitted.
2346 	 */
2347 	for (; cons != sc->jme_cdata.jme_tx_prod;) {
2348 		txd = &sc->jme_cdata.jme_txdesc[cons];
2349 		status = le32toh(txd->tx_desc->flags);
2350 		if ((status & JME_TD_OWN) == JME_TD_OWN)
2351 			break;
2352 
2353 		if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
2354 			ifp->if_oerrors++;
2355 		else {
2356 			ifp->if_opackets++;
2357 			if ((status & JME_TD_COLLISION) != 0)
2358 				ifp->if_collisions +=
2359 				    le32toh(txd->tx_desc->buflen) &
2360 				    JME_TD_BUF_LEN_MASK;
2361 		}
2362 		/*
2363 		 * Only the first descriptor of multi-descriptor
2364 		 * transmission is updated so driver have to skip entire
2365 		 * chained buffers for the transmiited frame. In other
2366 		 * words, JME_TD_OWN bit is valid only at the first
2367 		 * descriptor of a multi-descriptor transmission.
2368 		 */
2369 		for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2370 			sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2371 			JME_DESC_INC(cons, JME_TX_RING_CNT);
2372 		}
2373 
2374 		/* Reclaim transferred mbufs. */
2375 		bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
2376 		    BUS_DMASYNC_POSTWRITE);
2377 		bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2378 
2379 		KASSERT(txd->tx_m != NULL,
2380 		    ("%s: freeing NULL mbuf!\n", __func__));
2381 		m_freem(txd->tx_m);
2382 		txd->tx_m = NULL;
2383 		sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2384 		KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2385 		    ("%s: Active Tx desc counter was garbled\n", __func__));
2386 		txd->tx_ndesc = 0;
2387 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2388 	}
2389 	sc->jme_cdata.jme_tx_cons = cons;
2390 	/* Unarm watchog timer when there is no pending descriptors in queue. */
2391 	if (sc->jme_cdata.jme_tx_cnt == 0)
2392 		sc->jme_watchdog_timer = 0;
2393 
2394 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2395 	    sc->jme_cdata.jme_tx_ring_map,
2396 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2397 }
2398 
2399 static __inline void
2400 jme_discard_rxbuf(struct jme_softc *sc, int cons)
2401 {
2402 	struct jme_desc *desc;
2403 
2404 	desc = &sc->jme_rdata.jme_rx_ring[cons];
2405 	desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2406 	desc->buflen = htole32(MCLBYTES);
2407 }
2408 
2409 /* Receive a frame. */
2410 static void
2411 jme_rxeof(struct jme_softc *sc)
2412 {
2413 	struct ifnet *ifp;
2414 	struct jme_desc *desc;
2415 	struct jme_rxdesc *rxd;
2416 	struct mbuf *mp, *m;
2417 	uint32_t flags, status;
2418 	int cons, count, nsegs;
2419 
2420 	ifp = sc->jme_ifp;
2421 
2422 	cons = sc->jme_cdata.jme_rx_cons;
2423 	desc = &sc->jme_rdata.jme_rx_ring[cons];
2424 	flags = le32toh(desc->flags);
2425 	status = le32toh(desc->buflen);
2426 	nsegs = JME_RX_NSEGS(status);
2427 	sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2428 	if ((status & JME_RX_ERR_STAT) != 0) {
2429 		ifp->if_ierrors++;
2430 		jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons);
2431 #ifdef JME_SHOW_ERRORS
2432 		device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2433 		    __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2434 #endif
2435 		sc->jme_cdata.jme_rx_cons += nsegs;
2436 		sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2437 		return;
2438 	}
2439 
2440 	for (count = 0; count < nsegs; count++,
2441 	    JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2442 		rxd = &sc->jme_cdata.jme_rxdesc[cons];
2443 		mp = rxd->rx_m;
2444 		/* Add a new receive buffer to the ring. */
2445 		if (jme_newbuf(sc, rxd) != 0) {
2446 			ifp->if_iqdrops++;
2447 			/* Reuse buffer. */
2448 			for (; count < nsegs; count++) {
2449 				jme_discard_rxbuf(sc, cons);
2450 				JME_DESC_INC(cons, JME_RX_RING_CNT);
2451 			}
2452 			if (sc->jme_cdata.jme_rxhead != NULL) {
2453 				m_freem(sc->jme_cdata.jme_rxhead);
2454 				JME_RXCHAIN_RESET(sc);
2455 			}
2456 			break;
2457 		}
2458 
2459 		/*
2460 		 * Assume we've received a full sized frame.
2461 		 * Actual size is fixed when we encounter the end of
2462 		 * multi-segmented frame.
2463 		 */
2464 		mp->m_len = MCLBYTES;
2465 
2466 		/* Chain received mbufs. */
2467 		if (sc->jme_cdata.jme_rxhead == NULL) {
2468 			sc->jme_cdata.jme_rxhead = mp;
2469 			sc->jme_cdata.jme_rxtail = mp;
2470 		} else {
2471 			/*
2472 			 * Receive processor can receive a maximum frame
2473 			 * size of 65535 bytes.
2474 			 */
2475 			mp->m_flags &= ~M_PKTHDR;
2476 			sc->jme_cdata.jme_rxtail->m_next = mp;
2477 			sc->jme_cdata.jme_rxtail = mp;
2478 		}
2479 
2480 		if (count == nsegs - 1) {
2481 			/* Last desc. for this frame. */
2482 			m = sc->jme_cdata.jme_rxhead;
2483 			m->m_flags |= M_PKTHDR;
2484 			m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2485 			if (nsegs > 1) {
2486 				/* Set first mbuf size. */
2487 				m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2488 				/* Set last mbuf size. */
2489 				mp->m_len = sc->jme_cdata.jme_rxlen -
2490 				    ((MCLBYTES - JME_RX_PAD_BYTES) +
2491 				    (MCLBYTES * (nsegs - 2)));
2492 			} else
2493 				m->m_len = sc->jme_cdata.jme_rxlen;
2494 			m->m_pkthdr.rcvif = ifp;
2495 
2496 			/*
2497 			 * Account for 10bytes auto padding which is used
2498 			 * to align IP header on 32bit boundary. Also note,
2499 			 * CRC bytes is automatically removed by the
2500 			 * hardware.
2501 			 */
2502 			m->m_data += JME_RX_PAD_BYTES;
2503 
2504 			/* Set checksum information. */
2505 			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2506 			    (flags & JME_RD_IPV4) != 0) {
2507 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2508 				if ((flags & JME_RD_IPCSUM) != 0)
2509 					m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2510 				if (((flags & JME_RD_MORE_FRAG) == 0) &&
2511 				    ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2512 				    (JME_RD_TCP | JME_RD_TCPCSUM) ||
2513 				    (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2514 				    (JME_RD_UDP | JME_RD_UDPCSUM))) {
2515 					m->m_pkthdr.csum_flags |=
2516 					    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2517 					m->m_pkthdr.csum_data = 0xffff;
2518 				}
2519 			}
2520 
2521 			/* Check for VLAN tagged packets. */
2522 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2523 			    (flags & JME_RD_VLAN_TAG) != 0) {
2524 				m->m_pkthdr.ether_vtag =
2525 				    flags & JME_RD_VLAN_MASK;
2526 				m->m_flags |= M_VLANTAG;
2527 			}
2528 
2529 			ifp->if_ipackets++;
2530 			/* Pass it on. */
2531 			(*ifp->if_input)(ifp, m);
2532 
2533 			/* Reset mbuf chains. */
2534 			JME_RXCHAIN_RESET(sc);
2535 		}
2536 	}
2537 
2538 	sc->jme_cdata.jme_rx_cons += nsegs;
2539 	sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2540 }
2541 
2542 static int
2543 jme_rxintr(struct jme_softc *sc, int count)
2544 {
2545 	struct jme_desc *desc;
2546 	int nsegs, prog, pktlen;
2547 
2548 	bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2549 	    sc->jme_cdata.jme_rx_ring_map,
2550 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2551 
2552 	for (prog = 0; count > 0; prog++) {
2553 		desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2554 		if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2555 			break;
2556 		if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2557 			break;
2558 		nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2559 		/*
2560 		 * Check number of segments against received bytes.
2561 		 * Non-matching value would indicate that hardware
2562 		 * is still trying to update Rx descriptors. I'm not
2563 		 * sure whether this check is needed.
2564 		 */
2565 		pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2566 		if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES))
2567 			break;
2568 		prog++;
2569 		/* Received a frame. */
2570 		jme_rxeof(sc);
2571 		count -= nsegs;
2572 	}
2573 
2574 	if (prog > 0)
2575 		bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2576 		    sc->jme_cdata.jme_rx_ring_map,
2577 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2578 
2579 	return (count > 0 ? 0 : EAGAIN);
2580 }
2581 
2582 static void
2583 jme_tick(void *arg)
2584 {
2585 	struct jme_softc *sc;
2586 	struct mii_data *mii;
2587 
2588 	sc = (struct jme_softc *)arg;
2589 
2590 	JME_LOCK_ASSERT(sc);
2591 
2592 	mii = device_get_softc(sc->jme_miibus);
2593 	mii_tick(mii);
2594 	/*
2595 	 * Reclaim Tx buffers that have been completed. It's not
2596 	 * needed here but it would release allocated mbuf chains
2597 	 * faster and limit the maximum delay to a hz.
2598 	 */
2599 	jme_txeof(sc);
2600 	jme_stats_update(sc);
2601 	jme_watchdog(sc);
2602 	callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2603 }
2604 
2605 static void
2606 jme_reset(struct jme_softc *sc)
2607 {
2608 
2609 	/* Stop receiver, transmitter. */
2610 	jme_stop_rx(sc);
2611 	jme_stop_tx(sc);
2612 	CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2613 	DELAY(10);
2614 	CSR_WRITE_4(sc, JME_GHC, 0);
2615 }
2616 
2617 static void
2618 jme_init(void *xsc)
2619 {
2620 	struct jme_softc *sc;
2621 
2622 	sc = (struct jme_softc *)xsc;
2623 	JME_LOCK(sc);
2624 	jme_init_locked(sc);
2625 	JME_UNLOCK(sc);
2626 }
2627 
2628 static void
2629 jme_init_locked(struct jme_softc *sc)
2630 {
2631 	struct ifnet *ifp;
2632 	struct mii_data *mii;
2633 	uint8_t eaddr[ETHER_ADDR_LEN];
2634 	bus_addr_t paddr;
2635 	uint32_t reg;
2636 	int error;
2637 
2638 	JME_LOCK_ASSERT(sc);
2639 
2640 	ifp = sc->jme_ifp;
2641 	mii = device_get_softc(sc->jme_miibus);
2642 
2643 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2644 		return;
2645 	/*
2646 	 * Cancel any pending I/O.
2647 	 */
2648 	jme_stop(sc);
2649 
2650 	/*
2651 	 * Reset the chip to a known state.
2652 	 */
2653 	jme_reset(sc);
2654 
2655 	/* Init descriptors. */
2656 	error = jme_init_rx_ring(sc);
2657         if (error != 0) {
2658                 device_printf(sc->jme_dev,
2659                     "%s: initialization failed: no memory for Rx buffers.\n",
2660 		    __func__);
2661                 jme_stop(sc);
2662 		return;
2663         }
2664 	jme_init_tx_ring(sc);
2665 	/* Initialize shadow status block. */
2666 	jme_init_ssb(sc);
2667 
2668 	/* Reprogram the station address. */
2669 	bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2670 	CSR_WRITE_4(sc, JME_PAR0,
2671 	    eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2672 	CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2673 
2674 	/*
2675 	 * Configure Tx queue.
2676 	 *  Tx priority queue weight value : 0
2677 	 *  Tx FIFO threshold for processing next packet : 16QW
2678 	 *  Maximum Tx DMA length : 512
2679 	 *  Allow Tx DMA burst.
2680 	 */
2681 	sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2682 	sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2683 	sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2684 	sc->jme_txcsr |= sc->jme_tx_dma_size;
2685 	sc->jme_txcsr |= TXCSR_DMA_BURST;
2686 	CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2687 
2688 	/* Set Tx descriptor counter. */
2689 	CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2690 
2691 	/* Set Tx ring address to the hardware. */
2692 	paddr = JME_TX_RING_ADDR(sc, 0);
2693 	CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2694 	CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2695 
2696 	/* Configure TxMAC parameters. */
2697 	reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2698 	reg |= TXMAC_THRESH_1_PKT;
2699 	reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2700 	CSR_WRITE_4(sc, JME_TXMAC, reg);
2701 
2702 	/*
2703 	 * Configure Rx queue.
2704 	 *  FIFO full threshold for transmitting Tx pause packet : 128T
2705 	 *  FIFO threshold for processing next packet : 128QW
2706 	 *  Rx queue 0 select
2707 	 *  Max Rx DMA length : 128
2708 	 *  Rx descriptor retry : 32
2709 	 *  Rx descriptor retry time gap : 256ns
2710 	 *  Don't receive runt/bad frame.
2711 	 */
2712 	sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2713 	/*
2714 	 * Since Rx FIFO size is 4K bytes, receiving frames larger
2715 	 * than 4K bytes will suffer from Rx FIFO overruns. So
2716 	 * decrease FIFO threshold to reduce the FIFO overruns for
2717 	 * frames larger than 4000 bytes.
2718 	 * For best performance of standard MTU sized frames use
2719 	 * maximum allowable FIFO threshold, 128QW. Note these do
2720 	 * not hold on chip full mask verion >=2. For these
2721 	 * controllers 64QW and 128QW are not valid value.
2722 	 */
2723 	if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
2724 		sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2725 	else {
2726 		if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2727 		    ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
2728 			sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2729 		else
2730 			sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2731 	}
2732 	sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2733 	sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2734 	sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2735 	CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2736 
2737 	/* Set Rx descriptor counter. */
2738 	CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2739 
2740 	/* Set Rx ring address to the hardware. */
2741 	paddr = JME_RX_RING_ADDR(sc, 0);
2742 	CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2743 	CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2744 
2745 	/* Clear receive filter. */
2746 	CSR_WRITE_4(sc, JME_RXMAC, 0);
2747 	/* Set up the receive filter. */
2748 	jme_set_filter(sc);
2749 	jme_set_vlan(sc);
2750 
2751 	/*
2752 	 * Disable all WOL bits as WOL can interfere normal Rx
2753 	 * operation. Also clear WOL detection status bits.
2754 	 */
2755 	reg = CSR_READ_4(sc, JME_PMCS);
2756 	reg &= ~PMCS_WOL_ENB_MASK;
2757 	CSR_WRITE_4(sc, JME_PMCS, reg);
2758 
2759 	reg = CSR_READ_4(sc, JME_RXMAC);
2760 	/*
2761 	 * Pad 10bytes right before received frame. This will greatly
2762 	 * help Rx performance on strict-alignment architectures as
2763 	 * it does not need to copy the frame to align the payload.
2764 	 */
2765 	reg |= RXMAC_PAD_10BYTES;
2766 	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2767 		reg |= RXMAC_CSUM_ENB;
2768 	CSR_WRITE_4(sc, JME_RXMAC, reg);
2769 
2770 	/* Configure general purpose reg0 */
2771 	reg = CSR_READ_4(sc, JME_GPREG0);
2772 	reg &= ~GPREG0_PCC_UNIT_MASK;
2773 	/* Set PCC timer resolution to micro-seconds unit. */
2774 	reg |= GPREG0_PCC_UNIT_US;
2775 	/*
2776 	 * Disable all shadow register posting as we have to read
2777 	 * JME_INTR_STATUS register in jme_int_task. Also it seems
2778 	 * that it's hard to synchronize interrupt status between
2779 	 * hardware and software with shadow posting due to
2780 	 * requirements of bus_dmamap_sync(9).
2781 	 */
2782 	reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2783 	    GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2784 	    GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2785 	    GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2786 	/* Disable posting of DW0. */
2787 	reg &= ~GPREG0_POST_DW0_ENB;
2788 	/* Clear PME message. */
2789 	reg &= ~GPREG0_PME_ENB;
2790 	/* Set PHY address. */
2791 	reg &= ~GPREG0_PHY_ADDR_MASK;
2792 	reg |= sc->jme_phyaddr;
2793 	CSR_WRITE_4(sc, JME_GPREG0, reg);
2794 
2795 	/* Configure Tx queue 0 packet completion coalescing. */
2796 	reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2797 	    PCCTX_COAL_TO_MASK;
2798 	reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2799 	    PCCTX_COAL_PKT_MASK;
2800 	reg |= PCCTX_COAL_TXQ0;
2801 	CSR_WRITE_4(sc, JME_PCCTX, reg);
2802 
2803 	/* Configure Rx queue 0 packet completion coalescing. */
2804 	reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2805 	    PCCRX_COAL_TO_MASK;
2806 	reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2807 	    PCCRX_COAL_PKT_MASK;
2808 	CSR_WRITE_4(sc, JME_PCCRX0, reg);
2809 
2810 	/* Configure shadow status block but don't enable posting. */
2811 	paddr = sc->jme_rdata.jme_ssb_block_paddr;
2812 	CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2813 	CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2814 
2815 	/* Disable Timer 1 and Timer 2. */
2816 	CSR_WRITE_4(sc, JME_TIMER1, 0);
2817 	CSR_WRITE_4(sc, JME_TIMER2, 0);
2818 
2819 	/* Configure retry transmit period, retry limit value. */
2820 	CSR_WRITE_4(sc, JME_TXTRHD,
2821 	    ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2822 	    TXTRHD_RT_PERIOD_MASK) |
2823 	    ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2824 	    TXTRHD_RT_LIMIT_SHIFT));
2825 
2826 	/* Disable RSS. */
2827 	CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2828 
2829 	/* Initialize the interrupt mask. */
2830 	CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2831 	CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2832 
2833 	/*
2834 	 * Enabling Tx/Rx DMA engines and Rx queue processing is
2835 	 * done after detection of valid link in jme_link_task.
2836 	 */
2837 
2838 	sc->jme_flags &= ~JME_FLAG_LINK;
2839 	/* Set the current media. */
2840 	mii_mediachg(mii);
2841 
2842 	callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2843 
2844 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2845 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2846 }
2847 
2848 static void
2849 jme_stop(struct jme_softc *sc)
2850 {
2851 	struct ifnet *ifp;
2852 	struct jme_txdesc *txd;
2853 	struct jme_rxdesc *rxd;
2854 	int i;
2855 
2856 	JME_LOCK_ASSERT(sc);
2857 	/*
2858 	 * Mark the interface down and cancel the watchdog timer.
2859 	 */
2860 	ifp = sc->jme_ifp;
2861 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2862 	sc->jme_flags &= ~JME_FLAG_LINK;
2863 	callout_stop(&sc->jme_tick_ch);
2864 	sc->jme_watchdog_timer = 0;
2865 
2866 	/*
2867 	 * Disable interrupts.
2868 	 */
2869 	CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2870 	CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2871 
2872 	/* Disable updating shadow status block. */
2873 	CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2874 	    CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2875 
2876 	/* Stop receiver, transmitter. */
2877 	jme_stop_rx(sc);
2878 	jme_stop_tx(sc);
2879 
2880 	 /* Reclaim Rx/Tx buffers that have been completed. */
2881 	jme_rxintr(sc, JME_RX_RING_CNT);
2882 	if (sc->jme_cdata.jme_rxhead != NULL)
2883 		m_freem(sc->jme_cdata.jme_rxhead);
2884 	JME_RXCHAIN_RESET(sc);
2885 	jme_txeof(sc);
2886 	/*
2887 	 * Free RX and TX mbufs still in the queues.
2888 	 */
2889 	for (i = 0; i < JME_RX_RING_CNT; i++) {
2890 		rxd = &sc->jme_cdata.jme_rxdesc[i];
2891 		if (rxd->rx_m != NULL) {
2892 			bus_dmamap_sync(sc->jme_cdata.jme_rx_tag,
2893 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2894 			bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2895 			    rxd->rx_dmamap);
2896 			m_freem(rxd->rx_m);
2897 			rxd->rx_m = NULL;
2898 		}
2899         }
2900 	for (i = 0; i < JME_TX_RING_CNT; i++) {
2901 		txd = &sc->jme_cdata.jme_txdesc[i];
2902 		if (txd->tx_m != NULL) {
2903 			bus_dmamap_sync(sc->jme_cdata.jme_tx_tag,
2904 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2905 			bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2906 			    txd->tx_dmamap);
2907 			m_freem(txd->tx_m);
2908 			txd->tx_m = NULL;
2909 			txd->tx_ndesc = 0;
2910 		}
2911         }
2912 	jme_stats_update(sc);
2913 	jme_stats_save(sc);
2914 }
2915 
2916 static void
2917 jme_stop_tx(struct jme_softc *sc)
2918 {
2919 	uint32_t reg;
2920 	int i;
2921 
2922 	reg = CSR_READ_4(sc, JME_TXCSR);
2923 	if ((reg & TXCSR_TX_ENB) == 0)
2924 		return;
2925 	reg &= ~TXCSR_TX_ENB;
2926 	CSR_WRITE_4(sc, JME_TXCSR, reg);
2927 	for (i = JME_TIMEOUT; i > 0; i--) {
2928 		DELAY(1);
2929 		if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2930 			break;
2931 	}
2932 	if (i == 0)
2933 		device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2934 }
2935 
2936 static void
2937 jme_stop_rx(struct jme_softc *sc)
2938 {
2939 	uint32_t reg;
2940 	int i;
2941 
2942 	reg = CSR_READ_4(sc, JME_RXCSR);
2943 	if ((reg & RXCSR_RX_ENB) == 0)
2944 		return;
2945 	reg &= ~RXCSR_RX_ENB;
2946 	CSR_WRITE_4(sc, JME_RXCSR, reg);
2947 	for (i = JME_TIMEOUT; i > 0; i--) {
2948 		DELAY(1);
2949 		if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2950 			break;
2951 	}
2952 	if (i == 0)
2953 		device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2954 }
2955 
2956 static void
2957 jme_init_tx_ring(struct jme_softc *sc)
2958 {
2959 	struct jme_ring_data *rd;
2960 	struct jme_txdesc *txd;
2961 	int i;
2962 
2963 	sc->jme_cdata.jme_tx_prod = 0;
2964 	sc->jme_cdata.jme_tx_cons = 0;
2965 	sc->jme_cdata.jme_tx_cnt = 0;
2966 
2967 	rd = &sc->jme_rdata;
2968 	bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
2969 	for (i = 0; i < JME_TX_RING_CNT; i++) {
2970 		txd = &sc->jme_cdata.jme_txdesc[i];
2971 		txd->tx_m = NULL;
2972 		txd->tx_desc = &rd->jme_tx_ring[i];
2973 		txd->tx_ndesc = 0;
2974 	}
2975 
2976 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2977 	    sc->jme_cdata.jme_tx_ring_map,
2978 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2979 }
2980 
2981 static void
2982 jme_init_ssb(struct jme_softc *sc)
2983 {
2984 	struct jme_ring_data *rd;
2985 
2986 	rd = &sc->jme_rdata;
2987 	bzero(rd->jme_ssb_block, JME_SSB_SIZE);
2988 	bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
2989 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2990 }
2991 
2992 static int
2993 jme_init_rx_ring(struct jme_softc *sc)
2994 {
2995 	struct jme_ring_data *rd;
2996 	struct jme_rxdesc *rxd;
2997 	int i;
2998 
2999 	sc->jme_cdata.jme_rx_cons = 0;
3000 	JME_RXCHAIN_RESET(sc);
3001 	atomic_set_int(&sc->jme_morework, 0);
3002 
3003 	rd = &sc->jme_rdata;
3004 	bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
3005 	for (i = 0; i < JME_RX_RING_CNT; i++) {
3006 		rxd = &sc->jme_cdata.jme_rxdesc[i];
3007 		rxd->rx_m = NULL;
3008 		rxd->rx_desc = &rd->jme_rx_ring[i];
3009 		if (jme_newbuf(sc, rxd) != 0)
3010 			return (ENOBUFS);
3011 	}
3012 
3013 	bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
3014 	    sc->jme_cdata.jme_rx_ring_map,
3015 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3016 
3017 	return (0);
3018 }
3019 
3020 static int
3021 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd)
3022 {
3023 	struct jme_desc *desc;
3024 	struct mbuf *m;
3025 	bus_dma_segment_t segs[1];
3026 	bus_dmamap_t map;
3027 	int nsegs;
3028 
3029 	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3030 	if (m == NULL)
3031 		return (ENOBUFS);
3032 	/*
3033 	 * JMC250 has 64bit boundary alignment limitation so jme(4)
3034 	 * takes advantage of 10 bytes padding feature of hardware
3035 	 * in order not to copy entire frame to align IP header on
3036 	 * 32bit boundary.
3037 	 */
3038 	m->m_len = m->m_pkthdr.len = MCLBYTES;
3039 
3040 	if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag,
3041 	    sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3042 		m_freem(m);
3043 		return (ENOBUFS);
3044 	}
3045 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3046 
3047 	if (rxd->rx_m != NULL) {
3048 		bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3049 		    BUS_DMASYNC_POSTREAD);
3050 		bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
3051 	}
3052 	map = rxd->rx_dmamap;
3053 	rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
3054 	sc->jme_cdata.jme_rx_sparemap = map;
3055 	bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3056 	    BUS_DMASYNC_PREREAD);
3057 	rxd->rx_m = m;
3058 
3059 	desc = rxd->rx_desc;
3060 	desc->buflen = htole32(segs[0].ds_len);
3061 	desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr));
3062 	desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr));
3063 	desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
3064 
3065 	return (0);
3066 }
3067 
3068 static void
3069 jme_set_vlan(struct jme_softc *sc)
3070 {
3071 	struct ifnet *ifp;
3072 	uint32_t reg;
3073 
3074 	JME_LOCK_ASSERT(sc);
3075 
3076 	ifp = sc->jme_ifp;
3077 	reg = CSR_READ_4(sc, JME_RXMAC);
3078 	reg &= ~RXMAC_VLAN_ENB;
3079 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3080 		reg |= RXMAC_VLAN_ENB;
3081 	CSR_WRITE_4(sc, JME_RXMAC, reg);
3082 }
3083 
3084 static void
3085 jme_set_filter(struct jme_softc *sc)
3086 {
3087 	struct ifnet *ifp;
3088 	struct ifmultiaddr *ifma;
3089 	uint32_t crc;
3090 	uint32_t mchash[2];
3091 	uint32_t rxcfg;
3092 
3093 	JME_LOCK_ASSERT(sc);
3094 
3095 	ifp = sc->jme_ifp;
3096 
3097 	rxcfg = CSR_READ_4(sc, JME_RXMAC);
3098 	rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3099 	    RXMAC_ALLMULTI);
3100 	/* Always accept frames destined to our station address. */
3101 	rxcfg |= RXMAC_UNICAST;
3102 	if ((ifp->if_flags & IFF_BROADCAST) != 0)
3103 		rxcfg |= RXMAC_BROADCAST;
3104 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3105 		if ((ifp->if_flags & IFF_PROMISC) != 0)
3106 			rxcfg |= RXMAC_PROMISC;
3107 		if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3108 			rxcfg |= RXMAC_ALLMULTI;
3109 		CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3110 		CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3111 		CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3112 		return;
3113 	}
3114 
3115 	/*
3116 	 * Set up the multicast address filter by passing all multicast
3117 	 * addresses through a CRC generator, and then using the low-order
3118 	 * 6 bits as an index into the 64 bit multicast hash table.  The
3119 	 * high order bits select the register, while the rest of the bits
3120 	 * select the bit within the register.
3121 	 */
3122 	rxcfg |= RXMAC_MULTICAST;
3123 	bzero(mchash, sizeof(mchash));
3124 
3125 	if_maddr_rlock(ifp);
3126 	TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) {
3127 		if (ifma->ifma_addr->sa_family != AF_LINK)
3128 			continue;
3129 		crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3130 		    ifma->ifma_addr), ETHER_ADDR_LEN);
3131 
3132 		/* Just want the 6 least significant bits. */
3133 		crc &= 0x3f;
3134 
3135 		/* Set the corresponding bit in the hash table. */
3136 		mchash[crc >> 5] |= 1 << (crc & 0x1f);
3137 	}
3138 	if_maddr_runlock(ifp);
3139 
3140 	CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3141 	CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3142 	CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3143 }
3144 
3145 static void
3146 jme_stats_clear(struct jme_softc *sc)
3147 {
3148 
3149 	JME_LOCK_ASSERT(sc);
3150 
3151 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3152 		return;
3153 
3154 	/* Disable and clear counters. */
3155 	CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3156 	/* Activate hw counters. */
3157 	CSR_WRITE_4(sc, JME_STATCSR, 0);
3158 	CSR_READ_4(sc, JME_STATCSR);
3159 	bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
3160 }
3161 
3162 static void
3163 jme_stats_save(struct jme_softc *sc)
3164 {
3165 
3166 	JME_LOCK_ASSERT(sc);
3167 
3168 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3169 		return;
3170 	/* Save current counters. */
3171 	bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
3172 	/* Disable and clear counters. */
3173 	CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3174 }
3175 
3176 static void
3177 jme_stats_update(struct jme_softc *sc)
3178 {
3179 	struct jme_hw_stats *stat, *ostat;
3180 	uint32_t reg;
3181 
3182 	JME_LOCK_ASSERT(sc);
3183 
3184 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3185 		return;
3186 	stat = &sc->jme_stats;
3187 	ostat = &sc->jme_ostats;
3188 	stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
3189 	stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
3190 	reg = CSR_READ_4(sc, JME_STAT_CRCMII);
3191 	stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
3192 	    STAT_RX_CRC_ERR_SHIFT;
3193 	stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
3194 	    STAT_RX_MII_ERR_SHIFT;
3195 	reg = CSR_READ_4(sc, JME_STAT_RXERR);
3196 	stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
3197 	    STAT_RXERR_OFLOW_SHIFT;
3198 	stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
3199 	    STAT_RXERR_MPTY_SHIFT;
3200 	reg = CSR_READ_4(sc, JME_STAT_FAIL);
3201 	stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
3202 	stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
3203 
3204 	/* Account for previous counters. */
3205 	stat->rx_good_frames += ostat->rx_good_frames;
3206 	stat->rx_crc_errs += ostat->rx_crc_errs;
3207 	stat->rx_mii_errs += ostat->rx_mii_errs;
3208 	stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3209 	stat->rx_desc_empty += ostat->rx_desc_empty;
3210 	stat->rx_bad_frames += ostat->rx_bad_frames;
3211 	stat->tx_good_frames += ostat->tx_good_frames;
3212 	stat->tx_bad_frames += ostat->tx_bad_frames;
3213 }
3214 
3215 static int
3216 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3217 {
3218 	int error, value;
3219 
3220 	if (arg1 == NULL)
3221 		return (EINVAL);
3222 	value = *(int *)arg1;
3223 	error = sysctl_handle_int(oidp, &value, 0, req);
3224 	if (error || req->newptr == NULL)
3225 		return (error);
3226 	if (value < low || value > high)
3227 		return (EINVAL);
3228         *(int *)arg1 = value;
3229 
3230         return (0);
3231 }
3232 
3233 static int
3234 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
3235 {
3236 	return (sysctl_int_range(oidp, arg1, arg2, req,
3237 	    PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
3238 }
3239 
3240 static int
3241 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3242 {
3243 	return (sysctl_int_range(oidp, arg1, arg2, req,
3244 	    PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
3245 }
3246 
3247 static int
3248 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
3249 {
3250 	return (sysctl_int_range(oidp, arg1, arg2, req,
3251 	    PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
3252 }
3253 
3254 static int
3255 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3256 {
3257 	return (sysctl_int_range(oidp, arg1, arg2, req,
3258 	    PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));
3259 }
3260 
3261 static int
3262 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)
3263 {
3264 	return (sysctl_int_range(oidp, arg1, arg2, req,
3265 	    JME_PROC_MIN, JME_PROC_MAX));
3266 }
3267