xref: /freebsd/sys/dev/jme/if_jme.c (revision 10b9d77bf1ccf2f3affafa6261692cb92cf7e992)
1 /*-
2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/mbuf.h>
38 #include <sys/rman.h>
39 #include <sys/module.h>
40 #include <sys/proc.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46 
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_vlan_var.h>
55 
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/ip.h>
59 #include <netinet/tcp.h>
60 
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
63 
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66 
67 #include <machine/bus.h>
68 #include <machine/in_cksum.h>
69 
70 #include <dev/jme/if_jmereg.h>
71 #include <dev/jme/if_jmevar.h>
72 
73 /* "device miibus" required.  See GENERIC if you get errors here. */
74 #include "miibus_if.h"
75 
76 /* Define the following to disable printing Rx errors. */
77 #undef	JME_SHOW_ERRORS
78 
79 #define	JME_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
80 
81 MODULE_DEPEND(jme, pci, 1, 1, 1);
82 MODULE_DEPEND(jme, ether, 1, 1, 1);
83 MODULE_DEPEND(jme, miibus, 1, 1, 1);
84 
85 /* Tunables. */
86 static int msi_disable = 0;
87 static int msix_disable = 0;
88 TUNABLE_INT("hw.jme.msi_disable", &msi_disable);
89 TUNABLE_INT("hw.jme.msix_disable", &msix_disable);
90 
91 /*
92  * Devices supported by this driver.
93  */
94 static struct jme_dev {
95 	uint16_t	jme_vendorid;
96 	uint16_t	jme_deviceid;
97 	const char	*jme_name;
98 } jme_devs[] = {
99 	{ VENDORID_JMICRON, DEVICEID_JMC250,
100 	    "JMicron Inc, JMC25x Gigabit Ethernet" },
101 	{ VENDORID_JMICRON, DEVICEID_JMC260,
102 	    "JMicron Inc, JMC26x Fast Ethernet" },
103 };
104 
105 static int jme_miibus_readreg(device_t, int, int);
106 static int jme_miibus_writereg(device_t, int, int, int);
107 static void jme_miibus_statchg(device_t);
108 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
109 static int jme_mediachange(struct ifnet *);
110 static int jme_probe(device_t);
111 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
112 static int jme_eeprom_macaddr(struct jme_softc *);
113 static int jme_efuse_macaddr(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *);
115 static void jme_set_macaddr(struct jme_softc *, uint8_t *);
116 static void jme_map_intr_vector(struct jme_softc *);
117 static int jme_attach(device_t);
118 static int jme_detach(device_t);
119 static void jme_sysctl_node(struct jme_softc *);
120 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
121 static int jme_dma_alloc(struct jme_softc *);
122 static void jme_dma_free(struct jme_softc *);
123 static int jme_shutdown(device_t);
124 static void jme_setlinkspeed(struct jme_softc *);
125 static void jme_setwol(struct jme_softc *);
126 static int jme_suspend(device_t);
127 static int jme_resume(device_t);
128 static int jme_encap(struct jme_softc *, struct mbuf **);
129 static void jme_start(struct ifnet *);
130 static void jme_start_locked(struct ifnet *);
131 static void jme_watchdog(struct jme_softc *);
132 static int jme_ioctl(struct ifnet *, u_long, caddr_t);
133 static void jme_mac_config(struct jme_softc *);
134 static void jme_link_task(void *, int);
135 static int jme_intr(void *);
136 static void jme_int_task(void *, int);
137 static void jme_txeof(struct jme_softc *);
138 static __inline void jme_discard_rxbuf(struct jme_softc *, int);
139 static void jme_rxeof(struct jme_softc *);
140 static int jme_rxintr(struct jme_softc *, int);
141 static void jme_tick(void *);
142 static void jme_reset(struct jme_softc *);
143 static void jme_init(void *);
144 static void jme_init_locked(struct jme_softc *);
145 static void jme_stop(struct jme_softc *);
146 static void jme_stop_tx(struct jme_softc *);
147 static void jme_stop_rx(struct jme_softc *);
148 static int jme_init_rx_ring(struct jme_softc *);
149 static void jme_init_tx_ring(struct jme_softc *);
150 static void jme_init_ssb(struct jme_softc *);
151 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
152 static void jme_set_vlan(struct jme_softc *);
153 static void jme_set_filter(struct jme_softc *);
154 static void jme_stats_clear(struct jme_softc *);
155 static void jme_stats_save(struct jme_softc *);
156 static void jme_stats_update(struct jme_softc *);
157 static void jme_phy_down(struct jme_softc *);
158 static void jme_phy_up(struct jme_softc *);
159 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
160 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
161 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
162 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
163 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
164 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
165 
166 
167 static device_method_t jme_methods[] = {
168 	/* Device interface. */
169 	DEVMETHOD(device_probe,		jme_probe),
170 	DEVMETHOD(device_attach,	jme_attach),
171 	DEVMETHOD(device_detach,	jme_detach),
172 	DEVMETHOD(device_shutdown,	jme_shutdown),
173 	DEVMETHOD(device_suspend,	jme_suspend),
174 	DEVMETHOD(device_resume,	jme_resume),
175 
176 	/* MII interface. */
177 	DEVMETHOD(miibus_readreg,	jme_miibus_readreg),
178 	DEVMETHOD(miibus_writereg,	jme_miibus_writereg),
179 	DEVMETHOD(miibus_statchg,	jme_miibus_statchg),
180 
181 	{ NULL, NULL }
182 };
183 
184 static driver_t jme_driver = {
185 	"jme",
186 	jme_methods,
187 	sizeof(struct jme_softc)
188 };
189 
190 static devclass_t jme_devclass;
191 
192 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0);
193 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
194 
195 static struct resource_spec jme_res_spec_mem[] = {
196 	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
197 	{ -1,			0,		0 }
198 };
199 
200 static struct resource_spec jme_irq_spec_legacy[] = {
201 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
202 	{ -1,			0,		0 }
203 };
204 
205 static struct resource_spec jme_irq_spec_msi[] = {
206 	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
207 	{ -1,			0,		0 }
208 };
209 
210 /*
211  *	Read a PHY register on the MII of the JMC250.
212  */
213 static int
214 jme_miibus_readreg(device_t dev, int phy, int reg)
215 {
216 	struct jme_softc *sc;
217 	uint32_t val;
218 	int i;
219 
220 	sc = device_get_softc(dev);
221 
222 	/* For FPGA version, PHY address 0 should be ignored. */
223 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
224 		return (0);
225 
226 	CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
227 	    SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
228 	for (i = JME_PHY_TIMEOUT; i > 0; i--) {
229 		DELAY(1);
230 		if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
231 			break;
232 	}
233 
234 	if (i == 0) {
235 		device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
236 		return (0);
237 	}
238 
239 	return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
240 }
241 
242 /*
243  *	Write a PHY register on the MII of the JMC250.
244  */
245 static int
246 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
247 {
248 	struct jme_softc *sc;
249 	int i;
250 
251 	sc = device_get_softc(dev);
252 
253 	/* For FPGA version, PHY address 0 should be ignored. */
254 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
255 		return (0);
256 
257 	CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
258 	    ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
259 	    SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
260 	for (i = JME_PHY_TIMEOUT; i > 0; i--) {
261 		DELAY(1);
262 		if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
263 			break;
264 	}
265 
266 	if (i == 0)
267 		device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
268 
269 	return (0);
270 }
271 
272 /*
273  *	Callback from MII layer when media changes.
274  */
275 static void
276 jme_miibus_statchg(device_t dev)
277 {
278 	struct jme_softc *sc;
279 
280 	sc = device_get_softc(dev);
281 	taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task);
282 }
283 
284 /*
285  *	Get the current interface media status.
286  */
287 static void
288 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
289 {
290 	struct jme_softc *sc;
291 	struct mii_data *mii;
292 
293 	sc = ifp->if_softc;
294 	JME_LOCK(sc);
295 	if ((ifp->if_flags & IFF_UP) == 0) {
296 		JME_UNLOCK(sc);
297 		return;
298 	}
299 	mii = device_get_softc(sc->jme_miibus);
300 
301 	mii_pollstat(mii);
302 	ifmr->ifm_status = mii->mii_media_status;
303 	ifmr->ifm_active = mii->mii_media_active;
304 	JME_UNLOCK(sc);
305 }
306 
307 /*
308  *	Set hardware to newly-selected media.
309  */
310 static int
311 jme_mediachange(struct ifnet *ifp)
312 {
313 	struct jme_softc *sc;
314 	struct mii_data *mii;
315 	struct mii_softc *miisc;
316 	int error;
317 
318 	sc = ifp->if_softc;
319 	JME_LOCK(sc);
320 	mii = device_get_softc(sc->jme_miibus);
321 	if (mii->mii_instance != 0) {
322 		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
323 			mii_phy_reset(miisc);
324 	}
325 	error = mii_mediachg(mii);
326 	JME_UNLOCK(sc);
327 
328 	return (error);
329 }
330 
331 static int
332 jme_probe(device_t dev)
333 {
334 	struct jme_dev *sp;
335 	int i;
336 	uint16_t vendor, devid;
337 
338 	vendor = pci_get_vendor(dev);
339 	devid = pci_get_device(dev);
340 	sp = jme_devs;
341 	for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]);
342 	    i++, sp++) {
343 		if (vendor == sp->jme_vendorid &&
344 		    devid == sp->jme_deviceid) {
345 			device_set_desc(dev, sp->jme_name);
346 			return (BUS_PROBE_DEFAULT);
347 		}
348 	}
349 
350 	return (ENXIO);
351 }
352 
353 static int
354 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
355 {
356 	uint32_t reg;
357 	int i;
358 
359 	*val = 0;
360 	for (i = JME_TIMEOUT; i > 0; i--) {
361 		reg = CSR_READ_4(sc, JME_SMBCSR);
362 		if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
363 			break;
364 		DELAY(1);
365 	}
366 
367 	if (i == 0) {
368 		device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
369 		return (ETIMEDOUT);
370 	}
371 
372 	reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
373 	CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
374 	for (i = JME_TIMEOUT; i > 0; i--) {
375 		DELAY(1);
376 		reg = CSR_READ_4(sc, JME_SMBINTF);
377 		if ((reg & SMBINTF_CMD_TRIGGER) == 0)
378 			break;
379 	}
380 
381 	if (i == 0) {
382 		device_printf(sc->jme_dev, "EEPROM read timeout!\n");
383 		return (ETIMEDOUT);
384 	}
385 
386 	reg = CSR_READ_4(sc, JME_SMBINTF);
387 	*val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
388 
389 	return (0);
390 }
391 
392 static int
393 jme_eeprom_macaddr(struct jme_softc *sc)
394 {
395 	uint8_t eaddr[ETHER_ADDR_LEN];
396 	uint8_t fup, reg, val;
397 	uint32_t offset;
398 	int match;
399 
400 	offset = 0;
401 	if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
402 	    fup != JME_EEPROM_SIG0)
403 		return (ENOENT);
404 	if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
405 	    fup != JME_EEPROM_SIG1)
406 		return (ENOENT);
407 	match = 0;
408 	do {
409 		if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
410 			break;
411 		if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
412 		    (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
413 			if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
414 				break;
415 			if (reg >= JME_PAR0 &&
416 			    reg < JME_PAR0 + ETHER_ADDR_LEN) {
417 				if (jme_eeprom_read_byte(sc, offset + 2,
418 				    &val) != 0)
419 					break;
420 				eaddr[reg - JME_PAR0] = val;
421 				match++;
422 			}
423 		}
424 		/* Check for the end of EEPROM descriptor. */
425 		if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
426 			break;
427 		/* Try next eeprom descriptor. */
428 		offset += JME_EEPROM_DESC_BYTES;
429 	} while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
430 
431 	if (match == ETHER_ADDR_LEN) {
432 		bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
433 		return (0);
434 	}
435 
436 	return (ENOENT);
437 }
438 
439 static int
440 jme_efuse_macaddr(struct jme_softc *sc)
441 {
442 	uint32_t reg;
443 	int i;
444 
445 	reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
446 	if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) !=
447 	    EFUSE_CTL1_AUTOLAOD_DONE)
448 		return (ENOENT);
449 	/* Reset eFuse controller. */
450 	reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
451 	reg |= EFUSE_CTL2_RESET;
452 	pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
453 	reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
454 	reg &= ~EFUSE_CTL2_RESET;
455 	pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
456 
457 	/* Have eFuse reload station address to MAC controller. */
458 	reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
459 	reg &= ~EFUSE_CTL1_CMD_MASK;
460 	reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE;
461 	pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4);
462 
463 	/*
464 	 * Verify completion of eFuse autload command.  It should be
465 	 * completed within 108us.
466 	 */
467 	DELAY(110);
468 	for (i = 10; i > 0; i--) {
469 		reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
470 		if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR |
471 		    EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) {
472 			DELAY(20);
473 			continue;
474 		}
475 		if ((reg & EFUSE_CTL1_EXECUTE) == 0)
476 			break;
477 		/* Station address loading is still in progress. */
478 		DELAY(20);
479 	}
480 	if (i == 0) {
481 		device_printf(sc->jme_dev, "eFuse autoload timed out.\n");
482 		return (ETIMEDOUT);
483 	}
484 
485 	return (0);
486 }
487 
488 static void
489 jme_reg_macaddr(struct jme_softc *sc)
490 {
491 	uint32_t par0, par1;
492 
493 	/* Read station address. */
494 	par0 = CSR_READ_4(sc, JME_PAR0);
495 	par1 = CSR_READ_4(sc, JME_PAR1);
496 	par1 &= 0xFFFF;
497 	if ((par0 == 0 && par1 == 0) ||
498 	    (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
499 		device_printf(sc->jme_dev,
500 		    "Failed to retrieve Ethernet address.\n");
501 	} else {
502 		/*
503 		 * For controllers that use eFuse, the station address
504 		 * could also be extracted from JME_PCI_PAR0 and
505 		 * JME_PCI_PAR1 registers in PCI configuration space.
506 		 * Each register holds exactly half of station address(24bits)
507 		 * so use JME_PAR0, JME_PAR1 registers instead.
508 		 */
509 		sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
510 		sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
511 		sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
512 		sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
513 		sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
514 		sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
515 	}
516 }
517 
518 static void
519 jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr)
520 {
521 	uint32_t val;
522 	int i;
523 
524 	if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
525 		/*
526 		 * Avoid reprogramming station address if the address
527 		 * is the same as previous one.  Note, reprogrammed
528 		 * station address is permanent as if it was written
529 		 * to EEPROM. So if station address was changed by
530 		 * admistrator it's possible to lose factory configured
531 		 * address when driver fails to restore its address.
532 		 * (e.g. reboot or system crash)
533 		 */
534 		if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) {
535 			for (i = 0; i < ETHER_ADDR_LEN; i++) {
536 				val = JME_EFUSE_EEPROM_FUNC0 <<
537 				    JME_EFUSE_EEPROM_FUNC_SHIFT;
538 				val |= JME_EFUSE_EEPROM_PAGE_BAR1 <<
539 				    JME_EFUSE_EEPROM_PAGE_SHIFT;
540 				val |= (JME_PAR0 + i) <<
541 				    JME_EFUSE_EEPROM_ADDR_SHIFT;
542 				val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT;
543 				pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM,
544 				    val | JME_EFUSE_EEPROM_WRITE, 4);
545 			}
546 		}
547 	} else {
548 		CSR_WRITE_4(sc, JME_PAR0,
549 		    eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
550 		CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
551 	}
552 }
553 
554 static void
555 jme_map_intr_vector(struct jme_softc *sc)
556 {
557 	uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
558 
559 	bzero(map, sizeof(map));
560 
561 	/* Map Tx interrupts source to MSI/MSIX vector 2. */
562 	map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
563 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
564 	map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
565 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
566 	map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |=
567 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP);
568 	map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |=
569 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP);
570 	map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
571 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP);
572 	map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
573 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP);
574 	map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |=
575 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP);
576 	map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |=
577 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP);
578 	map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |=
579 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL);
580 	map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |=
581 	    MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
582 
583 	/* Map Rx interrupts source to MSI/MSIX vector 1. */
584 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
585 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
586 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
587 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
588 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
589 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
590 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
591 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
592 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
593 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
594 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
595 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
596 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
597 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
598 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
599 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
600 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
601 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
602 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
603 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
604 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
605 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
606 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
607 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
608 	map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
609 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
610 	map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
611 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
612 	map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
613 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
614 	map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
615 	    MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
616 
617 	/* Map all other interrupts source to MSI/MSIX vector 0. */
618 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);
619 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);
620 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);
621 	CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);
622 }
623 
624 static int
625 jme_attach(device_t dev)
626 {
627 	struct jme_softc *sc;
628 	struct ifnet *ifp;
629 	struct mii_softc *miisc;
630 	struct mii_data *mii;
631 	uint32_t reg;
632 	uint16_t burst;
633 	int error, i, mii_flags, msic, msixc, pmc;
634 
635 	error = 0;
636 	sc = device_get_softc(dev);
637 	sc->jme_dev = dev;
638 
639 	mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
640 	    MTX_DEF);
641 	callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);
642 	TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc);
643 	TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc);
644 
645 	/*
646 	 * Map the device. JMC250 supports both memory mapped and I/O
647 	 * register space access. Because I/O register access should
648 	 * use different BARs to access registers it's waste of time
649 	 * to use I/O register spce access. JMC250 uses 16K to map
650 	 * entire memory space.
651 	 */
652 	pci_enable_busmaster(dev);
653 	sc->jme_res_spec = jme_res_spec_mem;
654 	sc->jme_irq_spec = jme_irq_spec_legacy;
655 	error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res);
656 	if (error != 0) {
657 		device_printf(dev, "cannot allocate memory resources.\n");
658 		goto fail;
659 	}
660 
661 	/* Allocate IRQ resources. */
662 	msixc = pci_msix_count(dev);
663 	msic = pci_msi_count(dev);
664 	if (bootverbose) {
665 		device_printf(dev, "MSIX count : %d\n", msixc);
666 		device_printf(dev, "MSI count : %d\n", msic);
667 	}
668 
669 	/* Use 1 MSI/MSI-X. */
670 	if (msixc > 1)
671 		msixc = 1;
672 	if (msic > 1)
673 		msic = 1;
674 	/* Prefer MSIX over MSI. */
675 	if (msix_disable == 0 || msi_disable == 0) {
676 		if (msix_disable == 0 && msixc > 0 &&
677 		    pci_alloc_msix(dev, &msixc) == 0) {
678 			if (msixc == 1) {
679 				device_printf(dev, "Using %d MSIX messages.\n",
680 				    msixc);
681 				sc->jme_flags |= JME_FLAG_MSIX;
682 				sc->jme_irq_spec = jme_irq_spec_msi;
683 			} else
684 				pci_release_msi(dev);
685 		}
686 		if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
687 		    msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
688 			if (msic == 1) {
689 				device_printf(dev, "Using %d MSI messages.\n",
690 				    msic);
691 				sc->jme_flags |= JME_FLAG_MSI;
692 				sc->jme_irq_spec = jme_irq_spec_msi;
693 			} else
694 				pci_release_msi(dev);
695 		}
696 		/* Map interrupt vector 0, 1 and 2. */
697 		if ((sc->jme_flags & JME_FLAG_MSI) != 0 ||
698 		    (sc->jme_flags & JME_FLAG_MSIX) != 0)
699 			jme_map_intr_vector(sc);
700 	}
701 
702 	error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq);
703 	if (error != 0) {
704 		device_printf(dev, "cannot allocate IRQ resources.\n");
705 		goto fail;
706 	}
707 
708 	sc->jme_rev = pci_get_device(dev);
709 	if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) {
710 		sc->jme_flags |= JME_FLAG_FASTETH;
711 		sc->jme_flags |= JME_FLAG_NOJUMBO;
712 	}
713 	reg = CSR_READ_4(sc, JME_CHIPMODE);
714 	sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
715 	if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
716 	    CHIPMODE_NOT_FPGA)
717 		sc->jme_flags |= JME_FLAG_FPGA;
718 	if (bootverbose) {
719 		device_printf(dev, "PCI device revision : 0x%04x\n",
720 		    sc->jme_rev);
721 		device_printf(dev, "Chip revision : 0x%02x\n",
722 		    sc->jme_chip_rev);
723 		if ((sc->jme_flags & JME_FLAG_FPGA) != 0)
724 			device_printf(dev, "FPGA revision : 0x%04x\n",
725 			    (reg & CHIPMODE_FPGA_REV_MASK) >>
726 			    CHIPMODE_FPGA_REV_SHIFT);
727 	}
728 	if (sc->jme_chip_rev == 0xFF) {
729 		device_printf(dev, "Unknown chip revision : 0x%02x\n",
730 		    sc->jme_rev);
731 		error = ENXIO;
732 		goto fail;
733 	}
734 
735 	/* Identify controller features and bugs. */
736 	if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
737 		if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
738 		    CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
739 			sc->jme_flags |= JME_FLAG_DMA32BIT;
740 		if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
741 			sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD;
742 		sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK;
743 		sc->jme_flags |= JME_FLAG_HWMIB;
744 	}
745 
746 	/* Reset the ethernet controller. */
747 	jme_reset(sc);
748 
749 	/* Get station address. */
750 	if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
751 		error = jme_efuse_macaddr(sc);
752 		if (error == 0)
753 			jme_reg_macaddr(sc);
754 	} else {
755 		error = ENOENT;
756 		reg = CSR_READ_4(sc, JME_SMBCSR);
757 		if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
758 			error = jme_eeprom_macaddr(sc);
759 		if (error != 0 && bootverbose)
760 			device_printf(sc->jme_dev,
761 			    "ethernet hardware address not found in EEPROM.\n");
762 		if (error != 0)
763 			jme_reg_macaddr(sc);
764 	}
765 
766 	/*
767 	 * Save PHY address.
768 	 * Integrated JR0211 has fixed PHY address whereas FPGA version
769 	 * requires PHY probing to get correct PHY address.
770 	 */
771 	if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
772 		sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
773 		    GPREG0_PHY_ADDR_MASK;
774 		if (bootverbose)
775 			device_printf(dev, "PHY is at address %d.\n",
776 			    sc->jme_phyaddr);
777 	} else
778 		sc->jme_phyaddr = 0;
779 
780 	/* Set max allowable DMA size. */
781 	if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
782 		sc->jme_flags |= JME_FLAG_PCIE;
783 		burst = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2);
784 		if (bootverbose) {
785 			device_printf(dev, "Read request size : %d bytes.\n",
786 			    128 << ((burst >> 12) & 0x07));
787 			device_printf(dev, "TLP payload size : %d bytes.\n",
788 			    128 << ((burst >> 5) & 0x07));
789 		}
790 		switch ((burst >> 12) & 0x07) {
791 		case 0:
792 			sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
793 			break;
794 		case 1:
795 			sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
796 			break;
797 		default:
798 			sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
799 			break;
800 		}
801 		sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
802 	} else {
803 		sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
804 		sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
805 	}
806 	/* Create coalescing sysctl node. */
807 	jme_sysctl_node(sc);
808 	if ((error = jme_dma_alloc(sc) != 0))
809 		goto fail;
810 
811 	ifp = sc->jme_ifp = if_alloc(IFT_ETHER);
812 	if (ifp == NULL) {
813 		device_printf(dev, "cannot allocate ifnet structure.\n");
814 		error = ENXIO;
815 		goto fail;
816 	}
817 
818 	ifp->if_softc = sc;
819 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
820 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
821 	ifp->if_ioctl = jme_ioctl;
822 	ifp->if_start = jme_start;
823 	ifp->if_init = jme_init;
824 	ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1;
825 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
826 	IFQ_SET_READY(&ifp->if_snd);
827 	/* JMC250 supports Tx/Rx checksum offload as well as TSO. */
828 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
829 	ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
830 	if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
831 		sc->jme_flags |= JME_FLAG_PMCAP;
832 		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
833 	}
834 	ifp->if_capenable = ifp->if_capabilities;
835 
836 	/* Wakeup PHY. */
837 	jme_phy_up(sc);
838 	mii_flags = MIIF_DOPAUSE;
839 	/* Ask PHY calibration to PHY driver. */
840 	if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
841 		mii_flags |= MIIF_MACPRIV0;
842 	/* Set up MII bus. */
843 	error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
844 	    jme_mediastatus, BMSR_DEFCAPMASK,
845 	    sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr,
846 	    MII_OFFSET_ANY, mii_flags);
847 	if (error != 0) {
848 		device_printf(dev, "attaching PHYs failed\n");
849 		goto fail;
850 	}
851 
852 	/*
853 	 * Force PHY to FPGA mode.
854 	 */
855 	if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
856 		mii = device_get_softc(sc->jme_miibus);
857 		if (mii->mii_instance != 0) {
858 			LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
859 				if (miisc->mii_phy != 0) {
860 					sc->jme_phyaddr = miisc->mii_phy;
861 					break;
862 				}
863 			}
864 			if (sc->jme_phyaddr != 0) {
865 				device_printf(sc->jme_dev,
866 				    "FPGA PHY is at %d\n", sc->jme_phyaddr);
867 				/* vendor magic. */
868 				jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
869 				    0x0004);
870 			}
871 		}
872 	}
873 
874 	ether_ifattach(ifp, sc->jme_eaddr);
875 
876 	/* VLAN capability setup */
877 	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
878 	    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
879 	ifp->if_capenable = ifp->if_capabilities;
880 
881 	/* Tell the upper layer(s) we support long frames. */
882 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
883 
884 	/* Create local taskq. */
885 	sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK,
886 	    taskqueue_thread_enqueue, &sc->jme_tq);
887 	if (sc->jme_tq == NULL) {
888 		device_printf(dev, "could not create taskqueue.\n");
889 		ether_ifdetach(ifp);
890 		error = ENXIO;
891 		goto fail;
892 	}
893 	taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
894 	    device_get_nameunit(sc->jme_dev));
895 
896 	for (i = 0; i < 1; i++) {
897 		error = bus_setup_intr(dev, sc->jme_irq[i],
898 		    INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
899 		    &sc->jme_intrhand[i]);
900 		if (error != 0)
901 			break;
902 	}
903 
904 	if (error != 0) {
905 		device_printf(dev, "could not set up interrupt handler.\n");
906 		taskqueue_free(sc->jme_tq);
907 		sc->jme_tq = NULL;
908 		ether_ifdetach(ifp);
909 		goto fail;
910 	}
911 
912 fail:
913 	if (error != 0)
914 		jme_detach(dev);
915 
916 	return (error);
917 }
918 
919 static int
920 jme_detach(device_t dev)
921 {
922 	struct jme_softc *sc;
923 	struct ifnet *ifp;
924 	int i;
925 
926 	sc = device_get_softc(dev);
927 
928 	ifp = sc->jme_ifp;
929 	if (device_is_attached(dev)) {
930 		JME_LOCK(sc);
931 		sc->jme_flags |= JME_FLAG_DETACH;
932 		jme_stop(sc);
933 		JME_UNLOCK(sc);
934 		callout_drain(&sc->jme_tick_ch);
935 		taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
936 		taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
937 		/* Restore possibly modified station address. */
938 		if ((sc->jme_flags & JME_FLAG_EFUSE) != 0)
939 			jme_set_macaddr(sc, sc->jme_eaddr);
940 		ether_ifdetach(ifp);
941 	}
942 
943 	if (sc->jme_tq != NULL) {
944 		taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
945 		taskqueue_free(sc->jme_tq);
946 		sc->jme_tq = NULL;
947 	}
948 
949 	if (sc->jme_miibus != NULL) {
950 		device_delete_child(dev, sc->jme_miibus);
951 		sc->jme_miibus = NULL;
952 	}
953 	bus_generic_detach(dev);
954 	jme_dma_free(sc);
955 
956 	if (ifp != NULL) {
957 		if_free(ifp);
958 		sc->jme_ifp = NULL;
959 	}
960 
961 	for (i = 0; i < 1; i++) {
962 		if (sc->jme_intrhand[i] != NULL) {
963 			bus_teardown_intr(dev, sc->jme_irq[i],
964 			    sc->jme_intrhand[i]);
965 			sc->jme_intrhand[i] = NULL;
966 		}
967 	}
968 
969 	if (sc->jme_irq[0] != NULL)
970 		bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq);
971 	if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0)
972 		pci_release_msi(dev);
973 	if (sc->jme_res[0] != NULL)
974 		bus_release_resources(dev, sc->jme_res_spec, sc->jme_res);
975 	mtx_destroy(&sc->jme_mtx);
976 
977 	return (0);
978 }
979 
980 #define	JME_SYSCTL_STAT_ADD32(c, h, n, p, d)	\
981 	    SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
982 
983 static void
984 jme_sysctl_node(struct jme_softc *sc)
985 {
986 	struct sysctl_ctx_list *ctx;
987 	struct sysctl_oid_list *child, *parent;
988 	struct sysctl_oid *tree;
989 	struct jme_hw_stats *stats;
990 	int error;
991 
992 	stats = &sc->jme_stats;
993 	ctx = device_get_sysctl_ctx(sc->jme_dev);
994 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
995 
996 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
997 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0,
998 	    sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
999 
1000 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
1001 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0,
1002 	    sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
1003 
1004 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
1005 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0,
1006 	    sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
1007 
1008 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
1009 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0,
1010 	    sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
1011 
1012 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
1013 	    CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0,
1014 	    sysctl_hw_jme_proc_limit, "I",
1015 	    "max number of Rx events to process");
1016 
1017 	/* Pull in device tunables. */
1018 	sc->jme_process_limit = JME_PROC_DEFAULT;
1019 	error = resource_int_value(device_get_name(sc->jme_dev),
1020 	    device_get_unit(sc->jme_dev), "process_limit",
1021 	    &sc->jme_process_limit);
1022 	if (error == 0) {
1023 		if (sc->jme_process_limit < JME_PROC_MIN ||
1024 		    sc->jme_process_limit > JME_PROC_MAX) {
1025 			device_printf(sc->jme_dev,
1026 			    "process_limit value out of range; "
1027 			    "using default: %d\n", JME_PROC_DEFAULT);
1028 			sc->jme_process_limit = JME_PROC_DEFAULT;
1029 		}
1030 	}
1031 
1032 	sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1033 	error = resource_int_value(device_get_name(sc->jme_dev),
1034 	    device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
1035 	if (error == 0) {
1036 		if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
1037 		    sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
1038 			device_printf(sc->jme_dev,
1039 			    "tx_coal_to value out of range; "
1040 			    "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
1041 			sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1042 		}
1043 	}
1044 
1045 	sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1046 	error = resource_int_value(device_get_name(sc->jme_dev),
1047 	    device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
1048 	if (error == 0) {
1049 		if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
1050 		    sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
1051 			device_printf(sc->jme_dev,
1052 			    "tx_coal_pkt value out of range; "
1053 			    "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
1054 			sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1055 		}
1056 	}
1057 
1058 	sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1059 	error = resource_int_value(device_get_name(sc->jme_dev),
1060 	    device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
1061 	if (error == 0) {
1062 		if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
1063 		    sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
1064 			device_printf(sc->jme_dev,
1065 			    "rx_coal_to value out of range; "
1066 			    "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
1067 			sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1068 		}
1069 	}
1070 
1071 	sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1072 	error = resource_int_value(device_get_name(sc->jme_dev),
1073 	    device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
1074 	if (error == 0) {
1075 		if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
1076 		    sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
1077 			device_printf(sc->jme_dev,
1078 			    "tx_coal_pkt value out of range; "
1079 			    "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
1080 			sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1081 		}
1082 	}
1083 
1084 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
1085 		return;
1086 
1087 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1088 	    NULL, "JME statistics");
1089 	parent = SYSCTL_CHILDREN(tree);
1090 
1091 	/* Rx statistics. */
1092 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
1093 	    NULL, "Rx MAC statistics");
1094 	child = SYSCTL_CHILDREN(tree);
1095 	JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1096 	    &stats->rx_good_frames, "Good frames");
1097 	JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1098 	    &stats->rx_crc_errs, "CRC errors");
1099 	JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
1100 	    &stats->rx_mii_errs, "MII errors");
1101 	JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1102 	    &stats->rx_fifo_oflows, "FIFO overflows");
1103 	JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
1104 	    &stats->rx_desc_empty, "Descriptor empty");
1105 	JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1106 	    &stats->rx_bad_frames, "Bad frames");
1107 
1108 	/* Tx statistics. */
1109 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1110 	    NULL, "Tx MAC statistics");
1111 	child = SYSCTL_CHILDREN(tree);
1112 	JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1113 	    &stats->tx_good_frames, "Good frames");
1114 	JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1115 	    &stats->tx_bad_frames, "Bad frames");
1116 }
1117 
1118 #undef	JME_SYSCTL_STAT_ADD32
1119 
1120 struct jme_dmamap_arg {
1121 	bus_addr_t	jme_busaddr;
1122 };
1123 
1124 static void
1125 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1126 {
1127 	struct jme_dmamap_arg *ctx;
1128 
1129 	if (error != 0)
1130 		return;
1131 
1132 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1133 
1134 	ctx = (struct jme_dmamap_arg *)arg;
1135 	ctx->jme_busaddr = segs[0].ds_addr;
1136 }
1137 
1138 static int
1139 jme_dma_alloc(struct jme_softc *sc)
1140 {
1141 	struct jme_dmamap_arg ctx;
1142 	struct jme_txdesc *txd;
1143 	struct jme_rxdesc *rxd;
1144 	bus_addr_t lowaddr, rx_ring_end, tx_ring_end;
1145 	int error, i;
1146 
1147 	lowaddr = BUS_SPACE_MAXADDR;
1148 	if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1149 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1150 
1151 again:
1152 	/* Create parent ring tag. */
1153 	error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1154 	    1, 0,			/* algnmnt, boundary */
1155 	    lowaddr,			/* lowaddr */
1156 	    BUS_SPACE_MAXADDR,		/* highaddr */
1157 	    NULL, NULL,			/* filter, filterarg */
1158 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1159 	    0,				/* nsegments */
1160 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1161 	    0,				/* flags */
1162 	    NULL, NULL,			/* lockfunc, lockarg */
1163 	    &sc->jme_cdata.jme_ring_tag);
1164 	if (error != 0) {
1165 		device_printf(sc->jme_dev,
1166 		    "could not create parent ring DMA tag.\n");
1167 		goto fail;
1168 	}
1169 	/* Create tag for Tx ring. */
1170 	error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1171 	    JME_TX_RING_ALIGN, 0,	/* algnmnt, boundary */
1172 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1173 	    BUS_SPACE_MAXADDR,		/* highaddr */
1174 	    NULL, NULL,			/* filter, filterarg */
1175 	    JME_TX_RING_SIZE,		/* maxsize */
1176 	    1,				/* nsegments */
1177 	    JME_TX_RING_SIZE,		/* maxsegsize */
1178 	    0,				/* flags */
1179 	    NULL, NULL,			/* lockfunc, lockarg */
1180 	    &sc->jme_cdata.jme_tx_ring_tag);
1181 	if (error != 0) {
1182 		device_printf(sc->jme_dev,
1183 		    "could not allocate Tx ring DMA tag.\n");
1184 		goto fail;
1185 	}
1186 
1187 	/* Create tag for Rx ring. */
1188 	error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1189 	    JME_RX_RING_ALIGN, 0,	/* algnmnt, boundary */
1190 	    lowaddr,			/* lowaddr */
1191 	    BUS_SPACE_MAXADDR,		/* highaddr */
1192 	    NULL, NULL,			/* filter, filterarg */
1193 	    JME_RX_RING_SIZE,		/* maxsize */
1194 	    1,				/* nsegments */
1195 	    JME_RX_RING_SIZE,		/* maxsegsize */
1196 	    0,				/* flags */
1197 	    NULL, NULL,			/* lockfunc, lockarg */
1198 	    &sc->jme_cdata.jme_rx_ring_tag);
1199 	if (error != 0) {
1200 		device_printf(sc->jme_dev,
1201 		    "could not allocate Rx ring DMA tag.\n");
1202 		goto fail;
1203 	}
1204 
1205 	/* Allocate DMA'able memory and load the DMA map for Tx ring. */
1206 	error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1207 	    (void **)&sc->jme_rdata.jme_tx_ring,
1208 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1209 	    &sc->jme_cdata.jme_tx_ring_map);
1210 	if (error != 0) {
1211 		device_printf(sc->jme_dev,
1212 		    "could not allocate DMA'able memory for Tx ring.\n");
1213 		goto fail;
1214 	}
1215 
1216 	ctx.jme_busaddr = 0;
1217 	error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1218 	    sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1219 	    JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1220 	if (error != 0 || ctx.jme_busaddr == 0) {
1221 		device_printf(sc->jme_dev,
1222 		    "could not load DMA'able memory for Tx ring.\n");
1223 		goto fail;
1224 	}
1225 	sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr;
1226 
1227 	/* Allocate DMA'able memory and load the DMA map for Rx ring. */
1228 	error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1229 	    (void **)&sc->jme_rdata.jme_rx_ring,
1230 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1231 	    &sc->jme_cdata.jme_rx_ring_map);
1232 	if (error != 0) {
1233 		device_printf(sc->jme_dev,
1234 		    "could not allocate DMA'able memory for Rx ring.\n");
1235 		goto fail;
1236 	}
1237 
1238 	ctx.jme_busaddr = 0;
1239 	error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1240 	    sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1241 	    JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1242 	if (error != 0 || ctx.jme_busaddr == 0) {
1243 		device_printf(sc->jme_dev,
1244 		    "could not load DMA'able memory for Rx ring.\n");
1245 		goto fail;
1246 	}
1247 	sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
1248 
1249 	if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1250 		/* Tx/Rx descriptor queue should reside within 4GB boundary. */
1251 		tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1252 		    JME_TX_RING_SIZE;
1253 		rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1254 		    JME_RX_RING_SIZE;
1255 		if ((JME_ADDR_HI(tx_ring_end) !=
1256 		    JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1257 		    (JME_ADDR_HI(rx_ring_end) !=
1258 		     JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1259 			device_printf(sc->jme_dev, "4GB boundary crossed, "
1260 			    "switching to 32bit DMA address mode.\n");
1261 			jme_dma_free(sc);
1262 			/* Limit DMA address space to 32bit and try again. */
1263 			lowaddr = BUS_SPACE_MAXADDR_32BIT;
1264 			goto again;
1265 		}
1266 	}
1267 
1268 	lowaddr = BUS_SPACE_MAXADDR;
1269 	if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1270 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1271 	/* Create parent buffer tag. */
1272 	error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1273 	    1, 0,			/* algnmnt, boundary */
1274 	    lowaddr,			/* lowaddr */
1275 	    BUS_SPACE_MAXADDR,		/* highaddr */
1276 	    NULL, NULL,			/* filter, filterarg */
1277 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1278 	    0,				/* nsegments */
1279 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1280 	    0,				/* flags */
1281 	    NULL, NULL,			/* lockfunc, lockarg */
1282 	    &sc->jme_cdata.jme_buffer_tag);
1283 	if (error != 0) {
1284 		device_printf(sc->jme_dev,
1285 		    "could not create parent buffer DMA tag.\n");
1286 		goto fail;
1287 	}
1288 
1289 	/* Create shadow status block tag. */
1290 	error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1291 	    JME_SSB_ALIGN, 0,		/* algnmnt, boundary */
1292 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1293 	    BUS_SPACE_MAXADDR,		/* highaddr */
1294 	    NULL, NULL,			/* filter, filterarg */
1295 	    JME_SSB_SIZE,		/* maxsize */
1296 	    1,				/* nsegments */
1297 	    JME_SSB_SIZE,		/* maxsegsize */
1298 	    0,				/* flags */
1299 	    NULL, NULL,			/* lockfunc, lockarg */
1300 	    &sc->jme_cdata.jme_ssb_tag);
1301 	if (error != 0) {
1302 		device_printf(sc->jme_dev,
1303 		    "could not create shared status block DMA tag.\n");
1304 		goto fail;
1305 	}
1306 
1307 	/* Create tag for Tx buffers. */
1308 	error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1309 	    1, 0,			/* algnmnt, boundary */
1310 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1311 	    BUS_SPACE_MAXADDR,		/* highaddr */
1312 	    NULL, NULL,			/* filter, filterarg */
1313 	    JME_TSO_MAXSIZE,		/* maxsize */
1314 	    JME_MAXTXSEGS,		/* nsegments */
1315 	    JME_TSO_MAXSEGSIZE,		/* maxsegsize */
1316 	    0,				/* flags */
1317 	    NULL, NULL,			/* lockfunc, lockarg */
1318 	    &sc->jme_cdata.jme_tx_tag);
1319 	if (error != 0) {
1320 		device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1321 		goto fail;
1322 	}
1323 
1324 	/* Create tag for Rx buffers. */
1325 	error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1326 	    JME_RX_BUF_ALIGN, 0,	/* algnmnt, boundary */
1327 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1328 	    BUS_SPACE_MAXADDR,		/* highaddr */
1329 	    NULL, NULL,			/* filter, filterarg */
1330 	    MCLBYTES,			/* maxsize */
1331 	    1,				/* nsegments */
1332 	    MCLBYTES,			/* maxsegsize */
1333 	    0,				/* flags */
1334 	    NULL, NULL,			/* lockfunc, lockarg */
1335 	    &sc->jme_cdata.jme_rx_tag);
1336 	if (error != 0) {
1337 		device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1338 		goto fail;
1339 	}
1340 
1341 	/*
1342 	 * Allocate DMA'able memory and load the DMA map for shared
1343 	 * status block.
1344 	 */
1345 	error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1346 	    (void **)&sc->jme_rdata.jme_ssb_block,
1347 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1348 	    &sc->jme_cdata.jme_ssb_map);
1349 	if (error != 0) {
1350 		device_printf(sc->jme_dev, "could not allocate DMA'able "
1351 		    "memory for shared status block.\n");
1352 		goto fail;
1353 	}
1354 
1355 	ctx.jme_busaddr = 0;
1356 	error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1357 	    sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1358 	    JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1359 	if (error != 0 || ctx.jme_busaddr == 0) {
1360 		device_printf(sc->jme_dev, "could not load DMA'able memory "
1361 		    "for shared status block.\n");
1362 		goto fail;
1363 	}
1364 	sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr;
1365 
1366 	/* Create DMA maps for Tx buffers. */
1367 	for (i = 0; i < JME_TX_RING_CNT; i++) {
1368 		txd = &sc->jme_cdata.jme_txdesc[i];
1369 		txd->tx_m = NULL;
1370 		txd->tx_dmamap = NULL;
1371 		error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1372 		    &txd->tx_dmamap);
1373 		if (error != 0) {
1374 			device_printf(sc->jme_dev,
1375 			    "could not create Tx dmamap.\n");
1376 			goto fail;
1377 		}
1378 	}
1379 	/* Create DMA maps for Rx buffers. */
1380 	if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1381 	    &sc->jme_cdata.jme_rx_sparemap)) != 0) {
1382 		device_printf(sc->jme_dev,
1383 		    "could not create spare Rx dmamap.\n");
1384 		goto fail;
1385 	}
1386 	for (i = 0; i < JME_RX_RING_CNT; i++) {
1387 		rxd = &sc->jme_cdata.jme_rxdesc[i];
1388 		rxd->rx_m = NULL;
1389 		rxd->rx_dmamap = NULL;
1390 		error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1391 		    &rxd->rx_dmamap);
1392 		if (error != 0) {
1393 			device_printf(sc->jme_dev,
1394 			    "could not create Rx dmamap.\n");
1395 			goto fail;
1396 		}
1397 	}
1398 
1399 fail:
1400 	return (error);
1401 }
1402 
1403 static void
1404 jme_dma_free(struct jme_softc *sc)
1405 {
1406 	struct jme_txdesc *txd;
1407 	struct jme_rxdesc *rxd;
1408 	int i;
1409 
1410 	/* Tx ring */
1411 	if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1412 		if (sc->jme_cdata.jme_tx_ring_map)
1413 			bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1414 			    sc->jme_cdata.jme_tx_ring_map);
1415 		if (sc->jme_cdata.jme_tx_ring_map &&
1416 		    sc->jme_rdata.jme_tx_ring)
1417 			bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1418 			    sc->jme_rdata.jme_tx_ring,
1419 			    sc->jme_cdata.jme_tx_ring_map);
1420 		sc->jme_rdata.jme_tx_ring = NULL;
1421 		sc->jme_cdata.jme_tx_ring_map = NULL;
1422 		bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1423 		sc->jme_cdata.jme_tx_ring_tag = NULL;
1424 	}
1425 	/* Rx ring */
1426 	if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1427 		if (sc->jme_cdata.jme_rx_ring_map)
1428 			bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1429 			    sc->jme_cdata.jme_rx_ring_map);
1430 		if (sc->jme_cdata.jme_rx_ring_map &&
1431 		    sc->jme_rdata.jme_rx_ring)
1432 			bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1433 			    sc->jme_rdata.jme_rx_ring,
1434 			    sc->jme_cdata.jme_rx_ring_map);
1435 		sc->jme_rdata.jme_rx_ring = NULL;
1436 		sc->jme_cdata.jme_rx_ring_map = NULL;
1437 		bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1438 		sc->jme_cdata.jme_rx_ring_tag = NULL;
1439 	}
1440 	/* Tx buffers */
1441 	if (sc->jme_cdata.jme_tx_tag != NULL) {
1442 		for (i = 0; i < JME_TX_RING_CNT; i++) {
1443 			txd = &sc->jme_cdata.jme_txdesc[i];
1444 			if (txd->tx_dmamap != NULL) {
1445 				bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1446 				    txd->tx_dmamap);
1447 				txd->tx_dmamap = NULL;
1448 			}
1449 		}
1450 		bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1451 		sc->jme_cdata.jme_tx_tag = NULL;
1452 	}
1453 	/* Rx buffers */
1454 	if (sc->jme_cdata.jme_rx_tag != NULL) {
1455 		for (i = 0; i < JME_RX_RING_CNT; i++) {
1456 			rxd = &sc->jme_cdata.jme_rxdesc[i];
1457 			if (rxd->rx_dmamap != NULL) {
1458 				bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1459 				    rxd->rx_dmamap);
1460 				rxd->rx_dmamap = NULL;
1461 			}
1462 		}
1463 		if (sc->jme_cdata.jme_rx_sparemap != NULL) {
1464 			bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1465 			    sc->jme_cdata.jme_rx_sparemap);
1466 			sc->jme_cdata.jme_rx_sparemap = NULL;
1467 		}
1468 		bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1469 		sc->jme_cdata.jme_rx_tag = NULL;
1470 	}
1471 
1472 	/* Shared status block. */
1473 	if (sc->jme_cdata.jme_ssb_tag != NULL) {
1474 		if (sc->jme_cdata.jme_ssb_map)
1475 			bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1476 			    sc->jme_cdata.jme_ssb_map);
1477 		if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block)
1478 			bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1479 			    sc->jme_rdata.jme_ssb_block,
1480 			    sc->jme_cdata.jme_ssb_map);
1481 		sc->jme_rdata.jme_ssb_block = NULL;
1482 		sc->jme_cdata.jme_ssb_map = NULL;
1483 		bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1484 		sc->jme_cdata.jme_ssb_tag = NULL;
1485 	}
1486 
1487 	if (sc->jme_cdata.jme_buffer_tag != NULL) {
1488 		bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1489 		sc->jme_cdata.jme_buffer_tag = NULL;
1490 	}
1491 	if (sc->jme_cdata.jme_ring_tag != NULL) {
1492 		bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1493 		sc->jme_cdata.jme_ring_tag = NULL;
1494 	}
1495 }
1496 
1497 /*
1498  *	Make sure the interface is stopped at reboot time.
1499  */
1500 static int
1501 jme_shutdown(device_t dev)
1502 {
1503 
1504 	return (jme_suspend(dev));
1505 }
1506 
1507 /*
1508  * Unlike other ethernet controllers, JMC250 requires
1509  * explicit resetting link speed to 10/100Mbps as gigabit
1510  * link will cunsume more power than 375mA.
1511  * Note, we reset the link speed to 10/100Mbps with
1512  * auto-negotiation but we don't know whether that operation
1513  * would succeed or not as we have no control after powering
1514  * off. If the renegotiation fail WOL may not work. Running
1515  * at 1Gbps draws more power than 375mA at 3.3V which is
1516  * specified in PCI specification and that would result in
1517  * complete shutdowning power to ethernet controller.
1518  *
1519  * TODO
1520  *  Save current negotiated media speed/duplex/flow-control
1521  *  to softc and restore the same link again after resuming.
1522  *  PHY handling such as power down/resetting to 100Mbps
1523  *  may be better handled in suspend method in phy driver.
1524  */
1525 static void
1526 jme_setlinkspeed(struct jme_softc *sc)
1527 {
1528 	struct mii_data *mii;
1529 	int aneg, i;
1530 
1531 	JME_LOCK_ASSERT(sc);
1532 
1533 	mii = device_get_softc(sc->jme_miibus);
1534 	mii_pollstat(mii);
1535 	aneg = 0;
1536 	if ((mii->mii_media_status & IFM_AVALID) != 0) {
1537 		switch IFM_SUBTYPE(mii->mii_media_active) {
1538 		case IFM_10_T:
1539 		case IFM_100_TX:
1540 			return;
1541 		case IFM_1000_T:
1542 			aneg++;
1543 		default:
1544 			break;
1545 		}
1546 	}
1547 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1548 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1549 	    ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1550 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1551 	    BMCR_AUTOEN | BMCR_STARTNEG);
1552 	DELAY(1000);
1553 	if (aneg != 0) {
1554 		/* Poll link state until jme(4) get a 10/100 link. */
1555 		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1556 			mii_pollstat(mii);
1557 			if ((mii->mii_media_status & IFM_AVALID) != 0) {
1558 				switch (IFM_SUBTYPE(mii->mii_media_active)) {
1559 				case IFM_10_T:
1560 				case IFM_100_TX:
1561 					jme_mac_config(sc);
1562 					return;
1563 				default:
1564 					break;
1565 				}
1566 			}
1567 			JME_UNLOCK(sc);
1568 			pause("jmelnk", hz);
1569 			JME_LOCK(sc);
1570 		}
1571 		if (i == MII_ANEGTICKS_GIGE)
1572 			device_printf(sc->jme_dev, "establishing link failed, "
1573 			    "WOL may not work!");
1574 	}
1575 	/*
1576 	 * No link, force MAC to have 100Mbps, full-duplex link.
1577 	 * This is the last resort and may/may not work.
1578 	 */
1579 	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1580 	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1581 	jme_mac_config(sc);
1582 }
1583 
1584 static void
1585 jme_setwol(struct jme_softc *sc)
1586 {
1587 	struct ifnet *ifp;
1588 	uint32_t gpr, pmcs;
1589 	uint16_t pmstat;
1590 	int pmc;
1591 
1592 	JME_LOCK_ASSERT(sc);
1593 
1594 	if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1595 		/* Remove Tx MAC/offload clock to save more power. */
1596 		if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1597 			CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1598 			    ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1599 			    GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1600 		if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
1601 			CSR_WRITE_4(sc, JME_GPREG1,
1602 			    CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS);
1603 		/* No PME capability, PHY power down. */
1604 		jme_phy_down(sc);
1605 		return;
1606 	}
1607 
1608 	ifp = sc->jme_ifp;
1609 	gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1610 	pmcs = CSR_READ_4(sc, JME_PMCS);
1611 	pmcs &= ~PMCS_WOL_ENB_MASK;
1612 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1613 		pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1614 		/* Enable PME message. */
1615 		gpr |= GPREG0_PME_ENB;
1616 		/* For gigabit controllers, reset link speed to 10/100. */
1617 		if ((sc->jme_flags & JME_FLAG_FASTETH) == 0)
1618 			jme_setlinkspeed(sc);
1619 	}
1620 
1621 	CSR_WRITE_4(sc, JME_PMCS, pmcs);
1622 	CSR_WRITE_4(sc, JME_GPREG0, gpr);
1623 	/* Remove Tx MAC/offload clock to save more power. */
1624 	if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1625 		CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1626 		    ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1627 		    GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1628 	/* Request PME. */
1629 	pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1630 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1631 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1632 		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1633 	pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1634 	if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1635 		/* No WOL, PHY power down. */
1636 		jme_phy_down(sc);
1637 	}
1638 }
1639 
1640 static int
1641 jme_suspend(device_t dev)
1642 {
1643 	struct jme_softc *sc;
1644 
1645 	sc = device_get_softc(dev);
1646 
1647 	JME_LOCK(sc);
1648 	jme_stop(sc);
1649 	jme_setwol(sc);
1650 	JME_UNLOCK(sc);
1651 
1652 	return (0);
1653 }
1654 
1655 static int
1656 jme_resume(device_t dev)
1657 {
1658 	struct jme_softc *sc;
1659 	struct ifnet *ifp;
1660 	uint16_t pmstat;
1661 	int pmc;
1662 
1663 	sc = device_get_softc(dev);
1664 
1665 	JME_LOCK(sc);
1666 	if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1667 		pmstat = pci_read_config(sc->jme_dev,
1668 		    pmc + PCIR_POWER_STATUS, 2);
1669 		/* Disable PME clear PME status. */
1670 		pmstat &= ~PCIM_PSTAT_PMEENABLE;
1671 		pci_write_config(sc->jme_dev,
1672 		    pmc + PCIR_POWER_STATUS, pmstat, 2);
1673 	}
1674 	/* Wakeup PHY. */
1675 	jme_phy_up(sc);
1676 	ifp = sc->jme_ifp;
1677 	if ((ifp->if_flags & IFF_UP) != 0) {
1678 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1679 		jme_init_locked(sc);
1680 	}
1681 
1682 	JME_UNLOCK(sc);
1683 
1684 	return (0);
1685 }
1686 
1687 static int
1688 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1689 {
1690 	struct jme_txdesc *txd;
1691 	struct jme_desc *desc;
1692 	struct mbuf *m;
1693 	bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1694 	int error, i, nsegs, prod;
1695 	uint32_t cflags, tso_segsz;
1696 
1697 	JME_LOCK_ASSERT(sc);
1698 
1699 	M_ASSERTPKTHDR((*m_head));
1700 
1701 	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1702 		/*
1703 		 * Due to the adherence to NDIS specification JMC250
1704 		 * assumes upper stack computed TCP pseudo checksum
1705 		 * without including payload length. This breaks
1706 		 * checksum offload for TSO case so recompute TCP
1707 		 * pseudo checksum for JMC250. Hopefully this wouldn't
1708 		 * be much burden on modern CPUs.
1709 		 */
1710 		struct ether_header *eh;
1711 		struct ip *ip;
1712 		struct tcphdr *tcp;
1713 		uint32_t ip_off, poff;
1714 
1715 		if (M_WRITABLE(*m_head) == 0) {
1716 			/* Get a writable copy. */
1717 			m = m_dup(*m_head, M_DONTWAIT);
1718 			m_freem(*m_head);
1719 			if (m == NULL) {
1720 				*m_head = NULL;
1721 				return (ENOBUFS);
1722 			}
1723 			*m_head = m;
1724 		}
1725 		ip_off = sizeof(struct ether_header);
1726 		m = m_pullup(*m_head, ip_off);
1727 		if (m == NULL) {
1728 			*m_head = NULL;
1729 			return (ENOBUFS);
1730 		}
1731 		eh = mtod(m, struct ether_header *);
1732 		/* Check the existence of VLAN tag. */
1733 		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1734 			ip_off = sizeof(struct ether_vlan_header);
1735 			m = m_pullup(m, ip_off);
1736 			if (m == NULL) {
1737 				*m_head = NULL;
1738 				return (ENOBUFS);
1739 			}
1740 		}
1741 		m = m_pullup(m, ip_off + sizeof(struct ip));
1742 		if (m == NULL) {
1743 			*m_head = NULL;
1744 			return (ENOBUFS);
1745 		}
1746 		ip = (struct ip *)(mtod(m, char *) + ip_off);
1747 		poff = ip_off + (ip->ip_hl << 2);
1748 		m = m_pullup(m, poff + sizeof(struct tcphdr));
1749 		if (m == NULL) {
1750 			*m_head = NULL;
1751 			return (ENOBUFS);
1752 		}
1753 		/*
1754 		 * Reset IP checksum and recompute TCP pseudo
1755 		 * checksum that NDIS specification requires.
1756 		 */
1757 		ip = (struct ip *)(mtod(m, char *) + ip_off);
1758 		tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1759 		ip->ip_sum = 0;
1760 		if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1761 			tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1762 			    ip->ip_dst.s_addr,
1763 			    htons((tcp->th_off << 2) + IPPROTO_TCP));
1764 			/* No need to TSO, force IP checksum offload. */
1765 			(*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO;
1766 			(*m_head)->m_pkthdr.csum_flags |= CSUM_IP;
1767 		} else
1768 			tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1769 			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1770 		*m_head = m;
1771 	}
1772 
1773 	prod = sc->jme_cdata.jme_tx_prod;
1774 	txd = &sc->jme_cdata.jme_txdesc[prod];
1775 
1776 	error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1777 	    txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1778 	if (error == EFBIG) {
1779 		m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS);
1780 		if (m == NULL) {
1781 			m_freem(*m_head);
1782 			*m_head = NULL;
1783 			return (ENOMEM);
1784 		}
1785 		*m_head = m;
1786 		error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1787 		    txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1788 		if (error != 0) {
1789 			m_freem(*m_head);
1790 			*m_head = NULL;
1791 			return (error);
1792 		}
1793 	} else if (error != 0)
1794 		return (error);
1795 	if (nsegs == 0) {
1796 		m_freem(*m_head);
1797 		*m_head = NULL;
1798 		return (EIO);
1799 	}
1800 
1801 	/*
1802 	 * Check descriptor overrun. Leave one free descriptor.
1803 	 * Since we always use 64bit address mode for transmitting,
1804 	 * each Tx request requires one more dummy descriptor.
1805 	 */
1806 	if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) {
1807 		bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1808 		return (ENOBUFS);
1809 	}
1810 
1811 	m = *m_head;
1812 	cflags = 0;
1813 	tso_segsz = 0;
1814 	/* Configure checksum offload and TSO. */
1815 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1816 		tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz <<
1817 		    JME_TD_MSS_SHIFT;
1818 		cflags |= JME_TD_TSO;
1819 	} else {
1820 		if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1821 			cflags |= JME_TD_IPCSUM;
1822 		if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1823 			cflags |= JME_TD_TCPCSUM;
1824 		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1825 			cflags |= JME_TD_UDPCSUM;
1826 	}
1827 	/* Configure VLAN. */
1828 	if ((m->m_flags & M_VLANTAG) != 0) {
1829 		cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK);
1830 		cflags |= JME_TD_VLAN_TAG;
1831 	}
1832 
1833 	desc = &sc->jme_rdata.jme_tx_ring[prod];
1834 	desc->flags = htole32(cflags);
1835 	desc->buflen = htole32(tso_segsz);
1836 	desc->addr_hi = htole32(m->m_pkthdr.len);
1837 	desc->addr_lo = 0;
1838 	sc->jme_cdata.jme_tx_cnt++;
1839 	JME_DESC_INC(prod, JME_TX_RING_CNT);
1840 	for (i = 0; i < nsegs; i++) {
1841 		desc = &sc->jme_rdata.jme_tx_ring[prod];
1842 		desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1843 		desc->buflen = htole32(txsegs[i].ds_len);
1844 		desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1845 		desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1846 		sc->jme_cdata.jme_tx_cnt++;
1847 		JME_DESC_INC(prod, JME_TX_RING_CNT);
1848 	}
1849 
1850 	/* Update producer index. */
1851 	sc->jme_cdata.jme_tx_prod = prod;
1852 	/*
1853 	 * Finally request interrupt and give the first descriptor
1854 	 * owenership to hardware.
1855 	 */
1856 	desc = txd->tx_desc;
1857 	desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1858 
1859 	txd->tx_m = m;
1860 	txd->tx_ndesc = nsegs + 1;
1861 
1862 	/* Sync descriptors. */
1863 	bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1864 	    BUS_DMASYNC_PREWRITE);
1865 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1866 	    sc->jme_cdata.jme_tx_ring_map,
1867 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1868 
1869 	return (0);
1870 }
1871 
1872 static void
1873 jme_start(struct ifnet *ifp)
1874 {
1875         struct jme_softc *sc;
1876 
1877 	sc = ifp->if_softc;
1878 	JME_LOCK(sc);
1879 	jme_start_locked(ifp);
1880 	JME_UNLOCK(sc);
1881 }
1882 
1883 static void
1884 jme_start_locked(struct ifnet *ifp)
1885 {
1886         struct jme_softc *sc;
1887         struct mbuf *m_head;
1888 	int enq;
1889 
1890 	sc = ifp->if_softc;
1891 
1892 	JME_LOCK_ASSERT(sc);
1893 
1894 	if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1895 		jme_txeof(sc);
1896 
1897 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1898 	    IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0)
1899 		return;
1900 
1901 	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1902 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1903 		if (m_head == NULL)
1904 			break;
1905 		/*
1906 		 * Pack the data into the transmit ring. If we
1907 		 * don't have room, set the OACTIVE flag and wait
1908 		 * for the NIC to drain the ring.
1909 		 */
1910 		if (jme_encap(sc, &m_head)) {
1911 			if (m_head == NULL)
1912 				break;
1913 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1914 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1915 			break;
1916 		}
1917 
1918 		enq++;
1919 		/*
1920 		 * If there's a BPF listener, bounce a copy of this frame
1921 		 * to him.
1922 		 */
1923 		ETHER_BPF_MTAP(ifp, m_head);
1924 	}
1925 
1926 	if (enq > 0) {
1927 		/*
1928 		 * Reading TXCSR takes very long time under heavy load
1929 		 * so cache TXCSR value and writes the ORed value with
1930 		 * the kick command to the TXCSR. This saves one register
1931 		 * access cycle.
1932 		 */
1933 		CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1934 		    TXCSR_TXQ_N_START(TXCSR_TXQ0));
1935 		/* Set a timeout in case the chip goes out to lunch. */
1936 		sc->jme_watchdog_timer = JME_TX_TIMEOUT;
1937 	}
1938 }
1939 
1940 static void
1941 jme_watchdog(struct jme_softc *sc)
1942 {
1943 	struct ifnet *ifp;
1944 
1945 	JME_LOCK_ASSERT(sc);
1946 
1947 	if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer)
1948 		return;
1949 
1950 	ifp = sc->jme_ifp;
1951 	if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1952 		if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
1953 		ifp->if_oerrors++;
1954 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1955 		jme_init_locked(sc);
1956 		return;
1957 	}
1958 	jme_txeof(sc);
1959 	if (sc->jme_cdata.jme_tx_cnt == 0) {
1960 		if_printf(sc->jme_ifp,
1961 		    "watchdog timeout (missed Tx interrupts) -- recovering\n");
1962 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1963 			jme_start_locked(ifp);
1964 		return;
1965 	}
1966 
1967 	if_printf(sc->jme_ifp, "watchdog timeout\n");
1968 	ifp->if_oerrors++;
1969 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1970 	jme_init_locked(sc);
1971 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1972 		jme_start_locked(ifp);
1973 }
1974 
1975 static int
1976 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1977 {
1978 	struct jme_softc *sc;
1979 	struct ifreq *ifr;
1980 	struct mii_data *mii;
1981 	uint32_t reg;
1982 	int error, mask;
1983 
1984 	sc = ifp->if_softc;
1985 	ifr = (struct ifreq *)data;
1986 	error = 0;
1987 	switch (cmd) {
1988 	case SIOCSIFMTU:
1989 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1990 		    ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 &&
1991 		    ifr->ifr_mtu > JME_MAX_MTU)) {
1992 			error = EINVAL;
1993 			break;
1994 		}
1995 
1996 		if (ifp->if_mtu != ifr->ifr_mtu) {
1997 			/*
1998 			 * No special configuration is required when interface
1999 			 * MTU is changed but availability of TSO/Tx checksum
2000 			 * offload should be chcked against new MTU size as
2001 			 * FIFO size is just 2K.
2002 			 */
2003 			JME_LOCK(sc);
2004 			if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
2005 				ifp->if_capenable &=
2006 				    ~(IFCAP_TXCSUM | IFCAP_TSO4);
2007 				ifp->if_hwassist &=
2008 				    ~(JME_CSUM_FEATURES | CSUM_TSO);
2009 				VLAN_CAPABILITIES(ifp);
2010 			}
2011 			ifp->if_mtu = ifr->ifr_mtu;
2012 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2013 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2014 				jme_init_locked(sc);
2015 			}
2016 			JME_UNLOCK(sc);
2017 		}
2018 		break;
2019 	case SIOCSIFFLAGS:
2020 		JME_LOCK(sc);
2021 		if ((ifp->if_flags & IFF_UP) != 0) {
2022 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2023 				if (((ifp->if_flags ^ sc->jme_if_flags)
2024 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2025 					jme_set_filter(sc);
2026 			} else {
2027 				if ((sc->jme_flags & JME_FLAG_DETACH) == 0)
2028 					jme_init_locked(sc);
2029 			}
2030 		} else {
2031 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2032 				jme_stop(sc);
2033 		}
2034 		sc->jme_if_flags = ifp->if_flags;
2035 		JME_UNLOCK(sc);
2036 		break;
2037 	case SIOCADDMULTI:
2038 	case SIOCDELMULTI:
2039 		JME_LOCK(sc);
2040 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2041 			jme_set_filter(sc);
2042 		JME_UNLOCK(sc);
2043 		break;
2044 	case SIOCSIFMEDIA:
2045 	case SIOCGIFMEDIA:
2046 		mii = device_get_softc(sc->jme_miibus);
2047 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2048 		break;
2049 	case SIOCSIFCAP:
2050 		JME_LOCK(sc);
2051 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2052 		if ((mask & IFCAP_TXCSUM) != 0 &&
2053 		    ifp->if_mtu < JME_TX_FIFO_SIZE) {
2054 			if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
2055 				ifp->if_capenable ^= IFCAP_TXCSUM;
2056 				if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
2057 					ifp->if_hwassist |= JME_CSUM_FEATURES;
2058 				else
2059 					ifp->if_hwassist &= ~JME_CSUM_FEATURES;
2060 			}
2061 		}
2062 		if ((mask & IFCAP_RXCSUM) != 0 &&
2063 		    (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
2064 			ifp->if_capenable ^= IFCAP_RXCSUM;
2065 			reg = CSR_READ_4(sc, JME_RXMAC);
2066 			reg &= ~RXMAC_CSUM_ENB;
2067 			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2068 				reg |= RXMAC_CSUM_ENB;
2069 			CSR_WRITE_4(sc, JME_RXMAC, reg);
2070 		}
2071 		if ((mask & IFCAP_TSO4) != 0 &&
2072 		    ifp->if_mtu < JME_TX_FIFO_SIZE) {
2073 			if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) {
2074 				ifp->if_capenable ^= IFCAP_TSO4;
2075 				if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
2076 					ifp->if_hwassist |= CSUM_TSO;
2077 				else
2078 					ifp->if_hwassist &= ~CSUM_TSO;
2079 			}
2080 		}
2081 		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2082 		    (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0)
2083 			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2084 		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2085 		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2086 			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2087 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2088 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2089 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2090 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2091 		    (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
2092 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2093 			jme_set_vlan(sc);
2094 		}
2095 		JME_UNLOCK(sc);
2096 		VLAN_CAPABILITIES(ifp);
2097 		break;
2098 	default:
2099 		error = ether_ioctl(ifp, cmd, data);
2100 		break;
2101 	}
2102 
2103 	return (error);
2104 }
2105 
2106 static void
2107 jme_mac_config(struct jme_softc *sc)
2108 {
2109 	struct mii_data *mii;
2110 	uint32_t ghc, gpreg, rxmac, txmac, txpause;
2111 	uint32_t txclk;
2112 
2113 	JME_LOCK_ASSERT(sc);
2114 
2115 	mii = device_get_softc(sc->jme_miibus);
2116 
2117 	CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2118 	DELAY(10);
2119 	CSR_WRITE_4(sc, JME_GHC, 0);
2120 	ghc = 0;
2121 	txclk = 0;
2122 	rxmac = CSR_READ_4(sc, JME_RXMAC);
2123 	rxmac &= ~RXMAC_FC_ENB;
2124 	txmac = CSR_READ_4(sc, JME_TXMAC);
2125 	txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2126 	txpause = CSR_READ_4(sc, JME_TXPFC);
2127 	txpause &= ~TXPFC_PAUSE_ENB;
2128 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2129 		ghc |= GHC_FULL_DUPLEX;
2130 		rxmac &= ~RXMAC_COLL_DET_ENB;
2131 		txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2132 		    TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2133 		    TXMAC_FRAME_BURST);
2134 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2135 			txpause |= TXPFC_PAUSE_ENB;
2136 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2137 			rxmac |= RXMAC_FC_ENB;
2138 		/* Disable retry transmit timer/retry limit. */
2139 		CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2140 		    ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2141 	} else {
2142 		rxmac |= RXMAC_COLL_DET_ENB;
2143 		txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2144 		/* Enable retry transmit timer/retry limit. */
2145 		CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2146 		    TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2147 	}
2148 		/* Reprogram Tx/Rx MACs with resolved speed/duplex. */
2149 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
2150 	case IFM_10_T:
2151 		ghc |= GHC_SPEED_10;
2152 		txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2153 		break;
2154 	case IFM_100_TX:
2155 		ghc |= GHC_SPEED_100;
2156 		txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2157 		break;
2158 	case IFM_1000_T:
2159 		if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2160 			break;
2161 		ghc |= GHC_SPEED_1000;
2162 		txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
2163 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2164 			txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2165 		break;
2166 	default:
2167 		break;
2168 	}
2169 	if (sc->jme_rev == DEVICEID_JMC250 &&
2170 	    sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
2171 		/*
2172 		 * Workaround occasional packet loss issue of JMC250 A2
2173 		 * when it runs on half-duplex media.
2174 		 */
2175 		gpreg = CSR_READ_4(sc, JME_GPREG1);
2176 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
2177 			gpreg &= ~GPREG1_HDPX_FIX;
2178 		else
2179 			gpreg |= GPREG1_HDPX_FIX;
2180 		CSR_WRITE_4(sc, JME_GPREG1, gpreg);
2181 		/* Workaround CRC errors at 100Mbps on JMC250 A2. */
2182 		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2183 			/* Extend interface FIFO depth. */
2184 			jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2185 			    0x1B, 0x0000);
2186 		} else {
2187 			/* Select default interface FIFO depth. */
2188 			jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2189 			    0x1B, 0x0004);
2190 		}
2191 	}
2192 	if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2193 		ghc |= txclk;
2194 	CSR_WRITE_4(sc, JME_GHC, ghc);
2195 	CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2196 	CSR_WRITE_4(sc, JME_TXMAC, txmac);
2197 	CSR_WRITE_4(sc, JME_TXPFC, txpause);
2198 }
2199 
2200 static void
2201 jme_link_task(void *arg, int pending)
2202 {
2203 	struct jme_softc *sc;
2204 	struct mii_data *mii;
2205 	struct ifnet *ifp;
2206 	struct jme_txdesc *txd;
2207 	bus_addr_t paddr;
2208 	int i;
2209 
2210 	sc = (struct jme_softc *)arg;
2211 
2212 	JME_LOCK(sc);
2213 	mii = device_get_softc(sc->jme_miibus);
2214 	ifp = sc->jme_ifp;
2215 	if (mii == NULL || ifp == NULL ||
2216 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2217 		JME_UNLOCK(sc);
2218 		return;
2219 	}
2220 
2221 	sc->jme_flags &= ~JME_FLAG_LINK;
2222 	if ((mii->mii_media_status & IFM_AVALID) != 0) {
2223 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
2224 		case IFM_10_T:
2225 		case IFM_100_TX:
2226 			sc->jme_flags |= JME_FLAG_LINK;
2227 			break;
2228 		case IFM_1000_T:
2229 			if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2230 				break;
2231 			sc->jme_flags |= JME_FLAG_LINK;
2232 			break;
2233 		default:
2234 			break;
2235 		}
2236 	}
2237 
2238 	/*
2239 	 * Disabling Rx/Tx MACs have a side-effect of resetting
2240 	 * JME_TXNDA/JME_RXNDA register to the first address of
2241 	 * Tx/Rx descriptor address. So driver should reset its
2242 	 * internal procucer/consumer pointer and reclaim any
2243 	 * allocated resources. Note, just saving the value of
2244 	 * JME_TXNDA and JME_RXNDA registers before stopping MAC
2245 	 * and restoring JME_TXNDA/JME_RXNDA register is not
2246 	 * sufficient to make sure correct MAC state because
2247 	 * stopping MAC operation can take a while and hardware
2248 	 * might have updated JME_TXNDA/JME_RXNDA registers
2249 	 * during the stop operation.
2250 	 */
2251 	/* Block execution of task. */
2252 	taskqueue_block(sc->jme_tq);
2253 	/* Disable interrupts and stop driver. */
2254 	CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2255 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2256 	callout_stop(&sc->jme_tick_ch);
2257 	sc->jme_watchdog_timer = 0;
2258 
2259 	/* Stop receiver/transmitter. */
2260 	jme_stop_rx(sc);
2261 	jme_stop_tx(sc);
2262 
2263 	/* XXX Drain all queued tasks. */
2264 	JME_UNLOCK(sc);
2265 	taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
2266 	JME_LOCK(sc);
2267 
2268 	if (sc->jme_cdata.jme_rxhead != NULL)
2269 		m_freem(sc->jme_cdata.jme_rxhead);
2270 	JME_RXCHAIN_RESET(sc);
2271 	jme_txeof(sc);
2272 	if (sc->jme_cdata.jme_tx_cnt != 0) {
2273 		/* Remove queued packets for transmit. */
2274 		for (i = 0; i < JME_TX_RING_CNT; i++) {
2275 			txd = &sc->jme_cdata.jme_txdesc[i];
2276 			if (txd->tx_m != NULL) {
2277 				bus_dmamap_sync(
2278 				    sc->jme_cdata.jme_tx_tag,
2279 				    txd->tx_dmamap,
2280 				    BUS_DMASYNC_POSTWRITE);
2281 				bus_dmamap_unload(
2282 				    sc->jme_cdata.jme_tx_tag,
2283 				    txd->tx_dmamap);
2284 				m_freem(txd->tx_m);
2285 				txd->tx_m = NULL;
2286 				txd->tx_ndesc = 0;
2287 				ifp->if_oerrors++;
2288 			}
2289 		}
2290 	}
2291 
2292 	/*
2293 	 * Reuse configured Rx descriptors and reset
2294 	 * producer/consumer index.
2295 	 */
2296 	sc->jme_cdata.jme_rx_cons = 0;
2297 	sc->jme_morework = 0;
2298 	jme_init_tx_ring(sc);
2299 	/* Initialize shadow status block. */
2300 	jme_init_ssb(sc);
2301 
2302 	/* Program MAC with resolved speed/duplex/flow-control. */
2303 	if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
2304 		jme_mac_config(sc);
2305 		jme_stats_clear(sc);
2306 
2307 		CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2308 		CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2309 
2310 		/* Set Tx ring address to the hardware. */
2311 		paddr = JME_TX_RING_ADDR(sc, 0);
2312 		CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2313 		CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2314 
2315 		/* Set Rx ring address to the hardware. */
2316 		paddr = JME_RX_RING_ADDR(sc, 0);
2317 		CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2318 		CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2319 
2320 		/* Restart receiver/transmitter. */
2321 		CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2322 		    RXCSR_RXQ_START);
2323 		CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2324 		/* Lastly enable TX/RX clock. */
2325 		if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2326 			CSR_WRITE_4(sc, JME_GHC,
2327 			    CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS);
2328 		if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
2329 			CSR_WRITE_4(sc, JME_GPREG1,
2330 			    CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS);
2331 	}
2332 
2333 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2334 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2335 	callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2336 	/* Unblock execution of task. */
2337 	taskqueue_unblock(sc->jme_tq);
2338 	/* Reenable interrupts. */
2339 	CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2340 
2341 	JME_UNLOCK(sc);
2342 }
2343 
2344 static int
2345 jme_intr(void *arg)
2346 {
2347 	struct jme_softc *sc;
2348 	uint32_t status;
2349 
2350 	sc = (struct jme_softc *)arg;
2351 
2352 	status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2353 	if (status == 0 || status == 0xFFFFFFFF)
2354 		return (FILTER_STRAY);
2355 	/* Disable interrupts. */
2356 	CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2357 	taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2358 
2359 	return (FILTER_HANDLED);
2360 }
2361 
2362 static void
2363 jme_int_task(void *arg, int pending)
2364 {
2365 	struct jme_softc *sc;
2366 	struct ifnet *ifp;
2367 	uint32_t status;
2368 	int more;
2369 
2370 	sc = (struct jme_softc *)arg;
2371 	ifp = sc->jme_ifp;
2372 
2373 	JME_LOCK(sc);
2374 	status = CSR_READ_4(sc, JME_INTR_STATUS);
2375 	if (sc->jme_morework != 0) {
2376 		sc->jme_morework = 0;
2377 		status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO;
2378 	}
2379 	if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2380 		goto done;
2381 	/* Reset PCC counter/timer and Ack interrupts. */
2382 	status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2383 	if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
2384 		status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2385 	if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
2386 		status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2387 	CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2388 	more = 0;
2389 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2390 		if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) {
2391 			more = jme_rxintr(sc, sc->jme_process_limit);
2392 			if (more != 0)
2393 				sc->jme_morework = 1;
2394 		}
2395 		if ((status & INTR_RXQ_DESC_EMPTY) != 0) {
2396 			/*
2397 			 * Notify hardware availability of new Rx
2398 			 * buffers.
2399 			 * Reading RXCSR takes very long time under
2400 			 * heavy load so cache RXCSR value and writes
2401 			 * the ORed value with the kick command to
2402 			 * the RXCSR. This saves one register access
2403 			 * cycle.
2404 			 */
2405 			CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2406 			    RXCSR_RX_ENB | RXCSR_RXQ_START);
2407 		}
2408 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2409 			jme_start_locked(ifp);
2410 	}
2411 
2412 	if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {
2413 		taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2414 		JME_UNLOCK(sc);
2415 		return;
2416 	}
2417 done:
2418 	JME_UNLOCK(sc);
2419 
2420 	/* Reenable interrupts. */
2421 	CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2422 }
2423 
2424 static void
2425 jme_txeof(struct jme_softc *sc)
2426 {
2427 	struct ifnet *ifp;
2428 	struct jme_txdesc *txd;
2429 	uint32_t status;
2430 	int cons, nsegs;
2431 
2432 	JME_LOCK_ASSERT(sc);
2433 
2434 	ifp = sc->jme_ifp;
2435 
2436 	cons = sc->jme_cdata.jme_tx_cons;
2437 	if (cons == sc->jme_cdata.jme_tx_prod)
2438 		return;
2439 
2440 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2441 	    sc->jme_cdata.jme_tx_ring_map,
2442 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2443 
2444 	/*
2445 	 * Go through our Tx list and free mbufs for those
2446 	 * frames which have been transmitted.
2447 	 */
2448 	for (; cons != sc->jme_cdata.jme_tx_prod;) {
2449 		txd = &sc->jme_cdata.jme_txdesc[cons];
2450 		status = le32toh(txd->tx_desc->flags);
2451 		if ((status & JME_TD_OWN) == JME_TD_OWN)
2452 			break;
2453 
2454 		if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
2455 			ifp->if_oerrors++;
2456 		else {
2457 			ifp->if_opackets++;
2458 			if ((status & JME_TD_COLLISION) != 0)
2459 				ifp->if_collisions +=
2460 				    le32toh(txd->tx_desc->buflen) &
2461 				    JME_TD_BUF_LEN_MASK;
2462 		}
2463 		/*
2464 		 * Only the first descriptor of multi-descriptor
2465 		 * transmission is updated so driver have to skip entire
2466 		 * chained buffers for the transmiited frame. In other
2467 		 * words, JME_TD_OWN bit is valid only at the first
2468 		 * descriptor of a multi-descriptor transmission.
2469 		 */
2470 		for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2471 			sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2472 			JME_DESC_INC(cons, JME_TX_RING_CNT);
2473 		}
2474 
2475 		/* Reclaim transferred mbufs. */
2476 		bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
2477 		    BUS_DMASYNC_POSTWRITE);
2478 		bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2479 
2480 		KASSERT(txd->tx_m != NULL,
2481 		    ("%s: freeing NULL mbuf!\n", __func__));
2482 		m_freem(txd->tx_m);
2483 		txd->tx_m = NULL;
2484 		sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2485 		KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2486 		    ("%s: Active Tx desc counter was garbled\n", __func__));
2487 		txd->tx_ndesc = 0;
2488 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2489 	}
2490 	sc->jme_cdata.jme_tx_cons = cons;
2491 	/* Unarm watchog timer when there is no pending descriptors in queue. */
2492 	if (sc->jme_cdata.jme_tx_cnt == 0)
2493 		sc->jme_watchdog_timer = 0;
2494 
2495 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2496 	    sc->jme_cdata.jme_tx_ring_map,
2497 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2498 }
2499 
2500 static __inline void
2501 jme_discard_rxbuf(struct jme_softc *sc, int cons)
2502 {
2503 	struct jme_desc *desc;
2504 
2505 	desc = &sc->jme_rdata.jme_rx_ring[cons];
2506 	desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2507 	desc->buflen = htole32(MCLBYTES);
2508 }
2509 
2510 /* Receive a frame. */
2511 static void
2512 jme_rxeof(struct jme_softc *sc)
2513 {
2514 	struct ifnet *ifp;
2515 	struct jme_desc *desc;
2516 	struct jme_rxdesc *rxd;
2517 	struct mbuf *mp, *m;
2518 	uint32_t flags, status;
2519 	int cons, count, nsegs;
2520 
2521 	JME_LOCK_ASSERT(sc);
2522 
2523 	ifp = sc->jme_ifp;
2524 
2525 	cons = sc->jme_cdata.jme_rx_cons;
2526 	desc = &sc->jme_rdata.jme_rx_ring[cons];
2527 	flags = le32toh(desc->flags);
2528 	status = le32toh(desc->buflen);
2529 	nsegs = JME_RX_NSEGS(status);
2530 	sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2531 	if ((status & JME_RX_ERR_STAT) != 0) {
2532 		ifp->if_ierrors++;
2533 		jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons);
2534 #ifdef JME_SHOW_ERRORS
2535 		device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2536 		    __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2537 #endif
2538 		sc->jme_cdata.jme_rx_cons += nsegs;
2539 		sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2540 		return;
2541 	}
2542 
2543 	for (count = 0; count < nsegs; count++,
2544 	    JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2545 		rxd = &sc->jme_cdata.jme_rxdesc[cons];
2546 		mp = rxd->rx_m;
2547 		/* Add a new receive buffer to the ring. */
2548 		if (jme_newbuf(sc, rxd) != 0) {
2549 			ifp->if_iqdrops++;
2550 			/* Reuse buffer. */
2551 			for (; count < nsegs; count++) {
2552 				jme_discard_rxbuf(sc, cons);
2553 				JME_DESC_INC(cons, JME_RX_RING_CNT);
2554 			}
2555 			if (sc->jme_cdata.jme_rxhead != NULL) {
2556 				m_freem(sc->jme_cdata.jme_rxhead);
2557 				JME_RXCHAIN_RESET(sc);
2558 			}
2559 			break;
2560 		}
2561 
2562 		/*
2563 		 * Assume we've received a full sized frame.
2564 		 * Actual size is fixed when we encounter the end of
2565 		 * multi-segmented frame.
2566 		 */
2567 		mp->m_len = MCLBYTES;
2568 
2569 		/* Chain received mbufs. */
2570 		if (sc->jme_cdata.jme_rxhead == NULL) {
2571 			sc->jme_cdata.jme_rxhead = mp;
2572 			sc->jme_cdata.jme_rxtail = mp;
2573 		} else {
2574 			/*
2575 			 * Receive processor can receive a maximum frame
2576 			 * size of 65535 bytes.
2577 			 */
2578 			mp->m_flags &= ~M_PKTHDR;
2579 			sc->jme_cdata.jme_rxtail->m_next = mp;
2580 			sc->jme_cdata.jme_rxtail = mp;
2581 		}
2582 
2583 		if (count == nsegs - 1) {
2584 			/* Last desc. for this frame. */
2585 			m = sc->jme_cdata.jme_rxhead;
2586 			m->m_flags |= M_PKTHDR;
2587 			m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2588 			if (nsegs > 1) {
2589 				/* Set first mbuf size. */
2590 				m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2591 				/* Set last mbuf size. */
2592 				mp->m_len = sc->jme_cdata.jme_rxlen -
2593 				    ((MCLBYTES - JME_RX_PAD_BYTES) +
2594 				    (MCLBYTES * (nsegs - 2)));
2595 			} else
2596 				m->m_len = sc->jme_cdata.jme_rxlen;
2597 			m->m_pkthdr.rcvif = ifp;
2598 
2599 			/*
2600 			 * Account for 10bytes auto padding which is used
2601 			 * to align IP header on 32bit boundary. Also note,
2602 			 * CRC bytes is automatically removed by the
2603 			 * hardware.
2604 			 */
2605 			m->m_data += JME_RX_PAD_BYTES;
2606 
2607 			/* Set checksum information. */
2608 			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2609 			    (flags & JME_RD_IPV4) != 0) {
2610 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2611 				if ((flags & JME_RD_IPCSUM) != 0)
2612 					m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2613 				if (((flags & JME_RD_MORE_FRAG) == 0) &&
2614 				    ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2615 				    (JME_RD_TCP | JME_RD_TCPCSUM) ||
2616 				    (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2617 				    (JME_RD_UDP | JME_RD_UDPCSUM))) {
2618 					m->m_pkthdr.csum_flags |=
2619 					    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2620 					m->m_pkthdr.csum_data = 0xffff;
2621 				}
2622 			}
2623 
2624 			/* Check for VLAN tagged packets. */
2625 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2626 			    (flags & JME_RD_VLAN_TAG) != 0) {
2627 				m->m_pkthdr.ether_vtag =
2628 				    flags & JME_RD_VLAN_MASK;
2629 				m->m_flags |= M_VLANTAG;
2630 			}
2631 
2632 			ifp->if_ipackets++;
2633 			/* Pass it on. */
2634 			JME_UNLOCK(sc);
2635 			(*ifp->if_input)(ifp, m);
2636 			JME_LOCK(sc);
2637 
2638 			/* Reset mbuf chains. */
2639 			JME_RXCHAIN_RESET(sc);
2640 		}
2641 	}
2642 
2643 	sc->jme_cdata.jme_rx_cons += nsegs;
2644 	sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2645 }
2646 
2647 static int
2648 jme_rxintr(struct jme_softc *sc, int count)
2649 {
2650 	struct jme_desc *desc;
2651 	int nsegs, prog, pktlen;
2652 
2653 	bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2654 	    sc->jme_cdata.jme_rx_ring_map,
2655 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2656 
2657 	for (prog = 0; count > 0; prog++) {
2658 		desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2659 		if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2660 			break;
2661 		if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2662 			break;
2663 		nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2664 		/*
2665 		 * Check number of segments against received bytes.
2666 		 * Non-matching value would indicate that hardware
2667 		 * is still trying to update Rx descriptors. I'm not
2668 		 * sure whether this check is needed.
2669 		 */
2670 		pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2671 		if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES))
2672 			break;
2673 		prog++;
2674 		/* Received a frame. */
2675 		jme_rxeof(sc);
2676 		count -= nsegs;
2677 	}
2678 
2679 	if (prog > 0)
2680 		bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2681 		    sc->jme_cdata.jme_rx_ring_map,
2682 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2683 
2684 	return (count > 0 ? 0 : EAGAIN);
2685 }
2686 
2687 static void
2688 jme_tick(void *arg)
2689 {
2690 	struct jme_softc *sc;
2691 	struct mii_data *mii;
2692 
2693 	sc = (struct jme_softc *)arg;
2694 
2695 	JME_LOCK_ASSERT(sc);
2696 
2697 	mii = device_get_softc(sc->jme_miibus);
2698 	mii_tick(mii);
2699 	/*
2700 	 * Reclaim Tx buffers that have been completed. It's not
2701 	 * needed here but it would release allocated mbuf chains
2702 	 * faster and limit the maximum delay to a hz.
2703 	 */
2704 	jme_txeof(sc);
2705 	jme_stats_update(sc);
2706 	jme_watchdog(sc);
2707 	callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2708 }
2709 
2710 static void
2711 jme_reset(struct jme_softc *sc)
2712 {
2713 	uint32_t ghc, gpreg;
2714 
2715 	/* Stop receiver, transmitter. */
2716 	jme_stop_rx(sc);
2717 	jme_stop_tx(sc);
2718 
2719 	/* Reset controller. */
2720 	CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2721 	CSR_READ_4(sc, JME_GHC);
2722 	DELAY(10);
2723 	/*
2724 	 * Workaround Rx FIFO overruns seen under certain conditions.
2725 	 * Explicitly synchorize TX/RX clock.  TX/RX clock should be
2726 	 * enabled only after enabling TX/RX MACs.
2727 	 */
2728 	if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) {
2729 		/* Disable TX clock. */
2730 		CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS);
2731 		/* Disable RX clock. */
2732 		gpreg = CSR_READ_4(sc, JME_GPREG1);
2733 		CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
2734 		gpreg = CSR_READ_4(sc, JME_GPREG1);
2735 		/* De-assert RESET but still disable TX clock. */
2736 		CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
2737 		ghc = CSR_READ_4(sc, JME_GHC);
2738 
2739 		/* Enable TX clock. */
2740 		CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS);
2741 		/* Enable RX clock. */
2742 		CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS);
2743 		CSR_READ_4(sc, JME_GPREG1);
2744 
2745 		/* Disable TX/RX clock again. */
2746 		CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
2747 		CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
2748 	} else
2749 		CSR_WRITE_4(sc, JME_GHC, 0);
2750 	CSR_READ_4(sc, JME_GHC);
2751 	DELAY(10);
2752 }
2753 
2754 static void
2755 jme_init(void *xsc)
2756 {
2757 	struct jme_softc *sc;
2758 
2759 	sc = (struct jme_softc *)xsc;
2760 	JME_LOCK(sc);
2761 	jme_init_locked(sc);
2762 	JME_UNLOCK(sc);
2763 }
2764 
2765 static void
2766 jme_init_locked(struct jme_softc *sc)
2767 {
2768 	struct ifnet *ifp;
2769 	struct mii_data *mii;
2770 	bus_addr_t paddr;
2771 	uint32_t reg;
2772 	int error;
2773 
2774 	JME_LOCK_ASSERT(sc);
2775 
2776 	ifp = sc->jme_ifp;
2777 	mii = device_get_softc(sc->jme_miibus);
2778 
2779 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2780 		return;
2781 	/*
2782 	 * Cancel any pending I/O.
2783 	 */
2784 	jme_stop(sc);
2785 
2786 	/*
2787 	 * Reset the chip to a known state.
2788 	 */
2789 	jme_reset(sc);
2790 
2791 	/* Init descriptors. */
2792 	error = jme_init_rx_ring(sc);
2793         if (error != 0) {
2794                 device_printf(sc->jme_dev,
2795                     "%s: initialization failed: no memory for Rx buffers.\n",
2796 		    __func__);
2797                 jme_stop(sc);
2798 		return;
2799         }
2800 	jme_init_tx_ring(sc);
2801 	/* Initialize shadow status block. */
2802 	jme_init_ssb(sc);
2803 
2804 	/* Reprogram the station address. */
2805 	jme_set_macaddr(sc, IF_LLADDR(sc->jme_ifp));
2806 
2807 	/*
2808 	 * Configure Tx queue.
2809 	 *  Tx priority queue weight value : 0
2810 	 *  Tx FIFO threshold for processing next packet : 16QW
2811 	 *  Maximum Tx DMA length : 512
2812 	 *  Allow Tx DMA burst.
2813 	 */
2814 	sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2815 	sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2816 	sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2817 	sc->jme_txcsr |= sc->jme_tx_dma_size;
2818 	sc->jme_txcsr |= TXCSR_DMA_BURST;
2819 	CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2820 
2821 	/* Set Tx descriptor counter. */
2822 	CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2823 
2824 	/* Set Tx ring address to the hardware. */
2825 	paddr = JME_TX_RING_ADDR(sc, 0);
2826 	CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2827 	CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2828 
2829 	/* Configure TxMAC parameters. */
2830 	reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2831 	reg |= TXMAC_THRESH_1_PKT;
2832 	reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2833 	CSR_WRITE_4(sc, JME_TXMAC, reg);
2834 
2835 	/*
2836 	 * Configure Rx queue.
2837 	 *  FIFO full threshold for transmitting Tx pause packet : 128T
2838 	 *  FIFO threshold for processing next packet : 128QW
2839 	 *  Rx queue 0 select
2840 	 *  Max Rx DMA length : 128
2841 	 *  Rx descriptor retry : 32
2842 	 *  Rx descriptor retry time gap : 256ns
2843 	 *  Don't receive runt/bad frame.
2844 	 */
2845 	sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2846 	/*
2847 	 * Since Rx FIFO size is 4K bytes, receiving frames larger
2848 	 * than 4K bytes will suffer from Rx FIFO overruns. So
2849 	 * decrease FIFO threshold to reduce the FIFO overruns for
2850 	 * frames larger than 4000 bytes.
2851 	 * For best performance of standard MTU sized frames use
2852 	 * maximum allowable FIFO threshold, 128QW. Note these do
2853 	 * not hold on chip full mask verion >=2. For these
2854 	 * controllers 64QW and 128QW are not valid value.
2855 	 */
2856 	if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
2857 		sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2858 	else {
2859 		if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2860 		    ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
2861 			sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2862 		else
2863 			sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2864 	}
2865 	sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2866 	sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2867 	sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2868 	CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2869 
2870 	/* Set Rx descriptor counter. */
2871 	CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2872 
2873 	/* Set Rx ring address to the hardware. */
2874 	paddr = JME_RX_RING_ADDR(sc, 0);
2875 	CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2876 	CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2877 
2878 	/* Clear receive filter. */
2879 	CSR_WRITE_4(sc, JME_RXMAC, 0);
2880 	/* Set up the receive filter. */
2881 	jme_set_filter(sc);
2882 	jme_set_vlan(sc);
2883 
2884 	/*
2885 	 * Disable all WOL bits as WOL can interfere normal Rx
2886 	 * operation. Also clear WOL detection status bits.
2887 	 */
2888 	reg = CSR_READ_4(sc, JME_PMCS);
2889 	reg &= ~PMCS_WOL_ENB_MASK;
2890 	CSR_WRITE_4(sc, JME_PMCS, reg);
2891 
2892 	reg = CSR_READ_4(sc, JME_RXMAC);
2893 	/*
2894 	 * Pad 10bytes right before received frame. This will greatly
2895 	 * help Rx performance on strict-alignment architectures as
2896 	 * it does not need to copy the frame to align the payload.
2897 	 */
2898 	reg |= RXMAC_PAD_10BYTES;
2899 	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2900 		reg |= RXMAC_CSUM_ENB;
2901 	CSR_WRITE_4(sc, JME_RXMAC, reg);
2902 
2903 	/* Configure general purpose reg0 */
2904 	reg = CSR_READ_4(sc, JME_GPREG0);
2905 	reg &= ~GPREG0_PCC_UNIT_MASK;
2906 	/* Set PCC timer resolution to micro-seconds unit. */
2907 	reg |= GPREG0_PCC_UNIT_US;
2908 	/*
2909 	 * Disable all shadow register posting as we have to read
2910 	 * JME_INTR_STATUS register in jme_int_task. Also it seems
2911 	 * that it's hard to synchronize interrupt status between
2912 	 * hardware and software with shadow posting due to
2913 	 * requirements of bus_dmamap_sync(9).
2914 	 */
2915 	reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2916 	    GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2917 	    GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2918 	    GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2919 	/* Disable posting of DW0. */
2920 	reg &= ~GPREG0_POST_DW0_ENB;
2921 	/* Clear PME message. */
2922 	reg &= ~GPREG0_PME_ENB;
2923 	/* Set PHY address. */
2924 	reg &= ~GPREG0_PHY_ADDR_MASK;
2925 	reg |= sc->jme_phyaddr;
2926 	CSR_WRITE_4(sc, JME_GPREG0, reg);
2927 
2928 	/* Configure Tx queue 0 packet completion coalescing. */
2929 	reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2930 	    PCCTX_COAL_TO_MASK;
2931 	reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2932 	    PCCTX_COAL_PKT_MASK;
2933 	reg |= PCCTX_COAL_TXQ0;
2934 	CSR_WRITE_4(sc, JME_PCCTX, reg);
2935 
2936 	/* Configure Rx queue 0 packet completion coalescing. */
2937 	reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2938 	    PCCRX_COAL_TO_MASK;
2939 	reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2940 	    PCCRX_COAL_PKT_MASK;
2941 	CSR_WRITE_4(sc, JME_PCCRX0, reg);
2942 
2943 	/*
2944 	 * Configure PCD(Packet Completion Deferring).  It seems PCD
2945 	 * generates an interrupt when the time interval between two
2946 	 * back-to-back incoming/outgoing packet is long enough for
2947 	 * it to reach its timer value 0. The arrival of new packets
2948 	 * after timer has started causes the PCD timer to restart.
2949 	 * Unfortunately, it's not clear how PCD is useful at this
2950 	 * moment, so just use the same of PCC parameters.
2951 	 */
2952 	if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) {
2953 		sc->jme_rx_pcd_to = sc->jme_rx_coal_to;
2954 		if (sc->jme_rx_coal_to > PCDRX_TO_MAX)
2955 			sc->jme_rx_pcd_to = PCDRX_TO_MAX;
2956 		sc->jme_tx_pcd_to = sc->jme_tx_coal_to;
2957 		if (sc->jme_tx_coal_to > PCDTX_TO_MAX)
2958 			sc->jme_tx_pcd_to = PCDTX_TO_MAX;
2959 		reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT;
2960 		reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT;
2961 		CSR_WRITE_4(sc, PCDRX_REG(0), reg);
2962 		reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT;
2963 		reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT;
2964 		CSR_WRITE_4(sc, JME_PCDTX, reg);
2965 	}
2966 
2967 	/* Configure shadow status block but don't enable posting. */
2968 	paddr = sc->jme_rdata.jme_ssb_block_paddr;
2969 	CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2970 	CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2971 
2972 	/* Disable Timer 1 and Timer 2. */
2973 	CSR_WRITE_4(sc, JME_TIMER1, 0);
2974 	CSR_WRITE_4(sc, JME_TIMER2, 0);
2975 
2976 	/* Configure retry transmit period, retry limit value. */
2977 	CSR_WRITE_4(sc, JME_TXTRHD,
2978 	    ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2979 	    TXTRHD_RT_PERIOD_MASK) |
2980 	    ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2981 	    TXTRHD_RT_LIMIT_SHIFT));
2982 
2983 	/* Disable RSS. */
2984 	CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2985 
2986 	/* Initialize the interrupt mask. */
2987 	CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2988 	CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2989 
2990 	/*
2991 	 * Enabling Tx/Rx DMA engines and Rx queue processing is
2992 	 * done after detection of valid link in jme_link_task.
2993 	 */
2994 
2995 	sc->jme_flags &= ~JME_FLAG_LINK;
2996 	/* Set the current media. */
2997 	mii_mediachg(mii);
2998 
2999 	callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
3000 
3001 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3002 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3003 }
3004 
3005 static void
3006 jme_stop(struct jme_softc *sc)
3007 {
3008 	struct ifnet *ifp;
3009 	struct jme_txdesc *txd;
3010 	struct jme_rxdesc *rxd;
3011 	int i;
3012 
3013 	JME_LOCK_ASSERT(sc);
3014 	/*
3015 	 * Mark the interface down and cancel the watchdog timer.
3016 	 */
3017 	ifp = sc->jme_ifp;
3018 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3019 	sc->jme_flags &= ~JME_FLAG_LINK;
3020 	callout_stop(&sc->jme_tick_ch);
3021 	sc->jme_watchdog_timer = 0;
3022 
3023 	/*
3024 	 * Disable interrupts.
3025 	 */
3026 	CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3027 	CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
3028 
3029 	/* Disable updating shadow status block. */
3030 	CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
3031 	    CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
3032 
3033 	/* Stop receiver, transmitter. */
3034 	jme_stop_rx(sc);
3035 	jme_stop_tx(sc);
3036 
3037 	 /* Reclaim Rx/Tx buffers that have been completed. */
3038 	jme_rxintr(sc, JME_RX_RING_CNT);
3039 	if (sc->jme_cdata.jme_rxhead != NULL)
3040 		m_freem(sc->jme_cdata.jme_rxhead);
3041 	JME_RXCHAIN_RESET(sc);
3042 	jme_txeof(sc);
3043 	/*
3044 	 * Free RX and TX mbufs still in the queues.
3045 	 */
3046 	for (i = 0; i < JME_RX_RING_CNT; i++) {
3047 		rxd = &sc->jme_cdata.jme_rxdesc[i];
3048 		if (rxd->rx_m != NULL) {
3049 			bus_dmamap_sync(sc->jme_cdata.jme_rx_tag,
3050 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3051 			bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
3052 			    rxd->rx_dmamap);
3053 			m_freem(rxd->rx_m);
3054 			rxd->rx_m = NULL;
3055 		}
3056         }
3057 	for (i = 0; i < JME_TX_RING_CNT; i++) {
3058 		txd = &sc->jme_cdata.jme_txdesc[i];
3059 		if (txd->tx_m != NULL) {
3060 			bus_dmamap_sync(sc->jme_cdata.jme_tx_tag,
3061 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3062 			bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
3063 			    txd->tx_dmamap);
3064 			m_freem(txd->tx_m);
3065 			txd->tx_m = NULL;
3066 			txd->tx_ndesc = 0;
3067 		}
3068         }
3069 	jme_stats_update(sc);
3070 	jme_stats_save(sc);
3071 }
3072 
3073 static void
3074 jme_stop_tx(struct jme_softc *sc)
3075 {
3076 	uint32_t reg;
3077 	int i;
3078 
3079 	reg = CSR_READ_4(sc, JME_TXCSR);
3080 	if ((reg & TXCSR_TX_ENB) == 0)
3081 		return;
3082 	reg &= ~TXCSR_TX_ENB;
3083 	CSR_WRITE_4(sc, JME_TXCSR, reg);
3084 	for (i = JME_TIMEOUT; i > 0; i--) {
3085 		DELAY(1);
3086 		if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
3087 			break;
3088 	}
3089 	if (i == 0)
3090 		device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
3091 }
3092 
3093 static void
3094 jme_stop_rx(struct jme_softc *sc)
3095 {
3096 	uint32_t reg;
3097 	int i;
3098 
3099 	reg = CSR_READ_4(sc, JME_RXCSR);
3100 	if ((reg & RXCSR_RX_ENB) == 0)
3101 		return;
3102 	reg &= ~RXCSR_RX_ENB;
3103 	CSR_WRITE_4(sc, JME_RXCSR, reg);
3104 	for (i = JME_TIMEOUT; i > 0; i--) {
3105 		DELAY(1);
3106 		if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
3107 			break;
3108 	}
3109 	if (i == 0)
3110 		device_printf(sc->jme_dev, "stopping recevier timeout!\n");
3111 }
3112 
3113 static void
3114 jme_init_tx_ring(struct jme_softc *sc)
3115 {
3116 	struct jme_ring_data *rd;
3117 	struct jme_txdesc *txd;
3118 	int i;
3119 
3120 	sc->jme_cdata.jme_tx_prod = 0;
3121 	sc->jme_cdata.jme_tx_cons = 0;
3122 	sc->jme_cdata.jme_tx_cnt = 0;
3123 
3124 	rd = &sc->jme_rdata;
3125 	bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
3126 	for (i = 0; i < JME_TX_RING_CNT; i++) {
3127 		txd = &sc->jme_cdata.jme_txdesc[i];
3128 		txd->tx_m = NULL;
3129 		txd->tx_desc = &rd->jme_tx_ring[i];
3130 		txd->tx_ndesc = 0;
3131 	}
3132 
3133 	bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
3134 	    sc->jme_cdata.jme_tx_ring_map,
3135 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3136 }
3137 
3138 static void
3139 jme_init_ssb(struct jme_softc *sc)
3140 {
3141 	struct jme_ring_data *rd;
3142 
3143 	rd = &sc->jme_rdata;
3144 	bzero(rd->jme_ssb_block, JME_SSB_SIZE);
3145 	bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
3146 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3147 }
3148 
3149 static int
3150 jme_init_rx_ring(struct jme_softc *sc)
3151 {
3152 	struct jme_ring_data *rd;
3153 	struct jme_rxdesc *rxd;
3154 	int i;
3155 
3156 	sc->jme_cdata.jme_rx_cons = 0;
3157 	JME_RXCHAIN_RESET(sc);
3158 	sc->jme_morework = 0;
3159 
3160 	rd = &sc->jme_rdata;
3161 	bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
3162 	for (i = 0; i < JME_RX_RING_CNT; i++) {
3163 		rxd = &sc->jme_cdata.jme_rxdesc[i];
3164 		rxd->rx_m = NULL;
3165 		rxd->rx_desc = &rd->jme_rx_ring[i];
3166 		if (jme_newbuf(sc, rxd) != 0)
3167 			return (ENOBUFS);
3168 	}
3169 
3170 	bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
3171 	    sc->jme_cdata.jme_rx_ring_map,
3172 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3173 
3174 	return (0);
3175 }
3176 
3177 static int
3178 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd)
3179 {
3180 	struct jme_desc *desc;
3181 	struct mbuf *m;
3182 	bus_dma_segment_t segs[1];
3183 	bus_dmamap_t map;
3184 	int nsegs;
3185 
3186 	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3187 	if (m == NULL)
3188 		return (ENOBUFS);
3189 	/*
3190 	 * JMC250 has 64bit boundary alignment limitation so jme(4)
3191 	 * takes advantage of 10 bytes padding feature of hardware
3192 	 * in order not to copy entire frame to align IP header on
3193 	 * 32bit boundary.
3194 	 */
3195 	m->m_len = m->m_pkthdr.len = MCLBYTES;
3196 
3197 	if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag,
3198 	    sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3199 		m_freem(m);
3200 		return (ENOBUFS);
3201 	}
3202 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3203 
3204 	if (rxd->rx_m != NULL) {
3205 		bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3206 		    BUS_DMASYNC_POSTREAD);
3207 		bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
3208 	}
3209 	map = rxd->rx_dmamap;
3210 	rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
3211 	sc->jme_cdata.jme_rx_sparemap = map;
3212 	bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3213 	    BUS_DMASYNC_PREREAD);
3214 	rxd->rx_m = m;
3215 
3216 	desc = rxd->rx_desc;
3217 	desc->buflen = htole32(segs[0].ds_len);
3218 	desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr));
3219 	desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr));
3220 	desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
3221 
3222 	return (0);
3223 }
3224 
3225 static void
3226 jme_set_vlan(struct jme_softc *sc)
3227 {
3228 	struct ifnet *ifp;
3229 	uint32_t reg;
3230 
3231 	JME_LOCK_ASSERT(sc);
3232 
3233 	ifp = sc->jme_ifp;
3234 	reg = CSR_READ_4(sc, JME_RXMAC);
3235 	reg &= ~RXMAC_VLAN_ENB;
3236 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3237 		reg |= RXMAC_VLAN_ENB;
3238 	CSR_WRITE_4(sc, JME_RXMAC, reg);
3239 }
3240 
3241 static void
3242 jme_set_filter(struct jme_softc *sc)
3243 {
3244 	struct ifnet *ifp;
3245 	struct ifmultiaddr *ifma;
3246 	uint32_t crc;
3247 	uint32_t mchash[2];
3248 	uint32_t rxcfg;
3249 
3250 	JME_LOCK_ASSERT(sc);
3251 
3252 	ifp = sc->jme_ifp;
3253 
3254 	rxcfg = CSR_READ_4(sc, JME_RXMAC);
3255 	rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3256 	    RXMAC_ALLMULTI);
3257 	/* Always accept frames destined to our station address. */
3258 	rxcfg |= RXMAC_UNICAST;
3259 	if ((ifp->if_flags & IFF_BROADCAST) != 0)
3260 		rxcfg |= RXMAC_BROADCAST;
3261 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3262 		if ((ifp->if_flags & IFF_PROMISC) != 0)
3263 			rxcfg |= RXMAC_PROMISC;
3264 		if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3265 			rxcfg |= RXMAC_ALLMULTI;
3266 		CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3267 		CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3268 		CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3269 		return;
3270 	}
3271 
3272 	/*
3273 	 * Set up the multicast address filter by passing all multicast
3274 	 * addresses through a CRC generator, and then using the low-order
3275 	 * 6 bits as an index into the 64 bit multicast hash table.  The
3276 	 * high order bits select the register, while the rest of the bits
3277 	 * select the bit within the register.
3278 	 */
3279 	rxcfg |= RXMAC_MULTICAST;
3280 	bzero(mchash, sizeof(mchash));
3281 
3282 	if_maddr_rlock(ifp);
3283 	TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) {
3284 		if (ifma->ifma_addr->sa_family != AF_LINK)
3285 			continue;
3286 		crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3287 		    ifma->ifma_addr), ETHER_ADDR_LEN);
3288 
3289 		/* Just want the 6 least significant bits. */
3290 		crc &= 0x3f;
3291 
3292 		/* Set the corresponding bit in the hash table. */
3293 		mchash[crc >> 5] |= 1 << (crc & 0x1f);
3294 	}
3295 	if_maddr_runlock(ifp);
3296 
3297 	CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3298 	CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3299 	CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3300 }
3301 
3302 static void
3303 jme_stats_clear(struct jme_softc *sc)
3304 {
3305 
3306 	JME_LOCK_ASSERT(sc);
3307 
3308 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3309 		return;
3310 
3311 	/* Disable and clear counters. */
3312 	CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3313 	/* Activate hw counters. */
3314 	CSR_WRITE_4(sc, JME_STATCSR, 0);
3315 	CSR_READ_4(sc, JME_STATCSR);
3316 	bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
3317 }
3318 
3319 static void
3320 jme_stats_save(struct jme_softc *sc)
3321 {
3322 
3323 	JME_LOCK_ASSERT(sc);
3324 
3325 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3326 		return;
3327 	/* Save current counters. */
3328 	bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
3329 	/* Disable and clear counters. */
3330 	CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3331 }
3332 
3333 static void
3334 jme_stats_update(struct jme_softc *sc)
3335 {
3336 	struct jme_hw_stats *stat, *ostat;
3337 	uint32_t reg;
3338 
3339 	JME_LOCK_ASSERT(sc);
3340 
3341 	if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3342 		return;
3343 	stat = &sc->jme_stats;
3344 	ostat = &sc->jme_ostats;
3345 	stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
3346 	stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
3347 	reg = CSR_READ_4(sc, JME_STAT_CRCMII);
3348 	stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
3349 	    STAT_RX_CRC_ERR_SHIFT;
3350 	stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
3351 	    STAT_RX_MII_ERR_SHIFT;
3352 	reg = CSR_READ_4(sc, JME_STAT_RXERR);
3353 	stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
3354 	    STAT_RXERR_OFLOW_SHIFT;
3355 	stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
3356 	    STAT_RXERR_MPTY_SHIFT;
3357 	reg = CSR_READ_4(sc, JME_STAT_FAIL);
3358 	stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
3359 	stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
3360 
3361 	/* Account for previous counters. */
3362 	stat->rx_good_frames += ostat->rx_good_frames;
3363 	stat->rx_crc_errs += ostat->rx_crc_errs;
3364 	stat->rx_mii_errs += ostat->rx_mii_errs;
3365 	stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3366 	stat->rx_desc_empty += ostat->rx_desc_empty;
3367 	stat->rx_bad_frames += ostat->rx_bad_frames;
3368 	stat->tx_good_frames += ostat->tx_good_frames;
3369 	stat->tx_bad_frames += ostat->tx_bad_frames;
3370 }
3371 
3372 static void
3373 jme_phy_down(struct jme_softc *sc)
3374 {
3375 	uint32_t reg;
3376 
3377 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN);
3378 	if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
3379 		reg = CSR_READ_4(sc, JME_PHYPOWDN);
3380 		reg |= 0x0000000F;
3381 		CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
3382 		reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
3383 		reg &= ~PE1_GIGA_PDOWN_MASK;
3384 		reg |= PE1_GIGA_PDOWN_D3;
3385 		pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
3386 	}
3387 }
3388 
3389 static void
3390 jme_phy_up(struct jme_softc *sc)
3391 {
3392 	uint32_t reg;
3393 	uint16_t bmcr;
3394 
3395 	bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR);
3396 	bmcr &= ~BMCR_PDOWN;
3397 	jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr);
3398 	if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
3399 		reg = CSR_READ_4(sc, JME_PHYPOWDN);
3400 		reg &= ~0x0000000F;
3401 		CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
3402 		reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
3403 		reg &= ~PE1_GIGA_PDOWN_MASK;
3404 		reg |= PE1_GIGA_PDOWN_DIS;
3405 		pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
3406 	}
3407 }
3408 
3409 static int
3410 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3411 {
3412 	int error, value;
3413 
3414 	if (arg1 == NULL)
3415 		return (EINVAL);
3416 	value = *(int *)arg1;
3417 	error = sysctl_handle_int(oidp, &value, 0, req);
3418 	if (error || req->newptr == NULL)
3419 		return (error);
3420 	if (value < low || value > high)
3421 		return (EINVAL);
3422         *(int *)arg1 = value;
3423 
3424         return (0);
3425 }
3426 
3427 static int
3428 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
3429 {
3430 	return (sysctl_int_range(oidp, arg1, arg2, req,
3431 	    PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
3432 }
3433 
3434 static int
3435 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3436 {
3437 	return (sysctl_int_range(oidp, arg1, arg2, req,
3438 	    PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
3439 }
3440 
3441 static int
3442 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
3443 {
3444 	return (sysctl_int_range(oidp, arg1, arg2, req,
3445 	    PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
3446 }
3447 
3448 static int
3449 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3450 {
3451 	return (sysctl_int_range(oidp, arg1, arg2, req,
3452 	    PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));
3453 }
3454 
3455 static int
3456 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)
3457 {
3458 	return (sysctl_int_range(oidp, arg1, arg2, req,
3459 	    JME_PROC_MIN, JME_PROC_MAX));
3460 }
3461