1a5ebadc6SPyun YongHyeon /*- 2a5ebadc6SPyun YongHyeon * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3a5ebadc6SPyun YongHyeon * All rights reserved. 4a5ebadc6SPyun YongHyeon * 5a5ebadc6SPyun YongHyeon * Redistribution and use in source and binary forms, with or without 6a5ebadc6SPyun YongHyeon * modification, are permitted provided that the following conditions 7a5ebadc6SPyun YongHyeon * are met: 8a5ebadc6SPyun YongHyeon * 1. Redistributions of source code must retain the above copyright 9a5ebadc6SPyun YongHyeon * notice unmodified, this list of conditions, and the following 10a5ebadc6SPyun YongHyeon * disclaimer. 11a5ebadc6SPyun YongHyeon * 2. Redistributions in binary form must reproduce the above copyright 12a5ebadc6SPyun YongHyeon * notice, this list of conditions and the following disclaimer in the 13a5ebadc6SPyun YongHyeon * documentation and/or other materials provided with the distribution. 14a5ebadc6SPyun YongHyeon * 15a5ebadc6SPyun YongHyeon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16a5ebadc6SPyun YongHyeon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17a5ebadc6SPyun YongHyeon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18a5ebadc6SPyun YongHyeon * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19a5ebadc6SPyun YongHyeon * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20a5ebadc6SPyun YongHyeon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21a5ebadc6SPyun YongHyeon * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22a5ebadc6SPyun YongHyeon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23a5ebadc6SPyun YongHyeon * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24a5ebadc6SPyun YongHyeon * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25a5ebadc6SPyun YongHyeon * SUCH DAMAGE. 26a5ebadc6SPyun YongHyeon */ 27a5ebadc6SPyun YongHyeon 28a5ebadc6SPyun YongHyeon #include <sys/cdefs.h> 29a5ebadc6SPyun YongHyeon __FBSDID("$FreeBSD$"); 30a5ebadc6SPyun YongHyeon 31a5ebadc6SPyun YongHyeon #include <sys/param.h> 32a5ebadc6SPyun YongHyeon #include <sys/systm.h> 33a5ebadc6SPyun YongHyeon #include <sys/bus.h> 34a5ebadc6SPyun YongHyeon #include <sys/endian.h> 35a5ebadc6SPyun YongHyeon #include <sys/kernel.h> 36a5ebadc6SPyun YongHyeon #include <sys/malloc.h> 37a5ebadc6SPyun YongHyeon #include <sys/mbuf.h> 38a5ebadc6SPyun YongHyeon #include <sys/rman.h> 39a5ebadc6SPyun YongHyeon #include <sys/module.h> 40a5ebadc6SPyun YongHyeon #include <sys/proc.h> 41a5ebadc6SPyun YongHyeon #include <sys/queue.h> 42a5ebadc6SPyun YongHyeon #include <sys/socket.h> 43a5ebadc6SPyun YongHyeon #include <sys/sockio.h> 44a5ebadc6SPyun YongHyeon #include <sys/sysctl.h> 45a5ebadc6SPyun YongHyeon #include <sys/taskqueue.h> 46a5ebadc6SPyun YongHyeon 47a5ebadc6SPyun YongHyeon #include <net/bpf.h> 48a5ebadc6SPyun YongHyeon #include <net/if.h> 49a5ebadc6SPyun YongHyeon #include <net/if_arp.h> 50a5ebadc6SPyun YongHyeon #include <net/ethernet.h> 51a5ebadc6SPyun YongHyeon #include <net/if_dl.h> 52a5ebadc6SPyun YongHyeon #include <net/if_media.h> 53a5ebadc6SPyun YongHyeon #include <net/if_types.h> 54a5ebadc6SPyun YongHyeon #include <net/if_vlan_var.h> 55a5ebadc6SPyun YongHyeon 56a5ebadc6SPyun YongHyeon #include <netinet/in.h> 57a5ebadc6SPyun YongHyeon #include <netinet/in_systm.h> 58a5ebadc6SPyun YongHyeon #include <netinet/ip.h> 59a5ebadc6SPyun YongHyeon #include <netinet/tcp.h> 60a5ebadc6SPyun YongHyeon 61a5ebadc6SPyun YongHyeon #include <dev/mii/mii.h> 62a5ebadc6SPyun YongHyeon #include <dev/mii/miivar.h> 63a5ebadc6SPyun YongHyeon 64a5ebadc6SPyun YongHyeon #include <dev/pci/pcireg.h> 65a5ebadc6SPyun YongHyeon #include <dev/pci/pcivar.h> 66a5ebadc6SPyun YongHyeon 67a5ebadc6SPyun YongHyeon #include <machine/bus.h> 68a5ebadc6SPyun YongHyeon #include <machine/in_cksum.h> 69a5ebadc6SPyun YongHyeon 70a5ebadc6SPyun YongHyeon #include <dev/jme/if_jmereg.h> 71a5ebadc6SPyun YongHyeon #include <dev/jme/if_jmevar.h> 72a5ebadc6SPyun YongHyeon 73a5ebadc6SPyun YongHyeon /* "device miibus" required. See GENERIC if you get errors here. */ 74a5ebadc6SPyun YongHyeon #include "miibus_if.h" 75a5ebadc6SPyun YongHyeon 76a5ebadc6SPyun YongHyeon /* Define the following to disable printing Rx errors. */ 77a5ebadc6SPyun YongHyeon #undef JME_SHOW_ERRORS 78a5ebadc6SPyun YongHyeon 79a5ebadc6SPyun YongHyeon #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 80a5ebadc6SPyun YongHyeon 81a5ebadc6SPyun YongHyeon MODULE_DEPEND(jme, pci, 1, 1, 1); 82a5ebadc6SPyun YongHyeon MODULE_DEPEND(jme, ether, 1, 1, 1); 83a5ebadc6SPyun YongHyeon MODULE_DEPEND(jme, miibus, 1, 1, 1); 84a5ebadc6SPyun YongHyeon 85a5ebadc6SPyun YongHyeon /* Tunables. */ 86a5ebadc6SPyun YongHyeon static int msi_disable = 0; 87a5ebadc6SPyun YongHyeon static int msix_disable = 0; 88a5ebadc6SPyun YongHyeon TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 89a5ebadc6SPyun YongHyeon TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 90a5ebadc6SPyun YongHyeon 91a5ebadc6SPyun YongHyeon /* 92a5ebadc6SPyun YongHyeon * Devices supported by this driver. 93a5ebadc6SPyun YongHyeon */ 94a5ebadc6SPyun YongHyeon static struct jme_dev { 95a5ebadc6SPyun YongHyeon uint16_t jme_vendorid; 96a5ebadc6SPyun YongHyeon uint16_t jme_deviceid; 97a5ebadc6SPyun YongHyeon const char *jme_name; 98a5ebadc6SPyun YongHyeon } jme_devs[] = { 99a5ebadc6SPyun YongHyeon { VENDORID_JMICRON, DEVICEID_JMC250, 100a5ebadc6SPyun YongHyeon "JMicron Inc, JMC250 Gigabit Ethernet" }, 101a5ebadc6SPyun YongHyeon { VENDORID_JMICRON, DEVICEID_JMC260, 102a5ebadc6SPyun YongHyeon "JMicron Inc, JMC260 Fast Ethernet" }, 103a5ebadc6SPyun YongHyeon }; 104a5ebadc6SPyun YongHyeon 105a5ebadc6SPyun YongHyeon static int jme_miibus_readreg(device_t, int, int); 106a5ebadc6SPyun YongHyeon static int jme_miibus_writereg(device_t, int, int, int); 107a5ebadc6SPyun YongHyeon static void jme_miibus_statchg(device_t); 108a5ebadc6SPyun YongHyeon static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 109a5ebadc6SPyun YongHyeon static int jme_mediachange(struct ifnet *); 110a5ebadc6SPyun YongHyeon static int jme_probe(device_t); 111a5ebadc6SPyun YongHyeon static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 112a5ebadc6SPyun YongHyeon static int jme_eeprom_macaddr(struct jme_softc *); 113a5ebadc6SPyun YongHyeon static void jme_reg_macaddr(struct jme_softc *); 114a5ebadc6SPyun YongHyeon static void jme_map_intr_vector(struct jme_softc *); 115a5ebadc6SPyun YongHyeon static int jme_attach(device_t); 116a5ebadc6SPyun YongHyeon static int jme_detach(device_t); 117a5ebadc6SPyun YongHyeon static void jme_sysctl_node(struct jme_softc *); 118a5ebadc6SPyun YongHyeon static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 119a5ebadc6SPyun YongHyeon static int jme_dma_alloc(struct jme_softc *); 120a5ebadc6SPyun YongHyeon static void jme_dma_free(struct jme_softc *); 121a5ebadc6SPyun YongHyeon static int jme_shutdown(device_t); 122a5ebadc6SPyun YongHyeon static void jme_setlinkspeed(struct jme_softc *); 123a5ebadc6SPyun YongHyeon static void jme_setwol(struct jme_softc *); 124a5ebadc6SPyun YongHyeon static int jme_suspend(device_t); 125a5ebadc6SPyun YongHyeon static int jme_resume(device_t); 126a5ebadc6SPyun YongHyeon static int jme_encap(struct jme_softc *, struct mbuf **); 127a5ebadc6SPyun YongHyeon static void jme_tx_task(void *, int); 128a5ebadc6SPyun YongHyeon static void jme_start(struct ifnet *); 129a5ebadc6SPyun YongHyeon static void jme_watchdog(struct jme_softc *); 130a5ebadc6SPyun YongHyeon static int jme_ioctl(struct ifnet *, u_long, caddr_t); 131a5ebadc6SPyun YongHyeon static void jme_mac_config(struct jme_softc *); 132a5ebadc6SPyun YongHyeon static void jme_link_task(void *, int); 133a5ebadc6SPyun YongHyeon static int jme_intr(void *); 134a5ebadc6SPyun YongHyeon static void jme_int_task(void *, int); 135a5ebadc6SPyun YongHyeon static void jme_txeof(struct jme_softc *); 136a5ebadc6SPyun YongHyeon static __inline void jme_discard_rxbuf(struct jme_softc *, int); 137a5ebadc6SPyun YongHyeon static void jme_rxeof(struct jme_softc *); 138a5ebadc6SPyun YongHyeon static int jme_rxintr(struct jme_softc *, int); 139a5ebadc6SPyun YongHyeon static void jme_tick(void *); 140a5ebadc6SPyun YongHyeon static void jme_reset(struct jme_softc *); 141a5ebadc6SPyun YongHyeon static void jme_init(void *); 142a5ebadc6SPyun YongHyeon static void jme_init_locked(struct jme_softc *); 143a5ebadc6SPyun YongHyeon static void jme_stop(struct jme_softc *); 144a5ebadc6SPyun YongHyeon static void jme_stop_tx(struct jme_softc *); 145a5ebadc6SPyun YongHyeon static void jme_stop_rx(struct jme_softc *); 146a5ebadc6SPyun YongHyeon static int jme_init_rx_ring(struct jme_softc *); 147a5ebadc6SPyun YongHyeon static void jme_init_tx_ring(struct jme_softc *); 148a5ebadc6SPyun YongHyeon static void jme_init_ssb(struct jme_softc *); 149a5ebadc6SPyun YongHyeon static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 150a5ebadc6SPyun YongHyeon static void jme_set_vlan(struct jme_softc *); 151a5ebadc6SPyun YongHyeon static void jme_set_filter(struct jme_softc *); 152450ab472SPyun YongHyeon static void jme_stats_clear(struct jme_softc *); 153450ab472SPyun YongHyeon static void jme_stats_save(struct jme_softc *); 154450ab472SPyun YongHyeon static void jme_stats_update(struct jme_softc *); 155a5ebadc6SPyun YongHyeon static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 156a5ebadc6SPyun YongHyeon static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 157a5ebadc6SPyun YongHyeon static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 158a5ebadc6SPyun YongHyeon static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 159a5ebadc6SPyun YongHyeon static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 160a5ebadc6SPyun YongHyeon static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 161a5ebadc6SPyun YongHyeon 162a5ebadc6SPyun YongHyeon 163a5ebadc6SPyun YongHyeon static device_method_t jme_methods[] = { 164a5ebadc6SPyun YongHyeon /* Device interface. */ 165a5ebadc6SPyun YongHyeon DEVMETHOD(device_probe, jme_probe), 166a5ebadc6SPyun YongHyeon DEVMETHOD(device_attach, jme_attach), 167a5ebadc6SPyun YongHyeon DEVMETHOD(device_detach, jme_detach), 168a5ebadc6SPyun YongHyeon DEVMETHOD(device_shutdown, jme_shutdown), 169a5ebadc6SPyun YongHyeon DEVMETHOD(device_suspend, jme_suspend), 170a5ebadc6SPyun YongHyeon DEVMETHOD(device_resume, jme_resume), 171a5ebadc6SPyun YongHyeon 172a5ebadc6SPyun YongHyeon /* MII interface. */ 173a5ebadc6SPyun YongHyeon DEVMETHOD(miibus_readreg, jme_miibus_readreg), 174a5ebadc6SPyun YongHyeon DEVMETHOD(miibus_writereg, jme_miibus_writereg), 175a5ebadc6SPyun YongHyeon DEVMETHOD(miibus_statchg, jme_miibus_statchg), 176a5ebadc6SPyun YongHyeon 177a5ebadc6SPyun YongHyeon { NULL, NULL } 178a5ebadc6SPyun YongHyeon }; 179a5ebadc6SPyun YongHyeon 180a5ebadc6SPyun YongHyeon static driver_t jme_driver = { 181a5ebadc6SPyun YongHyeon "jme", 182a5ebadc6SPyun YongHyeon jme_methods, 183a5ebadc6SPyun YongHyeon sizeof(struct jme_softc) 184a5ebadc6SPyun YongHyeon }; 185a5ebadc6SPyun YongHyeon 186a5ebadc6SPyun YongHyeon static devclass_t jme_devclass; 187a5ebadc6SPyun YongHyeon 188a5ebadc6SPyun YongHyeon DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0); 189a5ebadc6SPyun YongHyeon DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0); 190a5ebadc6SPyun YongHyeon 191a5ebadc6SPyun YongHyeon static struct resource_spec jme_res_spec_mem[] = { 192a5ebadc6SPyun YongHyeon { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 193a5ebadc6SPyun YongHyeon { -1, 0, 0 } 194a5ebadc6SPyun YongHyeon }; 195a5ebadc6SPyun YongHyeon 196a5ebadc6SPyun YongHyeon static struct resource_spec jme_irq_spec_legacy[] = { 197a5ebadc6SPyun YongHyeon { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 198a5ebadc6SPyun YongHyeon { -1, 0, 0 } 199a5ebadc6SPyun YongHyeon }; 200a5ebadc6SPyun YongHyeon 201a5ebadc6SPyun YongHyeon static struct resource_spec jme_irq_spec_msi[] = { 202a5ebadc6SPyun YongHyeon { SYS_RES_IRQ, 1, RF_ACTIVE }, 203a5ebadc6SPyun YongHyeon { -1, 0, 0 } 204a5ebadc6SPyun YongHyeon }; 205a5ebadc6SPyun YongHyeon 206a5ebadc6SPyun YongHyeon /* 207a5ebadc6SPyun YongHyeon * Read a PHY register on the MII of the JMC250. 208a5ebadc6SPyun YongHyeon */ 209a5ebadc6SPyun YongHyeon static int 210a5ebadc6SPyun YongHyeon jme_miibus_readreg(device_t dev, int phy, int reg) 211a5ebadc6SPyun YongHyeon { 212a5ebadc6SPyun YongHyeon struct jme_softc *sc; 213a5ebadc6SPyun YongHyeon uint32_t val; 214a5ebadc6SPyun YongHyeon int i; 215a5ebadc6SPyun YongHyeon 216a5ebadc6SPyun YongHyeon sc = device_get_softc(dev); 217a5ebadc6SPyun YongHyeon 218a5ebadc6SPyun YongHyeon /* For FPGA version, PHY address 0 should be ignored. */ 2198e5d93dbSMarius Strobl if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 220a5ebadc6SPyun YongHyeon return (0); 221a5ebadc6SPyun YongHyeon 222a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 223a5ebadc6SPyun YongHyeon SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 224a5ebadc6SPyun YongHyeon for (i = JME_PHY_TIMEOUT; i > 0; i--) { 225a5ebadc6SPyun YongHyeon DELAY(1); 226a5ebadc6SPyun YongHyeon if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 227a5ebadc6SPyun YongHyeon break; 228a5ebadc6SPyun YongHyeon } 229a5ebadc6SPyun YongHyeon 230a5ebadc6SPyun YongHyeon if (i == 0) { 231a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 232a5ebadc6SPyun YongHyeon return (0); 233a5ebadc6SPyun YongHyeon } 234a5ebadc6SPyun YongHyeon 235a5ebadc6SPyun YongHyeon return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 236a5ebadc6SPyun YongHyeon } 237a5ebadc6SPyun YongHyeon 238a5ebadc6SPyun YongHyeon /* 239a5ebadc6SPyun YongHyeon * Write a PHY register on the MII of the JMC250. 240a5ebadc6SPyun YongHyeon */ 241a5ebadc6SPyun YongHyeon static int 242a5ebadc6SPyun YongHyeon jme_miibus_writereg(device_t dev, int phy, int reg, int val) 243a5ebadc6SPyun YongHyeon { 244a5ebadc6SPyun YongHyeon struct jme_softc *sc; 245a5ebadc6SPyun YongHyeon int i; 246a5ebadc6SPyun YongHyeon 247a5ebadc6SPyun YongHyeon sc = device_get_softc(dev); 248a5ebadc6SPyun YongHyeon 249a5ebadc6SPyun YongHyeon /* For FPGA version, PHY address 0 should be ignored. */ 2508e5d93dbSMarius Strobl if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 251a5ebadc6SPyun YongHyeon return (0); 252a5ebadc6SPyun YongHyeon 253a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 254a5ebadc6SPyun YongHyeon ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 255a5ebadc6SPyun YongHyeon SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 256a5ebadc6SPyun YongHyeon for (i = JME_PHY_TIMEOUT; i > 0; i--) { 257a5ebadc6SPyun YongHyeon DELAY(1); 258a5ebadc6SPyun YongHyeon if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 259a5ebadc6SPyun YongHyeon break; 260a5ebadc6SPyun YongHyeon } 261a5ebadc6SPyun YongHyeon 262a5ebadc6SPyun YongHyeon if (i == 0) 263a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 264a5ebadc6SPyun YongHyeon 265a5ebadc6SPyun YongHyeon return (0); 266a5ebadc6SPyun YongHyeon } 267a5ebadc6SPyun YongHyeon 268a5ebadc6SPyun YongHyeon /* 269a5ebadc6SPyun YongHyeon * Callback from MII layer when media changes. 270a5ebadc6SPyun YongHyeon */ 271a5ebadc6SPyun YongHyeon static void 272a5ebadc6SPyun YongHyeon jme_miibus_statchg(device_t dev) 273a5ebadc6SPyun YongHyeon { 274a5ebadc6SPyun YongHyeon struct jme_softc *sc; 275a5ebadc6SPyun YongHyeon 276a5ebadc6SPyun YongHyeon sc = device_get_softc(dev); 277a5ebadc6SPyun YongHyeon taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 278a5ebadc6SPyun YongHyeon } 279a5ebadc6SPyun YongHyeon 280a5ebadc6SPyun YongHyeon /* 281a5ebadc6SPyun YongHyeon * Get the current interface media status. 282a5ebadc6SPyun YongHyeon */ 283a5ebadc6SPyun YongHyeon static void 284a5ebadc6SPyun YongHyeon jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 285a5ebadc6SPyun YongHyeon { 286a5ebadc6SPyun YongHyeon struct jme_softc *sc; 287a5ebadc6SPyun YongHyeon struct mii_data *mii; 288a5ebadc6SPyun YongHyeon 289a5ebadc6SPyun YongHyeon sc = ifp->if_softc; 290a5ebadc6SPyun YongHyeon JME_LOCK(sc); 29132f8942aSPyun YongHyeon if ((ifp->if_flags & IFF_UP) == 0) { 29232f8942aSPyun YongHyeon JME_UNLOCK(sc); 29332f8942aSPyun YongHyeon return; 29432f8942aSPyun YongHyeon } 295a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 296a5ebadc6SPyun YongHyeon 297a5ebadc6SPyun YongHyeon mii_pollstat(mii); 298a5ebadc6SPyun YongHyeon ifmr->ifm_status = mii->mii_media_status; 299a5ebadc6SPyun YongHyeon ifmr->ifm_active = mii->mii_media_active; 300a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 301a5ebadc6SPyun YongHyeon } 302a5ebadc6SPyun YongHyeon 303a5ebadc6SPyun YongHyeon /* 304a5ebadc6SPyun YongHyeon * Set hardware to newly-selected media. 305a5ebadc6SPyun YongHyeon */ 306a5ebadc6SPyun YongHyeon static int 307a5ebadc6SPyun YongHyeon jme_mediachange(struct ifnet *ifp) 308a5ebadc6SPyun YongHyeon { 309a5ebadc6SPyun YongHyeon struct jme_softc *sc; 310a5ebadc6SPyun YongHyeon struct mii_data *mii; 311a5ebadc6SPyun YongHyeon struct mii_softc *miisc; 312a5ebadc6SPyun YongHyeon int error; 313a5ebadc6SPyun YongHyeon 314a5ebadc6SPyun YongHyeon sc = ifp->if_softc; 315a5ebadc6SPyun YongHyeon JME_LOCK(sc); 316a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 317a5ebadc6SPyun YongHyeon if (mii->mii_instance != 0) { 318a5ebadc6SPyun YongHyeon LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 319a5ebadc6SPyun YongHyeon mii_phy_reset(miisc); 320a5ebadc6SPyun YongHyeon } 321a5ebadc6SPyun YongHyeon error = mii_mediachg(mii); 322a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 323a5ebadc6SPyun YongHyeon 324a5ebadc6SPyun YongHyeon return (error); 325a5ebadc6SPyun YongHyeon } 326a5ebadc6SPyun YongHyeon 327a5ebadc6SPyun YongHyeon static int 328a5ebadc6SPyun YongHyeon jme_probe(device_t dev) 329a5ebadc6SPyun YongHyeon { 330a5ebadc6SPyun YongHyeon struct jme_dev *sp; 331a5ebadc6SPyun YongHyeon int i; 332a5ebadc6SPyun YongHyeon uint16_t vendor, devid; 333a5ebadc6SPyun YongHyeon 334a5ebadc6SPyun YongHyeon vendor = pci_get_vendor(dev); 335a5ebadc6SPyun YongHyeon devid = pci_get_device(dev); 336a5ebadc6SPyun YongHyeon sp = jme_devs; 337a5ebadc6SPyun YongHyeon for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]); 338a5ebadc6SPyun YongHyeon i++, sp++) { 339a5ebadc6SPyun YongHyeon if (vendor == sp->jme_vendorid && 340a5ebadc6SPyun YongHyeon devid == sp->jme_deviceid) { 341a5ebadc6SPyun YongHyeon device_set_desc(dev, sp->jme_name); 342a5ebadc6SPyun YongHyeon return (BUS_PROBE_DEFAULT); 343a5ebadc6SPyun YongHyeon } 344a5ebadc6SPyun YongHyeon } 345a5ebadc6SPyun YongHyeon 346a5ebadc6SPyun YongHyeon return (ENXIO); 347a5ebadc6SPyun YongHyeon } 348a5ebadc6SPyun YongHyeon 349a5ebadc6SPyun YongHyeon static int 350a5ebadc6SPyun YongHyeon jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 351a5ebadc6SPyun YongHyeon { 352a5ebadc6SPyun YongHyeon uint32_t reg; 353a5ebadc6SPyun YongHyeon int i; 354a5ebadc6SPyun YongHyeon 355a5ebadc6SPyun YongHyeon *val = 0; 356a5ebadc6SPyun YongHyeon for (i = JME_TIMEOUT; i > 0; i--) { 357a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_SMBCSR); 358a5ebadc6SPyun YongHyeon if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 359a5ebadc6SPyun YongHyeon break; 360a5ebadc6SPyun YongHyeon DELAY(1); 361a5ebadc6SPyun YongHyeon } 362a5ebadc6SPyun YongHyeon 363a5ebadc6SPyun YongHyeon if (i == 0) { 364a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 365a5ebadc6SPyun YongHyeon return (ETIMEDOUT); 366a5ebadc6SPyun YongHyeon } 367a5ebadc6SPyun YongHyeon 368a5ebadc6SPyun YongHyeon reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 369a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 370a5ebadc6SPyun YongHyeon for (i = JME_TIMEOUT; i > 0; i--) { 371a5ebadc6SPyun YongHyeon DELAY(1); 372a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_SMBINTF); 373a5ebadc6SPyun YongHyeon if ((reg & SMBINTF_CMD_TRIGGER) == 0) 374a5ebadc6SPyun YongHyeon break; 375a5ebadc6SPyun YongHyeon } 376a5ebadc6SPyun YongHyeon 377a5ebadc6SPyun YongHyeon if (i == 0) { 378a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 379a5ebadc6SPyun YongHyeon return (ETIMEDOUT); 380a5ebadc6SPyun YongHyeon } 381a5ebadc6SPyun YongHyeon 382a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_SMBINTF); 383a5ebadc6SPyun YongHyeon *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 384a5ebadc6SPyun YongHyeon 385a5ebadc6SPyun YongHyeon return (0); 386a5ebadc6SPyun YongHyeon } 387a5ebadc6SPyun YongHyeon 388a5ebadc6SPyun YongHyeon static int 389a5ebadc6SPyun YongHyeon jme_eeprom_macaddr(struct jme_softc *sc) 390a5ebadc6SPyun YongHyeon { 391a5ebadc6SPyun YongHyeon uint8_t eaddr[ETHER_ADDR_LEN]; 392a5ebadc6SPyun YongHyeon uint8_t fup, reg, val; 393a5ebadc6SPyun YongHyeon uint32_t offset; 394a5ebadc6SPyun YongHyeon int match; 395a5ebadc6SPyun YongHyeon 396a5ebadc6SPyun YongHyeon offset = 0; 397a5ebadc6SPyun YongHyeon if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 398a5ebadc6SPyun YongHyeon fup != JME_EEPROM_SIG0) 399a5ebadc6SPyun YongHyeon return (ENOENT); 400a5ebadc6SPyun YongHyeon if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 401a5ebadc6SPyun YongHyeon fup != JME_EEPROM_SIG1) 402a5ebadc6SPyun YongHyeon return (ENOENT); 403a5ebadc6SPyun YongHyeon match = 0; 404a5ebadc6SPyun YongHyeon do { 405a5ebadc6SPyun YongHyeon if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 406a5ebadc6SPyun YongHyeon break; 40708c23fcaSPyun YongHyeon if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 40808c23fcaSPyun YongHyeon (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 409a5ebadc6SPyun YongHyeon if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 410a5ebadc6SPyun YongHyeon break; 411a5ebadc6SPyun YongHyeon if (reg >= JME_PAR0 && 412a5ebadc6SPyun YongHyeon reg < JME_PAR0 + ETHER_ADDR_LEN) { 413a5ebadc6SPyun YongHyeon if (jme_eeprom_read_byte(sc, offset + 2, 414a5ebadc6SPyun YongHyeon &val) != 0) 415a5ebadc6SPyun YongHyeon break; 416a5ebadc6SPyun YongHyeon eaddr[reg - JME_PAR0] = val; 417a5ebadc6SPyun YongHyeon match++; 418a5ebadc6SPyun YongHyeon } 419a5ebadc6SPyun YongHyeon } 42008c23fcaSPyun YongHyeon /* Check for the end of EEPROM descriptor. */ 42108c23fcaSPyun YongHyeon if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 42208c23fcaSPyun YongHyeon break; 423a5ebadc6SPyun YongHyeon /* Try next eeprom descriptor. */ 424a5ebadc6SPyun YongHyeon offset += JME_EEPROM_DESC_BYTES; 425a5ebadc6SPyun YongHyeon } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 426a5ebadc6SPyun YongHyeon 427a5ebadc6SPyun YongHyeon if (match == ETHER_ADDR_LEN) { 428a5ebadc6SPyun YongHyeon bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 429a5ebadc6SPyun YongHyeon return (0); 430a5ebadc6SPyun YongHyeon } 431a5ebadc6SPyun YongHyeon 432a5ebadc6SPyun YongHyeon return (ENOENT); 433a5ebadc6SPyun YongHyeon } 434a5ebadc6SPyun YongHyeon 435a5ebadc6SPyun YongHyeon static void 436a5ebadc6SPyun YongHyeon jme_reg_macaddr(struct jme_softc *sc) 437a5ebadc6SPyun YongHyeon { 438a5ebadc6SPyun YongHyeon uint32_t par0, par1; 439a5ebadc6SPyun YongHyeon 440a5ebadc6SPyun YongHyeon /* Read station address. */ 441a5ebadc6SPyun YongHyeon par0 = CSR_READ_4(sc, JME_PAR0); 442a5ebadc6SPyun YongHyeon par1 = CSR_READ_4(sc, JME_PAR1); 443a5ebadc6SPyun YongHyeon par1 &= 0xFFFF; 444a5ebadc6SPyun YongHyeon if ((par0 == 0 && par1 == 0) || 445a5ebadc6SPyun YongHyeon (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 446a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 44751d930e7SGavin Atkinson "Failed to retrieve Ethernet address.\n"); 448a5ebadc6SPyun YongHyeon } else { 449a5ebadc6SPyun YongHyeon sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 450a5ebadc6SPyun YongHyeon sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 451a5ebadc6SPyun YongHyeon sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 452a5ebadc6SPyun YongHyeon sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 453a5ebadc6SPyun YongHyeon sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 454a5ebadc6SPyun YongHyeon sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 455a5ebadc6SPyun YongHyeon } 456a5ebadc6SPyun YongHyeon } 457a5ebadc6SPyun YongHyeon 458a5ebadc6SPyun YongHyeon static void 459a5ebadc6SPyun YongHyeon jme_map_intr_vector(struct jme_softc *sc) 460a5ebadc6SPyun YongHyeon { 461a5ebadc6SPyun YongHyeon uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 462a5ebadc6SPyun YongHyeon 463a5ebadc6SPyun YongHyeon bzero(map, sizeof(map)); 464a5ebadc6SPyun YongHyeon 465a5ebadc6SPyun YongHyeon /* Map Tx interrupts source to MSI/MSIX vector 2. */ 466a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 467a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 468a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 469a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 470a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 471a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 472a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 473a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 474a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 475a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 476a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 477a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 478a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 479a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 480a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 481a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 482a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 483a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 484a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 485a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 486a5ebadc6SPyun YongHyeon 487a5ebadc6SPyun YongHyeon /* Map Rx interrupts source to MSI/MSIX vector 1. */ 488a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 489a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 490a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 491a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 492a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 493a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 494a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 495a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 496a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 497a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 498a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 499a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 500a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 501a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 502a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 503a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 504a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 505a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 506a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 507a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 508a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 509a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 510a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 511a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 512a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 513a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 514a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 515a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 516a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 517a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 518a5ebadc6SPyun YongHyeon map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 519a5ebadc6SPyun YongHyeon MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 520a5ebadc6SPyun YongHyeon 521a5ebadc6SPyun YongHyeon /* Map all other interrupts source to MSI/MSIX vector 0. */ 522a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 523a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 524a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 525a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 526a5ebadc6SPyun YongHyeon } 527a5ebadc6SPyun YongHyeon 528a5ebadc6SPyun YongHyeon static int 529a5ebadc6SPyun YongHyeon jme_attach(device_t dev) 530a5ebadc6SPyun YongHyeon { 531a5ebadc6SPyun YongHyeon struct jme_softc *sc; 532a5ebadc6SPyun YongHyeon struct ifnet *ifp; 533a5ebadc6SPyun YongHyeon struct mii_softc *miisc; 534a5ebadc6SPyun YongHyeon struct mii_data *mii; 535a5ebadc6SPyun YongHyeon uint32_t reg; 536a5ebadc6SPyun YongHyeon uint16_t burst; 537a5ebadc6SPyun YongHyeon int error, i, msic, msixc, pmc; 538a5ebadc6SPyun YongHyeon 539a5ebadc6SPyun YongHyeon error = 0; 540a5ebadc6SPyun YongHyeon sc = device_get_softc(dev); 541a5ebadc6SPyun YongHyeon sc->jme_dev = dev; 542a5ebadc6SPyun YongHyeon 543a5ebadc6SPyun YongHyeon mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 544a5ebadc6SPyun YongHyeon MTX_DEF); 545a5ebadc6SPyun YongHyeon callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 546a5ebadc6SPyun YongHyeon TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 547a5ebadc6SPyun YongHyeon TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 548a5ebadc6SPyun YongHyeon 549a5ebadc6SPyun YongHyeon /* 550a5ebadc6SPyun YongHyeon * Map the device. JMC250 supports both memory mapped and I/O 551a5ebadc6SPyun YongHyeon * register space access. Because I/O register access should 552a5ebadc6SPyun YongHyeon * use different BARs to access registers it's waste of time 553a5ebadc6SPyun YongHyeon * to use I/O register spce access. JMC250 uses 16K to map 554a5ebadc6SPyun YongHyeon * entire memory space. 555a5ebadc6SPyun YongHyeon */ 556a5ebadc6SPyun YongHyeon pci_enable_busmaster(dev); 557a5ebadc6SPyun YongHyeon sc->jme_res_spec = jme_res_spec_mem; 558a5ebadc6SPyun YongHyeon sc->jme_irq_spec = jme_irq_spec_legacy; 559a5ebadc6SPyun YongHyeon error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 560a5ebadc6SPyun YongHyeon if (error != 0) { 561a5ebadc6SPyun YongHyeon device_printf(dev, "cannot allocate memory resources.\n"); 562a5ebadc6SPyun YongHyeon goto fail; 563a5ebadc6SPyun YongHyeon } 564a5ebadc6SPyun YongHyeon 565a5ebadc6SPyun YongHyeon /* Allocate IRQ resources. */ 566a5ebadc6SPyun YongHyeon msixc = pci_msix_count(dev); 567a5ebadc6SPyun YongHyeon msic = pci_msi_count(dev); 568a5ebadc6SPyun YongHyeon if (bootverbose) { 569a5ebadc6SPyun YongHyeon device_printf(dev, "MSIX count : %d\n", msixc); 570a5ebadc6SPyun YongHyeon device_printf(dev, "MSI count : %d\n", msic); 571a5ebadc6SPyun YongHyeon } 572a5ebadc6SPyun YongHyeon 5737bcbe6cbSPyun YongHyeon /* Use 1 MSI/MSI-X. */ 5747bcbe6cbSPyun YongHyeon if (msixc > 1) 5757bcbe6cbSPyun YongHyeon msixc = 1; 5767bcbe6cbSPyun YongHyeon if (msic > 1) 5777bcbe6cbSPyun YongHyeon msic = 1; 578a5ebadc6SPyun YongHyeon /* Prefer MSIX over MSI. */ 579a5ebadc6SPyun YongHyeon if (msix_disable == 0 || msi_disable == 0) { 5807bcbe6cbSPyun YongHyeon if (msix_disable == 0 && msixc > 0 && 581a5ebadc6SPyun YongHyeon pci_alloc_msix(dev, &msixc) == 0) { 5827bcbe6cbSPyun YongHyeon if (msixc == 1) { 583a5ebadc6SPyun YongHyeon device_printf(dev, "Using %d MSIX messages.\n", 584a5ebadc6SPyun YongHyeon msixc); 585a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_MSIX; 586a5ebadc6SPyun YongHyeon sc->jme_irq_spec = jme_irq_spec_msi; 587a5ebadc6SPyun YongHyeon } else 588a5ebadc6SPyun YongHyeon pci_release_msi(dev); 589a5ebadc6SPyun YongHyeon } 590a5ebadc6SPyun YongHyeon if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 5917bcbe6cbSPyun YongHyeon msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 5927bcbe6cbSPyun YongHyeon if (msic == 1) { 593a5ebadc6SPyun YongHyeon device_printf(dev, "Using %d MSI messages.\n", 594a5ebadc6SPyun YongHyeon msic); 595a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_MSI; 596a5ebadc6SPyun YongHyeon sc->jme_irq_spec = jme_irq_spec_msi; 597a5ebadc6SPyun YongHyeon } else 598a5ebadc6SPyun YongHyeon pci_release_msi(dev); 599a5ebadc6SPyun YongHyeon } 600a5ebadc6SPyun YongHyeon /* Map interrupt vector 0, 1 and 2. */ 601a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 602a5ebadc6SPyun YongHyeon (sc->jme_flags & JME_FLAG_MSIX) != 0) 603a5ebadc6SPyun YongHyeon jme_map_intr_vector(sc); 604a5ebadc6SPyun YongHyeon } 605a5ebadc6SPyun YongHyeon 606a5ebadc6SPyun YongHyeon error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 607a5ebadc6SPyun YongHyeon if (error != 0) { 608a5ebadc6SPyun YongHyeon device_printf(dev, "cannot allocate IRQ resources.\n"); 609a5ebadc6SPyun YongHyeon goto fail; 610a5ebadc6SPyun YongHyeon } 611a5ebadc6SPyun YongHyeon 612a8061cb7SPyun YongHyeon sc->jme_rev = pci_get_device(dev); 613a8061cb7SPyun YongHyeon if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 614a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_FASTETH; 615a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_NOJUMBO; 616a5ebadc6SPyun YongHyeon } 617a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_CHIPMODE); 618a5ebadc6SPyun YongHyeon sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 619a5ebadc6SPyun YongHyeon if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 620a5ebadc6SPyun YongHyeon CHIPMODE_NOT_FPGA) 621a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_FPGA; 622a5ebadc6SPyun YongHyeon if (bootverbose) { 623a5ebadc6SPyun YongHyeon device_printf(dev, "PCI device revision : 0x%04x\n", 624a5ebadc6SPyun YongHyeon sc->jme_rev); 625a5ebadc6SPyun YongHyeon device_printf(dev, "Chip revision : 0x%02x\n", 626a5ebadc6SPyun YongHyeon sc->jme_chip_rev); 627a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 628a5ebadc6SPyun YongHyeon device_printf(dev, "FPGA revision : 0x%04x\n", 629a5ebadc6SPyun YongHyeon (reg & CHIPMODE_FPGA_REV_MASK) >> 630a5ebadc6SPyun YongHyeon CHIPMODE_FPGA_REV_SHIFT); 631a5ebadc6SPyun YongHyeon } 632a5ebadc6SPyun YongHyeon if (sc->jme_chip_rev == 0xFF) { 633a5ebadc6SPyun YongHyeon device_printf(dev, "Unknown chip revision : 0x%02x\n", 634a5ebadc6SPyun YongHyeon sc->jme_rev); 635a5ebadc6SPyun YongHyeon error = ENXIO; 636a5ebadc6SPyun YongHyeon goto fail; 637a5ebadc6SPyun YongHyeon } 638a5ebadc6SPyun YongHyeon 639f37739d7SPyun YongHyeon if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 640f37739d7SPyun YongHyeon if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 641f37739d7SPyun YongHyeon CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 642f37739d7SPyun YongHyeon sc->jme_flags |= JME_FLAG_DMA32BIT; 643f37739d7SPyun YongHyeon sc->jme_flags |= JME_FLAG_TXCLK; 644450ab472SPyun YongHyeon sc->jme_flags |= JME_FLAG_HWMIB; 645f37739d7SPyun YongHyeon } 646f37739d7SPyun YongHyeon 647a5ebadc6SPyun YongHyeon /* Reset the ethernet controller. */ 648a5ebadc6SPyun YongHyeon jme_reset(sc); 649a5ebadc6SPyun YongHyeon 650a5ebadc6SPyun YongHyeon /* Get station address. */ 651a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_SMBCSR); 652a5ebadc6SPyun YongHyeon if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 653a5ebadc6SPyun YongHyeon error = jme_eeprom_macaddr(sc); 654a5ebadc6SPyun YongHyeon if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 655a5ebadc6SPyun YongHyeon if (error != 0 && (bootverbose)) 656a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 657a5ebadc6SPyun YongHyeon "ethernet hardware address not found in EEPROM.\n"); 658a5ebadc6SPyun YongHyeon jme_reg_macaddr(sc); 659a5ebadc6SPyun YongHyeon } 660a5ebadc6SPyun YongHyeon 661a5ebadc6SPyun YongHyeon /* 662a5ebadc6SPyun YongHyeon * Save PHY address. 663a5ebadc6SPyun YongHyeon * Integrated JR0211 has fixed PHY address whereas FPGA version 664a5ebadc6SPyun YongHyeon * requires PHY probing to get correct PHY address. 665a5ebadc6SPyun YongHyeon */ 666a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 667a5ebadc6SPyun YongHyeon sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 668a5ebadc6SPyun YongHyeon GPREG0_PHY_ADDR_MASK; 669a5ebadc6SPyun YongHyeon if (bootverbose) 670a5ebadc6SPyun YongHyeon device_printf(dev, "PHY is at address %d.\n", 671a5ebadc6SPyun YongHyeon sc->jme_phyaddr); 672a5ebadc6SPyun YongHyeon } else 673a5ebadc6SPyun YongHyeon sc->jme_phyaddr = 0; 674a5ebadc6SPyun YongHyeon 675a5ebadc6SPyun YongHyeon /* Set max allowable DMA size. */ 676a5ebadc6SPyun YongHyeon if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 677a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_PCIE; 678a5ebadc6SPyun YongHyeon burst = pci_read_config(dev, i + 0x08, 2); 679a5ebadc6SPyun YongHyeon if (bootverbose) { 680a5ebadc6SPyun YongHyeon device_printf(dev, "Read request size : %d bytes.\n", 681a5ebadc6SPyun YongHyeon 128 << ((burst >> 12) & 0x07)); 682a5ebadc6SPyun YongHyeon device_printf(dev, "TLP payload size : %d bytes.\n", 683a5ebadc6SPyun YongHyeon 128 << ((burst >> 5) & 0x07)); 684a5ebadc6SPyun YongHyeon } 685a5ebadc6SPyun YongHyeon switch ((burst >> 12) & 0x07) { 686a5ebadc6SPyun YongHyeon case 0: 687a5ebadc6SPyun YongHyeon sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 688a5ebadc6SPyun YongHyeon break; 689a5ebadc6SPyun YongHyeon case 1: 690a5ebadc6SPyun YongHyeon sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 691a5ebadc6SPyun YongHyeon break; 692a5ebadc6SPyun YongHyeon default: 693a5ebadc6SPyun YongHyeon sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 694a5ebadc6SPyun YongHyeon break; 695a5ebadc6SPyun YongHyeon } 696a5ebadc6SPyun YongHyeon sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 697a5ebadc6SPyun YongHyeon } else { 698a5ebadc6SPyun YongHyeon sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 699a5ebadc6SPyun YongHyeon sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 700a5ebadc6SPyun YongHyeon } 701a5ebadc6SPyun YongHyeon /* Create coalescing sysctl node. */ 702a5ebadc6SPyun YongHyeon jme_sysctl_node(sc); 703a5ebadc6SPyun YongHyeon if ((error = jme_dma_alloc(sc) != 0)) 704a5ebadc6SPyun YongHyeon goto fail; 705a5ebadc6SPyun YongHyeon 706a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 707a5ebadc6SPyun YongHyeon if (ifp == NULL) { 708a5ebadc6SPyun YongHyeon device_printf(dev, "cannot allocate ifnet structure.\n"); 709a5ebadc6SPyun YongHyeon error = ENXIO; 710a5ebadc6SPyun YongHyeon goto fail; 711a5ebadc6SPyun YongHyeon } 712a5ebadc6SPyun YongHyeon 713a5ebadc6SPyun YongHyeon ifp->if_softc = sc; 714a5ebadc6SPyun YongHyeon if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 715a5ebadc6SPyun YongHyeon ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 716a5ebadc6SPyun YongHyeon ifp->if_ioctl = jme_ioctl; 717a5ebadc6SPyun YongHyeon ifp->if_start = jme_start; 718a5ebadc6SPyun YongHyeon ifp->if_init = jme_init; 719a5ebadc6SPyun YongHyeon ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1; 720a5ebadc6SPyun YongHyeon IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 721a5ebadc6SPyun YongHyeon IFQ_SET_READY(&ifp->if_snd); 722a5ebadc6SPyun YongHyeon /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 723a5ebadc6SPyun YongHyeon ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 724a5ebadc6SPyun YongHyeon ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; 725a5ebadc6SPyun YongHyeon if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 726a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_PMCAP; 727a5ebadc6SPyun YongHyeon ifp->if_capabilities |= IFCAP_WOL_MAGIC; 728a5ebadc6SPyun YongHyeon } 729a5ebadc6SPyun YongHyeon ifp->if_capenable = ifp->if_capabilities; 730a5ebadc6SPyun YongHyeon 731a5ebadc6SPyun YongHyeon /* Set up MII bus. */ 7328e5d93dbSMarius Strobl error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange, 733*f25c5972SPyun YongHyeon jme_mediastatus, BMSR_DEFCAPMASK, 734*f25c5972SPyun YongHyeon sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, 735*f25c5972SPyun YongHyeon MII_OFFSET_ANY, MIIF_DOPAUSE); 7368e5d93dbSMarius Strobl if (error != 0) { 7378e5d93dbSMarius Strobl device_printf(dev, "attaching PHYs failed\n"); 738a5ebadc6SPyun YongHyeon goto fail; 739a5ebadc6SPyun YongHyeon } 740a5ebadc6SPyun YongHyeon 741a5ebadc6SPyun YongHyeon /* 742a5ebadc6SPyun YongHyeon * Force PHY to FPGA mode. 743a5ebadc6SPyun YongHyeon */ 744a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 745a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 746a5ebadc6SPyun YongHyeon if (mii->mii_instance != 0) { 747a5ebadc6SPyun YongHyeon LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 748a5ebadc6SPyun YongHyeon if (miisc->mii_phy != 0) { 749a5ebadc6SPyun YongHyeon sc->jme_phyaddr = miisc->mii_phy; 750a5ebadc6SPyun YongHyeon break; 751a5ebadc6SPyun YongHyeon } 752a5ebadc6SPyun YongHyeon } 753a5ebadc6SPyun YongHyeon if (sc->jme_phyaddr != 0) { 754a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 755a5ebadc6SPyun YongHyeon "FPGA PHY is at %d\n", sc->jme_phyaddr); 756a5ebadc6SPyun YongHyeon /* vendor magic. */ 757a5ebadc6SPyun YongHyeon jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 758a5ebadc6SPyun YongHyeon 0x0004); 759a5ebadc6SPyun YongHyeon } 760a5ebadc6SPyun YongHyeon } 761a5ebadc6SPyun YongHyeon } 762a5ebadc6SPyun YongHyeon 763a5ebadc6SPyun YongHyeon ether_ifattach(ifp, sc->jme_eaddr); 764a5ebadc6SPyun YongHyeon 765a5ebadc6SPyun YongHyeon /* VLAN capability setup */ 766a5ebadc6SPyun YongHyeon ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 7677bd35300SPyun YongHyeon IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 768a5ebadc6SPyun YongHyeon ifp->if_capenable = ifp->if_capabilities; 769a5ebadc6SPyun YongHyeon 770a5ebadc6SPyun YongHyeon /* Tell the upper layer(s) we support long frames. */ 771a5ebadc6SPyun YongHyeon ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 772a5ebadc6SPyun YongHyeon 773a5ebadc6SPyun YongHyeon /* Create local taskq. */ 774a5ebadc6SPyun YongHyeon TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp); 775a5ebadc6SPyun YongHyeon sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 776a5ebadc6SPyun YongHyeon taskqueue_thread_enqueue, &sc->jme_tq); 777a5ebadc6SPyun YongHyeon if (sc->jme_tq == NULL) { 778a5ebadc6SPyun YongHyeon device_printf(dev, "could not create taskqueue.\n"); 779a5ebadc6SPyun YongHyeon ether_ifdetach(ifp); 780a5ebadc6SPyun YongHyeon error = ENXIO; 781a5ebadc6SPyun YongHyeon goto fail; 782a5ebadc6SPyun YongHyeon } 783a5ebadc6SPyun YongHyeon taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 784a5ebadc6SPyun YongHyeon device_get_nameunit(sc->jme_dev)); 785a5ebadc6SPyun YongHyeon 7867bcbe6cbSPyun YongHyeon for (i = 0; i < 1; i++) { 787a5ebadc6SPyun YongHyeon error = bus_setup_intr(dev, sc->jme_irq[i], 788a5ebadc6SPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 789a5ebadc6SPyun YongHyeon &sc->jme_intrhand[i]); 790a5ebadc6SPyun YongHyeon if (error != 0) 791a5ebadc6SPyun YongHyeon break; 792a5ebadc6SPyun YongHyeon } 793a5ebadc6SPyun YongHyeon 794a5ebadc6SPyun YongHyeon if (error != 0) { 795a5ebadc6SPyun YongHyeon device_printf(dev, "could not set up interrupt handler.\n"); 796a5ebadc6SPyun YongHyeon taskqueue_free(sc->jme_tq); 797a5ebadc6SPyun YongHyeon sc->jme_tq = NULL; 798a5ebadc6SPyun YongHyeon ether_ifdetach(ifp); 799a5ebadc6SPyun YongHyeon goto fail; 800a5ebadc6SPyun YongHyeon } 801a5ebadc6SPyun YongHyeon 802a5ebadc6SPyun YongHyeon fail: 803a5ebadc6SPyun YongHyeon if (error != 0) 804a5ebadc6SPyun YongHyeon jme_detach(dev); 805a5ebadc6SPyun YongHyeon 806a5ebadc6SPyun YongHyeon return (error); 807a5ebadc6SPyun YongHyeon } 808a5ebadc6SPyun YongHyeon 809a5ebadc6SPyun YongHyeon static int 810a5ebadc6SPyun YongHyeon jme_detach(device_t dev) 811a5ebadc6SPyun YongHyeon { 812a5ebadc6SPyun YongHyeon struct jme_softc *sc; 813a5ebadc6SPyun YongHyeon struct ifnet *ifp; 8147bcbe6cbSPyun YongHyeon int i; 815a5ebadc6SPyun YongHyeon 816a5ebadc6SPyun YongHyeon sc = device_get_softc(dev); 817a5ebadc6SPyun YongHyeon 818a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 819a5ebadc6SPyun YongHyeon if (device_is_attached(dev)) { 820a5ebadc6SPyun YongHyeon JME_LOCK(sc); 821a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_DETACH; 822a5ebadc6SPyun YongHyeon jme_stop(sc); 823a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 824a5ebadc6SPyun YongHyeon callout_drain(&sc->jme_tick_ch); 825a5ebadc6SPyun YongHyeon taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 826a5ebadc6SPyun YongHyeon taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 827a5ebadc6SPyun YongHyeon taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 828a5ebadc6SPyun YongHyeon ether_ifdetach(ifp); 829a5ebadc6SPyun YongHyeon } 830a5ebadc6SPyun YongHyeon 831a5ebadc6SPyun YongHyeon if (sc->jme_tq != NULL) { 832a5ebadc6SPyun YongHyeon taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 833a5ebadc6SPyun YongHyeon taskqueue_free(sc->jme_tq); 834a5ebadc6SPyun YongHyeon sc->jme_tq = NULL; 835a5ebadc6SPyun YongHyeon } 836a5ebadc6SPyun YongHyeon 837a5ebadc6SPyun YongHyeon if (sc->jme_miibus != NULL) { 838a5ebadc6SPyun YongHyeon device_delete_child(dev, sc->jme_miibus); 839a5ebadc6SPyun YongHyeon sc->jme_miibus = NULL; 840a5ebadc6SPyun YongHyeon } 841a5ebadc6SPyun YongHyeon bus_generic_detach(dev); 842a5ebadc6SPyun YongHyeon jme_dma_free(sc); 843a5ebadc6SPyun YongHyeon 844a5ebadc6SPyun YongHyeon if (ifp != NULL) { 845a5ebadc6SPyun YongHyeon if_free(ifp); 846a5ebadc6SPyun YongHyeon sc->jme_ifp = NULL; 847a5ebadc6SPyun YongHyeon } 848a5ebadc6SPyun YongHyeon 8497bcbe6cbSPyun YongHyeon for (i = 0; i < 1; i++) { 850a5ebadc6SPyun YongHyeon if (sc->jme_intrhand[i] != NULL) { 851a5ebadc6SPyun YongHyeon bus_teardown_intr(dev, sc->jme_irq[i], 852a5ebadc6SPyun YongHyeon sc->jme_intrhand[i]); 853a5ebadc6SPyun YongHyeon sc->jme_intrhand[i] = NULL; 854a5ebadc6SPyun YongHyeon } 855a5ebadc6SPyun YongHyeon } 856a5ebadc6SPyun YongHyeon 857a5ebadc6SPyun YongHyeon bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 858a5ebadc6SPyun YongHyeon if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 859a5ebadc6SPyun YongHyeon pci_release_msi(dev); 860a5ebadc6SPyun YongHyeon bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 861a5ebadc6SPyun YongHyeon mtx_destroy(&sc->jme_mtx); 862a5ebadc6SPyun YongHyeon 863a5ebadc6SPyun YongHyeon return (0); 864a5ebadc6SPyun YongHyeon } 865a5ebadc6SPyun YongHyeon 866450ab472SPyun YongHyeon #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 867450ab472SPyun YongHyeon SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 868450ab472SPyun YongHyeon 869a5ebadc6SPyun YongHyeon static void 870a5ebadc6SPyun YongHyeon jme_sysctl_node(struct jme_softc *sc) 871a5ebadc6SPyun YongHyeon { 872450ab472SPyun YongHyeon struct sysctl_ctx_list *ctx; 873450ab472SPyun YongHyeon struct sysctl_oid_list *child, *parent; 874450ab472SPyun YongHyeon struct sysctl_oid *tree; 875450ab472SPyun YongHyeon struct jme_hw_stats *stats; 876a5ebadc6SPyun YongHyeon int error; 877a5ebadc6SPyun YongHyeon 878450ab472SPyun YongHyeon stats = &sc->jme_stats; 879450ab472SPyun YongHyeon ctx = device_get_sysctl_ctx(sc->jme_dev); 880450ab472SPyun YongHyeon child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 881a5ebadc6SPyun YongHyeon 882450ab472SPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 883450ab472SPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0, 884450ab472SPyun YongHyeon sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 885a5ebadc6SPyun YongHyeon 886450ab472SPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 887450ab472SPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0, 888450ab472SPyun YongHyeon sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 889a5ebadc6SPyun YongHyeon 890450ab472SPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 891450ab472SPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0, 892450ab472SPyun YongHyeon sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 893a5ebadc6SPyun YongHyeon 894450ab472SPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 895450ab472SPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0, 896450ab472SPyun YongHyeon sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 897450ab472SPyun YongHyeon 898450ab472SPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 899450ab472SPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0, 900450ab472SPyun YongHyeon sysctl_hw_jme_proc_limit, "I", 901a5ebadc6SPyun YongHyeon "max number of Rx events to process"); 902a5ebadc6SPyun YongHyeon 903a5ebadc6SPyun YongHyeon /* Pull in device tunables. */ 904a5ebadc6SPyun YongHyeon sc->jme_process_limit = JME_PROC_DEFAULT; 905a5ebadc6SPyun YongHyeon error = resource_int_value(device_get_name(sc->jme_dev), 906a5ebadc6SPyun YongHyeon device_get_unit(sc->jme_dev), "process_limit", 907a5ebadc6SPyun YongHyeon &sc->jme_process_limit); 908a5ebadc6SPyun YongHyeon if (error == 0) { 909a5ebadc6SPyun YongHyeon if (sc->jme_process_limit < JME_PROC_MIN || 910a5ebadc6SPyun YongHyeon sc->jme_process_limit > JME_PROC_MAX) { 911a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 912a5ebadc6SPyun YongHyeon "process_limit value out of range; " 913a5ebadc6SPyun YongHyeon "using default: %d\n", JME_PROC_DEFAULT); 914a5ebadc6SPyun YongHyeon sc->jme_process_limit = JME_PROC_DEFAULT; 915a5ebadc6SPyun YongHyeon } 916a5ebadc6SPyun YongHyeon } 917a5ebadc6SPyun YongHyeon 918a5ebadc6SPyun YongHyeon sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 919a5ebadc6SPyun YongHyeon error = resource_int_value(device_get_name(sc->jme_dev), 920a5ebadc6SPyun YongHyeon device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 921a5ebadc6SPyun YongHyeon if (error == 0) { 922a5ebadc6SPyun YongHyeon if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 923a5ebadc6SPyun YongHyeon sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 924a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 925a5ebadc6SPyun YongHyeon "tx_coal_to value out of range; " 926a5ebadc6SPyun YongHyeon "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 927a5ebadc6SPyun YongHyeon sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 928a5ebadc6SPyun YongHyeon } 929a5ebadc6SPyun YongHyeon } 930a5ebadc6SPyun YongHyeon 931a5ebadc6SPyun YongHyeon sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 932a5ebadc6SPyun YongHyeon error = resource_int_value(device_get_name(sc->jme_dev), 933a5ebadc6SPyun YongHyeon device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 934a5ebadc6SPyun YongHyeon if (error == 0) { 935a5ebadc6SPyun YongHyeon if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 936a5ebadc6SPyun YongHyeon sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 937a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 938a5ebadc6SPyun YongHyeon "tx_coal_pkt value out of range; " 939a5ebadc6SPyun YongHyeon "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 940a5ebadc6SPyun YongHyeon sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 941a5ebadc6SPyun YongHyeon } 942a5ebadc6SPyun YongHyeon } 943a5ebadc6SPyun YongHyeon 944a5ebadc6SPyun YongHyeon sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 945a5ebadc6SPyun YongHyeon error = resource_int_value(device_get_name(sc->jme_dev), 946a5ebadc6SPyun YongHyeon device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 947a5ebadc6SPyun YongHyeon if (error == 0) { 948a5ebadc6SPyun YongHyeon if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 949a5ebadc6SPyun YongHyeon sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 950a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 951a5ebadc6SPyun YongHyeon "rx_coal_to value out of range; " 952a5ebadc6SPyun YongHyeon "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 953a5ebadc6SPyun YongHyeon sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 954a5ebadc6SPyun YongHyeon } 955a5ebadc6SPyun YongHyeon } 956a5ebadc6SPyun YongHyeon 957a5ebadc6SPyun YongHyeon sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 958a5ebadc6SPyun YongHyeon error = resource_int_value(device_get_name(sc->jme_dev), 959a5ebadc6SPyun YongHyeon device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 960a5ebadc6SPyun YongHyeon if (error == 0) { 961a5ebadc6SPyun YongHyeon if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 962a5ebadc6SPyun YongHyeon sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 963a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 964a5ebadc6SPyun YongHyeon "tx_coal_pkt value out of range; " 965a5ebadc6SPyun YongHyeon "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 966a5ebadc6SPyun YongHyeon sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 967a5ebadc6SPyun YongHyeon } 968a5ebadc6SPyun YongHyeon } 969450ab472SPyun YongHyeon 970450ab472SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 971450ab472SPyun YongHyeon return; 972450ab472SPyun YongHyeon 973450ab472SPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 974450ab472SPyun YongHyeon NULL, "JME statistics"); 975450ab472SPyun YongHyeon parent = SYSCTL_CHILDREN(tree); 976450ab472SPyun YongHyeon 977450ab472SPyun YongHyeon /* Rx statistics. */ 978450ab472SPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 979450ab472SPyun YongHyeon NULL, "Rx MAC statistics"); 980450ab472SPyun YongHyeon child = SYSCTL_CHILDREN(tree); 981450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 982450ab472SPyun YongHyeon &stats->rx_good_frames, "Good frames"); 983450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 984450ab472SPyun YongHyeon &stats->rx_crc_errs, "CRC errors"); 985450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 986450ab472SPyun YongHyeon &stats->rx_mii_errs, "MII errors"); 987450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 988450ab472SPyun YongHyeon &stats->rx_fifo_oflows, "FIFO overflows"); 989450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 990450ab472SPyun YongHyeon &stats->rx_desc_empty, "Descriptor empty"); 991450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 992450ab472SPyun YongHyeon &stats->rx_bad_frames, "Bad frames"); 993450ab472SPyun YongHyeon 994450ab472SPyun YongHyeon /* Tx statistics. */ 995450ab472SPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 996450ab472SPyun YongHyeon NULL, "Tx MAC statistics"); 997450ab472SPyun YongHyeon child = SYSCTL_CHILDREN(tree); 998450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 999450ab472SPyun YongHyeon &stats->tx_good_frames, "Good frames"); 1000450ab472SPyun YongHyeon JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1001450ab472SPyun YongHyeon &stats->tx_bad_frames, "Bad frames"); 1002a5ebadc6SPyun YongHyeon } 1003a5ebadc6SPyun YongHyeon 1004450ab472SPyun YongHyeon #undef JME_SYSCTL_STAT_ADD32 1005450ab472SPyun YongHyeon 1006a5ebadc6SPyun YongHyeon struct jme_dmamap_arg { 1007a5ebadc6SPyun YongHyeon bus_addr_t jme_busaddr; 1008a5ebadc6SPyun YongHyeon }; 1009a5ebadc6SPyun YongHyeon 1010a5ebadc6SPyun YongHyeon static void 1011a5ebadc6SPyun YongHyeon jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1012a5ebadc6SPyun YongHyeon { 1013a5ebadc6SPyun YongHyeon struct jme_dmamap_arg *ctx; 1014a5ebadc6SPyun YongHyeon 1015a5ebadc6SPyun YongHyeon if (error != 0) 1016a5ebadc6SPyun YongHyeon return; 1017a5ebadc6SPyun YongHyeon 1018a5ebadc6SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1019a5ebadc6SPyun YongHyeon 1020a5ebadc6SPyun YongHyeon ctx = (struct jme_dmamap_arg *)arg; 1021a5ebadc6SPyun YongHyeon ctx->jme_busaddr = segs[0].ds_addr; 1022a5ebadc6SPyun YongHyeon } 1023a5ebadc6SPyun YongHyeon 1024a5ebadc6SPyun YongHyeon static int 1025a5ebadc6SPyun YongHyeon jme_dma_alloc(struct jme_softc *sc) 1026a5ebadc6SPyun YongHyeon { 1027a5ebadc6SPyun YongHyeon struct jme_dmamap_arg ctx; 1028a5ebadc6SPyun YongHyeon struct jme_txdesc *txd; 1029a5ebadc6SPyun YongHyeon struct jme_rxdesc *rxd; 1030a5ebadc6SPyun YongHyeon bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1031a5ebadc6SPyun YongHyeon int error, i; 1032a5ebadc6SPyun YongHyeon 1033a5ebadc6SPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR; 1034f37739d7SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1035f37739d7SPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR_32BIT; 1036a5ebadc6SPyun YongHyeon 1037a5ebadc6SPyun YongHyeon again: 1038a5ebadc6SPyun YongHyeon /* Create parent ring tag. */ 1039a5ebadc6SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1040a5ebadc6SPyun YongHyeon 1, 0, /* algnmnt, boundary */ 1041a5ebadc6SPyun YongHyeon lowaddr, /* lowaddr */ 1042a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1043a5ebadc6SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1044a5ebadc6SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1045a5ebadc6SPyun YongHyeon 0, /* nsegments */ 1046a5ebadc6SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1047a5ebadc6SPyun YongHyeon 0, /* flags */ 1048a5ebadc6SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1049a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_ring_tag); 1050a5ebadc6SPyun YongHyeon if (error != 0) { 1051a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1052a5ebadc6SPyun YongHyeon "could not create parent ring DMA tag.\n"); 1053a5ebadc6SPyun YongHyeon goto fail; 1054a5ebadc6SPyun YongHyeon } 1055a5ebadc6SPyun YongHyeon /* Create tag for Tx ring. */ 1056a5ebadc6SPyun YongHyeon error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1057a5ebadc6SPyun YongHyeon JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1058a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1059a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1060a5ebadc6SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1061a5ebadc6SPyun YongHyeon JME_TX_RING_SIZE, /* maxsize */ 1062a5ebadc6SPyun YongHyeon 1, /* nsegments */ 1063a5ebadc6SPyun YongHyeon JME_TX_RING_SIZE, /* maxsegsize */ 1064a5ebadc6SPyun YongHyeon 0, /* flags */ 1065a5ebadc6SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1066a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_tx_ring_tag); 1067a5ebadc6SPyun YongHyeon if (error != 0) { 1068a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1069a5ebadc6SPyun YongHyeon "could not allocate Tx ring DMA tag.\n"); 1070a5ebadc6SPyun YongHyeon goto fail; 1071a5ebadc6SPyun YongHyeon } 1072a5ebadc6SPyun YongHyeon 1073a5ebadc6SPyun YongHyeon /* Create tag for Rx ring. */ 1074a5ebadc6SPyun YongHyeon error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1075a5ebadc6SPyun YongHyeon JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1076a5ebadc6SPyun YongHyeon lowaddr, /* lowaddr */ 1077a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1078a5ebadc6SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1079a5ebadc6SPyun YongHyeon JME_RX_RING_SIZE, /* maxsize */ 1080a5ebadc6SPyun YongHyeon 1, /* nsegments */ 1081a5ebadc6SPyun YongHyeon JME_RX_RING_SIZE, /* maxsegsize */ 1082a5ebadc6SPyun YongHyeon 0, /* flags */ 1083a5ebadc6SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1084a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_rx_ring_tag); 1085a5ebadc6SPyun YongHyeon if (error != 0) { 1086a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1087a5ebadc6SPyun YongHyeon "could not allocate Rx ring DMA tag.\n"); 1088a5ebadc6SPyun YongHyeon goto fail; 1089a5ebadc6SPyun YongHyeon } 1090a5ebadc6SPyun YongHyeon 1091a5ebadc6SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1092a5ebadc6SPyun YongHyeon error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1093a5ebadc6SPyun YongHyeon (void **)&sc->jme_rdata.jme_tx_ring, 1094a5ebadc6SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1095a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_tx_ring_map); 1096a5ebadc6SPyun YongHyeon if (error != 0) { 1097a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1098a5ebadc6SPyun YongHyeon "could not allocate DMA'able memory for Tx ring.\n"); 1099a5ebadc6SPyun YongHyeon goto fail; 1100a5ebadc6SPyun YongHyeon } 1101a5ebadc6SPyun YongHyeon 1102a5ebadc6SPyun YongHyeon ctx.jme_busaddr = 0; 1103a5ebadc6SPyun YongHyeon error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1104a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1105a5ebadc6SPyun YongHyeon JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1106a5ebadc6SPyun YongHyeon if (error != 0 || ctx.jme_busaddr == 0) { 1107a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1108a5ebadc6SPyun YongHyeon "could not load DMA'able memory for Tx ring.\n"); 1109a5ebadc6SPyun YongHyeon goto fail; 1110a5ebadc6SPyun YongHyeon } 1111a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1112a5ebadc6SPyun YongHyeon 1113a5ebadc6SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1114a5ebadc6SPyun YongHyeon error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1115a5ebadc6SPyun YongHyeon (void **)&sc->jme_rdata.jme_rx_ring, 1116a5ebadc6SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1117a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_rx_ring_map); 1118a5ebadc6SPyun YongHyeon if (error != 0) { 1119a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1120a5ebadc6SPyun YongHyeon "could not allocate DMA'able memory for Rx ring.\n"); 1121a5ebadc6SPyun YongHyeon goto fail; 1122a5ebadc6SPyun YongHyeon } 1123a5ebadc6SPyun YongHyeon 1124a5ebadc6SPyun YongHyeon ctx.jme_busaddr = 0; 1125a5ebadc6SPyun YongHyeon error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1126a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1127a5ebadc6SPyun YongHyeon JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1128a5ebadc6SPyun YongHyeon if (error != 0 || ctx.jme_busaddr == 0) { 1129a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1130a5ebadc6SPyun YongHyeon "could not load DMA'able memory for Rx ring.\n"); 1131a5ebadc6SPyun YongHyeon goto fail; 1132a5ebadc6SPyun YongHyeon } 1133a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1134a5ebadc6SPyun YongHyeon 1135f37739d7SPyun YongHyeon if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1136a5ebadc6SPyun YongHyeon /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1137f37739d7SPyun YongHyeon tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1138f37739d7SPyun YongHyeon JME_TX_RING_SIZE; 1139f37739d7SPyun YongHyeon rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1140f37739d7SPyun YongHyeon JME_RX_RING_SIZE; 1141a5ebadc6SPyun YongHyeon if ((JME_ADDR_HI(tx_ring_end) != 1142a5ebadc6SPyun YongHyeon JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1143a5ebadc6SPyun YongHyeon (JME_ADDR_HI(rx_ring_end) != 1144a5ebadc6SPyun YongHyeon JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1145a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "4GB boundary crossed, " 1146a5ebadc6SPyun YongHyeon "switching to 32bit DMA address mode.\n"); 1147a5ebadc6SPyun YongHyeon jme_dma_free(sc); 1148a5ebadc6SPyun YongHyeon /* Limit DMA address space to 32bit and try again. */ 1149a5ebadc6SPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR_32BIT; 1150a5ebadc6SPyun YongHyeon goto again; 1151a5ebadc6SPyun YongHyeon } 1152f37739d7SPyun YongHyeon } 1153a5ebadc6SPyun YongHyeon 1154f37739d7SPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR; 1155f37739d7SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1156f37739d7SPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR_32BIT; 1157a5ebadc6SPyun YongHyeon /* Create parent buffer tag. */ 1158a5ebadc6SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1159a5ebadc6SPyun YongHyeon 1, 0, /* algnmnt, boundary */ 1160f37739d7SPyun YongHyeon lowaddr, /* lowaddr */ 1161a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1162a5ebadc6SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1163a5ebadc6SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1164a5ebadc6SPyun YongHyeon 0, /* nsegments */ 1165a5ebadc6SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1166a5ebadc6SPyun YongHyeon 0, /* flags */ 1167a5ebadc6SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1168a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_buffer_tag); 1169a5ebadc6SPyun YongHyeon if (error != 0) { 1170a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1171a5ebadc6SPyun YongHyeon "could not create parent buffer DMA tag.\n"); 1172a5ebadc6SPyun YongHyeon goto fail; 1173a5ebadc6SPyun YongHyeon } 1174a5ebadc6SPyun YongHyeon 1175a5ebadc6SPyun YongHyeon /* Create shadow status block tag. */ 1176a5ebadc6SPyun YongHyeon error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1177a5ebadc6SPyun YongHyeon JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1178a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1179a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1180a5ebadc6SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1181a5ebadc6SPyun YongHyeon JME_SSB_SIZE, /* maxsize */ 1182a5ebadc6SPyun YongHyeon 1, /* nsegments */ 1183a5ebadc6SPyun YongHyeon JME_SSB_SIZE, /* maxsegsize */ 1184a5ebadc6SPyun YongHyeon 0, /* flags */ 1185a5ebadc6SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1186a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_ssb_tag); 1187a5ebadc6SPyun YongHyeon if (error != 0) { 1188a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1189a5ebadc6SPyun YongHyeon "could not create shared status block DMA tag.\n"); 1190a5ebadc6SPyun YongHyeon goto fail; 1191a5ebadc6SPyun YongHyeon } 1192a5ebadc6SPyun YongHyeon 1193a5ebadc6SPyun YongHyeon /* Create tag for Tx buffers. */ 1194a5ebadc6SPyun YongHyeon error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1195a5ebadc6SPyun YongHyeon 1, 0, /* algnmnt, boundary */ 1196a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1197a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1198a5ebadc6SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1199a5ebadc6SPyun YongHyeon JME_TSO_MAXSIZE, /* maxsize */ 1200a5ebadc6SPyun YongHyeon JME_MAXTXSEGS, /* nsegments */ 1201a5ebadc6SPyun YongHyeon JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1202a5ebadc6SPyun YongHyeon 0, /* flags */ 1203a5ebadc6SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1204a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_tx_tag); 1205a5ebadc6SPyun YongHyeon if (error != 0) { 1206a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1207a5ebadc6SPyun YongHyeon goto fail; 1208a5ebadc6SPyun YongHyeon } 1209a5ebadc6SPyun YongHyeon 1210a5ebadc6SPyun YongHyeon /* Create tag for Rx buffers. */ 1211a5ebadc6SPyun YongHyeon error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1212a5ebadc6SPyun YongHyeon JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1213a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1214a5ebadc6SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1215a5ebadc6SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1216a5ebadc6SPyun YongHyeon MCLBYTES, /* maxsize */ 1217a5ebadc6SPyun YongHyeon 1, /* nsegments */ 1218a5ebadc6SPyun YongHyeon MCLBYTES, /* maxsegsize */ 1219a5ebadc6SPyun YongHyeon 0, /* flags */ 1220a5ebadc6SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1221a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_rx_tag); 1222a5ebadc6SPyun YongHyeon if (error != 0) { 1223a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1224a5ebadc6SPyun YongHyeon goto fail; 1225a5ebadc6SPyun YongHyeon } 1226a5ebadc6SPyun YongHyeon 1227a5ebadc6SPyun YongHyeon /* 1228a5ebadc6SPyun YongHyeon * Allocate DMA'able memory and load the DMA map for shared 1229a5ebadc6SPyun YongHyeon * status block. 1230a5ebadc6SPyun YongHyeon */ 1231a5ebadc6SPyun YongHyeon error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1232a5ebadc6SPyun YongHyeon (void **)&sc->jme_rdata.jme_ssb_block, 1233a5ebadc6SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1234a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_ssb_map); 1235a5ebadc6SPyun YongHyeon if (error != 0) { 1236a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "could not allocate DMA'able " 1237a5ebadc6SPyun YongHyeon "memory for shared status block.\n"); 1238a5ebadc6SPyun YongHyeon goto fail; 1239a5ebadc6SPyun YongHyeon } 1240a5ebadc6SPyun YongHyeon 1241a5ebadc6SPyun YongHyeon ctx.jme_busaddr = 0; 1242a5ebadc6SPyun YongHyeon error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1243a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1244a5ebadc6SPyun YongHyeon JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1245a5ebadc6SPyun YongHyeon if (error != 0 || ctx.jme_busaddr == 0) { 1246a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "could not load DMA'able memory " 1247a5ebadc6SPyun YongHyeon "for shared status block.\n"); 1248a5ebadc6SPyun YongHyeon goto fail; 1249a5ebadc6SPyun YongHyeon } 1250a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1251a5ebadc6SPyun YongHyeon 1252a5ebadc6SPyun YongHyeon /* Create DMA maps for Tx buffers. */ 1253a5ebadc6SPyun YongHyeon for (i = 0; i < JME_TX_RING_CNT; i++) { 1254a5ebadc6SPyun YongHyeon txd = &sc->jme_cdata.jme_txdesc[i]; 1255a5ebadc6SPyun YongHyeon txd->tx_m = NULL; 1256a5ebadc6SPyun YongHyeon txd->tx_dmamap = NULL; 1257a5ebadc6SPyun YongHyeon error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1258a5ebadc6SPyun YongHyeon &txd->tx_dmamap); 1259a5ebadc6SPyun YongHyeon if (error != 0) { 1260a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1261a5ebadc6SPyun YongHyeon "could not create Tx dmamap.\n"); 1262a5ebadc6SPyun YongHyeon goto fail; 1263a5ebadc6SPyun YongHyeon } 1264a5ebadc6SPyun YongHyeon } 1265a5ebadc6SPyun YongHyeon /* Create DMA maps for Rx buffers. */ 1266a5ebadc6SPyun YongHyeon if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1267a5ebadc6SPyun YongHyeon &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1268a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1269a5ebadc6SPyun YongHyeon "could not create spare Rx dmamap.\n"); 1270a5ebadc6SPyun YongHyeon goto fail; 1271a5ebadc6SPyun YongHyeon } 1272a5ebadc6SPyun YongHyeon for (i = 0; i < JME_RX_RING_CNT; i++) { 1273a5ebadc6SPyun YongHyeon rxd = &sc->jme_cdata.jme_rxdesc[i]; 1274a5ebadc6SPyun YongHyeon rxd->rx_m = NULL; 1275a5ebadc6SPyun YongHyeon rxd->rx_dmamap = NULL; 1276a5ebadc6SPyun YongHyeon error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1277a5ebadc6SPyun YongHyeon &rxd->rx_dmamap); 1278a5ebadc6SPyun YongHyeon if (error != 0) { 1279a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 1280a5ebadc6SPyun YongHyeon "could not create Rx dmamap.\n"); 1281a5ebadc6SPyun YongHyeon goto fail; 1282a5ebadc6SPyun YongHyeon } 1283a5ebadc6SPyun YongHyeon } 1284a5ebadc6SPyun YongHyeon 1285a5ebadc6SPyun YongHyeon fail: 1286a5ebadc6SPyun YongHyeon return (error); 1287a5ebadc6SPyun YongHyeon } 1288a5ebadc6SPyun YongHyeon 1289a5ebadc6SPyun YongHyeon static void 1290a5ebadc6SPyun YongHyeon jme_dma_free(struct jme_softc *sc) 1291a5ebadc6SPyun YongHyeon { 1292a5ebadc6SPyun YongHyeon struct jme_txdesc *txd; 1293a5ebadc6SPyun YongHyeon struct jme_rxdesc *rxd; 1294a5ebadc6SPyun YongHyeon int i; 1295a5ebadc6SPyun YongHyeon 1296a5ebadc6SPyun YongHyeon /* Tx ring */ 1297a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1298a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_ring_map) 1299a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1300a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map); 1301a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_ring_map && 1302a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_tx_ring) 1303a5ebadc6SPyun YongHyeon bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1304a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_tx_ring, 1305a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map); 1306a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_tx_ring = NULL; 1307a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map = NULL; 1308a5ebadc6SPyun YongHyeon bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1309a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_tag = NULL; 1310a5ebadc6SPyun YongHyeon } 1311a5ebadc6SPyun YongHyeon /* Rx ring */ 1312a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1313a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rx_ring_map) 1314a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1315a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_map); 1316a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rx_ring_map && 1317a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_rx_ring) 1318a5ebadc6SPyun YongHyeon bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1319a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_rx_ring, 1320a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_map); 1321a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_rx_ring = NULL; 1322a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_map = NULL; 1323a5ebadc6SPyun YongHyeon bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1324a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_tag = NULL; 1325a5ebadc6SPyun YongHyeon } 1326a5ebadc6SPyun YongHyeon /* Tx buffers */ 1327a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_tag != NULL) { 1328a5ebadc6SPyun YongHyeon for (i = 0; i < JME_TX_RING_CNT; i++) { 1329a5ebadc6SPyun YongHyeon txd = &sc->jme_cdata.jme_txdesc[i]; 1330a5ebadc6SPyun YongHyeon if (txd->tx_dmamap != NULL) { 1331a5ebadc6SPyun YongHyeon bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1332a5ebadc6SPyun YongHyeon txd->tx_dmamap); 1333a5ebadc6SPyun YongHyeon txd->tx_dmamap = NULL; 1334a5ebadc6SPyun YongHyeon } 1335a5ebadc6SPyun YongHyeon } 1336a5ebadc6SPyun YongHyeon bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1337a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_tag = NULL; 1338a5ebadc6SPyun YongHyeon } 1339a5ebadc6SPyun YongHyeon /* Rx buffers */ 1340a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rx_tag != NULL) { 1341a5ebadc6SPyun YongHyeon for (i = 0; i < JME_RX_RING_CNT; i++) { 1342a5ebadc6SPyun YongHyeon rxd = &sc->jme_cdata.jme_rxdesc[i]; 1343a5ebadc6SPyun YongHyeon if (rxd->rx_dmamap != NULL) { 1344a5ebadc6SPyun YongHyeon bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1345a5ebadc6SPyun YongHyeon rxd->rx_dmamap); 1346a5ebadc6SPyun YongHyeon rxd->rx_dmamap = NULL; 1347a5ebadc6SPyun YongHyeon } 1348a5ebadc6SPyun YongHyeon } 1349a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1350a5ebadc6SPyun YongHyeon bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1351a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_sparemap); 1352a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_sparemap = NULL; 1353a5ebadc6SPyun YongHyeon } 1354a5ebadc6SPyun YongHyeon bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1355a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_tag = NULL; 1356a5ebadc6SPyun YongHyeon } 1357a5ebadc6SPyun YongHyeon 1358a5ebadc6SPyun YongHyeon /* Shared status block. */ 1359a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_ssb_tag != NULL) { 1360a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_ssb_map) 1361a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1362a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_ssb_map); 1363a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block) 1364a5ebadc6SPyun YongHyeon bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1365a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_ssb_block, 1366a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_ssb_map); 1367a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_ssb_block = NULL; 1368a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_ssb_map = NULL; 1369a5ebadc6SPyun YongHyeon bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1370a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_ssb_tag = NULL; 1371a5ebadc6SPyun YongHyeon } 1372a5ebadc6SPyun YongHyeon 1373a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_buffer_tag != NULL) { 1374a5ebadc6SPyun YongHyeon bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1375a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_buffer_tag = NULL; 1376a5ebadc6SPyun YongHyeon } 1377a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_ring_tag != NULL) { 1378a5ebadc6SPyun YongHyeon bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1379a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_ring_tag = NULL; 1380a5ebadc6SPyun YongHyeon } 1381a5ebadc6SPyun YongHyeon } 1382a5ebadc6SPyun YongHyeon 1383a5ebadc6SPyun YongHyeon /* 1384a5ebadc6SPyun YongHyeon * Make sure the interface is stopped at reboot time. 1385a5ebadc6SPyun YongHyeon */ 1386a5ebadc6SPyun YongHyeon static int 1387a5ebadc6SPyun YongHyeon jme_shutdown(device_t dev) 1388a5ebadc6SPyun YongHyeon { 1389a5ebadc6SPyun YongHyeon 1390a5ebadc6SPyun YongHyeon return (jme_suspend(dev)); 1391a5ebadc6SPyun YongHyeon } 1392a5ebadc6SPyun YongHyeon 1393a5ebadc6SPyun YongHyeon /* 1394a5ebadc6SPyun YongHyeon * Unlike other ethernet controllers, JMC250 requires 1395a5ebadc6SPyun YongHyeon * explicit resetting link speed to 10/100Mbps as gigabit 1396a5ebadc6SPyun YongHyeon * link will cunsume more power than 375mA. 1397a5ebadc6SPyun YongHyeon * Note, we reset the link speed to 10/100Mbps with 1398a5ebadc6SPyun YongHyeon * auto-negotiation but we don't know whether that operation 1399a5ebadc6SPyun YongHyeon * would succeed or not as we have no control after powering 1400a5ebadc6SPyun YongHyeon * off. If the renegotiation fail WOL may not work. Running 1401a5ebadc6SPyun YongHyeon * at 1Gbps draws more power than 375mA at 3.3V which is 1402a5ebadc6SPyun YongHyeon * specified in PCI specification and that would result in 1403a5ebadc6SPyun YongHyeon * complete shutdowning power to ethernet controller. 1404a5ebadc6SPyun YongHyeon * 1405a5ebadc6SPyun YongHyeon * TODO 1406a5ebadc6SPyun YongHyeon * Save current negotiated media speed/duplex/flow-control 1407a5ebadc6SPyun YongHyeon * to softc and restore the same link again after resuming. 1408a5ebadc6SPyun YongHyeon * PHY handling such as power down/resetting to 100Mbps 1409a5ebadc6SPyun YongHyeon * may be better handled in suspend method in phy driver. 1410a5ebadc6SPyun YongHyeon */ 1411a5ebadc6SPyun YongHyeon static void 1412a5ebadc6SPyun YongHyeon jme_setlinkspeed(struct jme_softc *sc) 1413a5ebadc6SPyun YongHyeon { 1414a5ebadc6SPyun YongHyeon struct mii_data *mii; 1415a5ebadc6SPyun YongHyeon int aneg, i; 1416a5ebadc6SPyun YongHyeon 1417a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 1418a5ebadc6SPyun YongHyeon 1419a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 1420a5ebadc6SPyun YongHyeon mii_pollstat(mii); 1421a5ebadc6SPyun YongHyeon aneg = 0; 1422a5ebadc6SPyun YongHyeon if ((mii->mii_media_status & IFM_AVALID) != 0) { 1423a5ebadc6SPyun YongHyeon switch IFM_SUBTYPE(mii->mii_media_active) { 1424a5ebadc6SPyun YongHyeon case IFM_10_T: 1425a5ebadc6SPyun YongHyeon case IFM_100_TX: 1426a5ebadc6SPyun YongHyeon return; 1427a5ebadc6SPyun YongHyeon case IFM_1000_T: 1428a5ebadc6SPyun YongHyeon aneg++; 1429a5ebadc6SPyun YongHyeon default: 1430a5ebadc6SPyun YongHyeon break; 1431a5ebadc6SPyun YongHyeon } 1432a5ebadc6SPyun YongHyeon } 1433a5ebadc6SPyun YongHyeon jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1434a5ebadc6SPyun YongHyeon jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1435a5ebadc6SPyun YongHyeon ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1436a5ebadc6SPyun YongHyeon jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1437a5ebadc6SPyun YongHyeon BMCR_AUTOEN | BMCR_STARTNEG); 1438a5ebadc6SPyun YongHyeon DELAY(1000); 1439a5ebadc6SPyun YongHyeon if (aneg != 0) { 1440a5ebadc6SPyun YongHyeon /* Poll link state until jme(4) get a 10/100 link. */ 1441a5ebadc6SPyun YongHyeon for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1442a5ebadc6SPyun YongHyeon mii_pollstat(mii); 1443a5ebadc6SPyun YongHyeon if ((mii->mii_media_status & IFM_AVALID) != 0) { 1444a5ebadc6SPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 1445a5ebadc6SPyun YongHyeon case IFM_10_T: 1446a5ebadc6SPyun YongHyeon case IFM_100_TX: 1447a5ebadc6SPyun YongHyeon jme_mac_config(sc); 1448a5ebadc6SPyun YongHyeon return; 1449a5ebadc6SPyun YongHyeon default: 1450a5ebadc6SPyun YongHyeon break; 1451a5ebadc6SPyun YongHyeon } 1452a5ebadc6SPyun YongHyeon } 1453a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1454a5ebadc6SPyun YongHyeon pause("jmelnk", hz); 1455a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1456a5ebadc6SPyun YongHyeon } 1457a5ebadc6SPyun YongHyeon if (i == MII_ANEGTICKS_GIGE) 1458a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "establishing link failed, " 1459a5ebadc6SPyun YongHyeon "WOL may not work!"); 1460a5ebadc6SPyun YongHyeon } 1461a5ebadc6SPyun YongHyeon /* 1462a5ebadc6SPyun YongHyeon * No link, force MAC to have 100Mbps, full-duplex link. 1463a5ebadc6SPyun YongHyeon * This is the last resort and may/may not work. 1464a5ebadc6SPyun YongHyeon */ 1465a5ebadc6SPyun YongHyeon mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1466a5ebadc6SPyun YongHyeon mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1467a5ebadc6SPyun YongHyeon jme_mac_config(sc); 1468a5ebadc6SPyun YongHyeon } 1469a5ebadc6SPyun YongHyeon 1470a5ebadc6SPyun YongHyeon static void 1471a5ebadc6SPyun YongHyeon jme_setwol(struct jme_softc *sc) 1472a5ebadc6SPyun YongHyeon { 1473a5ebadc6SPyun YongHyeon struct ifnet *ifp; 1474a5ebadc6SPyun YongHyeon uint32_t gpr, pmcs; 1475a5ebadc6SPyun YongHyeon uint16_t pmstat; 1476a5ebadc6SPyun YongHyeon int pmc; 1477a5ebadc6SPyun YongHyeon 1478a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 1479a5ebadc6SPyun YongHyeon 1480a5ebadc6SPyun YongHyeon if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1481f37739d7SPyun YongHyeon /* Remove Tx MAC/offload clock to save more power. */ 1482f37739d7SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1483f37739d7SPyun YongHyeon CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1484f37739d7SPyun YongHyeon ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1485f37739d7SPyun YongHyeon GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1486a5ebadc6SPyun YongHyeon /* No PME capability, PHY power down. */ 1487a5ebadc6SPyun YongHyeon jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1488a5ebadc6SPyun YongHyeon MII_BMCR, BMCR_PDOWN); 1489a5ebadc6SPyun YongHyeon return; 1490a5ebadc6SPyun YongHyeon } 1491a5ebadc6SPyun YongHyeon 1492a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 1493a5ebadc6SPyun YongHyeon gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1494a5ebadc6SPyun YongHyeon pmcs = CSR_READ_4(sc, JME_PMCS); 1495a5ebadc6SPyun YongHyeon pmcs &= ~PMCS_WOL_ENB_MASK; 1496a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1497a5ebadc6SPyun YongHyeon pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1498a5ebadc6SPyun YongHyeon /* Enable PME message. */ 1499a5ebadc6SPyun YongHyeon gpr |= GPREG0_PME_ENB; 1500a5ebadc6SPyun YongHyeon /* For gigabit controllers, reset link speed to 10/100. */ 1501a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1502a5ebadc6SPyun YongHyeon jme_setlinkspeed(sc); 1503a5ebadc6SPyun YongHyeon } 1504a5ebadc6SPyun YongHyeon 1505a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_PMCS, pmcs); 1506a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_GPREG0, gpr); 1507f37739d7SPyun YongHyeon /* Remove Tx MAC/offload clock to save more power. */ 1508f37739d7SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1509f37739d7SPyun YongHyeon CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1510f37739d7SPyun YongHyeon ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1511f37739d7SPyun YongHyeon GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1512a5ebadc6SPyun YongHyeon /* Request PME. */ 1513a5ebadc6SPyun YongHyeon pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1514a5ebadc6SPyun YongHyeon pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1515a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) != 0) 1516a5ebadc6SPyun YongHyeon pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1517a5ebadc6SPyun YongHyeon pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1518a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1519a5ebadc6SPyun YongHyeon /* No WOL, PHY power down. */ 1520a5ebadc6SPyun YongHyeon jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1521a5ebadc6SPyun YongHyeon MII_BMCR, BMCR_PDOWN); 1522a5ebadc6SPyun YongHyeon } 1523a5ebadc6SPyun YongHyeon } 1524a5ebadc6SPyun YongHyeon 1525a5ebadc6SPyun YongHyeon static int 1526a5ebadc6SPyun YongHyeon jme_suspend(device_t dev) 1527a5ebadc6SPyun YongHyeon { 1528a5ebadc6SPyun YongHyeon struct jme_softc *sc; 1529a5ebadc6SPyun YongHyeon 1530a5ebadc6SPyun YongHyeon sc = device_get_softc(dev); 1531a5ebadc6SPyun YongHyeon 1532a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1533a5ebadc6SPyun YongHyeon jme_stop(sc); 1534a5ebadc6SPyun YongHyeon jme_setwol(sc); 1535a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1536a5ebadc6SPyun YongHyeon 1537a5ebadc6SPyun YongHyeon return (0); 1538a5ebadc6SPyun YongHyeon } 1539a5ebadc6SPyun YongHyeon 1540a5ebadc6SPyun YongHyeon static int 1541a5ebadc6SPyun YongHyeon jme_resume(device_t dev) 1542a5ebadc6SPyun YongHyeon { 1543a5ebadc6SPyun YongHyeon struct jme_softc *sc; 1544a5ebadc6SPyun YongHyeon struct ifnet *ifp; 1545a5ebadc6SPyun YongHyeon uint16_t pmstat; 1546a5ebadc6SPyun YongHyeon int pmc; 1547a5ebadc6SPyun YongHyeon 1548a5ebadc6SPyun YongHyeon sc = device_get_softc(dev); 1549a5ebadc6SPyun YongHyeon 1550a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1551a5ebadc6SPyun YongHyeon if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1552a5ebadc6SPyun YongHyeon pmstat = pci_read_config(sc->jme_dev, 1553a5ebadc6SPyun YongHyeon pmc + PCIR_POWER_STATUS, 2); 1554a5ebadc6SPyun YongHyeon /* Disable PME clear PME status. */ 1555a5ebadc6SPyun YongHyeon pmstat &= ~PCIM_PSTAT_PMEENABLE; 1556a5ebadc6SPyun YongHyeon pci_write_config(sc->jme_dev, 1557a5ebadc6SPyun YongHyeon pmc + PCIR_POWER_STATUS, pmstat, 2); 1558a5ebadc6SPyun YongHyeon } 1559a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 156032f8942aSPyun YongHyeon if ((ifp->if_flags & IFF_UP) != 0) { 156132f8942aSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1562a5ebadc6SPyun YongHyeon jme_init_locked(sc); 156332f8942aSPyun YongHyeon } 1564a5ebadc6SPyun YongHyeon 1565a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1566a5ebadc6SPyun YongHyeon 1567a5ebadc6SPyun YongHyeon return (0); 1568a5ebadc6SPyun YongHyeon } 1569a5ebadc6SPyun YongHyeon 1570a5ebadc6SPyun YongHyeon static int 1571a5ebadc6SPyun YongHyeon jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1572a5ebadc6SPyun YongHyeon { 1573a5ebadc6SPyun YongHyeon struct jme_txdesc *txd; 1574a5ebadc6SPyun YongHyeon struct jme_desc *desc; 1575a5ebadc6SPyun YongHyeon struct mbuf *m; 1576a5ebadc6SPyun YongHyeon bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1577a5ebadc6SPyun YongHyeon int error, i, nsegs, prod; 1578a5ebadc6SPyun YongHyeon uint32_t cflags, tso_segsz; 1579a5ebadc6SPyun YongHyeon 1580a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 1581a5ebadc6SPyun YongHyeon 1582a5ebadc6SPyun YongHyeon M_ASSERTPKTHDR((*m_head)); 1583a5ebadc6SPyun YongHyeon 1584a5ebadc6SPyun YongHyeon if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1585a5ebadc6SPyun YongHyeon /* 1586a5ebadc6SPyun YongHyeon * Due to the adherence to NDIS specification JMC250 1587a5ebadc6SPyun YongHyeon * assumes upper stack computed TCP pseudo checksum 1588a5ebadc6SPyun YongHyeon * without including payload length. This breaks 1589a5ebadc6SPyun YongHyeon * checksum offload for TSO case so recompute TCP 1590a5ebadc6SPyun YongHyeon * pseudo checksum for JMC250. Hopefully this wouldn't 1591a5ebadc6SPyun YongHyeon * be much burden on modern CPUs. 1592a5ebadc6SPyun YongHyeon */ 1593a5ebadc6SPyun YongHyeon struct ether_header *eh; 1594a5ebadc6SPyun YongHyeon struct ip *ip; 1595a5ebadc6SPyun YongHyeon struct tcphdr *tcp; 1596a5ebadc6SPyun YongHyeon uint32_t ip_off, poff; 1597a5ebadc6SPyun YongHyeon 1598a5ebadc6SPyun YongHyeon if (M_WRITABLE(*m_head) == 0) { 1599a5ebadc6SPyun YongHyeon /* Get a writable copy. */ 1600a5ebadc6SPyun YongHyeon m = m_dup(*m_head, M_DONTWAIT); 1601a5ebadc6SPyun YongHyeon m_freem(*m_head); 1602a5ebadc6SPyun YongHyeon if (m == NULL) { 1603a5ebadc6SPyun YongHyeon *m_head = NULL; 1604a5ebadc6SPyun YongHyeon return (ENOBUFS); 1605a5ebadc6SPyun YongHyeon } 1606a5ebadc6SPyun YongHyeon *m_head = m; 1607a5ebadc6SPyun YongHyeon } 1608a5ebadc6SPyun YongHyeon ip_off = sizeof(struct ether_header); 1609a5ebadc6SPyun YongHyeon m = m_pullup(*m_head, ip_off); 1610a5ebadc6SPyun YongHyeon if (m == NULL) { 1611a5ebadc6SPyun YongHyeon *m_head = NULL; 1612a5ebadc6SPyun YongHyeon return (ENOBUFS); 1613a5ebadc6SPyun YongHyeon } 1614a5ebadc6SPyun YongHyeon eh = mtod(m, struct ether_header *); 1615a5ebadc6SPyun YongHyeon /* Check the existence of VLAN tag. */ 1616a5ebadc6SPyun YongHyeon if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1617a5ebadc6SPyun YongHyeon ip_off = sizeof(struct ether_vlan_header); 1618a5ebadc6SPyun YongHyeon m = m_pullup(m, ip_off); 1619a5ebadc6SPyun YongHyeon if (m == NULL) { 1620a5ebadc6SPyun YongHyeon *m_head = NULL; 1621a5ebadc6SPyun YongHyeon return (ENOBUFS); 1622a5ebadc6SPyun YongHyeon } 1623a5ebadc6SPyun YongHyeon } 1624a5ebadc6SPyun YongHyeon m = m_pullup(m, ip_off + sizeof(struct ip)); 1625a5ebadc6SPyun YongHyeon if (m == NULL) { 1626a5ebadc6SPyun YongHyeon *m_head = NULL; 1627a5ebadc6SPyun YongHyeon return (ENOBUFS); 1628a5ebadc6SPyun YongHyeon } 1629a5ebadc6SPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + ip_off); 1630a5ebadc6SPyun YongHyeon poff = ip_off + (ip->ip_hl << 2); 1631a5ebadc6SPyun YongHyeon m = m_pullup(m, poff + sizeof(struct tcphdr)); 1632a5ebadc6SPyun YongHyeon if (m == NULL) { 1633a5ebadc6SPyun YongHyeon *m_head = NULL; 1634a5ebadc6SPyun YongHyeon return (ENOBUFS); 1635a5ebadc6SPyun YongHyeon } 1636a5ebadc6SPyun YongHyeon /* 1637a5ebadc6SPyun YongHyeon * Reset IP checksum and recompute TCP pseudo 1638a5ebadc6SPyun YongHyeon * checksum that NDIS specification requires. 1639a5ebadc6SPyun YongHyeon */ 164096486faaSPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + ip_off); 164196486faaSPyun YongHyeon tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1642a5ebadc6SPyun YongHyeon ip->ip_sum = 0; 1643a5ebadc6SPyun YongHyeon if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1644a5ebadc6SPyun YongHyeon tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1645a5ebadc6SPyun YongHyeon ip->ip_dst.s_addr, 1646a5ebadc6SPyun YongHyeon htons((tcp->th_off << 2) + IPPROTO_TCP)); 1647a5ebadc6SPyun YongHyeon /* No need to TSO, force IP checksum offload. */ 1648a5ebadc6SPyun YongHyeon (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1649a5ebadc6SPyun YongHyeon (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1650a5ebadc6SPyun YongHyeon } else 1651a5ebadc6SPyun YongHyeon tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1652a5ebadc6SPyun YongHyeon ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1653a5ebadc6SPyun YongHyeon *m_head = m; 1654a5ebadc6SPyun YongHyeon } 1655a5ebadc6SPyun YongHyeon 1656a5ebadc6SPyun YongHyeon prod = sc->jme_cdata.jme_tx_prod; 1657a5ebadc6SPyun YongHyeon txd = &sc->jme_cdata.jme_txdesc[prod]; 1658a5ebadc6SPyun YongHyeon 1659a5ebadc6SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1660a5ebadc6SPyun YongHyeon txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1661a5ebadc6SPyun YongHyeon if (error == EFBIG) { 1662a5ebadc6SPyun YongHyeon m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS); 1663a5ebadc6SPyun YongHyeon if (m == NULL) { 1664a5ebadc6SPyun YongHyeon m_freem(*m_head); 1665a5ebadc6SPyun YongHyeon *m_head = NULL; 1666a5ebadc6SPyun YongHyeon return (ENOMEM); 1667a5ebadc6SPyun YongHyeon } 1668a5ebadc6SPyun YongHyeon *m_head = m; 1669a5ebadc6SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1670a5ebadc6SPyun YongHyeon txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1671a5ebadc6SPyun YongHyeon if (error != 0) { 1672a5ebadc6SPyun YongHyeon m_freem(*m_head); 1673a5ebadc6SPyun YongHyeon *m_head = NULL; 1674a5ebadc6SPyun YongHyeon return (error); 1675a5ebadc6SPyun YongHyeon } 1676a5ebadc6SPyun YongHyeon } else if (error != 0) 1677a5ebadc6SPyun YongHyeon return (error); 1678a5ebadc6SPyun YongHyeon if (nsegs == 0) { 1679a5ebadc6SPyun YongHyeon m_freem(*m_head); 1680a5ebadc6SPyun YongHyeon *m_head = NULL; 1681a5ebadc6SPyun YongHyeon return (EIO); 1682a5ebadc6SPyun YongHyeon } 1683a5ebadc6SPyun YongHyeon 1684a5ebadc6SPyun YongHyeon /* 1685a5ebadc6SPyun YongHyeon * Check descriptor overrun. Leave one free descriptor. 1686a5ebadc6SPyun YongHyeon * Since we always use 64bit address mode for transmitting, 1687a5ebadc6SPyun YongHyeon * each Tx request requires one more dummy descriptor. 1688a5ebadc6SPyun YongHyeon */ 1689a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1690a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1691a5ebadc6SPyun YongHyeon return (ENOBUFS); 1692a5ebadc6SPyun YongHyeon } 1693a5ebadc6SPyun YongHyeon 1694a5ebadc6SPyun YongHyeon m = *m_head; 1695a5ebadc6SPyun YongHyeon cflags = 0; 1696a5ebadc6SPyun YongHyeon tso_segsz = 0; 1697a5ebadc6SPyun YongHyeon /* Configure checksum offload and TSO. */ 1698a5ebadc6SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1699a5ebadc6SPyun YongHyeon tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz << 1700a5ebadc6SPyun YongHyeon JME_TD_MSS_SHIFT; 1701a5ebadc6SPyun YongHyeon cflags |= JME_TD_TSO; 1702a5ebadc6SPyun YongHyeon } else { 1703a5ebadc6SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1704a5ebadc6SPyun YongHyeon cflags |= JME_TD_IPCSUM; 1705a5ebadc6SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1706a5ebadc6SPyun YongHyeon cflags |= JME_TD_TCPCSUM; 1707a5ebadc6SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1708a5ebadc6SPyun YongHyeon cflags |= JME_TD_UDPCSUM; 1709a5ebadc6SPyun YongHyeon } 1710a5ebadc6SPyun YongHyeon /* Configure VLAN. */ 1711a5ebadc6SPyun YongHyeon if ((m->m_flags & M_VLANTAG) != 0) { 1712a5ebadc6SPyun YongHyeon cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1713a5ebadc6SPyun YongHyeon cflags |= JME_TD_VLAN_TAG; 1714a5ebadc6SPyun YongHyeon } 1715a5ebadc6SPyun YongHyeon 1716a5ebadc6SPyun YongHyeon desc = &sc->jme_rdata.jme_tx_ring[prod]; 1717a5ebadc6SPyun YongHyeon desc->flags = htole32(cflags); 1718a5ebadc6SPyun YongHyeon desc->buflen = htole32(tso_segsz); 1719a5ebadc6SPyun YongHyeon desc->addr_hi = htole32(m->m_pkthdr.len); 1720a5ebadc6SPyun YongHyeon desc->addr_lo = 0; 1721a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_cnt++; 1722a5ebadc6SPyun YongHyeon JME_DESC_INC(prod, JME_TX_RING_CNT); 1723a5ebadc6SPyun YongHyeon for (i = 0; i < nsegs; i++) { 1724a5ebadc6SPyun YongHyeon desc = &sc->jme_rdata.jme_tx_ring[prod]; 1725a5ebadc6SPyun YongHyeon desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1726a5ebadc6SPyun YongHyeon desc->buflen = htole32(txsegs[i].ds_len); 1727a5ebadc6SPyun YongHyeon desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1728a5ebadc6SPyun YongHyeon desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1729a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_cnt++; 1730a5ebadc6SPyun YongHyeon JME_DESC_INC(prod, JME_TX_RING_CNT); 1731a5ebadc6SPyun YongHyeon } 1732a5ebadc6SPyun YongHyeon 1733a5ebadc6SPyun YongHyeon /* Update producer index. */ 1734a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_prod = prod; 1735a5ebadc6SPyun YongHyeon /* 1736a5ebadc6SPyun YongHyeon * Finally request interrupt and give the first descriptor 1737a5ebadc6SPyun YongHyeon * owenership to hardware. 1738a5ebadc6SPyun YongHyeon */ 1739a5ebadc6SPyun YongHyeon desc = txd->tx_desc; 1740a5ebadc6SPyun YongHyeon desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1741a5ebadc6SPyun YongHyeon 1742a5ebadc6SPyun YongHyeon txd->tx_m = m; 1743a5ebadc6SPyun YongHyeon txd->tx_ndesc = nsegs + 1; 1744a5ebadc6SPyun YongHyeon 1745a5ebadc6SPyun YongHyeon /* Sync descriptors. */ 1746a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1747a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREWRITE); 1748a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1749a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map, 1750a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1751a5ebadc6SPyun YongHyeon 1752a5ebadc6SPyun YongHyeon return (0); 1753a5ebadc6SPyun YongHyeon } 1754a5ebadc6SPyun YongHyeon 1755a5ebadc6SPyun YongHyeon static void 1756a5ebadc6SPyun YongHyeon jme_tx_task(void *arg, int pending) 1757a5ebadc6SPyun YongHyeon { 1758a5ebadc6SPyun YongHyeon struct ifnet *ifp; 1759a5ebadc6SPyun YongHyeon 1760a5ebadc6SPyun YongHyeon ifp = (struct ifnet *)arg; 1761a5ebadc6SPyun YongHyeon jme_start(ifp); 1762a5ebadc6SPyun YongHyeon } 1763a5ebadc6SPyun YongHyeon 1764a5ebadc6SPyun YongHyeon static void 1765a5ebadc6SPyun YongHyeon jme_start(struct ifnet *ifp) 1766a5ebadc6SPyun YongHyeon { 1767a5ebadc6SPyun YongHyeon struct jme_softc *sc; 1768a5ebadc6SPyun YongHyeon struct mbuf *m_head; 1769a5ebadc6SPyun YongHyeon int enq; 1770a5ebadc6SPyun YongHyeon 1771a5ebadc6SPyun YongHyeon sc = ifp->if_softc; 1772a5ebadc6SPyun YongHyeon 1773a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1774a5ebadc6SPyun YongHyeon 1775a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1776a5ebadc6SPyun YongHyeon jme_txeof(sc); 1777a5ebadc6SPyun YongHyeon 1778a5ebadc6SPyun YongHyeon if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1779a5ebadc6SPyun YongHyeon IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) { 1780a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1781a5ebadc6SPyun YongHyeon return; 1782a5ebadc6SPyun YongHyeon } 1783a5ebadc6SPyun YongHyeon 1784a5ebadc6SPyun YongHyeon for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1785a5ebadc6SPyun YongHyeon IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1786a5ebadc6SPyun YongHyeon if (m_head == NULL) 1787a5ebadc6SPyun YongHyeon break; 1788a5ebadc6SPyun YongHyeon /* 1789a5ebadc6SPyun YongHyeon * Pack the data into the transmit ring. If we 1790a5ebadc6SPyun YongHyeon * don't have room, set the OACTIVE flag and wait 1791a5ebadc6SPyun YongHyeon * for the NIC to drain the ring. 1792a5ebadc6SPyun YongHyeon */ 1793a5ebadc6SPyun YongHyeon if (jme_encap(sc, &m_head)) { 1794a5ebadc6SPyun YongHyeon if (m_head == NULL) 1795a5ebadc6SPyun YongHyeon break; 1796a5ebadc6SPyun YongHyeon IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1797a5ebadc6SPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1798a5ebadc6SPyun YongHyeon break; 1799a5ebadc6SPyun YongHyeon } 1800a5ebadc6SPyun YongHyeon 1801a5ebadc6SPyun YongHyeon enq++; 1802a5ebadc6SPyun YongHyeon /* 1803a5ebadc6SPyun YongHyeon * If there's a BPF listener, bounce a copy of this frame 1804a5ebadc6SPyun YongHyeon * to him. 1805a5ebadc6SPyun YongHyeon */ 1806a5ebadc6SPyun YongHyeon ETHER_BPF_MTAP(ifp, m_head); 1807a5ebadc6SPyun YongHyeon } 1808a5ebadc6SPyun YongHyeon 1809a5ebadc6SPyun YongHyeon if (enq > 0) { 1810a5ebadc6SPyun YongHyeon /* 1811a5ebadc6SPyun YongHyeon * Reading TXCSR takes very long time under heavy load 1812a5ebadc6SPyun YongHyeon * so cache TXCSR value and writes the ORed value with 1813a5ebadc6SPyun YongHyeon * the kick command to the TXCSR. This saves one register 1814a5ebadc6SPyun YongHyeon * access cycle. 1815a5ebadc6SPyun YongHyeon */ 1816a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1817a5ebadc6SPyun YongHyeon TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1818a5ebadc6SPyun YongHyeon /* Set a timeout in case the chip goes out to lunch. */ 1819a5ebadc6SPyun YongHyeon sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1820a5ebadc6SPyun YongHyeon } 1821a5ebadc6SPyun YongHyeon 1822a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1823a5ebadc6SPyun YongHyeon } 1824a5ebadc6SPyun YongHyeon 1825a5ebadc6SPyun YongHyeon static void 1826a5ebadc6SPyun YongHyeon jme_watchdog(struct jme_softc *sc) 1827a5ebadc6SPyun YongHyeon { 1828a5ebadc6SPyun YongHyeon struct ifnet *ifp; 1829a5ebadc6SPyun YongHyeon 1830a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 1831a5ebadc6SPyun YongHyeon 1832a5ebadc6SPyun YongHyeon if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1833a5ebadc6SPyun YongHyeon return; 1834a5ebadc6SPyun YongHyeon 1835a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 1836a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1837a5ebadc6SPyun YongHyeon if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1838a5ebadc6SPyun YongHyeon ifp->if_oerrors++; 183932f8942aSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1840a5ebadc6SPyun YongHyeon jme_init_locked(sc); 1841a5ebadc6SPyun YongHyeon return; 1842a5ebadc6SPyun YongHyeon } 1843a5ebadc6SPyun YongHyeon jme_txeof(sc); 1844a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_cnt == 0) { 1845a5ebadc6SPyun YongHyeon if_printf(sc->jme_ifp, 1846a5ebadc6SPyun YongHyeon "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1847a5ebadc6SPyun YongHyeon if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1848a5ebadc6SPyun YongHyeon taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1849a5ebadc6SPyun YongHyeon return; 1850a5ebadc6SPyun YongHyeon } 1851a5ebadc6SPyun YongHyeon 1852a5ebadc6SPyun YongHyeon if_printf(sc->jme_ifp, "watchdog timeout\n"); 1853a5ebadc6SPyun YongHyeon ifp->if_oerrors++; 185432f8942aSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1855a5ebadc6SPyun YongHyeon jme_init_locked(sc); 1856a5ebadc6SPyun YongHyeon if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1857a5ebadc6SPyun YongHyeon taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1858a5ebadc6SPyun YongHyeon } 1859a5ebadc6SPyun YongHyeon 1860a5ebadc6SPyun YongHyeon static int 1861a5ebadc6SPyun YongHyeon jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1862a5ebadc6SPyun YongHyeon { 1863a5ebadc6SPyun YongHyeon struct jme_softc *sc; 1864a5ebadc6SPyun YongHyeon struct ifreq *ifr; 1865a5ebadc6SPyun YongHyeon struct mii_data *mii; 1866a5ebadc6SPyun YongHyeon uint32_t reg; 1867a5ebadc6SPyun YongHyeon int error, mask; 1868a5ebadc6SPyun YongHyeon 1869a5ebadc6SPyun YongHyeon sc = ifp->if_softc; 1870a5ebadc6SPyun YongHyeon ifr = (struct ifreq *)data; 1871a5ebadc6SPyun YongHyeon error = 0; 1872a5ebadc6SPyun YongHyeon switch (cmd) { 1873a5ebadc6SPyun YongHyeon case SIOCSIFMTU: 1874a5ebadc6SPyun YongHyeon if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1875a5ebadc6SPyun YongHyeon ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1876a5ebadc6SPyun YongHyeon ifr->ifr_mtu > JME_MAX_MTU)) { 1877a5ebadc6SPyun YongHyeon error = EINVAL; 1878a5ebadc6SPyun YongHyeon break; 1879a5ebadc6SPyun YongHyeon } 1880a5ebadc6SPyun YongHyeon 1881a5ebadc6SPyun YongHyeon if (ifp->if_mtu != ifr->ifr_mtu) { 1882a5ebadc6SPyun YongHyeon /* 1883a5ebadc6SPyun YongHyeon * No special configuration is required when interface 1884a5ebadc6SPyun YongHyeon * MTU is changed but availability of TSO/Tx checksum 1885a5ebadc6SPyun YongHyeon * offload should be chcked against new MTU size as 1886a5ebadc6SPyun YongHyeon * FIFO size is just 2K. 1887a5ebadc6SPyun YongHyeon */ 1888a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1889a5ebadc6SPyun YongHyeon if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1890a5ebadc6SPyun YongHyeon ifp->if_capenable &= 1891a5ebadc6SPyun YongHyeon ~(IFCAP_TXCSUM | IFCAP_TSO4); 1892a5ebadc6SPyun YongHyeon ifp->if_hwassist &= 1893a5ebadc6SPyun YongHyeon ~(JME_CSUM_FEATURES | CSUM_TSO); 1894a5ebadc6SPyun YongHyeon VLAN_CAPABILITIES(ifp); 1895a5ebadc6SPyun YongHyeon } 1896a5ebadc6SPyun YongHyeon ifp->if_mtu = ifr->ifr_mtu; 189732f8942aSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 189832f8942aSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1899a5ebadc6SPyun YongHyeon jme_init_locked(sc); 190032f8942aSPyun YongHyeon } 1901a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1902a5ebadc6SPyun YongHyeon } 1903a5ebadc6SPyun YongHyeon break; 1904a5ebadc6SPyun YongHyeon case SIOCSIFFLAGS: 1905a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1906a5ebadc6SPyun YongHyeon if ((ifp->if_flags & IFF_UP) != 0) { 1907a5ebadc6SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1908a5ebadc6SPyun YongHyeon if (((ifp->if_flags ^ sc->jme_if_flags) 1909a5ebadc6SPyun YongHyeon & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1910a5ebadc6SPyun YongHyeon jme_set_filter(sc); 1911a5ebadc6SPyun YongHyeon } else { 1912a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 1913a5ebadc6SPyun YongHyeon jme_init_locked(sc); 1914a5ebadc6SPyun YongHyeon } 1915a5ebadc6SPyun YongHyeon } else { 1916a5ebadc6SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1917a5ebadc6SPyun YongHyeon jme_stop(sc); 1918a5ebadc6SPyun YongHyeon } 1919a5ebadc6SPyun YongHyeon sc->jme_if_flags = ifp->if_flags; 1920a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1921a5ebadc6SPyun YongHyeon break; 1922a5ebadc6SPyun YongHyeon case SIOCADDMULTI: 1923a5ebadc6SPyun YongHyeon case SIOCDELMULTI: 1924a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1925a5ebadc6SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1926a5ebadc6SPyun YongHyeon jme_set_filter(sc); 1927a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1928a5ebadc6SPyun YongHyeon break; 1929a5ebadc6SPyun YongHyeon case SIOCSIFMEDIA: 1930a5ebadc6SPyun YongHyeon case SIOCGIFMEDIA: 1931a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 1932a5ebadc6SPyun YongHyeon error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1933a5ebadc6SPyun YongHyeon break; 1934a5ebadc6SPyun YongHyeon case SIOCSIFCAP: 1935a5ebadc6SPyun YongHyeon JME_LOCK(sc); 1936a5ebadc6SPyun YongHyeon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1937a5ebadc6SPyun YongHyeon if ((mask & IFCAP_TXCSUM) != 0 && 1938a5ebadc6SPyun YongHyeon ifp->if_mtu < JME_TX_FIFO_SIZE) { 1939a5ebadc6SPyun YongHyeon if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1940a5ebadc6SPyun YongHyeon ifp->if_capenable ^= IFCAP_TXCSUM; 1941a5ebadc6SPyun YongHyeon if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1942a5ebadc6SPyun YongHyeon ifp->if_hwassist |= JME_CSUM_FEATURES; 1943a5ebadc6SPyun YongHyeon else 1944a5ebadc6SPyun YongHyeon ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1945a5ebadc6SPyun YongHyeon } 1946a5ebadc6SPyun YongHyeon } 1947a5ebadc6SPyun YongHyeon if ((mask & IFCAP_RXCSUM) != 0 && 1948a5ebadc6SPyun YongHyeon (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1949a5ebadc6SPyun YongHyeon ifp->if_capenable ^= IFCAP_RXCSUM; 1950a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_RXMAC); 1951a5ebadc6SPyun YongHyeon reg &= ~RXMAC_CSUM_ENB; 1952a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1953a5ebadc6SPyun YongHyeon reg |= RXMAC_CSUM_ENB; 1954a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXMAC, reg); 1955a5ebadc6SPyun YongHyeon } 1956a5ebadc6SPyun YongHyeon if ((mask & IFCAP_TSO4) != 0 && 1957a5ebadc6SPyun YongHyeon ifp->if_mtu < JME_TX_FIFO_SIZE) { 1958a5ebadc6SPyun YongHyeon if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1959a5ebadc6SPyun YongHyeon ifp->if_capenable ^= IFCAP_TSO4; 1960a5ebadc6SPyun YongHyeon if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1961a5ebadc6SPyun YongHyeon ifp->if_hwassist |= CSUM_TSO; 1962a5ebadc6SPyun YongHyeon else 1963a5ebadc6SPyun YongHyeon ifp->if_hwassist &= ~CSUM_TSO; 1964a5ebadc6SPyun YongHyeon } 1965a5ebadc6SPyun YongHyeon } 1966a5ebadc6SPyun YongHyeon if ((mask & IFCAP_WOL_MAGIC) != 0 && 1967a5ebadc6SPyun YongHyeon (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0) 1968a5ebadc6SPyun YongHyeon ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1969a5ebadc6SPyun YongHyeon if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1970a5ebadc6SPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1971a5ebadc6SPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 19727bd35300SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTSO) != 0 && 19737bd35300SPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 19747bd35300SPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1975a5ebadc6SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1976a5ebadc6SPyun YongHyeon (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1977a5ebadc6SPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1978a5ebadc6SPyun YongHyeon jme_set_vlan(sc); 1979a5ebadc6SPyun YongHyeon } 1980a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 1981a5ebadc6SPyun YongHyeon VLAN_CAPABILITIES(ifp); 1982a5ebadc6SPyun YongHyeon break; 1983a5ebadc6SPyun YongHyeon default: 1984a5ebadc6SPyun YongHyeon error = ether_ioctl(ifp, cmd, data); 1985a5ebadc6SPyun YongHyeon break; 1986a5ebadc6SPyun YongHyeon } 1987a5ebadc6SPyun YongHyeon 1988a5ebadc6SPyun YongHyeon return (error); 1989a5ebadc6SPyun YongHyeon } 1990a5ebadc6SPyun YongHyeon 1991a5ebadc6SPyun YongHyeon static void 1992a5ebadc6SPyun YongHyeon jme_mac_config(struct jme_softc *sc) 1993a5ebadc6SPyun YongHyeon { 1994a5ebadc6SPyun YongHyeon struct mii_data *mii; 1995cf8f254fSPyun YongHyeon uint32_t ghc, gpreg, rxmac, txmac, txpause; 1996f37739d7SPyun YongHyeon uint32_t txclk; 1997a5ebadc6SPyun YongHyeon 1998a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 1999a5ebadc6SPyun YongHyeon 2000a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 2001a5ebadc6SPyun YongHyeon 2002a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2003a5ebadc6SPyun YongHyeon DELAY(10); 2004a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_GHC, 0); 2005a5ebadc6SPyun YongHyeon ghc = 0; 2006f37739d7SPyun YongHyeon txclk = 0; 2007a5ebadc6SPyun YongHyeon rxmac = CSR_READ_4(sc, JME_RXMAC); 2008a5ebadc6SPyun YongHyeon rxmac &= ~RXMAC_FC_ENB; 2009a5ebadc6SPyun YongHyeon txmac = CSR_READ_4(sc, JME_TXMAC); 2010a5ebadc6SPyun YongHyeon txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2011a5ebadc6SPyun YongHyeon txpause = CSR_READ_4(sc, JME_TXPFC); 2012a5ebadc6SPyun YongHyeon txpause &= ~TXPFC_PAUSE_ENB; 2013a5ebadc6SPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2014a5ebadc6SPyun YongHyeon ghc |= GHC_FULL_DUPLEX; 2015a5ebadc6SPyun YongHyeon rxmac &= ~RXMAC_COLL_DET_ENB; 2016a5ebadc6SPyun YongHyeon txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2017a5ebadc6SPyun YongHyeon TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2018a5ebadc6SPyun YongHyeon TXMAC_FRAME_BURST); 2019a5ebadc6SPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2020a5ebadc6SPyun YongHyeon txpause |= TXPFC_PAUSE_ENB; 2021a5ebadc6SPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2022a5ebadc6SPyun YongHyeon rxmac |= RXMAC_FC_ENB; 2023a5ebadc6SPyun YongHyeon /* Disable retry transmit timer/retry limit. */ 2024a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2025a5ebadc6SPyun YongHyeon ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2026a5ebadc6SPyun YongHyeon } else { 2027a5ebadc6SPyun YongHyeon rxmac |= RXMAC_COLL_DET_ENB; 2028a5ebadc6SPyun YongHyeon txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2029a5ebadc6SPyun YongHyeon /* Enable retry transmit timer/retry limit. */ 2030a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2031a5ebadc6SPyun YongHyeon TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2032a5ebadc6SPyun YongHyeon } 2033a5ebadc6SPyun YongHyeon /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2034a5ebadc6SPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 2035a5ebadc6SPyun YongHyeon case IFM_10_T: 2036a5ebadc6SPyun YongHyeon ghc |= GHC_SPEED_10; 2037f37739d7SPyun YongHyeon txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2038a5ebadc6SPyun YongHyeon break; 2039a5ebadc6SPyun YongHyeon case IFM_100_TX: 2040a5ebadc6SPyun YongHyeon ghc |= GHC_SPEED_100; 2041f37739d7SPyun YongHyeon txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2042a5ebadc6SPyun YongHyeon break; 2043a5ebadc6SPyun YongHyeon case IFM_1000_T: 2044a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2045a5ebadc6SPyun YongHyeon break; 2046a5ebadc6SPyun YongHyeon ghc |= GHC_SPEED_1000; 2047f37739d7SPyun YongHyeon txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2048a5ebadc6SPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2049a5ebadc6SPyun YongHyeon txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2050a5ebadc6SPyun YongHyeon break; 2051a5ebadc6SPyun YongHyeon default: 2052a5ebadc6SPyun YongHyeon break; 2053a5ebadc6SPyun YongHyeon } 20548de8f265SPyun YongHyeon if (sc->jme_rev == DEVICEID_JMC250 && 20558de8f265SPyun YongHyeon sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2056cf8f254fSPyun YongHyeon /* 2057cf8f254fSPyun YongHyeon * Workaround occasional packet loss issue of JMC250 A2 2058cf8f254fSPyun YongHyeon * when it runs on half-duplex media. 2059cf8f254fSPyun YongHyeon */ 2060cf8f254fSPyun YongHyeon gpreg = CSR_READ_4(sc, JME_GPREG1); 2061cf8f254fSPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2062cf8f254fSPyun YongHyeon gpreg &= ~GPREG1_HDPX_FIX; 2063cf8f254fSPyun YongHyeon else 2064cf8f254fSPyun YongHyeon gpreg |= GPREG1_HDPX_FIX; 2065cf8f254fSPyun YongHyeon CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2066cf8f254fSPyun YongHyeon /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 20678de8f265SPyun YongHyeon if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 20688de8f265SPyun YongHyeon /* Extend interface FIFO depth. */ 20698de8f265SPyun YongHyeon jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 20708de8f265SPyun YongHyeon 0x1B, 0x0000); 20718de8f265SPyun YongHyeon } else { 20728de8f265SPyun YongHyeon /* Select default interface FIFO depth. */ 20738de8f265SPyun YongHyeon jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 20748de8f265SPyun YongHyeon 0x1B, 0x0004); 20758de8f265SPyun YongHyeon } 20768de8f265SPyun YongHyeon } 2077f37739d7SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2078f37739d7SPyun YongHyeon ghc |= txclk; 2079a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_GHC, ghc); 2080a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2081a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXMAC, txmac); 2082a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXPFC, txpause); 2083a5ebadc6SPyun YongHyeon } 2084a5ebadc6SPyun YongHyeon 2085a5ebadc6SPyun YongHyeon static void 2086a5ebadc6SPyun YongHyeon jme_link_task(void *arg, int pending) 2087a5ebadc6SPyun YongHyeon { 2088a5ebadc6SPyun YongHyeon struct jme_softc *sc; 2089a5ebadc6SPyun YongHyeon struct mii_data *mii; 2090a5ebadc6SPyun YongHyeon struct ifnet *ifp; 2091a5ebadc6SPyun YongHyeon struct jme_txdesc *txd; 2092a5ebadc6SPyun YongHyeon bus_addr_t paddr; 2093a5ebadc6SPyun YongHyeon int i; 2094a5ebadc6SPyun YongHyeon 2095a5ebadc6SPyun YongHyeon sc = (struct jme_softc *)arg; 2096a5ebadc6SPyun YongHyeon 2097a5ebadc6SPyun YongHyeon JME_LOCK(sc); 2098a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 2099a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 2100a5ebadc6SPyun YongHyeon if (mii == NULL || ifp == NULL || 2101a5ebadc6SPyun YongHyeon (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2102a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 2103a5ebadc6SPyun YongHyeon return; 2104a5ebadc6SPyun YongHyeon } 2105a5ebadc6SPyun YongHyeon 2106a5ebadc6SPyun YongHyeon sc->jme_flags &= ~JME_FLAG_LINK; 2107a5ebadc6SPyun YongHyeon if ((mii->mii_media_status & IFM_AVALID) != 0) { 2108a5ebadc6SPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 2109a5ebadc6SPyun YongHyeon case IFM_10_T: 2110a5ebadc6SPyun YongHyeon case IFM_100_TX: 2111a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_LINK; 2112a5ebadc6SPyun YongHyeon break; 2113a5ebadc6SPyun YongHyeon case IFM_1000_T: 21147a4e8171SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2115a5ebadc6SPyun YongHyeon break; 2116a5ebadc6SPyun YongHyeon sc->jme_flags |= JME_FLAG_LINK; 2117a5ebadc6SPyun YongHyeon break; 2118a5ebadc6SPyun YongHyeon default: 2119a5ebadc6SPyun YongHyeon break; 2120a5ebadc6SPyun YongHyeon } 2121a5ebadc6SPyun YongHyeon } 2122a5ebadc6SPyun YongHyeon 2123a5ebadc6SPyun YongHyeon /* 2124a5ebadc6SPyun YongHyeon * Disabling Rx/Tx MACs have a side-effect of resetting 2125a5ebadc6SPyun YongHyeon * JME_TXNDA/JME_RXNDA register to the first address of 2126a5ebadc6SPyun YongHyeon * Tx/Rx descriptor address. So driver should reset its 2127a5ebadc6SPyun YongHyeon * internal procucer/consumer pointer and reclaim any 2128a5ebadc6SPyun YongHyeon * allocated resources. Note, just saving the value of 2129a5ebadc6SPyun YongHyeon * JME_TXNDA and JME_RXNDA registers before stopping MAC 2130a5ebadc6SPyun YongHyeon * and restoring JME_TXNDA/JME_RXNDA register is not 2131a5ebadc6SPyun YongHyeon * sufficient to make sure correct MAC state because 2132a5ebadc6SPyun YongHyeon * stopping MAC operation can take a while and hardware 2133a5ebadc6SPyun YongHyeon * might have updated JME_TXNDA/JME_RXNDA registers 2134a5ebadc6SPyun YongHyeon * during the stop operation. 2135a5ebadc6SPyun YongHyeon */ 2136a5ebadc6SPyun YongHyeon /* Block execution of task. */ 2137a5ebadc6SPyun YongHyeon taskqueue_block(sc->jme_tq); 2138a5ebadc6SPyun YongHyeon /* Disable interrupts and stop driver. */ 2139a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2140a5ebadc6SPyun YongHyeon ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2141a5ebadc6SPyun YongHyeon callout_stop(&sc->jme_tick_ch); 2142a5ebadc6SPyun YongHyeon sc->jme_watchdog_timer = 0; 2143a5ebadc6SPyun YongHyeon 2144a5ebadc6SPyun YongHyeon /* Stop receiver/transmitter. */ 2145a5ebadc6SPyun YongHyeon jme_stop_rx(sc); 2146a5ebadc6SPyun YongHyeon jme_stop_tx(sc); 2147a5ebadc6SPyun YongHyeon 2148a5ebadc6SPyun YongHyeon /* XXX Drain all queued tasks. */ 2149a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 2150a5ebadc6SPyun YongHyeon taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2151a5ebadc6SPyun YongHyeon taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 2152a5ebadc6SPyun YongHyeon JME_LOCK(sc); 2153a5ebadc6SPyun YongHyeon 2154a5ebadc6SPyun YongHyeon jme_rxintr(sc, JME_RX_RING_CNT); 2155a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rxhead != NULL) 2156a5ebadc6SPyun YongHyeon m_freem(sc->jme_cdata.jme_rxhead); 2157a5ebadc6SPyun YongHyeon JME_RXCHAIN_RESET(sc); 2158a5ebadc6SPyun YongHyeon jme_txeof(sc); 2159a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_cnt != 0) { 2160a5ebadc6SPyun YongHyeon /* Remove queued packets for transmit. */ 2161a5ebadc6SPyun YongHyeon for (i = 0; i < JME_TX_RING_CNT; i++) { 2162a5ebadc6SPyun YongHyeon txd = &sc->jme_cdata.jme_txdesc[i]; 2163a5ebadc6SPyun YongHyeon if (txd->tx_m != NULL) { 2164a5ebadc6SPyun YongHyeon bus_dmamap_sync( 2165a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_tag, 2166a5ebadc6SPyun YongHyeon txd->tx_dmamap, 2167a5ebadc6SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 2168a5ebadc6SPyun YongHyeon bus_dmamap_unload( 2169a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_tag, 2170a5ebadc6SPyun YongHyeon txd->tx_dmamap); 2171a5ebadc6SPyun YongHyeon m_freem(txd->tx_m); 2172a5ebadc6SPyun YongHyeon txd->tx_m = NULL; 2173a5ebadc6SPyun YongHyeon txd->tx_ndesc = 0; 2174a5ebadc6SPyun YongHyeon ifp->if_oerrors++; 2175a5ebadc6SPyun YongHyeon } 2176a5ebadc6SPyun YongHyeon } 2177a5ebadc6SPyun YongHyeon } 2178a5ebadc6SPyun YongHyeon 2179a5ebadc6SPyun YongHyeon /* 2180a5ebadc6SPyun YongHyeon * Reuse configured Rx descriptors and reset 2181a5ebadc6SPyun YongHyeon * procuder/consumer index. 2182a5ebadc6SPyun YongHyeon */ 2183a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_cons = 0; 21847e86a37eSPyun YongHyeon sc->jme_morework = 0; 2185a5ebadc6SPyun YongHyeon jme_init_tx_ring(sc); 2186a5ebadc6SPyun YongHyeon /* Initialize shadow status block. */ 2187a5ebadc6SPyun YongHyeon jme_init_ssb(sc); 2188a5ebadc6SPyun YongHyeon 2189a5ebadc6SPyun YongHyeon /* Program MAC with resolved speed/duplex/flow-control. */ 2190a5ebadc6SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2191a5ebadc6SPyun YongHyeon jme_mac_config(sc); 2192450ab472SPyun YongHyeon jme_stats_clear(sc); 2193a5ebadc6SPyun YongHyeon 2194a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2195a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2196a5ebadc6SPyun YongHyeon 2197a5ebadc6SPyun YongHyeon /* Set Tx ring address to the hardware. */ 2198a5ebadc6SPyun YongHyeon paddr = JME_TX_RING_ADDR(sc, 0); 2199a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2200a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2201a5ebadc6SPyun YongHyeon 2202a5ebadc6SPyun YongHyeon /* Set Rx ring address to the hardware. */ 2203a5ebadc6SPyun YongHyeon paddr = JME_RX_RING_ADDR(sc, 0); 2204a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2205a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2206a5ebadc6SPyun YongHyeon 2207a5ebadc6SPyun YongHyeon /* Restart receiver/transmitter. */ 2208a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2209a5ebadc6SPyun YongHyeon RXCSR_RXQ_START); 2210a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2211a5ebadc6SPyun YongHyeon } 2212a5ebadc6SPyun YongHyeon 2213a5ebadc6SPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_RUNNING; 2214a5ebadc6SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2215a5ebadc6SPyun YongHyeon callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2216a5ebadc6SPyun YongHyeon /* Unblock execution of task. */ 2217a5ebadc6SPyun YongHyeon taskqueue_unblock(sc->jme_tq); 2218a5ebadc6SPyun YongHyeon /* Reenable interrupts. */ 2219a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2220a5ebadc6SPyun YongHyeon 2221a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 2222a5ebadc6SPyun YongHyeon } 2223a5ebadc6SPyun YongHyeon 2224a5ebadc6SPyun YongHyeon static int 2225a5ebadc6SPyun YongHyeon jme_intr(void *arg) 2226a5ebadc6SPyun YongHyeon { 2227a5ebadc6SPyun YongHyeon struct jme_softc *sc; 2228a5ebadc6SPyun YongHyeon uint32_t status; 2229a5ebadc6SPyun YongHyeon 2230a5ebadc6SPyun YongHyeon sc = (struct jme_softc *)arg; 2231a5ebadc6SPyun YongHyeon 2232a5ebadc6SPyun YongHyeon status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2233a5ebadc6SPyun YongHyeon if (status == 0 || status == 0xFFFFFFFF) 2234a5ebadc6SPyun YongHyeon return (FILTER_STRAY); 2235a5ebadc6SPyun YongHyeon /* Disable interrupts. */ 2236a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2237a5ebadc6SPyun YongHyeon taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2238a5ebadc6SPyun YongHyeon 2239a5ebadc6SPyun YongHyeon return (FILTER_HANDLED); 2240a5ebadc6SPyun YongHyeon } 2241a5ebadc6SPyun YongHyeon 2242a5ebadc6SPyun YongHyeon static void 2243a5ebadc6SPyun YongHyeon jme_int_task(void *arg, int pending) 2244a5ebadc6SPyun YongHyeon { 2245a5ebadc6SPyun YongHyeon struct jme_softc *sc; 2246a5ebadc6SPyun YongHyeon struct ifnet *ifp; 2247a5ebadc6SPyun YongHyeon uint32_t status; 2248a5ebadc6SPyun YongHyeon int more; 2249a5ebadc6SPyun YongHyeon 2250a5ebadc6SPyun YongHyeon sc = (struct jme_softc *)arg; 2251a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 2252a5ebadc6SPyun YongHyeon 2253a5ebadc6SPyun YongHyeon status = CSR_READ_4(sc, JME_INTR_STATUS); 22547e86a37eSPyun YongHyeon if (sc->jme_morework != 0) { 22557e86a37eSPyun YongHyeon sc->jme_morework = 0; 2256a5ebadc6SPyun YongHyeon status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2257a5ebadc6SPyun YongHyeon } 2258a5ebadc6SPyun YongHyeon if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2259a5ebadc6SPyun YongHyeon goto done; 2260a5ebadc6SPyun YongHyeon /* Reset PCC counter/timer and Ack interrupts. */ 2261a5ebadc6SPyun YongHyeon status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2262a5ebadc6SPyun YongHyeon if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2263a5ebadc6SPyun YongHyeon status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2264a5ebadc6SPyun YongHyeon if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2265a5ebadc6SPyun YongHyeon status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2266a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2267a5ebadc6SPyun YongHyeon more = 0; 2268a5ebadc6SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2269a5ebadc6SPyun YongHyeon if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2270a5ebadc6SPyun YongHyeon more = jme_rxintr(sc, sc->jme_process_limit); 2271a5ebadc6SPyun YongHyeon if (more != 0) 22727e86a37eSPyun YongHyeon sc->jme_morework = 1; 2273a5ebadc6SPyun YongHyeon } 2274a5ebadc6SPyun YongHyeon if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2275a5ebadc6SPyun YongHyeon /* 2276a5ebadc6SPyun YongHyeon * Notify hardware availability of new Rx 2277a5ebadc6SPyun YongHyeon * buffers. 2278a5ebadc6SPyun YongHyeon * Reading RXCSR takes very long time under 2279a5ebadc6SPyun YongHyeon * heavy load so cache RXCSR value and writes 2280a5ebadc6SPyun YongHyeon * the ORed value with the kick command to 2281a5ebadc6SPyun YongHyeon * the RXCSR. This saves one register access 2282a5ebadc6SPyun YongHyeon * cycle. 2283a5ebadc6SPyun YongHyeon */ 2284a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2285a5ebadc6SPyun YongHyeon RXCSR_RX_ENB | RXCSR_RXQ_START); 2286a5ebadc6SPyun YongHyeon } 2287a5ebadc6SPyun YongHyeon /* 2288a5ebadc6SPyun YongHyeon * Reclaiming Tx buffers are deferred to make jme(4) run 2289a5ebadc6SPyun YongHyeon * without locks held. 2290a5ebadc6SPyun YongHyeon */ 2291a5ebadc6SPyun YongHyeon if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2292a5ebadc6SPyun YongHyeon taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 2293a5ebadc6SPyun YongHyeon } 2294a5ebadc6SPyun YongHyeon 2295a5ebadc6SPyun YongHyeon if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2296a5ebadc6SPyun YongHyeon taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2297a5ebadc6SPyun YongHyeon return; 2298a5ebadc6SPyun YongHyeon } 2299a5ebadc6SPyun YongHyeon done: 2300a5ebadc6SPyun YongHyeon /* Reenable interrupts. */ 2301a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2302a5ebadc6SPyun YongHyeon } 2303a5ebadc6SPyun YongHyeon 2304a5ebadc6SPyun YongHyeon static void 2305a5ebadc6SPyun YongHyeon jme_txeof(struct jme_softc *sc) 2306a5ebadc6SPyun YongHyeon { 2307a5ebadc6SPyun YongHyeon struct ifnet *ifp; 2308a5ebadc6SPyun YongHyeon struct jme_txdesc *txd; 2309a5ebadc6SPyun YongHyeon uint32_t status; 2310a5ebadc6SPyun YongHyeon int cons, nsegs; 2311a5ebadc6SPyun YongHyeon 2312a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 2313a5ebadc6SPyun YongHyeon 2314a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 2315a5ebadc6SPyun YongHyeon 2316a5ebadc6SPyun YongHyeon cons = sc->jme_cdata.jme_tx_cons; 2317a5ebadc6SPyun YongHyeon if (cons == sc->jme_cdata.jme_tx_prod) 2318a5ebadc6SPyun YongHyeon return; 2319a5ebadc6SPyun YongHyeon 2320a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2321a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map, 2322a5ebadc6SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2323a5ebadc6SPyun YongHyeon 2324a5ebadc6SPyun YongHyeon /* 2325a5ebadc6SPyun YongHyeon * Go through our Tx list and free mbufs for those 2326a5ebadc6SPyun YongHyeon * frames which have been transmitted. 2327a5ebadc6SPyun YongHyeon */ 2328a5ebadc6SPyun YongHyeon for (; cons != sc->jme_cdata.jme_tx_prod;) { 2329a5ebadc6SPyun YongHyeon txd = &sc->jme_cdata.jme_txdesc[cons]; 2330a5ebadc6SPyun YongHyeon status = le32toh(txd->tx_desc->flags); 2331a5ebadc6SPyun YongHyeon if ((status & JME_TD_OWN) == JME_TD_OWN) 2332a5ebadc6SPyun YongHyeon break; 2333a5ebadc6SPyun YongHyeon 2334a5ebadc6SPyun YongHyeon if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2335a5ebadc6SPyun YongHyeon ifp->if_oerrors++; 2336a5ebadc6SPyun YongHyeon else { 2337a5ebadc6SPyun YongHyeon ifp->if_opackets++; 2338a5ebadc6SPyun YongHyeon if ((status & JME_TD_COLLISION) != 0) 2339a5ebadc6SPyun YongHyeon ifp->if_collisions += 2340a5ebadc6SPyun YongHyeon le32toh(txd->tx_desc->buflen) & 2341a5ebadc6SPyun YongHyeon JME_TD_BUF_LEN_MASK; 2342a5ebadc6SPyun YongHyeon } 2343a5ebadc6SPyun YongHyeon /* 2344a5ebadc6SPyun YongHyeon * Only the first descriptor of multi-descriptor 2345a5ebadc6SPyun YongHyeon * transmission is updated so driver have to skip entire 2346a5ebadc6SPyun YongHyeon * chained buffers for the transmiited frame. In other 2347a5ebadc6SPyun YongHyeon * words, JME_TD_OWN bit is valid only at the first 2348a5ebadc6SPyun YongHyeon * descriptor of a multi-descriptor transmission. 2349a5ebadc6SPyun YongHyeon */ 2350a5ebadc6SPyun YongHyeon for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2351a5ebadc6SPyun YongHyeon sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2352a5ebadc6SPyun YongHyeon JME_DESC_INC(cons, JME_TX_RING_CNT); 2353a5ebadc6SPyun YongHyeon } 2354a5ebadc6SPyun YongHyeon 2355a5ebadc6SPyun YongHyeon /* Reclaim transferred mbufs. */ 2356a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2357a5ebadc6SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 2358a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2359a5ebadc6SPyun YongHyeon 2360a5ebadc6SPyun YongHyeon KASSERT(txd->tx_m != NULL, 2361a5ebadc6SPyun YongHyeon ("%s: freeing NULL mbuf!\n", __func__)); 2362a5ebadc6SPyun YongHyeon m_freem(txd->tx_m); 2363a5ebadc6SPyun YongHyeon txd->tx_m = NULL; 2364a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2365a5ebadc6SPyun YongHyeon KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2366a5ebadc6SPyun YongHyeon ("%s: Active Tx desc counter was garbled\n", __func__)); 2367a5ebadc6SPyun YongHyeon txd->tx_ndesc = 0; 2368a5ebadc6SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2369a5ebadc6SPyun YongHyeon } 2370a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_cons = cons; 2371a5ebadc6SPyun YongHyeon /* Unarm watchog timer when there is no pending descriptors in queue. */ 2372a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_tx_cnt == 0) 2373a5ebadc6SPyun YongHyeon sc->jme_watchdog_timer = 0; 2374a5ebadc6SPyun YongHyeon 2375a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2376a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map, 2377a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2378a5ebadc6SPyun YongHyeon } 2379a5ebadc6SPyun YongHyeon 2380a5ebadc6SPyun YongHyeon static __inline void 2381a5ebadc6SPyun YongHyeon jme_discard_rxbuf(struct jme_softc *sc, int cons) 2382a5ebadc6SPyun YongHyeon { 2383a5ebadc6SPyun YongHyeon struct jme_desc *desc; 2384a5ebadc6SPyun YongHyeon 2385a5ebadc6SPyun YongHyeon desc = &sc->jme_rdata.jme_rx_ring[cons]; 2386a5ebadc6SPyun YongHyeon desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2387a5ebadc6SPyun YongHyeon desc->buflen = htole32(MCLBYTES); 2388a5ebadc6SPyun YongHyeon } 2389a5ebadc6SPyun YongHyeon 2390a5ebadc6SPyun YongHyeon /* Receive a frame. */ 2391a5ebadc6SPyun YongHyeon static void 2392a5ebadc6SPyun YongHyeon jme_rxeof(struct jme_softc *sc) 2393a5ebadc6SPyun YongHyeon { 2394a5ebadc6SPyun YongHyeon struct ifnet *ifp; 2395a5ebadc6SPyun YongHyeon struct jme_desc *desc; 2396a5ebadc6SPyun YongHyeon struct jme_rxdesc *rxd; 2397a5ebadc6SPyun YongHyeon struct mbuf *mp, *m; 2398a5ebadc6SPyun YongHyeon uint32_t flags, status; 2399a5ebadc6SPyun YongHyeon int cons, count, nsegs; 2400a5ebadc6SPyun YongHyeon 2401a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 2402a5ebadc6SPyun YongHyeon 2403a5ebadc6SPyun YongHyeon cons = sc->jme_cdata.jme_rx_cons; 2404a5ebadc6SPyun YongHyeon desc = &sc->jme_rdata.jme_rx_ring[cons]; 2405a5ebadc6SPyun YongHyeon flags = le32toh(desc->flags); 2406a5ebadc6SPyun YongHyeon status = le32toh(desc->buflen); 2407a5ebadc6SPyun YongHyeon nsegs = JME_RX_NSEGS(status); 2408a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2409a5ebadc6SPyun YongHyeon if ((status & JME_RX_ERR_STAT) != 0) { 2410a5ebadc6SPyun YongHyeon ifp->if_ierrors++; 2411a5ebadc6SPyun YongHyeon jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2412a5ebadc6SPyun YongHyeon #ifdef JME_SHOW_ERRORS 2413a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2414a5ebadc6SPyun YongHyeon __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2415a5ebadc6SPyun YongHyeon #endif 2416a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_cons += nsegs; 2417a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2418a5ebadc6SPyun YongHyeon return; 2419a5ebadc6SPyun YongHyeon } 2420a5ebadc6SPyun YongHyeon 2421a5ebadc6SPyun YongHyeon for (count = 0; count < nsegs; count++, 2422a5ebadc6SPyun YongHyeon JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2423a5ebadc6SPyun YongHyeon rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2424a5ebadc6SPyun YongHyeon mp = rxd->rx_m; 2425a5ebadc6SPyun YongHyeon /* Add a new receive buffer to the ring. */ 2426a5ebadc6SPyun YongHyeon if (jme_newbuf(sc, rxd) != 0) { 2427a5ebadc6SPyun YongHyeon ifp->if_iqdrops++; 2428a5ebadc6SPyun YongHyeon /* Reuse buffer. */ 242943742818SPyun YongHyeon for (; count < nsegs; count++) { 243043742818SPyun YongHyeon jme_discard_rxbuf(sc, cons); 243143742818SPyun YongHyeon JME_DESC_INC(cons, JME_RX_RING_CNT); 243243742818SPyun YongHyeon } 2433a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rxhead != NULL) { 2434a5ebadc6SPyun YongHyeon m_freem(sc->jme_cdata.jme_rxhead); 2435a5ebadc6SPyun YongHyeon JME_RXCHAIN_RESET(sc); 2436a5ebadc6SPyun YongHyeon } 2437a5ebadc6SPyun YongHyeon break; 2438a5ebadc6SPyun YongHyeon } 2439a5ebadc6SPyun YongHyeon 2440a5ebadc6SPyun YongHyeon /* 2441a5ebadc6SPyun YongHyeon * Assume we've received a full sized frame. 2442a5ebadc6SPyun YongHyeon * Actual size is fixed when we encounter the end of 2443a5ebadc6SPyun YongHyeon * multi-segmented frame. 2444a5ebadc6SPyun YongHyeon */ 2445a5ebadc6SPyun YongHyeon mp->m_len = MCLBYTES; 2446a5ebadc6SPyun YongHyeon 2447a5ebadc6SPyun YongHyeon /* Chain received mbufs. */ 2448a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rxhead == NULL) { 2449a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rxhead = mp; 2450a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rxtail = mp; 2451a5ebadc6SPyun YongHyeon } else { 2452a5ebadc6SPyun YongHyeon /* 2453a5ebadc6SPyun YongHyeon * Receive processor can receive a maximum frame 2454a5ebadc6SPyun YongHyeon * size of 65535 bytes. 2455a5ebadc6SPyun YongHyeon */ 2456a5ebadc6SPyun YongHyeon mp->m_flags &= ~M_PKTHDR; 2457a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rxtail->m_next = mp; 2458a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rxtail = mp; 2459a5ebadc6SPyun YongHyeon } 2460a5ebadc6SPyun YongHyeon 2461a5ebadc6SPyun YongHyeon if (count == nsegs - 1) { 2462a5ebadc6SPyun YongHyeon /* Last desc. for this frame. */ 2463a5ebadc6SPyun YongHyeon m = sc->jme_cdata.jme_rxhead; 2464a5ebadc6SPyun YongHyeon m->m_flags |= M_PKTHDR; 2465a5ebadc6SPyun YongHyeon m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2466a5ebadc6SPyun YongHyeon if (nsegs > 1) { 2467a5ebadc6SPyun YongHyeon /* Set first mbuf size. */ 2468a5ebadc6SPyun YongHyeon m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2469a5ebadc6SPyun YongHyeon /* Set last mbuf size. */ 2470a5ebadc6SPyun YongHyeon mp->m_len = sc->jme_cdata.jme_rxlen - 2471a5ebadc6SPyun YongHyeon ((MCLBYTES - JME_RX_PAD_BYTES) + 2472a5ebadc6SPyun YongHyeon (MCLBYTES * (nsegs - 2))); 2473a5ebadc6SPyun YongHyeon } else 2474a5ebadc6SPyun YongHyeon m->m_len = sc->jme_cdata.jme_rxlen; 2475a5ebadc6SPyun YongHyeon m->m_pkthdr.rcvif = ifp; 2476a5ebadc6SPyun YongHyeon 2477a5ebadc6SPyun YongHyeon /* 2478a5ebadc6SPyun YongHyeon * Account for 10bytes auto padding which is used 2479a5ebadc6SPyun YongHyeon * to align IP header on 32bit boundary. Also note, 2480a5ebadc6SPyun YongHyeon * CRC bytes is automatically removed by the 2481a5ebadc6SPyun YongHyeon * hardware. 2482a5ebadc6SPyun YongHyeon */ 2483a5ebadc6SPyun YongHyeon m->m_data += JME_RX_PAD_BYTES; 2484a5ebadc6SPyun YongHyeon 2485a5ebadc6SPyun YongHyeon /* Set checksum information. */ 2486a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2487a5ebadc6SPyun YongHyeon (flags & JME_RD_IPV4) != 0) { 2488a5ebadc6SPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2489a5ebadc6SPyun YongHyeon if ((flags & JME_RD_IPCSUM) != 0) 2490a5ebadc6SPyun YongHyeon m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2491a5ebadc6SPyun YongHyeon if (((flags & JME_RD_MORE_FRAG) == 0) && 2492a5ebadc6SPyun YongHyeon ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2493a5ebadc6SPyun YongHyeon (JME_RD_TCP | JME_RD_TCPCSUM) || 2494a5ebadc6SPyun YongHyeon (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2495a5ebadc6SPyun YongHyeon (JME_RD_UDP | JME_RD_UDPCSUM))) { 2496a5ebadc6SPyun YongHyeon m->m_pkthdr.csum_flags |= 2497a5ebadc6SPyun YongHyeon CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2498a5ebadc6SPyun YongHyeon m->m_pkthdr.csum_data = 0xffff; 2499a5ebadc6SPyun YongHyeon } 2500a5ebadc6SPyun YongHyeon } 2501a5ebadc6SPyun YongHyeon 2502a5ebadc6SPyun YongHyeon /* Check for VLAN tagged packets. */ 2503a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2504a5ebadc6SPyun YongHyeon (flags & JME_RD_VLAN_TAG) != 0) { 2505a5ebadc6SPyun YongHyeon m->m_pkthdr.ether_vtag = 2506a5ebadc6SPyun YongHyeon flags & JME_RD_VLAN_MASK; 2507a5ebadc6SPyun YongHyeon m->m_flags |= M_VLANTAG; 2508a5ebadc6SPyun YongHyeon } 2509a5ebadc6SPyun YongHyeon 2510a5ebadc6SPyun YongHyeon ifp->if_ipackets++; 2511a5ebadc6SPyun YongHyeon /* Pass it on. */ 2512a5ebadc6SPyun YongHyeon (*ifp->if_input)(ifp, m); 2513a5ebadc6SPyun YongHyeon 2514a5ebadc6SPyun YongHyeon /* Reset mbuf chains. */ 2515a5ebadc6SPyun YongHyeon JME_RXCHAIN_RESET(sc); 2516a5ebadc6SPyun YongHyeon } 2517a5ebadc6SPyun YongHyeon } 2518a5ebadc6SPyun YongHyeon 2519a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_cons += nsegs; 2520a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2521a5ebadc6SPyun YongHyeon } 2522a5ebadc6SPyun YongHyeon 2523a5ebadc6SPyun YongHyeon static int 2524a5ebadc6SPyun YongHyeon jme_rxintr(struct jme_softc *sc, int count) 2525a5ebadc6SPyun YongHyeon { 2526a5ebadc6SPyun YongHyeon struct jme_desc *desc; 2527a5ebadc6SPyun YongHyeon int nsegs, prog, pktlen; 2528a5ebadc6SPyun YongHyeon 2529a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2530a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_map, 2531a5ebadc6SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2532a5ebadc6SPyun YongHyeon 2533a5ebadc6SPyun YongHyeon for (prog = 0; count > 0; prog++) { 2534a5ebadc6SPyun YongHyeon desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2535a5ebadc6SPyun YongHyeon if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2536a5ebadc6SPyun YongHyeon break; 2537a5ebadc6SPyun YongHyeon if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2538a5ebadc6SPyun YongHyeon break; 2539a5ebadc6SPyun YongHyeon nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2540a5ebadc6SPyun YongHyeon /* 2541a5ebadc6SPyun YongHyeon * Check number of segments against received bytes. 2542a5ebadc6SPyun YongHyeon * Non-matching value would indicate that hardware 2543a5ebadc6SPyun YongHyeon * is still trying to update Rx descriptors. I'm not 2544a5ebadc6SPyun YongHyeon * sure whether this check is needed. 2545a5ebadc6SPyun YongHyeon */ 2546a5ebadc6SPyun YongHyeon pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2547a5ebadc6SPyun YongHyeon if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES)) 2548a5ebadc6SPyun YongHyeon break; 2549a5ebadc6SPyun YongHyeon prog++; 2550a5ebadc6SPyun YongHyeon /* Received a frame. */ 2551a5ebadc6SPyun YongHyeon jme_rxeof(sc); 2552a5ebadc6SPyun YongHyeon count -= nsegs; 2553a5ebadc6SPyun YongHyeon } 2554a5ebadc6SPyun YongHyeon 2555a5ebadc6SPyun YongHyeon if (prog > 0) 2556a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2557a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_map, 2558a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2559a5ebadc6SPyun YongHyeon 2560a5ebadc6SPyun YongHyeon return (count > 0 ? 0 : EAGAIN); 2561a5ebadc6SPyun YongHyeon } 2562a5ebadc6SPyun YongHyeon 2563a5ebadc6SPyun YongHyeon static void 2564a5ebadc6SPyun YongHyeon jme_tick(void *arg) 2565a5ebadc6SPyun YongHyeon { 2566a5ebadc6SPyun YongHyeon struct jme_softc *sc; 2567a5ebadc6SPyun YongHyeon struct mii_data *mii; 2568a5ebadc6SPyun YongHyeon 2569a5ebadc6SPyun YongHyeon sc = (struct jme_softc *)arg; 2570a5ebadc6SPyun YongHyeon 2571a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 2572a5ebadc6SPyun YongHyeon 2573a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 2574a5ebadc6SPyun YongHyeon mii_tick(mii); 2575a5ebadc6SPyun YongHyeon /* 2576a5ebadc6SPyun YongHyeon * Reclaim Tx buffers that have been completed. It's not 2577a5ebadc6SPyun YongHyeon * needed here but it would release allocated mbuf chains 2578a5ebadc6SPyun YongHyeon * faster and limit the maximum delay to a hz. 2579a5ebadc6SPyun YongHyeon */ 2580a5ebadc6SPyun YongHyeon jme_txeof(sc); 2581450ab472SPyun YongHyeon jme_stats_update(sc); 2582a5ebadc6SPyun YongHyeon jme_watchdog(sc); 2583a5ebadc6SPyun YongHyeon callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2584a5ebadc6SPyun YongHyeon } 2585a5ebadc6SPyun YongHyeon 2586a5ebadc6SPyun YongHyeon static void 2587a5ebadc6SPyun YongHyeon jme_reset(struct jme_softc *sc) 2588a5ebadc6SPyun YongHyeon { 2589a5ebadc6SPyun YongHyeon 2590a5ebadc6SPyun YongHyeon /* Stop receiver, transmitter. */ 2591a5ebadc6SPyun YongHyeon jme_stop_rx(sc); 2592a5ebadc6SPyun YongHyeon jme_stop_tx(sc); 2593a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2594a5ebadc6SPyun YongHyeon DELAY(10); 2595a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_GHC, 0); 2596a5ebadc6SPyun YongHyeon } 2597a5ebadc6SPyun YongHyeon 2598a5ebadc6SPyun YongHyeon static void 2599a5ebadc6SPyun YongHyeon jme_init(void *xsc) 2600a5ebadc6SPyun YongHyeon { 2601a5ebadc6SPyun YongHyeon struct jme_softc *sc; 2602a5ebadc6SPyun YongHyeon 2603a5ebadc6SPyun YongHyeon sc = (struct jme_softc *)xsc; 2604a5ebadc6SPyun YongHyeon JME_LOCK(sc); 2605a5ebadc6SPyun YongHyeon jme_init_locked(sc); 2606a5ebadc6SPyun YongHyeon JME_UNLOCK(sc); 2607a5ebadc6SPyun YongHyeon } 2608a5ebadc6SPyun YongHyeon 2609a5ebadc6SPyun YongHyeon static void 2610a5ebadc6SPyun YongHyeon jme_init_locked(struct jme_softc *sc) 2611a5ebadc6SPyun YongHyeon { 2612a5ebadc6SPyun YongHyeon struct ifnet *ifp; 2613a5ebadc6SPyun YongHyeon struct mii_data *mii; 2614a5ebadc6SPyun YongHyeon uint8_t eaddr[ETHER_ADDR_LEN]; 2615a5ebadc6SPyun YongHyeon bus_addr_t paddr; 2616a5ebadc6SPyun YongHyeon uint32_t reg; 2617a5ebadc6SPyun YongHyeon int error; 2618a5ebadc6SPyun YongHyeon 2619a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 2620a5ebadc6SPyun YongHyeon 2621a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 2622a5ebadc6SPyun YongHyeon mii = device_get_softc(sc->jme_miibus); 2623a5ebadc6SPyun YongHyeon 262432f8942aSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 262532f8942aSPyun YongHyeon return; 2626a5ebadc6SPyun YongHyeon /* 2627a5ebadc6SPyun YongHyeon * Cancel any pending I/O. 2628a5ebadc6SPyun YongHyeon */ 2629a5ebadc6SPyun YongHyeon jme_stop(sc); 2630a5ebadc6SPyun YongHyeon 2631a5ebadc6SPyun YongHyeon /* 2632a5ebadc6SPyun YongHyeon * Reset the chip to a known state. 2633a5ebadc6SPyun YongHyeon */ 2634a5ebadc6SPyun YongHyeon jme_reset(sc); 2635a5ebadc6SPyun YongHyeon 2636a5ebadc6SPyun YongHyeon /* Init descriptors. */ 2637a5ebadc6SPyun YongHyeon error = jme_init_rx_ring(sc); 2638a5ebadc6SPyun YongHyeon if (error != 0) { 2639a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, 2640a5ebadc6SPyun YongHyeon "%s: initialization failed: no memory for Rx buffers.\n", 2641a5ebadc6SPyun YongHyeon __func__); 2642a5ebadc6SPyun YongHyeon jme_stop(sc); 2643a5ebadc6SPyun YongHyeon return; 2644a5ebadc6SPyun YongHyeon } 2645a5ebadc6SPyun YongHyeon jme_init_tx_ring(sc); 2646a5ebadc6SPyun YongHyeon /* Initialize shadow status block. */ 2647a5ebadc6SPyun YongHyeon jme_init_ssb(sc); 2648a5ebadc6SPyun YongHyeon 2649a5ebadc6SPyun YongHyeon /* Reprogram the station address. */ 2650a5ebadc6SPyun YongHyeon bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2651a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_PAR0, 2652a5ebadc6SPyun YongHyeon eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2653a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2654a5ebadc6SPyun YongHyeon 2655a5ebadc6SPyun YongHyeon /* 2656a5ebadc6SPyun YongHyeon * Configure Tx queue. 2657a5ebadc6SPyun YongHyeon * Tx priority queue weight value : 0 2658a5ebadc6SPyun YongHyeon * Tx FIFO threshold for processing next packet : 16QW 2659a5ebadc6SPyun YongHyeon * Maximum Tx DMA length : 512 2660a5ebadc6SPyun YongHyeon * Allow Tx DMA burst. 2661a5ebadc6SPyun YongHyeon */ 2662a5ebadc6SPyun YongHyeon sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2663a5ebadc6SPyun YongHyeon sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2664a5ebadc6SPyun YongHyeon sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2665a5ebadc6SPyun YongHyeon sc->jme_txcsr |= sc->jme_tx_dma_size; 2666a5ebadc6SPyun YongHyeon sc->jme_txcsr |= TXCSR_DMA_BURST; 2667a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2668a5ebadc6SPyun YongHyeon 2669a5ebadc6SPyun YongHyeon /* Set Tx descriptor counter. */ 2670a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2671a5ebadc6SPyun YongHyeon 2672a5ebadc6SPyun YongHyeon /* Set Tx ring address to the hardware. */ 2673a5ebadc6SPyun YongHyeon paddr = JME_TX_RING_ADDR(sc, 0); 2674a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2675a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2676a5ebadc6SPyun YongHyeon 2677a5ebadc6SPyun YongHyeon /* Configure TxMAC parameters. */ 2678a5ebadc6SPyun YongHyeon reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2679a5ebadc6SPyun YongHyeon reg |= TXMAC_THRESH_1_PKT; 2680a5ebadc6SPyun YongHyeon reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2681a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXMAC, reg); 2682a5ebadc6SPyun YongHyeon 2683a5ebadc6SPyun YongHyeon /* 2684a5ebadc6SPyun YongHyeon * Configure Rx queue. 2685a5ebadc6SPyun YongHyeon * FIFO full threshold for transmitting Tx pause packet : 128T 2686a5ebadc6SPyun YongHyeon * FIFO threshold for processing next packet : 128QW 2687a5ebadc6SPyun YongHyeon * Rx queue 0 select 2688a5ebadc6SPyun YongHyeon * Max Rx DMA length : 128 2689a5ebadc6SPyun YongHyeon * Rx descriptor retry : 32 2690a5ebadc6SPyun YongHyeon * Rx descriptor retry time gap : 256ns 2691a5ebadc6SPyun YongHyeon * Don't receive runt/bad frame. 2692a5ebadc6SPyun YongHyeon */ 2693a5ebadc6SPyun YongHyeon sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2694a5ebadc6SPyun YongHyeon /* 2695a5ebadc6SPyun YongHyeon * Since Rx FIFO size is 4K bytes, receiving frames larger 2696a5ebadc6SPyun YongHyeon * than 4K bytes will suffer from Rx FIFO overruns. So 2697a5ebadc6SPyun YongHyeon * decrease FIFO threshold to reduce the FIFO overruns for 2698a5ebadc6SPyun YongHyeon * frames larger than 4000 bytes. 2699a5ebadc6SPyun YongHyeon * For best performance of standard MTU sized frames use 2700f37739d7SPyun YongHyeon * maximum allowable FIFO threshold, 128QW. Note these do 2701f37739d7SPyun YongHyeon * not hold on chip full mask verion >=2. For these 2702f37739d7SPyun YongHyeon * controllers 64QW and 128QW are not valid value. 2703a5ebadc6SPyun YongHyeon */ 2704f37739d7SPyun YongHyeon if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2705f37739d7SPyun YongHyeon sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2706f37739d7SPyun YongHyeon else { 2707a5ebadc6SPyun YongHyeon if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2708a5ebadc6SPyun YongHyeon ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2709a5ebadc6SPyun YongHyeon sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2710a5ebadc6SPyun YongHyeon else 2711a5ebadc6SPyun YongHyeon sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2712f37739d7SPyun YongHyeon } 2713a5ebadc6SPyun YongHyeon sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2714a5ebadc6SPyun YongHyeon sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2715a5ebadc6SPyun YongHyeon sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2716a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2717a5ebadc6SPyun YongHyeon 2718a5ebadc6SPyun YongHyeon /* Set Rx descriptor counter. */ 2719a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2720a5ebadc6SPyun YongHyeon 2721a5ebadc6SPyun YongHyeon /* Set Rx ring address to the hardware. */ 2722a5ebadc6SPyun YongHyeon paddr = JME_RX_RING_ADDR(sc, 0); 2723a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2724a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2725a5ebadc6SPyun YongHyeon 2726a5ebadc6SPyun YongHyeon /* Clear receive filter. */ 2727a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXMAC, 0); 2728a5ebadc6SPyun YongHyeon /* Set up the receive filter. */ 2729a5ebadc6SPyun YongHyeon jme_set_filter(sc); 2730a5ebadc6SPyun YongHyeon jme_set_vlan(sc); 2731a5ebadc6SPyun YongHyeon 2732a5ebadc6SPyun YongHyeon /* 2733a5ebadc6SPyun YongHyeon * Disable all WOL bits as WOL can interfere normal Rx 2734a5ebadc6SPyun YongHyeon * operation. Also clear WOL detection status bits. 2735a5ebadc6SPyun YongHyeon */ 2736a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_PMCS); 2737a5ebadc6SPyun YongHyeon reg &= ~PMCS_WOL_ENB_MASK; 2738a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_PMCS, reg); 2739a5ebadc6SPyun YongHyeon 2740a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_RXMAC); 2741a5ebadc6SPyun YongHyeon /* 2742a5ebadc6SPyun YongHyeon * Pad 10bytes right before received frame. This will greatly 2743a5ebadc6SPyun YongHyeon * help Rx performance on strict-alignment architectures as 2744a5ebadc6SPyun YongHyeon * it does not need to copy the frame to align the payload. 2745a5ebadc6SPyun YongHyeon */ 2746a5ebadc6SPyun YongHyeon reg |= RXMAC_PAD_10BYTES; 2747a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2748a5ebadc6SPyun YongHyeon reg |= RXMAC_CSUM_ENB; 2749a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXMAC, reg); 2750a5ebadc6SPyun YongHyeon 2751a5ebadc6SPyun YongHyeon /* Configure general purpose reg0 */ 2752a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_GPREG0); 2753a5ebadc6SPyun YongHyeon reg &= ~GPREG0_PCC_UNIT_MASK; 2754a5ebadc6SPyun YongHyeon /* Set PCC timer resolution to micro-seconds unit. */ 2755a5ebadc6SPyun YongHyeon reg |= GPREG0_PCC_UNIT_US; 2756a5ebadc6SPyun YongHyeon /* 2757a5ebadc6SPyun YongHyeon * Disable all shadow register posting as we have to read 2758a5ebadc6SPyun YongHyeon * JME_INTR_STATUS register in jme_int_task. Also it seems 2759a5ebadc6SPyun YongHyeon * that it's hard to synchronize interrupt status between 2760a5ebadc6SPyun YongHyeon * hardware and software with shadow posting due to 2761a5ebadc6SPyun YongHyeon * requirements of bus_dmamap_sync(9). 2762a5ebadc6SPyun YongHyeon */ 2763a5ebadc6SPyun YongHyeon reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2764a5ebadc6SPyun YongHyeon GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2765a5ebadc6SPyun YongHyeon GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2766a5ebadc6SPyun YongHyeon GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2767a5ebadc6SPyun YongHyeon /* Disable posting of DW0. */ 2768a5ebadc6SPyun YongHyeon reg &= ~GPREG0_POST_DW0_ENB; 2769a5ebadc6SPyun YongHyeon /* Clear PME message. */ 2770a5ebadc6SPyun YongHyeon reg &= ~GPREG0_PME_ENB; 2771a5ebadc6SPyun YongHyeon /* Set PHY address. */ 2772a5ebadc6SPyun YongHyeon reg &= ~GPREG0_PHY_ADDR_MASK; 2773a5ebadc6SPyun YongHyeon reg |= sc->jme_phyaddr; 2774a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_GPREG0, reg); 2775a5ebadc6SPyun YongHyeon 2776a5ebadc6SPyun YongHyeon /* Configure Tx queue 0 packet completion coalescing. */ 2777a5ebadc6SPyun YongHyeon reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2778a5ebadc6SPyun YongHyeon PCCTX_COAL_TO_MASK; 2779a5ebadc6SPyun YongHyeon reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2780a5ebadc6SPyun YongHyeon PCCTX_COAL_PKT_MASK; 2781a5ebadc6SPyun YongHyeon reg |= PCCTX_COAL_TXQ0; 2782a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_PCCTX, reg); 2783a5ebadc6SPyun YongHyeon 2784a5ebadc6SPyun YongHyeon /* Configure Rx queue 0 packet completion coalescing. */ 2785a5ebadc6SPyun YongHyeon reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2786a5ebadc6SPyun YongHyeon PCCRX_COAL_TO_MASK; 2787a5ebadc6SPyun YongHyeon reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2788a5ebadc6SPyun YongHyeon PCCRX_COAL_PKT_MASK; 2789a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_PCCRX0, reg); 2790a5ebadc6SPyun YongHyeon 2791a5ebadc6SPyun YongHyeon /* Configure shadow status block but don't enable posting. */ 2792a5ebadc6SPyun YongHyeon paddr = sc->jme_rdata.jme_ssb_block_paddr; 2793a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2794a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2795a5ebadc6SPyun YongHyeon 2796a5ebadc6SPyun YongHyeon /* Disable Timer 1 and Timer 2. */ 2797a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TIMER1, 0); 2798a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TIMER2, 0); 2799a5ebadc6SPyun YongHyeon 2800a5ebadc6SPyun YongHyeon /* Configure retry transmit period, retry limit value. */ 2801a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXTRHD, 2802a5ebadc6SPyun YongHyeon ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2803a5ebadc6SPyun YongHyeon TXTRHD_RT_PERIOD_MASK) | 2804a5ebadc6SPyun YongHyeon ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2805a5ebadc6SPyun YongHyeon TXTRHD_RT_LIMIT_SHIFT)); 2806a5ebadc6SPyun YongHyeon 2807a5ebadc6SPyun YongHyeon /* Disable RSS. */ 2808a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2809a5ebadc6SPyun YongHyeon 2810a5ebadc6SPyun YongHyeon /* Initialize the interrupt mask. */ 2811a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2812a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2813a5ebadc6SPyun YongHyeon 2814a5ebadc6SPyun YongHyeon /* 2815a5ebadc6SPyun YongHyeon * Enabling Tx/Rx DMA engines and Rx queue processing is 2816a5ebadc6SPyun YongHyeon * done after detection of valid link in jme_link_task. 2817a5ebadc6SPyun YongHyeon */ 2818a5ebadc6SPyun YongHyeon 2819a5ebadc6SPyun YongHyeon sc->jme_flags &= ~JME_FLAG_LINK; 2820a5ebadc6SPyun YongHyeon /* Set the current media. */ 2821a5ebadc6SPyun YongHyeon mii_mediachg(mii); 2822a5ebadc6SPyun YongHyeon 2823a5ebadc6SPyun YongHyeon callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2824a5ebadc6SPyun YongHyeon 2825a5ebadc6SPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_RUNNING; 2826a5ebadc6SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2827a5ebadc6SPyun YongHyeon } 2828a5ebadc6SPyun YongHyeon 2829a5ebadc6SPyun YongHyeon static void 2830a5ebadc6SPyun YongHyeon jme_stop(struct jme_softc *sc) 2831a5ebadc6SPyun YongHyeon { 2832a5ebadc6SPyun YongHyeon struct ifnet *ifp; 2833a5ebadc6SPyun YongHyeon struct jme_txdesc *txd; 2834a5ebadc6SPyun YongHyeon struct jme_rxdesc *rxd; 2835a5ebadc6SPyun YongHyeon int i; 2836a5ebadc6SPyun YongHyeon 2837a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 2838a5ebadc6SPyun YongHyeon /* 2839a5ebadc6SPyun YongHyeon * Mark the interface down and cancel the watchdog timer. 2840a5ebadc6SPyun YongHyeon */ 2841a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 2842a5ebadc6SPyun YongHyeon ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2843a5ebadc6SPyun YongHyeon sc->jme_flags &= ~JME_FLAG_LINK; 2844a5ebadc6SPyun YongHyeon callout_stop(&sc->jme_tick_ch); 2845a5ebadc6SPyun YongHyeon sc->jme_watchdog_timer = 0; 2846a5ebadc6SPyun YongHyeon 2847a5ebadc6SPyun YongHyeon /* 2848a5ebadc6SPyun YongHyeon * Disable interrupts. 2849a5ebadc6SPyun YongHyeon */ 2850a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2851a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2852a5ebadc6SPyun YongHyeon 2853a5ebadc6SPyun YongHyeon /* Disable updating shadow status block. */ 2854a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2855a5ebadc6SPyun YongHyeon CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2856a5ebadc6SPyun YongHyeon 2857a5ebadc6SPyun YongHyeon /* Stop receiver, transmitter. */ 2858a5ebadc6SPyun YongHyeon jme_stop_rx(sc); 2859a5ebadc6SPyun YongHyeon jme_stop_tx(sc); 2860a5ebadc6SPyun YongHyeon 2861a5ebadc6SPyun YongHyeon /* Reclaim Rx/Tx buffers that have been completed. */ 2862a5ebadc6SPyun YongHyeon jme_rxintr(sc, JME_RX_RING_CNT); 2863a5ebadc6SPyun YongHyeon if (sc->jme_cdata.jme_rxhead != NULL) 2864a5ebadc6SPyun YongHyeon m_freem(sc->jme_cdata.jme_rxhead); 2865a5ebadc6SPyun YongHyeon JME_RXCHAIN_RESET(sc); 2866a5ebadc6SPyun YongHyeon jme_txeof(sc); 2867a5ebadc6SPyun YongHyeon /* 2868a5ebadc6SPyun YongHyeon * Free RX and TX mbufs still in the queues. 2869a5ebadc6SPyun YongHyeon */ 2870a5ebadc6SPyun YongHyeon for (i = 0; i < JME_RX_RING_CNT; i++) { 2871a5ebadc6SPyun YongHyeon rxd = &sc->jme_cdata.jme_rxdesc[i]; 2872a5ebadc6SPyun YongHyeon if (rxd->rx_m != NULL) { 2873a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 2874a5ebadc6SPyun YongHyeon rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2875a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 2876a5ebadc6SPyun YongHyeon rxd->rx_dmamap); 2877a5ebadc6SPyun YongHyeon m_freem(rxd->rx_m); 2878a5ebadc6SPyun YongHyeon rxd->rx_m = NULL; 2879a5ebadc6SPyun YongHyeon } 2880a5ebadc6SPyun YongHyeon } 2881a5ebadc6SPyun YongHyeon for (i = 0; i < JME_TX_RING_CNT; i++) { 2882a5ebadc6SPyun YongHyeon txd = &sc->jme_cdata.jme_txdesc[i]; 2883a5ebadc6SPyun YongHyeon if (txd->tx_m != NULL) { 2884a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 2885a5ebadc6SPyun YongHyeon txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2886a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 2887a5ebadc6SPyun YongHyeon txd->tx_dmamap); 2888a5ebadc6SPyun YongHyeon m_freem(txd->tx_m); 2889a5ebadc6SPyun YongHyeon txd->tx_m = NULL; 2890a5ebadc6SPyun YongHyeon txd->tx_ndesc = 0; 2891a5ebadc6SPyun YongHyeon } 2892a5ebadc6SPyun YongHyeon } 2893450ab472SPyun YongHyeon jme_stats_update(sc); 2894450ab472SPyun YongHyeon jme_stats_save(sc); 2895a5ebadc6SPyun YongHyeon } 2896a5ebadc6SPyun YongHyeon 2897a5ebadc6SPyun YongHyeon static void 2898a5ebadc6SPyun YongHyeon jme_stop_tx(struct jme_softc *sc) 2899a5ebadc6SPyun YongHyeon { 2900a5ebadc6SPyun YongHyeon uint32_t reg; 2901a5ebadc6SPyun YongHyeon int i; 2902a5ebadc6SPyun YongHyeon 2903a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_TXCSR); 2904a5ebadc6SPyun YongHyeon if ((reg & TXCSR_TX_ENB) == 0) 2905a5ebadc6SPyun YongHyeon return; 2906a5ebadc6SPyun YongHyeon reg &= ~TXCSR_TX_ENB; 2907a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_TXCSR, reg); 2908a5ebadc6SPyun YongHyeon for (i = JME_TIMEOUT; i > 0; i--) { 2909a5ebadc6SPyun YongHyeon DELAY(1); 2910a5ebadc6SPyun YongHyeon if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2911a5ebadc6SPyun YongHyeon break; 2912a5ebadc6SPyun YongHyeon } 2913a5ebadc6SPyun YongHyeon if (i == 0) 2914a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2915a5ebadc6SPyun YongHyeon } 2916a5ebadc6SPyun YongHyeon 2917a5ebadc6SPyun YongHyeon static void 2918a5ebadc6SPyun YongHyeon jme_stop_rx(struct jme_softc *sc) 2919a5ebadc6SPyun YongHyeon { 2920a5ebadc6SPyun YongHyeon uint32_t reg; 2921a5ebadc6SPyun YongHyeon int i; 2922a5ebadc6SPyun YongHyeon 2923a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_RXCSR); 2924a5ebadc6SPyun YongHyeon if ((reg & RXCSR_RX_ENB) == 0) 2925a5ebadc6SPyun YongHyeon return; 2926a5ebadc6SPyun YongHyeon reg &= ~RXCSR_RX_ENB; 2927a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXCSR, reg); 2928a5ebadc6SPyun YongHyeon for (i = JME_TIMEOUT; i > 0; i--) { 2929a5ebadc6SPyun YongHyeon DELAY(1); 2930a5ebadc6SPyun YongHyeon if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 2931a5ebadc6SPyun YongHyeon break; 2932a5ebadc6SPyun YongHyeon } 2933a5ebadc6SPyun YongHyeon if (i == 0) 2934a5ebadc6SPyun YongHyeon device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 2935a5ebadc6SPyun YongHyeon } 2936a5ebadc6SPyun YongHyeon 2937a5ebadc6SPyun YongHyeon static void 2938a5ebadc6SPyun YongHyeon jme_init_tx_ring(struct jme_softc *sc) 2939a5ebadc6SPyun YongHyeon { 2940a5ebadc6SPyun YongHyeon struct jme_ring_data *rd; 2941a5ebadc6SPyun YongHyeon struct jme_txdesc *txd; 2942a5ebadc6SPyun YongHyeon int i; 2943a5ebadc6SPyun YongHyeon 2944a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_prod = 0; 2945a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_cons = 0; 2946a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_cnt = 0; 2947a5ebadc6SPyun YongHyeon 2948a5ebadc6SPyun YongHyeon rd = &sc->jme_rdata; 2949a5ebadc6SPyun YongHyeon bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 2950a5ebadc6SPyun YongHyeon for (i = 0; i < JME_TX_RING_CNT; i++) { 2951a5ebadc6SPyun YongHyeon txd = &sc->jme_cdata.jme_txdesc[i]; 2952a5ebadc6SPyun YongHyeon txd->tx_m = NULL; 2953a5ebadc6SPyun YongHyeon txd->tx_desc = &rd->jme_tx_ring[i]; 2954a5ebadc6SPyun YongHyeon txd->tx_ndesc = 0; 2955a5ebadc6SPyun YongHyeon } 2956a5ebadc6SPyun YongHyeon 2957a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2958a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_tx_ring_map, 2959a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2960a5ebadc6SPyun YongHyeon } 2961a5ebadc6SPyun YongHyeon 2962a5ebadc6SPyun YongHyeon static void 2963a5ebadc6SPyun YongHyeon jme_init_ssb(struct jme_softc *sc) 2964a5ebadc6SPyun YongHyeon { 2965a5ebadc6SPyun YongHyeon struct jme_ring_data *rd; 2966a5ebadc6SPyun YongHyeon 2967a5ebadc6SPyun YongHyeon rd = &sc->jme_rdata; 2968a5ebadc6SPyun YongHyeon bzero(rd->jme_ssb_block, JME_SSB_SIZE); 2969a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 2970a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2971a5ebadc6SPyun YongHyeon } 2972a5ebadc6SPyun YongHyeon 2973a5ebadc6SPyun YongHyeon static int 2974a5ebadc6SPyun YongHyeon jme_init_rx_ring(struct jme_softc *sc) 2975a5ebadc6SPyun YongHyeon { 2976a5ebadc6SPyun YongHyeon struct jme_ring_data *rd; 2977a5ebadc6SPyun YongHyeon struct jme_rxdesc *rxd; 2978a5ebadc6SPyun YongHyeon int i; 2979a5ebadc6SPyun YongHyeon 2980a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_cons = 0; 2981a5ebadc6SPyun YongHyeon JME_RXCHAIN_RESET(sc); 29827e86a37eSPyun YongHyeon sc->jme_morework = 0; 2983a5ebadc6SPyun YongHyeon 2984a5ebadc6SPyun YongHyeon rd = &sc->jme_rdata; 2985a5ebadc6SPyun YongHyeon bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 2986a5ebadc6SPyun YongHyeon for (i = 0; i < JME_RX_RING_CNT; i++) { 2987a5ebadc6SPyun YongHyeon rxd = &sc->jme_cdata.jme_rxdesc[i]; 2988a5ebadc6SPyun YongHyeon rxd->rx_m = NULL; 2989a5ebadc6SPyun YongHyeon rxd->rx_desc = &rd->jme_rx_ring[i]; 2990a5ebadc6SPyun YongHyeon if (jme_newbuf(sc, rxd) != 0) 2991a5ebadc6SPyun YongHyeon return (ENOBUFS); 2992a5ebadc6SPyun YongHyeon } 2993a5ebadc6SPyun YongHyeon 2994a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2995a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_ring_map, 2996a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2997a5ebadc6SPyun YongHyeon 2998a5ebadc6SPyun YongHyeon return (0); 2999a5ebadc6SPyun YongHyeon } 3000a5ebadc6SPyun YongHyeon 3001a5ebadc6SPyun YongHyeon static int 3002a5ebadc6SPyun YongHyeon jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3003a5ebadc6SPyun YongHyeon { 3004a5ebadc6SPyun YongHyeon struct jme_desc *desc; 3005a5ebadc6SPyun YongHyeon struct mbuf *m; 3006a5ebadc6SPyun YongHyeon bus_dma_segment_t segs[1]; 3007a5ebadc6SPyun YongHyeon bus_dmamap_t map; 3008a5ebadc6SPyun YongHyeon int nsegs; 3009a5ebadc6SPyun YongHyeon 3010a5ebadc6SPyun YongHyeon m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3011a5ebadc6SPyun YongHyeon if (m == NULL) 3012a5ebadc6SPyun YongHyeon return (ENOBUFS); 3013a5ebadc6SPyun YongHyeon /* 3014a5ebadc6SPyun YongHyeon * JMC250 has 64bit boundary alignment limitation so jme(4) 3015a5ebadc6SPyun YongHyeon * takes advantage of 10 bytes padding feature of hardware 3016a5ebadc6SPyun YongHyeon * in order not to copy entire frame to align IP header on 3017a5ebadc6SPyun YongHyeon * 32bit boundary. 3018a5ebadc6SPyun YongHyeon */ 3019a5ebadc6SPyun YongHyeon m->m_len = m->m_pkthdr.len = MCLBYTES; 3020a5ebadc6SPyun YongHyeon 3021a5ebadc6SPyun YongHyeon if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3022a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3023a5ebadc6SPyun YongHyeon m_freem(m); 3024a5ebadc6SPyun YongHyeon return (ENOBUFS); 3025a5ebadc6SPyun YongHyeon } 3026a5ebadc6SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3027a5ebadc6SPyun YongHyeon 3028a5ebadc6SPyun YongHyeon if (rxd->rx_m != NULL) { 3029a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3030a5ebadc6SPyun YongHyeon BUS_DMASYNC_POSTREAD); 3031a5ebadc6SPyun YongHyeon bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3032a5ebadc6SPyun YongHyeon } 3033a5ebadc6SPyun YongHyeon map = rxd->rx_dmamap; 3034a5ebadc6SPyun YongHyeon rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3035a5ebadc6SPyun YongHyeon sc->jme_cdata.jme_rx_sparemap = map; 3036a5ebadc6SPyun YongHyeon bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3037a5ebadc6SPyun YongHyeon BUS_DMASYNC_PREREAD); 3038a5ebadc6SPyun YongHyeon rxd->rx_m = m; 3039a5ebadc6SPyun YongHyeon 3040a5ebadc6SPyun YongHyeon desc = rxd->rx_desc; 3041a5ebadc6SPyun YongHyeon desc->buflen = htole32(segs[0].ds_len); 3042a5ebadc6SPyun YongHyeon desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3043a5ebadc6SPyun YongHyeon desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3044a5ebadc6SPyun YongHyeon desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3045a5ebadc6SPyun YongHyeon 3046a5ebadc6SPyun YongHyeon return (0); 3047a5ebadc6SPyun YongHyeon } 3048a5ebadc6SPyun YongHyeon 3049a5ebadc6SPyun YongHyeon static void 3050a5ebadc6SPyun YongHyeon jme_set_vlan(struct jme_softc *sc) 3051a5ebadc6SPyun YongHyeon { 3052a5ebadc6SPyun YongHyeon struct ifnet *ifp; 3053a5ebadc6SPyun YongHyeon uint32_t reg; 3054a5ebadc6SPyun YongHyeon 3055a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 3056a5ebadc6SPyun YongHyeon 3057a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 3058a5ebadc6SPyun YongHyeon reg = CSR_READ_4(sc, JME_RXMAC); 3059a5ebadc6SPyun YongHyeon reg &= ~RXMAC_VLAN_ENB; 3060a5ebadc6SPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3061a5ebadc6SPyun YongHyeon reg |= RXMAC_VLAN_ENB; 3062a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXMAC, reg); 3063a5ebadc6SPyun YongHyeon } 3064a5ebadc6SPyun YongHyeon 3065a5ebadc6SPyun YongHyeon static void 3066a5ebadc6SPyun YongHyeon jme_set_filter(struct jme_softc *sc) 3067a5ebadc6SPyun YongHyeon { 3068a5ebadc6SPyun YongHyeon struct ifnet *ifp; 3069a5ebadc6SPyun YongHyeon struct ifmultiaddr *ifma; 3070a5ebadc6SPyun YongHyeon uint32_t crc; 3071a5ebadc6SPyun YongHyeon uint32_t mchash[2]; 3072a5ebadc6SPyun YongHyeon uint32_t rxcfg; 3073a5ebadc6SPyun YongHyeon 3074a5ebadc6SPyun YongHyeon JME_LOCK_ASSERT(sc); 3075a5ebadc6SPyun YongHyeon 3076a5ebadc6SPyun YongHyeon ifp = sc->jme_ifp; 3077a5ebadc6SPyun YongHyeon 3078a5ebadc6SPyun YongHyeon rxcfg = CSR_READ_4(sc, JME_RXMAC); 3079a5ebadc6SPyun YongHyeon rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3080a5ebadc6SPyun YongHyeon RXMAC_ALLMULTI); 3081a5ebadc6SPyun YongHyeon /* Always accept frames destined to our station address. */ 3082a5ebadc6SPyun YongHyeon rxcfg |= RXMAC_UNICAST; 3083a5ebadc6SPyun YongHyeon if ((ifp->if_flags & IFF_BROADCAST) != 0) 3084a5ebadc6SPyun YongHyeon rxcfg |= RXMAC_BROADCAST; 3085a5ebadc6SPyun YongHyeon if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3086a5ebadc6SPyun YongHyeon if ((ifp->if_flags & IFF_PROMISC) != 0) 3087a5ebadc6SPyun YongHyeon rxcfg |= RXMAC_PROMISC; 3088a5ebadc6SPyun YongHyeon if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3089a5ebadc6SPyun YongHyeon rxcfg |= RXMAC_ALLMULTI; 3090a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3091a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3092a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3093a5ebadc6SPyun YongHyeon return; 3094a5ebadc6SPyun YongHyeon } 3095a5ebadc6SPyun YongHyeon 3096a5ebadc6SPyun YongHyeon /* 3097a5ebadc6SPyun YongHyeon * Set up the multicast address filter by passing all multicast 3098a5ebadc6SPyun YongHyeon * addresses through a CRC generator, and then using the low-order 3099a5ebadc6SPyun YongHyeon * 6 bits as an index into the 64 bit multicast hash table. The 3100a5ebadc6SPyun YongHyeon * high order bits select the register, while the rest of the bits 3101a5ebadc6SPyun YongHyeon * select the bit within the register. 3102a5ebadc6SPyun YongHyeon */ 3103a5ebadc6SPyun YongHyeon rxcfg |= RXMAC_MULTICAST; 3104a5ebadc6SPyun YongHyeon bzero(mchash, sizeof(mchash)); 3105a5ebadc6SPyun YongHyeon 3106eb956cd0SRobert Watson if_maddr_rlock(ifp); 3107a5ebadc6SPyun YongHyeon TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) { 3108a5ebadc6SPyun YongHyeon if (ifma->ifma_addr->sa_family != AF_LINK) 3109a5ebadc6SPyun YongHyeon continue; 3110a5ebadc6SPyun YongHyeon crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3111a5ebadc6SPyun YongHyeon ifma->ifma_addr), ETHER_ADDR_LEN); 3112a5ebadc6SPyun YongHyeon 3113a5ebadc6SPyun YongHyeon /* Just want the 6 least significant bits. */ 3114a5ebadc6SPyun YongHyeon crc &= 0x3f; 3115a5ebadc6SPyun YongHyeon 3116a5ebadc6SPyun YongHyeon /* Set the corresponding bit in the hash table. */ 3117a5ebadc6SPyun YongHyeon mchash[crc >> 5] |= 1 << (crc & 0x1f); 3118a5ebadc6SPyun YongHyeon } 3119eb956cd0SRobert Watson if_maddr_runlock(ifp); 3120a5ebadc6SPyun YongHyeon 3121a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3122a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3123a5ebadc6SPyun YongHyeon CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3124a5ebadc6SPyun YongHyeon } 3125a5ebadc6SPyun YongHyeon 3126450ab472SPyun YongHyeon static void 3127450ab472SPyun YongHyeon jme_stats_clear(struct jme_softc *sc) 3128450ab472SPyun YongHyeon { 3129450ab472SPyun YongHyeon 3130450ab472SPyun YongHyeon JME_LOCK_ASSERT(sc); 3131450ab472SPyun YongHyeon 3132450ab472SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3133450ab472SPyun YongHyeon return; 3134450ab472SPyun YongHyeon 3135450ab472SPyun YongHyeon /* Disable and clear counters. */ 3136450ab472SPyun YongHyeon CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3137450ab472SPyun YongHyeon /* Activate hw counters. */ 3138450ab472SPyun YongHyeon CSR_WRITE_4(sc, JME_STATCSR, 0); 3139450ab472SPyun YongHyeon CSR_READ_4(sc, JME_STATCSR); 3140450ab472SPyun YongHyeon bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3141450ab472SPyun YongHyeon } 3142450ab472SPyun YongHyeon 3143450ab472SPyun YongHyeon static void 3144450ab472SPyun YongHyeon jme_stats_save(struct jme_softc *sc) 3145450ab472SPyun YongHyeon { 3146450ab472SPyun YongHyeon 3147450ab472SPyun YongHyeon JME_LOCK_ASSERT(sc); 3148450ab472SPyun YongHyeon 3149450ab472SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3150450ab472SPyun YongHyeon return; 3151450ab472SPyun YongHyeon /* Save current counters. */ 3152450ab472SPyun YongHyeon bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3153450ab472SPyun YongHyeon /* Disable and clear counters. */ 3154450ab472SPyun YongHyeon CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3155450ab472SPyun YongHyeon } 3156450ab472SPyun YongHyeon 3157450ab472SPyun YongHyeon static void 3158450ab472SPyun YongHyeon jme_stats_update(struct jme_softc *sc) 3159450ab472SPyun YongHyeon { 3160450ab472SPyun YongHyeon struct jme_hw_stats *stat, *ostat; 3161450ab472SPyun YongHyeon uint32_t reg; 3162450ab472SPyun YongHyeon 3163450ab472SPyun YongHyeon JME_LOCK_ASSERT(sc); 3164450ab472SPyun YongHyeon 3165450ab472SPyun YongHyeon if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3166450ab472SPyun YongHyeon return; 3167450ab472SPyun YongHyeon stat = &sc->jme_stats; 3168450ab472SPyun YongHyeon ostat = &sc->jme_ostats; 3169450ab472SPyun YongHyeon stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3170450ab472SPyun YongHyeon stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3171450ab472SPyun YongHyeon reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3172450ab472SPyun YongHyeon stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3173450ab472SPyun YongHyeon STAT_RX_CRC_ERR_SHIFT; 3174450ab472SPyun YongHyeon stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3175450ab472SPyun YongHyeon STAT_RX_MII_ERR_SHIFT; 3176450ab472SPyun YongHyeon reg = CSR_READ_4(sc, JME_STAT_RXERR); 3177450ab472SPyun YongHyeon stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3178450ab472SPyun YongHyeon STAT_RXERR_OFLOW_SHIFT; 3179450ab472SPyun YongHyeon stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3180450ab472SPyun YongHyeon STAT_RXERR_MPTY_SHIFT; 3181450ab472SPyun YongHyeon reg = CSR_READ_4(sc, JME_STAT_FAIL); 3182450ab472SPyun YongHyeon stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3183450ab472SPyun YongHyeon stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3184450ab472SPyun YongHyeon 3185450ab472SPyun YongHyeon /* Account for previous counters. */ 3186450ab472SPyun YongHyeon stat->rx_good_frames += ostat->rx_good_frames; 3187450ab472SPyun YongHyeon stat->rx_crc_errs += ostat->rx_crc_errs; 3188450ab472SPyun YongHyeon stat->rx_mii_errs += ostat->rx_mii_errs; 3189450ab472SPyun YongHyeon stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3190450ab472SPyun YongHyeon stat->rx_desc_empty += ostat->rx_desc_empty; 3191450ab472SPyun YongHyeon stat->rx_bad_frames += ostat->rx_bad_frames; 3192450ab472SPyun YongHyeon stat->tx_good_frames += ostat->tx_good_frames; 3193450ab472SPyun YongHyeon stat->tx_bad_frames += ostat->tx_bad_frames; 3194450ab472SPyun YongHyeon } 3195450ab472SPyun YongHyeon 3196a5ebadc6SPyun YongHyeon static int 3197a5ebadc6SPyun YongHyeon sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3198a5ebadc6SPyun YongHyeon { 3199a5ebadc6SPyun YongHyeon int error, value; 3200a5ebadc6SPyun YongHyeon 3201a5ebadc6SPyun YongHyeon if (arg1 == NULL) 3202a5ebadc6SPyun YongHyeon return (EINVAL); 3203a5ebadc6SPyun YongHyeon value = *(int *)arg1; 3204a5ebadc6SPyun YongHyeon error = sysctl_handle_int(oidp, &value, 0, req); 3205a5ebadc6SPyun YongHyeon if (error || req->newptr == NULL) 3206a5ebadc6SPyun YongHyeon return (error); 3207a5ebadc6SPyun YongHyeon if (value < low || value > high) 3208a5ebadc6SPyun YongHyeon return (EINVAL); 3209a5ebadc6SPyun YongHyeon *(int *)arg1 = value; 3210a5ebadc6SPyun YongHyeon 3211a5ebadc6SPyun YongHyeon return (0); 3212a5ebadc6SPyun YongHyeon } 3213a5ebadc6SPyun YongHyeon 3214a5ebadc6SPyun YongHyeon static int 3215a5ebadc6SPyun YongHyeon sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3216a5ebadc6SPyun YongHyeon { 3217a5ebadc6SPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, 3218a5ebadc6SPyun YongHyeon PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3219a5ebadc6SPyun YongHyeon } 3220a5ebadc6SPyun YongHyeon 3221a5ebadc6SPyun YongHyeon static int 3222a5ebadc6SPyun YongHyeon sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3223a5ebadc6SPyun YongHyeon { 3224a5ebadc6SPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, 3225a5ebadc6SPyun YongHyeon PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3226a5ebadc6SPyun YongHyeon } 3227a5ebadc6SPyun YongHyeon 3228a5ebadc6SPyun YongHyeon static int 3229a5ebadc6SPyun YongHyeon sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3230a5ebadc6SPyun YongHyeon { 3231a5ebadc6SPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, 3232a5ebadc6SPyun YongHyeon PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3233a5ebadc6SPyun YongHyeon } 3234a5ebadc6SPyun YongHyeon 3235a5ebadc6SPyun YongHyeon static int 3236a5ebadc6SPyun YongHyeon sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3237a5ebadc6SPyun YongHyeon { 3238a5ebadc6SPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, 3239a5ebadc6SPyun YongHyeon PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3240a5ebadc6SPyun YongHyeon } 3241a5ebadc6SPyun YongHyeon 3242a5ebadc6SPyun YongHyeon static int 3243a5ebadc6SPyun YongHyeon sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3244a5ebadc6SPyun YongHyeon { 3245a5ebadc6SPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, 3246a5ebadc6SPyun YongHyeon JME_PROC_MIN, JME_PROC_MAX)); 3247a5ebadc6SPyun YongHyeon } 3248