1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Authors: Ravi Pokala (rpokala@freebsd.org) 5 * 6 * Copyright (c) 2018-2023 Panasas 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ 31 #define _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ 32 33 /* JEDEC DIMMs include one or more SMBus devices. 34 * 35 * At a minimum, they have an EEPROM containing either 256 bytes (DDR3) or 512 36 * bytes (DDR4) of "Serial Presence Detect" (SPD) information. The SPD contains 37 * data used by the memory controller to configure itself, and it also includes 38 * asset information. The layout of SPD data is defined in: 39 * 40 * JEDEC Standard 21-C, Annex K (DDR3) 41 * JEDEC Standard 21-C, Annex L (DDR4) 42 * 43 * DIMMs may also include a "Thermal Sensor on DIMM" (TSOD), which reports 44 * temperature data. While not strictly required, the TSOD is so often included 45 * that JEDEC defined standards for single chips which include both SPD and TSOD 46 * functions. They respond on multiple SMBus addresses, depending on the 47 * function. 48 * 49 * JEDEC Standard 21-C, TSE2002av (DDR3) 50 * JEDEC Standard 21-C, TSE2004av (DDR4) 51 */ 52 53 /* TSE2004av defines several Device Type Identifiers (DTIs), which are the high 54 * nybble of the SMBus address. Addresses with DTIs of PROTECT (or PAGE, which 55 * has the same value) are essentially "broadcast" addresses; all SPD devices 56 * respond to them, changing their mode based on the Logical Serial Address 57 * (LSA) encoded in bits [3:1]. For normal SPD access, bits [3:1] encode the 58 * DIMM slot number. 59 */ 60 #define JEDEC_SPD_PAGE_SIZE 256 61 #define JEDEC_DTI_SPD 0xa0 62 #define JEDEC_DTI_TSOD 0x30 63 #define JEDEC_DTI_PROTECT 0x60 64 #define JEDEC_LSA_PROTECT_SET0 0x02 65 #define JEDEC_LSA_PROTECT_SET1 0x08 66 #define JEDEC_LSA_PROTECT_SET2 0x0a 67 #define JEDEC_LSA_PROTECT_SET3 0x00 68 #define JEDEC_LSA_PROTECT_CLR 0x06 69 #define JEDEC_LSA_PROTECT_GET0 0x03 70 #define JEDEC_LSA_PROTECT_GET1 0x09 71 #define JEDEC_LSA_PROTECT_GET2 0x0b 72 #define JEDEC_LSA_PROTECT_GET3 0x01 73 #define JEDEC_DTI_PAGE 0x60 74 #define JEDEC_LSA_PAGE_SET0 0x0c 75 #define JEDEC_LSA_PAGE_SET1 0x0e 76 #define JEDEC_LSA_PAGE_GET 0x0d 77 78 /* The offsets and lengths of various SPD bytes are defined in Annex K (DDR3) 79 * and Annex L (DDR4). Conveniently, the DRAM type is at the same offset for 80 * both versions. 81 * 82 * This list only includes information needed to get the asset information and 83 * calculate the DIMM capacity. 84 */ 85 #define SPD_OFFSET_DRAM_TYPE 2 86 #define SPD_OFFSET_DDR3_SDRAM_CAPACITY 4 87 #define SPD_OFFSET_DDR3_DIMM_RANKS 7 88 #define SPD_OFFSET_DDR3_SDRAM_WIDTH 7 89 #define SPD_OFFSET_DDR3_BUS_WIDTH 8 90 #define SPD_OFFSET_DDR3_TSOD_PRESENT 32 91 #define SPD_OFFSET_DDR3_MOD_MFG_YEAR 120 92 #define SPD_OFFSET_DDR3_MOD_MFG_WEEK 121 93 #define SPD_OFFSET_DDR3_SERIAL 122 94 #define SPD_LEN_DDR3_SERIAL 4 95 #define SPD_OFFSET_DDR3_PARTNUM 128 96 #define SPD_LEN_DDR3_PARTNUM 18 97 #define SPD_OFFSET_DDR4_SDRAM_CAPACITY 4 98 #define SPD_OFFSET_DDR4_SDRAM_PKG_TYPE 6 99 #define SPD_OFFSET_DDR4_DIMM_RANKS 12 100 #define SPD_OFFSET_DDR4_SDRAM_WIDTH 12 101 #define SPD_OFFSET_DDR4_BUS_WIDTH 13 102 #define SPD_OFFSET_DDR4_TSOD_PRESENT 14 103 #define SPD_OFFSET_DDR4_MOD_MFG_YEAR 323 104 #define SPD_OFFSET_DDR4_MOD_MFG_WEEK 324 105 #define SPD_OFFSET_DDR4_SERIAL 325 106 #define SPD_LEN_DDR4_SERIAL 4 107 #define SPD_OFFSET_DDR4_PARTNUM 329 108 #define SPD_LEN_DDR4_PARTNUM 20 109 110 /* The "DRAM Type" field of the SPD enumerates various memory technologies which 111 * have been used over the years. The list is append-only, so we need only refer 112 * to the latest SPD specification. In this case, Annex L for DDR4. 113 */ 114 enum dram_type { 115 DRAM_TYPE_RESERVED = 0x00, 116 DRAM_TYPE_FAST_PAGE_MODE = 0x01, 117 DRAM_TYPE_EDO = 0x02, 118 DRAM_TYPE_PIPLEINED_NYBBLE = 0x03, 119 DRAM_TYPE_SDRAM = 0x04, 120 DRAM_TYPE_ROM = 0x05, 121 DRAM_TYPE_DDR_SGRAM = 0x06, 122 DRAM_TYPE_DDR_SDRAM = 0x07, 123 DRAM_TYPE_DDR2_SDRAM = 0x08, 124 DRAM_TYPE_DDR2_SDRAM_FBDIMM = 0x09, 125 DRAM_TYPE_DDR2_SDRAM_FBDIMM_PROBE = 0x0a, 126 DRAM_TYPE_DDR3_SDRAM = 0x0b, 127 DRAM_TYPE_DDR4_SDRAM = 0x0c, 128 DRAM_TYPE_RESERVED_0D = 0x0d, 129 DRAM_TYPE_DDR4E_SDRAM = 0x0e, 130 DRAM_TYPE_LPDDR3_SDRAM = 0x0f, 131 DRAM_TYPE_LPDDR4_SDRAM = 0x10, 132 }; 133 134 /* The TSOD is accessed using a simple word interface, which is identical 135 * between TSE2002av (DDR3) and TSE2004av (DDR4). 136 */ 137 #define TSOD_REG_CAPABILITES 0 138 #define TSOD_REG_CONFIG 1 139 #define TSOD_REG_LIM_HIGH 2 140 #define TSOD_REG_LIM_LOW 3 141 #define TSOD_REG_LIM_CRIT 4 142 #define TSOD_REG_TEMPERATURE 5 143 #define TSOD_REG_MANUFACTURER 6 144 #define TSOD_REG_DEV_REV 7 145 146 #endif /* _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ */ 147 148 /* vi: set ts=8 sw=4 sts=8 noet: */ 149