xref: /freebsd/sys/dev/ixl/i40e_osdep.h (revision 98e0ffaefb0f241cda3a72395d3be04192ae0d47)
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3   Copyright (c) 2013-2014, Intel Corporation
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _I40E_OSDEP_H_
36 #define _I40E_OSDEP_H_
37 
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/endian.h>
42 #include <sys/mbuf.h>
43 #include <sys/protosw.h>
44 #include <sys/socket.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/bus.h>
48 #include <machine/bus.h>
49 #include <sys/rman.h>
50 #include <machine/resource.h>
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53 #include <machine/clock.h>
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pcireg.h>
56 
57 #define ASSERT(x) if(!(x)) panic("IXL: x")
58 
59 #define i40e_usec_delay(x) DELAY(x)
60 #define i40e_msec_delay(x) DELAY(1000*(x))
61 
62 #define DBG 0
63 #define MSGOUT(S, A, B)     printf(S "\n", A, B)
64 #define DEBUGFUNC(F)        DEBUGOUT(F);
65 #if DBG
66 	#define DEBUGOUT(S)         printf(S "\n")
67 	#define DEBUGOUT1(S,A)      printf(S "\n",A)
68 	#define DEBUGOUT2(S,A,B)    printf(S "\n",A,B)
69 	#define DEBUGOUT3(S,A,B,C)  printf(S "\n",A,B,C)
70 	#define DEBUGOUT7(S,A,B,C,D,E,F,G)  printf(S "\n",A,B,C,D,E,F,G)
71 #else
72 	#define DEBUGOUT(S)
73 	#define DEBUGOUT1(S,A)
74 	#define DEBUGOUT2(S,A,B)
75 	#define DEBUGOUT3(S,A,B,C)
76 	#define DEBUGOUT6(S,A,B,C,D,E,F)
77 	#define DEBUGOUT7(S,A,B,C,D,E,F,G)
78 #endif
79 
80 #define UNREFERENCED_XPARAMETER
81 #define UNREFERENCED_PARAMETER(_p)
82 #define UNREFERENCED_1PARAMETER(_p)
83 #define UNREFERENCED_2PARAMETER(_p, _q)
84 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
85 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
86 
87 #define STATIC	static
88 #define INLINE  inline
89 
90 #define FALSE               0
91 #define false               0 /* shared code requires this */
92 #define TRUE                1
93 #define true                1
94 #define CMD_MEM_WRT_INVALIDATE          0x0010  /* BIT_4 */
95 #define PCI_COMMAND_REGISTER            PCIR_COMMAND
96 #define ARRAY_SIZE(a)		(sizeof(a) / sizeof((a)[0]))
97 
98 #define i40e_memset(a, b, c, d)  memset((a), (b), (c))
99 #define i40e_memcpy(a, b, c, d)  memcpy((a), (b), (c))
100 
101 #define CPU_TO_LE16(o)	htole16(o)
102 #define CPU_TO_LE32(s)	htole32(s)
103 #define CPU_TO_LE64(h)	htole64(h)
104 #define LE16_TO_CPU(a)	le16toh(a)
105 #define LE32_TO_CPU(c)	le32toh(c)
106 #define LE64_TO_CPU(k)	le64toh(k)
107 
108 #define I40E_NTOHS(a)	ntohs(a)
109 #define I40E_NTOHL(a)	ntohl(a)
110 #define I40E_HTONS(a)	htons(a)
111 #define I40E_HTONL(a)	htonl(a)
112 
113 #define FIELD_SIZEOF(x, y) (sizeof(((x*)0)->y))
114 
115 typedef uint8_t		u8;
116 typedef int8_t		s8;
117 typedef uint16_t	u16;
118 typedef int16_t		s16;
119 typedef uint32_t	u32;
120 typedef int32_t		s32;
121 typedef uint64_t	u64;
122 
123 /* long string relief */
124 typedef enum i40e_status_code i40e_status;
125 
126 #define __le16  u16
127 #define __le32  u32
128 #define __le64  u64
129 #define __be16  u16
130 #define __be32  u32
131 #define __be64  u64
132 
133 /* SW spinlock */
134 struct i40e_spinlock {
135         struct mtx mutex;
136 };
137 
138 #define le16_to_cpu
139 
140 #if defined(__amd64__) || defined(i386)
141 static __inline
142 void prefetch(void *x)
143 {
144 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
145 }
146 #else
147 #define	prefetch(x)
148 #endif
149 
150 struct i40e_osdep {
151 	bus_space_tag_t		mem_bus_space_tag;
152 	bus_space_handle_t	mem_bus_space_handle;
153 	bus_size_t		mem_bus_space_size;
154 	uint32_t		flush_reg;
155 	struct device		*dev;
156 };
157 
158 struct i40e_dma_mem {
159 	void			*va;
160 	u64			pa;
161 	bus_dma_tag_t		tag;
162 	bus_dmamap_t		map;
163 	bus_dma_segment_t	seg;
164 	bus_size_t              size;
165 	int			nseg;
166 	int                     flags;
167 };
168 
169 struct i40e_hw; /* forward decl */
170 u16	i40e_read_pci_cfg(struct i40e_hw *, u32);
171 void	i40e_write_pci_cfg(struct i40e_hw *, u32, u16);
172 
173 #define i40e_debug(h, m, s, ...)  i40e_debug_d(h, m, s, ##__VA_ARGS__)
174 extern void i40e_debug_d(void *hw, u32 mask, char *fmt_str, ...);
175 
176 struct i40e_virt_mem {
177 	void *va;
178 	u32 size;
179 };
180 
181 /*
182 ** This hardware supports either 16 or 32 byte rx descriptors
183 ** we default here to the larger size.
184 */
185 #define i40e_rx_desc i40e_32byte_rx_desc
186 
187 static __inline uint32_t
188 rd32_osdep(struct i40e_osdep *osdep, uint32_t reg)
189 {
190 
191 	KASSERT(reg < osdep->mem_bus_space_size,
192 	    ("ixl: register offset %#jx too large (max is %#jx",
193 	    (uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));
194 
195 	return (bus_space_read_4(osdep->mem_bus_space_tag,
196 	    osdep->mem_bus_space_handle, reg));
197 }
198 
199 static __inline void
200 wr32_osdep(struct i40e_osdep *osdep, uint32_t reg, uint32_t value)
201 {
202 
203 	KASSERT(reg < osdep->mem_bus_space_size,
204 	    ("ixl: register offset %#jx too large (max is %#jx",
205 	    (uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));
206 
207 	bus_space_write_4(osdep->mem_bus_space_tag,
208 	    osdep->mem_bus_space_handle, reg, value);
209 }
210 
211 static __inline void
212 ixl_flush_osdep(struct i40e_osdep *osdep)
213 {
214 
215 	rd32_osdep(osdep, osdep->flush_reg);
216 }
217 
218 #define rd32(a, reg)		rd32_osdep((a)->back, (reg))
219 #define wr32(a, reg, value)	wr32_osdep((a)->back, (reg), (value))
220 
221 #define rd64(a, reg) (\
222    bus_space_read_8( ((struct i40e_osdep *)(a)->back)->mem_bus_space_tag, \
223                      ((struct i40e_osdep *)(a)->back)->mem_bus_space_handle, \
224                      reg))
225 
226 #define wr64(a, reg, value) (\
227    bus_space_write_8( ((struct i40e_osdep *)(a)->back)->mem_bus_space_tag, \
228                      ((struct i40e_osdep *)(a)->back)->mem_bus_space_handle, \
229                      reg, value))
230 
231 #define ixl_flush(a)		ixl_flush_osdep((a)->back)
232 
233 #endif /* _I40E_OSDEP_H_ */
234