1 /****************************************************************************** 2 3 Copyright (c) 2013-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include <machine/stdarg.h> 36 37 #include "ixl.h" 38 39 /******************************************************************** 40 * Manage DMA'able memory. 41 *******************************************************************/ 42 static void 43 i40e_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 44 { 45 if (error) 46 return; 47 *(bus_addr_t *) arg = segs->ds_addr; 48 return; 49 } 50 51 i40e_status 52 i40e_allocate_virt(struct i40e_hw *hw, struct i40e_virt_mem *m, u32 size) 53 { 54 m->va = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 55 return(m->va == NULL); 56 } 57 58 i40e_status 59 i40e_free_virt(struct i40e_hw *hw, struct i40e_virt_mem *m) 60 { 61 free(m->va, M_DEVBUF); 62 return(0); 63 } 64 65 i40e_status 66 i40e_allocate_dma(struct i40e_hw *hw, struct i40e_dma_mem *dma, 67 bus_size_t size, u32 alignment) 68 { 69 device_t dev = ((struct i40e_osdep *)hw->back)->dev; 70 int err; 71 72 73 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 74 alignment, 0, /* alignment, bounds */ 75 BUS_SPACE_MAXADDR, /* lowaddr */ 76 BUS_SPACE_MAXADDR, /* highaddr */ 77 NULL, NULL, /* filter, filterarg */ 78 size, /* maxsize */ 79 1, /* nsegments */ 80 size, /* maxsegsize */ 81 BUS_DMA_ALLOCNOW, /* flags */ 82 NULL, /* lockfunc */ 83 NULL, /* lockfuncarg */ 84 &dma->tag); 85 if (err != 0) { 86 device_printf(dev, 87 "i40e_allocate_dma: bus_dma_tag_create failed, " 88 "error %u\n", err); 89 goto fail_0; 90 } 91 err = bus_dmamem_alloc(dma->tag, (void **)&dma->va, 92 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->map); 93 if (err != 0) { 94 device_printf(dev, 95 "i40e_allocate_dma: bus_dmamem_alloc failed, " 96 "error %u\n", err); 97 goto fail_1; 98 } 99 err = bus_dmamap_load(dma->tag, dma->map, dma->va, 100 size, 101 i40e_dmamap_cb, 102 &dma->pa, 103 BUS_DMA_NOWAIT); 104 if (err != 0) { 105 device_printf(dev, 106 "i40e_allocate_dma: bus_dmamap_load failed, " 107 "error %u\n", err); 108 goto fail_2; 109 } 110 dma->size = size; 111 bus_dmamap_sync(dma->tag, dma->map, 112 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 113 return (0); 114 fail_2: 115 bus_dmamem_free(dma->tag, dma->va, dma->map); 116 fail_1: 117 bus_dma_tag_destroy(dma->tag); 118 fail_0: 119 dma->map = NULL; 120 dma->tag = NULL; 121 return (err); 122 } 123 124 i40e_status 125 i40e_free_dma(struct i40e_hw *hw, struct i40e_dma_mem *dma) 126 { 127 bus_dmamap_sync(dma->tag, dma->map, 128 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 129 bus_dmamap_unload(dma->tag, dma->map); 130 bus_dmamem_free(dma->tag, dma->va, dma->map); 131 bus_dma_tag_destroy(dma->tag); 132 return (0); 133 } 134 135 void 136 i40e_init_spinlock(struct i40e_spinlock *lock) 137 { 138 mtx_init(&lock->mutex, "mutex", 139 MTX_NETWORK_LOCK, MTX_DEF | MTX_DUPOK); 140 } 141 142 void 143 i40e_acquire_spinlock(struct i40e_spinlock *lock) 144 { 145 mtx_lock(&lock->mutex); 146 } 147 148 void 149 i40e_release_spinlock(struct i40e_spinlock *lock) 150 { 151 mtx_unlock(&lock->mutex); 152 } 153 154 void 155 i40e_destroy_spinlock(struct i40e_spinlock *lock) 156 { 157 mtx_destroy(&lock->mutex); 158 } 159 160 /* 161 ** i40e_debug_d - OS dependent version of shared code debug printing 162 */ 163 void i40e_debug_d(void *hw, u32 mask, char *fmt, ...) 164 { 165 char buf[512]; 166 va_list args; 167 168 if (!(mask & ((struct i40e_hw *)hw)->debug_mask)) 169 return; 170 171 va_start(args, fmt); 172 vsnprintf(buf, sizeof(buf), fmt, args); 173 va_end(args); 174 175 /* the debug string is already formatted with a newline */ 176 printf("%s", buf); 177 } 178 179 u16 180 i40e_read_pci_cfg(struct i40e_hw *hw, u32 reg) 181 { 182 u16 value; 183 184 value = pci_read_config(((struct i40e_osdep *)hw->back)->dev, 185 reg, 2); 186 187 return (value); 188 } 189 190 void 191 i40e_write_pci_cfg(struct i40e_hw *hw, u32 reg, u16 value) 192 { 193 pci_write_config(((struct i40e_osdep *)hw->back)->dev, 194 reg, value, 2); 195 196 return; 197 } 198 199