1 /****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_DCB_H_ 36 #define _I40E_DCB_H_ 37 38 #include "i40e_type.h" 39 40 #define I40E_DCBX_OFFLOAD_DISABLED 0 41 #define I40E_DCBX_OFFLOAD_ENABLED 1 42 43 #define I40E_DCBX_STATUS_NOT_STARTED 0 44 #define I40E_DCBX_STATUS_IN_PROGRESS 1 45 #define I40E_DCBX_STATUS_DONE 2 46 #define I40E_DCBX_STATUS_MULTIPLE_PEERS 3 47 #define I40E_DCBX_STATUS_DISABLED 7 48 49 #define I40E_TLV_TYPE_END 0 50 #define I40E_TLV_TYPE_ORG 127 51 52 #define I40E_IEEE_8021QAZ_OUI 0x0080C2 53 #define I40E_IEEE_SUBTYPE_ETS_CFG 9 54 #define I40E_IEEE_SUBTYPE_ETS_REC 10 55 #define I40E_IEEE_SUBTYPE_PFC_CFG 11 56 #define I40E_IEEE_SUBTYPE_APP_PRI 12 57 58 #define I40E_CEE_DCBX_OUI 0x001b21 59 #define I40E_CEE_DCBX_TYPE 2 60 61 #define I40E_CEE_SUBTYPE_CTRL 1 62 #define I40E_CEE_SUBTYPE_PG_CFG 2 63 #define I40E_CEE_SUBTYPE_PFC_CFG 3 64 #define I40E_CEE_SUBTYPE_APP_PRI 4 65 66 #define I40E_CEE_MAX_FEAT_TYPE 3 67 #define I40E_LLDP_ADMINSTATUS_DISABLED 0 68 #define I40E_LLDP_ADMINSTATUS_ENABLED_RX 1 69 #define I40E_LLDP_ADMINSTATUS_ENABLED_TX 2 70 #define I40E_LLDP_ADMINSTATUS_ENABLED_RXTX 3 71 72 /* Defines for LLDP TLV header */ 73 #define I40E_LLDP_MIB_HLEN 14 74 #define I40E_LLDP_TLV_LEN_SHIFT 0 75 #define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT) 76 #define I40E_LLDP_TLV_TYPE_SHIFT 9 77 #define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT) 78 #define I40E_LLDP_TLV_SUBTYPE_SHIFT 0 79 #define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT) 80 #define I40E_LLDP_TLV_OUI_SHIFT 8 81 #define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT) 82 83 /* Defines for IEEE ETS TLV */ 84 #define I40E_IEEE_ETS_MAXTC_SHIFT 0 85 #define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT) 86 #define I40E_IEEE_ETS_CBS_SHIFT 6 87 #define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT) 88 #define I40E_IEEE_ETS_WILLING_SHIFT 7 89 #define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT) 90 #define I40E_IEEE_ETS_PRIO_0_SHIFT 0 91 #define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT) 92 #define I40E_IEEE_ETS_PRIO_1_SHIFT 4 93 #define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT) 94 #define I40E_CEE_PGID_PRIO_0_SHIFT 0 95 #define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT) 96 #define I40E_CEE_PGID_PRIO_1_SHIFT 4 97 #define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT) 98 #define I40E_CEE_PGID_STRICT 15 99 100 /* Defines for IEEE TSA types */ 101 #define I40E_IEEE_TSA_STRICT 0 102 #define I40E_IEEE_TSA_CBS 1 103 #define I40E_IEEE_TSA_ETS 2 104 #define I40E_IEEE_TSA_VENDOR 255 105 106 /* Defines for IEEE PFC TLV */ 107 #define I40E_IEEE_PFC_CAP_SHIFT 0 108 #define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT) 109 #define I40E_IEEE_PFC_MBC_SHIFT 6 110 #define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT) 111 #define I40E_IEEE_PFC_WILLING_SHIFT 7 112 #define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT) 113 114 /* Defines for IEEE APP TLV */ 115 #define I40E_IEEE_APP_SEL_SHIFT 0 116 #define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT) 117 #define I40E_IEEE_APP_PRIO_SHIFT 5 118 #define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT) 119 120 /* TLV definitions for preparing MIB */ 121 #define I40E_TLV_ID_CHASSIS_ID 0 122 #define I40E_TLV_ID_PORT_ID 1 123 #define I40E_TLV_ID_TIME_TO_LIVE 2 124 #define I40E_IEEE_TLV_ID_ETS_CFG 3 125 #define I40E_IEEE_TLV_ID_ETS_REC 4 126 #define I40E_IEEE_TLV_ID_PFC_CFG 5 127 #define I40E_IEEE_TLV_ID_APP_PRI 6 128 #define I40E_TLV_ID_END_OF_LLDPPDU 7 129 #define I40E_TLV_ID_START I40E_IEEE_TLV_ID_ETS_CFG 130 131 #define I40E_IEEE_ETS_TLV_LENGTH 25 132 #define I40E_IEEE_PFC_TLV_LENGTH 6 133 #define I40E_IEEE_APP_TLV_LENGTH 11 134 135 #pragma pack(1) 136 137 /* IEEE 802.1AB LLDP TLV structure */ 138 struct i40e_lldp_generic_tlv { 139 __be16 typelength; 140 u8 tlvinfo[1]; 141 }; 142 143 /* IEEE 802.1AB LLDP Organization specific TLV */ 144 struct i40e_lldp_org_tlv { 145 __be16 typelength; 146 __be32 ouisubtype; 147 u8 tlvinfo[1]; 148 }; 149 150 struct i40e_cee_tlv_hdr { 151 __be16 typelen; 152 u8 operver; 153 u8 maxver; 154 }; 155 156 struct i40e_cee_ctrl_tlv { 157 struct i40e_cee_tlv_hdr hdr; 158 __be32 seqno; 159 __be32 ackno; 160 }; 161 162 struct i40e_cee_feat_tlv { 163 struct i40e_cee_tlv_hdr hdr; 164 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */ 165 #define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80 166 #define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40 167 #define I40E_CEE_FEAT_TLV_ERR_MASK 0x20 168 u8 subtype; 169 u8 tlvinfo[1]; 170 }; 171 172 struct i40e_cee_app_prio { 173 __be16 protocol; 174 u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */ 175 #define I40E_CEE_APP_SELECTOR_MASK 0x03 176 __be16 lower_oui; 177 u8 prio_map; 178 }; 179 #pragma pack() 180 181 /* 182 * TODO: The below structures related LLDP/DCBX variables 183 * and statistics are defined but need to find how to get 184 * the required information from the Firmware to use them 185 */ 186 187 /* IEEE 802.1AB LLDP Agent Statistics */ 188 struct i40e_lldp_stats { 189 u64 remtablelastchangetime; 190 u64 remtableinserts; 191 u64 remtabledeletes; 192 u64 remtabledrops; 193 u64 remtableageouts; 194 u64 txframestotal; 195 u64 rxframesdiscarded; 196 u64 rxportframeerrors; 197 u64 rxportframestotal; 198 u64 rxporttlvsdiscardedtotal; 199 u64 rxporttlvsunrecognizedtotal; 200 u64 remtoomanyneighbors; 201 }; 202 203 /* IEEE 802.1Qaz DCBX variables */ 204 struct i40e_dcbx_variables { 205 u32 defmaxtrafficclasses; 206 u32 defprioritytcmapping; 207 u32 deftcbandwidth; 208 u32 deftsaassignment; 209 }; 210 211 enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw, 212 u16 *status); 213 enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib, 214 struct i40e_dcbx_config *dcbcfg); 215 enum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type, 216 u8 bridgetype, 217 struct i40e_dcbx_config *dcbcfg); 218 enum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw); 219 enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw); 220 enum i40e_status_code i40e_set_dcb_config(struct i40e_hw *hw); 221 enum i40e_status_code i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen, 222 struct i40e_dcbx_config *dcbcfg); 223 224 #endif /* _I40E_DCB_H_ */ 225