1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "i40e_virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 hw->mac.type = I40E_MAC_XL710; 68 break; 69 case I40E_DEV_ID_VF: 70 case I40E_DEV_ID_VF_HV: 71 hw->mac.type = I40E_MAC_VF; 72 break; 73 default: 74 hw->mac.type = I40E_MAC_GENERIC; 75 break; 76 } 77 } else { 78 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 79 } 80 81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 82 hw->mac.type, status); 83 return status; 84 } 85 86 /** 87 * i40e_aq_str - convert AQ err code to a string 88 * @hw: pointer to the HW structure 89 * @aq_err: the AQ error code to convert 90 **/ 91 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 92 { 93 switch (aq_err) { 94 case I40E_AQ_RC_OK: 95 return "OK"; 96 case I40E_AQ_RC_EPERM: 97 return "I40E_AQ_RC_EPERM"; 98 case I40E_AQ_RC_ENOENT: 99 return "I40E_AQ_RC_ENOENT"; 100 case I40E_AQ_RC_ESRCH: 101 return "I40E_AQ_RC_ESRCH"; 102 case I40E_AQ_RC_EINTR: 103 return "I40E_AQ_RC_EINTR"; 104 case I40E_AQ_RC_EIO: 105 return "I40E_AQ_RC_EIO"; 106 case I40E_AQ_RC_ENXIO: 107 return "I40E_AQ_RC_ENXIO"; 108 case I40E_AQ_RC_E2BIG: 109 return "I40E_AQ_RC_E2BIG"; 110 case I40E_AQ_RC_EAGAIN: 111 return "I40E_AQ_RC_EAGAIN"; 112 case I40E_AQ_RC_ENOMEM: 113 return "I40E_AQ_RC_ENOMEM"; 114 case I40E_AQ_RC_EACCES: 115 return "I40E_AQ_RC_EACCES"; 116 case I40E_AQ_RC_EFAULT: 117 return "I40E_AQ_RC_EFAULT"; 118 case I40E_AQ_RC_EBUSY: 119 return "I40E_AQ_RC_EBUSY"; 120 case I40E_AQ_RC_EEXIST: 121 return "I40E_AQ_RC_EEXIST"; 122 case I40E_AQ_RC_EINVAL: 123 return "I40E_AQ_RC_EINVAL"; 124 case I40E_AQ_RC_ENOTTY: 125 return "I40E_AQ_RC_ENOTTY"; 126 case I40E_AQ_RC_ENOSPC: 127 return "I40E_AQ_RC_ENOSPC"; 128 case I40E_AQ_RC_ENOSYS: 129 return "I40E_AQ_RC_ENOSYS"; 130 case I40E_AQ_RC_ERANGE: 131 return "I40E_AQ_RC_ERANGE"; 132 case I40E_AQ_RC_EFLUSHED: 133 return "I40E_AQ_RC_EFLUSHED"; 134 case I40E_AQ_RC_BAD_ADDR: 135 return "I40E_AQ_RC_BAD_ADDR"; 136 case I40E_AQ_RC_EMODE: 137 return "I40E_AQ_RC_EMODE"; 138 case I40E_AQ_RC_EFBIG: 139 return "I40E_AQ_RC_EFBIG"; 140 } 141 142 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 143 return hw->err_str; 144 } 145 146 /** 147 * i40e_stat_str - convert status err code to a string 148 * @hw: pointer to the HW structure 149 * @stat_err: the status error code to convert 150 **/ 151 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 152 { 153 switch (stat_err) { 154 case I40E_SUCCESS: 155 return "OK"; 156 case I40E_ERR_NVM: 157 return "I40E_ERR_NVM"; 158 case I40E_ERR_NVM_CHECKSUM: 159 return "I40E_ERR_NVM_CHECKSUM"; 160 case I40E_ERR_PHY: 161 return "I40E_ERR_PHY"; 162 case I40E_ERR_CONFIG: 163 return "I40E_ERR_CONFIG"; 164 case I40E_ERR_PARAM: 165 return "I40E_ERR_PARAM"; 166 case I40E_ERR_MAC_TYPE: 167 return "I40E_ERR_MAC_TYPE"; 168 case I40E_ERR_UNKNOWN_PHY: 169 return "I40E_ERR_UNKNOWN_PHY"; 170 case I40E_ERR_LINK_SETUP: 171 return "I40E_ERR_LINK_SETUP"; 172 case I40E_ERR_ADAPTER_STOPPED: 173 return "I40E_ERR_ADAPTER_STOPPED"; 174 case I40E_ERR_INVALID_MAC_ADDR: 175 return "I40E_ERR_INVALID_MAC_ADDR"; 176 case I40E_ERR_DEVICE_NOT_SUPPORTED: 177 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 178 case I40E_ERR_MASTER_REQUESTS_PENDING: 179 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 180 case I40E_ERR_INVALID_LINK_SETTINGS: 181 return "I40E_ERR_INVALID_LINK_SETTINGS"; 182 case I40E_ERR_AUTONEG_NOT_COMPLETE: 183 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 184 case I40E_ERR_RESET_FAILED: 185 return "I40E_ERR_RESET_FAILED"; 186 case I40E_ERR_SWFW_SYNC: 187 return "I40E_ERR_SWFW_SYNC"; 188 case I40E_ERR_NO_AVAILABLE_VSI: 189 return "I40E_ERR_NO_AVAILABLE_VSI"; 190 case I40E_ERR_NO_MEMORY: 191 return "I40E_ERR_NO_MEMORY"; 192 case I40E_ERR_BAD_PTR: 193 return "I40E_ERR_BAD_PTR"; 194 case I40E_ERR_RING_FULL: 195 return "I40E_ERR_RING_FULL"; 196 case I40E_ERR_INVALID_PD_ID: 197 return "I40E_ERR_INVALID_PD_ID"; 198 case I40E_ERR_INVALID_QP_ID: 199 return "I40E_ERR_INVALID_QP_ID"; 200 case I40E_ERR_INVALID_CQ_ID: 201 return "I40E_ERR_INVALID_CQ_ID"; 202 case I40E_ERR_INVALID_CEQ_ID: 203 return "I40E_ERR_INVALID_CEQ_ID"; 204 case I40E_ERR_INVALID_AEQ_ID: 205 return "I40E_ERR_INVALID_AEQ_ID"; 206 case I40E_ERR_INVALID_SIZE: 207 return "I40E_ERR_INVALID_SIZE"; 208 case I40E_ERR_INVALID_ARP_INDEX: 209 return "I40E_ERR_INVALID_ARP_INDEX"; 210 case I40E_ERR_INVALID_FPM_FUNC_ID: 211 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 212 case I40E_ERR_QP_INVALID_MSG_SIZE: 213 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 214 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 215 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 216 case I40E_ERR_INVALID_FRAG_COUNT: 217 return "I40E_ERR_INVALID_FRAG_COUNT"; 218 case I40E_ERR_QUEUE_EMPTY: 219 return "I40E_ERR_QUEUE_EMPTY"; 220 case I40E_ERR_INVALID_ALIGNMENT: 221 return "I40E_ERR_INVALID_ALIGNMENT"; 222 case I40E_ERR_FLUSHED_QUEUE: 223 return "I40E_ERR_FLUSHED_QUEUE"; 224 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 225 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 226 case I40E_ERR_INVALID_IMM_DATA_SIZE: 227 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 228 case I40E_ERR_TIMEOUT: 229 return "I40E_ERR_TIMEOUT"; 230 case I40E_ERR_OPCODE_MISMATCH: 231 return "I40E_ERR_OPCODE_MISMATCH"; 232 case I40E_ERR_CQP_COMPL_ERROR: 233 return "I40E_ERR_CQP_COMPL_ERROR"; 234 case I40E_ERR_INVALID_VF_ID: 235 return "I40E_ERR_INVALID_VF_ID"; 236 case I40E_ERR_INVALID_HMCFN_ID: 237 return "I40E_ERR_INVALID_HMCFN_ID"; 238 case I40E_ERR_BACKING_PAGE_ERROR: 239 return "I40E_ERR_BACKING_PAGE_ERROR"; 240 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 241 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 242 case I40E_ERR_INVALID_PBLE_INDEX: 243 return "I40E_ERR_INVALID_PBLE_INDEX"; 244 case I40E_ERR_INVALID_SD_INDEX: 245 return "I40E_ERR_INVALID_SD_INDEX"; 246 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 247 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 248 case I40E_ERR_INVALID_SD_TYPE: 249 return "I40E_ERR_INVALID_SD_TYPE"; 250 case I40E_ERR_MEMCPY_FAILED: 251 return "I40E_ERR_MEMCPY_FAILED"; 252 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 253 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 254 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 255 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 256 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 257 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 258 case I40E_ERR_SRQ_ENABLED: 259 return "I40E_ERR_SRQ_ENABLED"; 260 case I40E_ERR_ADMIN_QUEUE_ERROR: 261 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 262 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 263 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 264 case I40E_ERR_BUF_TOO_SHORT: 265 return "I40E_ERR_BUF_TOO_SHORT"; 266 case I40E_ERR_ADMIN_QUEUE_FULL: 267 return "I40E_ERR_ADMIN_QUEUE_FULL"; 268 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 269 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 270 case I40E_ERR_BAD_IWARP_CQE: 271 return "I40E_ERR_BAD_IWARP_CQE"; 272 case I40E_ERR_NVM_BLANK_MODE: 273 return "I40E_ERR_NVM_BLANK_MODE"; 274 case I40E_ERR_NOT_IMPLEMENTED: 275 return "I40E_ERR_NOT_IMPLEMENTED"; 276 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 277 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 278 case I40E_ERR_DIAG_TEST_FAILED: 279 return "I40E_ERR_DIAG_TEST_FAILED"; 280 case I40E_ERR_NOT_READY: 281 return "I40E_ERR_NOT_READY"; 282 case I40E_NOT_SUPPORTED: 283 return "I40E_NOT_SUPPORTED"; 284 case I40E_ERR_FIRMWARE_API_VERSION: 285 return "I40E_ERR_FIRMWARE_API_VERSION"; 286 } 287 288 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 289 return hw->err_str; 290 } 291 292 /** 293 * i40e_debug_aq 294 * @hw: debug mask related to admin queue 295 * @mask: debug mask 296 * @desc: pointer to admin queue descriptor 297 * @buffer: pointer to command buffer 298 * @buf_len: max length of buffer 299 * 300 * Dumps debug log about adminq command with descriptor contents. 301 **/ 302 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 303 void *buffer, u16 buf_len) 304 { 305 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 306 u16 len = LE16_TO_CPU(aq_desc->datalen); 307 u8 *buf = (u8 *)buffer; 308 u16 i = 0; 309 310 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 311 return; 312 313 i40e_debug(hw, mask, 314 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 315 LE16_TO_CPU(aq_desc->opcode), 316 LE16_TO_CPU(aq_desc->flags), 317 LE16_TO_CPU(aq_desc->datalen), 318 LE16_TO_CPU(aq_desc->retval)); 319 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 320 LE32_TO_CPU(aq_desc->cookie_high), 321 LE32_TO_CPU(aq_desc->cookie_low)); 322 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 323 LE32_TO_CPU(aq_desc->params.internal.param0), 324 LE32_TO_CPU(aq_desc->params.internal.param1)); 325 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 326 LE32_TO_CPU(aq_desc->params.external.addr_high), 327 LE32_TO_CPU(aq_desc->params.external.addr_low)); 328 329 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 330 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 331 if (buf_len < len) 332 len = buf_len; 333 /* write the full 16-byte chunks */ 334 for (i = 0; i < (len - 16); i += 16) 335 i40e_debug(hw, mask, 336 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 337 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 338 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 339 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 340 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 341 /* the most we could have left is 16 bytes, pad with zeros */ 342 if (i < len) { 343 char d_buf[16]; 344 int j; 345 346 memset(d_buf, 0, sizeof(d_buf)); 347 for (j = 0; i < len; j++, i++) 348 d_buf[j] = buf[i]; 349 i40e_debug(hw, mask, 350 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 351 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 352 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 353 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 354 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 355 } 356 } 357 } 358 359 /** 360 * i40e_check_asq_alive 361 * @hw: pointer to the hw struct 362 * 363 * Returns TRUE if Queue is enabled else FALSE. 364 **/ 365 bool i40e_check_asq_alive(struct i40e_hw *hw) 366 { 367 if (hw->aq.asq.len) 368 if (!i40e_is_vf(hw)) 369 return !!(rd32(hw, hw->aq.asq.len) & 370 I40E_PF_ATQLEN_ATQENABLE_MASK); 371 if (i40e_is_vf(hw)) 372 return !!(rd32(hw, hw->aq.asq.len) & 373 I40E_VF_ATQLEN1_ATQENABLE_MASK); 374 return FALSE; 375 } 376 377 /** 378 * i40e_aq_queue_shutdown 379 * @hw: pointer to the hw struct 380 * @unloading: is the driver unloading itself 381 * 382 * Tell the Firmware that we're shutting down the AdminQ and whether 383 * or not the driver is unloading as well. 384 **/ 385 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 386 bool unloading) 387 { 388 struct i40e_aq_desc desc; 389 struct i40e_aqc_queue_shutdown *cmd = 390 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 391 enum i40e_status_code status; 392 393 i40e_fill_default_direct_cmd_desc(&desc, 394 i40e_aqc_opc_queue_shutdown); 395 396 if (unloading) 397 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 398 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 399 400 return status; 401 } 402 403 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 404 * hardware to a bit-field that can be used by SW to more easily determine the 405 * packet type. 406 * 407 * Macros are used to shorten the table lines and make this table human 408 * readable. 409 * 410 * We store the PTYPE in the top byte of the bit field - this is just so that 411 * we can check that the table doesn't have a row missing, as the index into 412 * the table should be the PTYPE. 413 * 414 * Typical work flow: 415 * 416 * IF NOT i40e_ptype_lookup[ptype].known 417 * THEN 418 * Packet is unknown 419 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 420 * Use the rest of the fields to look at the tunnels, inner protocols, etc 421 * ELSE 422 * Use the enum i40e_rx_l2_ptype to decode the packet type 423 * ENDIF 424 */ 425 426 /* macro to make the table lines short */ 427 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 428 { PTYPE, \ 429 1, \ 430 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 431 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 432 I40E_RX_PTYPE_##OUTER_FRAG, \ 433 I40E_RX_PTYPE_TUNNEL_##T, \ 434 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 435 I40E_RX_PTYPE_##TEF, \ 436 I40E_RX_PTYPE_INNER_PROT_##I, \ 437 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 438 439 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 440 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 441 442 /* shorter macros makes the table fit but are terse */ 443 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 444 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 445 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 446 447 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 448 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 449 /* L2 Packet types */ 450 I40E_PTT_UNUSED_ENTRY(0), 451 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 452 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 453 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 454 I40E_PTT_UNUSED_ENTRY(4), 455 I40E_PTT_UNUSED_ENTRY(5), 456 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 457 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 458 I40E_PTT_UNUSED_ENTRY(8), 459 I40E_PTT_UNUSED_ENTRY(9), 460 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 461 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 462 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 463 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 464 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 465 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 466 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 467 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 468 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 469 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 470 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 471 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 472 473 /* Non Tunneled IPv4 */ 474 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 475 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 476 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 477 I40E_PTT_UNUSED_ENTRY(25), 478 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 479 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 480 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 481 482 /* IPv4 --> IPv4 */ 483 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 484 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 485 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 486 I40E_PTT_UNUSED_ENTRY(32), 487 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 488 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 489 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 490 491 /* IPv4 --> IPv6 */ 492 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 493 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 494 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 495 I40E_PTT_UNUSED_ENTRY(39), 496 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 497 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 498 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 499 500 /* IPv4 --> GRE/NAT */ 501 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 502 503 /* IPv4 --> GRE/NAT --> IPv4 */ 504 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 505 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 506 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 507 I40E_PTT_UNUSED_ENTRY(47), 508 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 509 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 510 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 511 512 /* IPv4 --> GRE/NAT --> IPv6 */ 513 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 514 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 515 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 516 I40E_PTT_UNUSED_ENTRY(54), 517 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 518 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 519 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 520 521 /* IPv4 --> GRE/NAT --> MAC */ 522 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 523 524 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 525 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 526 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 527 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 528 I40E_PTT_UNUSED_ENTRY(62), 529 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 530 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 531 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 532 533 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 534 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 535 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 536 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 537 I40E_PTT_UNUSED_ENTRY(69), 538 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 539 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 540 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 541 542 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 543 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 544 545 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 546 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 547 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 548 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 549 I40E_PTT_UNUSED_ENTRY(77), 550 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 551 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 552 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 553 554 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 555 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 556 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 557 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 558 I40E_PTT_UNUSED_ENTRY(84), 559 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 560 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 561 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 562 563 /* Non Tunneled IPv6 */ 564 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 565 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 566 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 567 I40E_PTT_UNUSED_ENTRY(91), 568 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 569 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 570 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 571 572 /* IPv6 --> IPv4 */ 573 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 574 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 575 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 576 I40E_PTT_UNUSED_ENTRY(98), 577 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 578 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 579 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 580 581 /* IPv6 --> IPv6 */ 582 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 583 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 584 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 585 I40E_PTT_UNUSED_ENTRY(105), 586 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 587 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 588 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 589 590 /* IPv6 --> GRE/NAT */ 591 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 592 593 /* IPv6 --> GRE/NAT -> IPv4 */ 594 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 595 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 596 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 597 I40E_PTT_UNUSED_ENTRY(113), 598 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 599 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 600 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 601 602 /* IPv6 --> GRE/NAT -> IPv6 */ 603 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 604 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 605 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 606 I40E_PTT_UNUSED_ENTRY(120), 607 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 608 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 609 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 610 611 /* IPv6 --> GRE/NAT -> MAC */ 612 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 613 614 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 615 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 616 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 617 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 618 I40E_PTT_UNUSED_ENTRY(128), 619 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 620 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 621 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 622 623 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 624 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 625 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 626 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 627 I40E_PTT_UNUSED_ENTRY(135), 628 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 629 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 630 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 631 632 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 633 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 634 635 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 636 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 637 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 638 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 639 I40E_PTT_UNUSED_ENTRY(143), 640 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 641 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 642 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 643 644 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 645 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 646 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 647 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(150), 649 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 650 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 651 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 652 653 /* unused entries */ 654 I40E_PTT_UNUSED_ENTRY(154), 655 I40E_PTT_UNUSED_ENTRY(155), 656 I40E_PTT_UNUSED_ENTRY(156), 657 I40E_PTT_UNUSED_ENTRY(157), 658 I40E_PTT_UNUSED_ENTRY(158), 659 I40E_PTT_UNUSED_ENTRY(159), 660 661 I40E_PTT_UNUSED_ENTRY(160), 662 I40E_PTT_UNUSED_ENTRY(161), 663 I40E_PTT_UNUSED_ENTRY(162), 664 I40E_PTT_UNUSED_ENTRY(163), 665 I40E_PTT_UNUSED_ENTRY(164), 666 I40E_PTT_UNUSED_ENTRY(165), 667 I40E_PTT_UNUSED_ENTRY(166), 668 I40E_PTT_UNUSED_ENTRY(167), 669 I40E_PTT_UNUSED_ENTRY(168), 670 I40E_PTT_UNUSED_ENTRY(169), 671 672 I40E_PTT_UNUSED_ENTRY(170), 673 I40E_PTT_UNUSED_ENTRY(171), 674 I40E_PTT_UNUSED_ENTRY(172), 675 I40E_PTT_UNUSED_ENTRY(173), 676 I40E_PTT_UNUSED_ENTRY(174), 677 I40E_PTT_UNUSED_ENTRY(175), 678 I40E_PTT_UNUSED_ENTRY(176), 679 I40E_PTT_UNUSED_ENTRY(177), 680 I40E_PTT_UNUSED_ENTRY(178), 681 I40E_PTT_UNUSED_ENTRY(179), 682 683 I40E_PTT_UNUSED_ENTRY(180), 684 I40E_PTT_UNUSED_ENTRY(181), 685 I40E_PTT_UNUSED_ENTRY(182), 686 I40E_PTT_UNUSED_ENTRY(183), 687 I40E_PTT_UNUSED_ENTRY(184), 688 I40E_PTT_UNUSED_ENTRY(185), 689 I40E_PTT_UNUSED_ENTRY(186), 690 I40E_PTT_UNUSED_ENTRY(187), 691 I40E_PTT_UNUSED_ENTRY(188), 692 I40E_PTT_UNUSED_ENTRY(189), 693 694 I40E_PTT_UNUSED_ENTRY(190), 695 I40E_PTT_UNUSED_ENTRY(191), 696 I40E_PTT_UNUSED_ENTRY(192), 697 I40E_PTT_UNUSED_ENTRY(193), 698 I40E_PTT_UNUSED_ENTRY(194), 699 I40E_PTT_UNUSED_ENTRY(195), 700 I40E_PTT_UNUSED_ENTRY(196), 701 I40E_PTT_UNUSED_ENTRY(197), 702 I40E_PTT_UNUSED_ENTRY(198), 703 I40E_PTT_UNUSED_ENTRY(199), 704 705 I40E_PTT_UNUSED_ENTRY(200), 706 I40E_PTT_UNUSED_ENTRY(201), 707 I40E_PTT_UNUSED_ENTRY(202), 708 I40E_PTT_UNUSED_ENTRY(203), 709 I40E_PTT_UNUSED_ENTRY(204), 710 I40E_PTT_UNUSED_ENTRY(205), 711 I40E_PTT_UNUSED_ENTRY(206), 712 I40E_PTT_UNUSED_ENTRY(207), 713 I40E_PTT_UNUSED_ENTRY(208), 714 I40E_PTT_UNUSED_ENTRY(209), 715 716 I40E_PTT_UNUSED_ENTRY(210), 717 I40E_PTT_UNUSED_ENTRY(211), 718 I40E_PTT_UNUSED_ENTRY(212), 719 I40E_PTT_UNUSED_ENTRY(213), 720 I40E_PTT_UNUSED_ENTRY(214), 721 I40E_PTT_UNUSED_ENTRY(215), 722 I40E_PTT_UNUSED_ENTRY(216), 723 I40E_PTT_UNUSED_ENTRY(217), 724 I40E_PTT_UNUSED_ENTRY(218), 725 I40E_PTT_UNUSED_ENTRY(219), 726 727 I40E_PTT_UNUSED_ENTRY(220), 728 I40E_PTT_UNUSED_ENTRY(221), 729 I40E_PTT_UNUSED_ENTRY(222), 730 I40E_PTT_UNUSED_ENTRY(223), 731 I40E_PTT_UNUSED_ENTRY(224), 732 I40E_PTT_UNUSED_ENTRY(225), 733 I40E_PTT_UNUSED_ENTRY(226), 734 I40E_PTT_UNUSED_ENTRY(227), 735 I40E_PTT_UNUSED_ENTRY(228), 736 I40E_PTT_UNUSED_ENTRY(229), 737 738 I40E_PTT_UNUSED_ENTRY(230), 739 I40E_PTT_UNUSED_ENTRY(231), 740 I40E_PTT_UNUSED_ENTRY(232), 741 I40E_PTT_UNUSED_ENTRY(233), 742 I40E_PTT_UNUSED_ENTRY(234), 743 I40E_PTT_UNUSED_ENTRY(235), 744 I40E_PTT_UNUSED_ENTRY(236), 745 I40E_PTT_UNUSED_ENTRY(237), 746 I40E_PTT_UNUSED_ENTRY(238), 747 I40E_PTT_UNUSED_ENTRY(239), 748 749 I40E_PTT_UNUSED_ENTRY(240), 750 I40E_PTT_UNUSED_ENTRY(241), 751 I40E_PTT_UNUSED_ENTRY(242), 752 I40E_PTT_UNUSED_ENTRY(243), 753 I40E_PTT_UNUSED_ENTRY(244), 754 I40E_PTT_UNUSED_ENTRY(245), 755 I40E_PTT_UNUSED_ENTRY(246), 756 I40E_PTT_UNUSED_ENTRY(247), 757 I40E_PTT_UNUSED_ENTRY(248), 758 I40E_PTT_UNUSED_ENTRY(249), 759 760 I40E_PTT_UNUSED_ENTRY(250), 761 I40E_PTT_UNUSED_ENTRY(251), 762 I40E_PTT_UNUSED_ENTRY(252), 763 I40E_PTT_UNUSED_ENTRY(253), 764 I40E_PTT_UNUSED_ENTRY(254), 765 I40E_PTT_UNUSED_ENTRY(255) 766 }; 767 768 769 /** 770 * i40e_validate_mac_addr - Validate unicast MAC address 771 * @mac_addr: pointer to MAC address 772 * 773 * Tests a MAC address to ensure it is a valid Individual Address 774 **/ 775 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 776 { 777 enum i40e_status_code status = I40E_SUCCESS; 778 779 DEBUGFUNC("i40e_validate_mac_addr"); 780 781 /* Broadcast addresses ARE multicast addresses 782 * Make sure it is not a multicast address 783 * Reject the zero address 784 */ 785 if (I40E_IS_MULTICAST(mac_addr) || 786 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 787 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 788 status = I40E_ERR_INVALID_MAC_ADDR; 789 790 return status; 791 } 792 793 /** 794 * i40e_init_shared_code - Initialize the shared code 795 * @hw: pointer to hardware structure 796 * 797 * This assigns the MAC type and PHY code and inits the NVM. 798 * Does not touch the hardware. This function must be called prior to any 799 * other function in the shared code. The i40e_hw structure should be 800 * memset to 0 prior to calling this function. The following fields in 801 * hw structure should be filled in prior to calling this function: 802 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 803 * subsystem_vendor_id, and revision_id 804 **/ 805 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 806 { 807 enum i40e_status_code status = I40E_SUCCESS; 808 u32 port, ari, func_rid; 809 810 DEBUGFUNC("i40e_init_shared_code"); 811 812 i40e_set_mac_type(hw); 813 814 switch (hw->mac.type) { 815 case I40E_MAC_XL710: 816 break; 817 default: 818 return I40E_ERR_DEVICE_NOT_SUPPORTED; 819 } 820 821 hw->phy.get_link_info = TRUE; 822 823 /* Determine port number and PF number*/ 824 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 825 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 826 hw->port = (u8)port; 827 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 828 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 829 func_rid = rd32(hw, I40E_PF_FUNC_RID); 830 if (ari) 831 hw->pf_id = (u8)(func_rid & 0xff); 832 else 833 hw->pf_id = (u8)(func_rid & 0x7); 834 835 status = i40e_init_nvm(hw); 836 return status; 837 } 838 839 /** 840 * i40e_aq_mac_address_read - Retrieve the MAC addresses 841 * @hw: pointer to the hw struct 842 * @flags: a return indicator of what addresses were added to the addr store 843 * @addrs: the requestor's mac addr store 844 * @cmd_details: pointer to command details structure or NULL 845 **/ 846 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 847 u16 *flags, 848 struct i40e_aqc_mac_address_read_data *addrs, 849 struct i40e_asq_cmd_details *cmd_details) 850 { 851 struct i40e_aq_desc desc; 852 struct i40e_aqc_mac_address_read *cmd_data = 853 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 854 enum i40e_status_code status; 855 856 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 857 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 858 859 status = i40e_asq_send_command(hw, &desc, addrs, 860 sizeof(*addrs), cmd_details); 861 *flags = LE16_TO_CPU(cmd_data->command_flags); 862 863 return status; 864 } 865 866 /** 867 * i40e_aq_mac_address_write - Change the MAC addresses 868 * @hw: pointer to the hw struct 869 * @flags: indicates which MAC to be written 870 * @mac_addr: address to write 871 * @cmd_details: pointer to command details structure or NULL 872 **/ 873 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 874 u16 flags, u8 *mac_addr, 875 struct i40e_asq_cmd_details *cmd_details) 876 { 877 struct i40e_aq_desc desc; 878 struct i40e_aqc_mac_address_write *cmd_data = 879 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 880 enum i40e_status_code status; 881 882 i40e_fill_default_direct_cmd_desc(&desc, 883 i40e_aqc_opc_mac_address_write); 884 cmd_data->command_flags = CPU_TO_LE16(flags); 885 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 886 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 887 ((u32)mac_addr[3] << 16) | 888 ((u32)mac_addr[4] << 8) | 889 mac_addr[5]); 890 891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 892 893 return status; 894 } 895 896 /** 897 * i40e_get_mac_addr - get MAC address 898 * @hw: pointer to the HW structure 899 * @mac_addr: pointer to MAC address 900 * 901 * Reads the adapter's MAC address from register 902 **/ 903 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 904 { 905 struct i40e_aqc_mac_address_read_data addrs; 906 enum i40e_status_code status; 907 u16 flags = 0; 908 909 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 910 911 if (flags & I40E_AQC_LAN_ADDR_VALID) 912 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 913 914 return status; 915 } 916 917 /** 918 * i40e_get_port_mac_addr - get Port MAC address 919 * @hw: pointer to the HW structure 920 * @mac_addr: pointer to Port MAC address 921 * 922 * Reads the adapter's Port MAC address 923 **/ 924 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 925 { 926 struct i40e_aqc_mac_address_read_data addrs; 927 enum i40e_status_code status; 928 u16 flags = 0; 929 930 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 931 if (status) 932 return status; 933 934 if (flags & I40E_AQC_PORT_ADDR_VALID) 935 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 936 else 937 status = I40E_ERR_INVALID_MAC_ADDR; 938 939 return status; 940 } 941 942 /** 943 * i40e_pre_tx_queue_cfg - pre tx queue configure 944 * @hw: pointer to the HW structure 945 * @queue: target pf queue index 946 * @enable: state change request 947 * 948 * Handles hw requirement to indicate intention to enable 949 * or disable target queue. 950 **/ 951 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 952 { 953 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 954 u32 reg_block = 0; 955 u32 reg_val; 956 957 if (abs_queue_idx >= 128) { 958 reg_block = abs_queue_idx / 128; 959 abs_queue_idx %= 128; 960 } 961 962 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 963 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 964 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 965 966 if (enable) 967 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 968 else 969 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 970 971 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 972 } 973 974 /** 975 * i40e_read_pba_string - Reads part number string from EEPROM 976 * @hw: pointer to hardware structure 977 * @pba_num: stores the part number string from the EEPROM 978 * @pba_num_size: part number string buffer length 979 * 980 * Reads the part number string from the EEPROM. 981 **/ 982 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 983 u32 pba_num_size) 984 { 985 enum i40e_status_code status = I40E_SUCCESS; 986 u16 pba_word = 0; 987 u16 pba_size = 0; 988 u16 pba_ptr = 0; 989 u16 i = 0; 990 991 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 992 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 993 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 994 return status; 995 } 996 997 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 998 if (status != I40E_SUCCESS) { 999 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1000 return status; 1001 } 1002 1003 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1004 if (status != I40E_SUCCESS) { 1005 DEBUGOUT("Failed to read PBA Block size.\n"); 1006 return status; 1007 } 1008 1009 /* Subtract one to get PBA word count (PBA Size word is included in 1010 * total size) 1011 */ 1012 pba_size--; 1013 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1014 DEBUGOUT("Buffer to small for PBA data.\n"); 1015 return I40E_ERR_PARAM; 1016 } 1017 1018 for (i = 0; i < pba_size; i++) { 1019 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1020 if (status != I40E_SUCCESS) { 1021 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1022 return status; 1023 } 1024 1025 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1026 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1027 } 1028 pba_num[(pba_size * 2)] = '\0'; 1029 1030 return status; 1031 } 1032 1033 /** 1034 * i40e_get_media_type - Gets media type 1035 * @hw: pointer to the hardware structure 1036 **/ 1037 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1038 { 1039 enum i40e_media_type media; 1040 1041 switch (hw->phy.link_info.phy_type) { 1042 case I40E_PHY_TYPE_10GBASE_SR: 1043 case I40E_PHY_TYPE_10GBASE_LR: 1044 case I40E_PHY_TYPE_1000BASE_SX: 1045 case I40E_PHY_TYPE_1000BASE_LX: 1046 case I40E_PHY_TYPE_40GBASE_SR4: 1047 case I40E_PHY_TYPE_40GBASE_LR4: 1048 media = I40E_MEDIA_TYPE_FIBER; 1049 break; 1050 case I40E_PHY_TYPE_100BASE_TX: 1051 case I40E_PHY_TYPE_1000BASE_T: 1052 case I40E_PHY_TYPE_10GBASE_T: 1053 media = I40E_MEDIA_TYPE_BASET; 1054 break; 1055 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1056 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1057 case I40E_PHY_TYPE_10GBASE_CR1: 1058 case I40E_PHY_TYPE_40GBASE_CR4: 1059 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1060 case I40E_PHY_TYPE_40GBASE_AOC: 1061 case I40E_PHY_TYPE_10GBASE_AOC: 1062 media = I40E_MEDIA_TYPE_DA; 1063 break; 1064 case I40E_PHY_TYPE_1000BASE_KX: 1065 case I40E_PHY_TYPE_10GBASE_KX4: 1066 case I40E_PHY_TYPE_10GBASE_KR: 1067 case I40E_PHY_TYPE_40GBASE_KR4: 1068 case I40E_PHY_TYPE_20GBASE_KR2: 1069 media = I40E_MEDIA_TYPE_BACKPLANE; 1070 break; 1071 case I40E_PHY_TYPE_SGMII: 1072 case I40E_PHY_TYPE_XAUI: 1073 case I40E_PHY_TYPE_XFI: 1074 case I40E_PHY_TYPE_XLAUI: 1075 case I40E_PHY_TYPE_XLPPI: 1076 default: 1077 media = I40E_MEDIA_TYPE_UNKNOWN; 1078 break; 1079 } 1080 1081 return media; 1082 } 1083 1084 #define I40E_PF_RESET_WAIT_COUNT 200 1085 /** 1086 * i40e_pf_reset - Reset the PF 1087 * @hw: pointer to the hardware structure 1088 * 1089 * Assuming someone else has triggered a global reset, 1090 * assure the global reset is complete and then reset the PF 1091 **/ 1092 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1093 { 1094 u32 cnt = 0; 1095 u32 cnt1 = 0; 1096 u32 reg = 0; 1097 u32 grst_del; 1098 1099 /* Poll for Global Reset steady state in case of recent GRST. 1100 * The grst delay value is in 100ms units, and we'll wait a 1101 * couple counts longer to be sure we don't just miss the end. 1102 */ 1103 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1104 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1105 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1106 for (cnt = 0; cnt < grst_del + 10; cnt++) { 1107 reg = rd32(hw, I40E_GLGEN_RSTAT); 1108 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1109 break; 1110 i40e_msec_delay(100); 1111 } 1112 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1113 DEBUGOUT("Global reset polling failed to complete.\n"); 1114 return I40E_ERR_RESET_FAILED; 1115 } 1116 1117 /* Now Wait for the FW to be ready */ 1118 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1119 reg = rd32(hw, I40E_GLNVM_ULD); 1120 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1121 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1122 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1123 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1124 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1125 break; 1126 } 1127 i40e_msec_delay(10); 1128 } 1129 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1130 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1131 DEBUGOUT("wait for FW Reset complete timedout\n"); 1132 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1133 return I40E_ERR_RESET_FAILED; 1134 } 1135 1136 /* If there was a Global Reset in progress when we got here, 1137 * we don't need to do the PF Reset 1138 */ 1139 if (!cnt) { 1140 reg = rd32(hw, I40E_PFGEN_CTRL); 1141 wr32(hw, I40E_PFGEN_CTRL, 1142 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1143 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1144 reg = rd32(hw, I40E_PFGEN_CTRL); 1145 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1146 break; 1147 i40e_msec_delay(1); 1148 } 1149 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1150 DEBUGOUT("PF reset polling failed to complete.\n"); 1151 return I40E_ERR_RESET_FAILED; 1152 } 1153 } 1154 1155 i40e_clear_pxe_mode(hw); 1156 1157 1158 return I40E_SUCCESS; 1159 } 1160 1161 /** 1162 * i40e_clear_hw - clear out any left over hw state 1163 * @hw: pointer to the hw struct 1164 * 1165 * Clear queues and interrupts, typically called at init time, 1166 * but after the capabilities have been found so we know how many 1167 * queues and msix vectors have been allocated. 1168 **/ 1169 void i40e_clear_hw(struct i40e_hw *hw) 1170 { 1171 u32 num_queues, base_queue; 1172 u32 num_pf_int; 1173 u32 num_vf_int; 1174 u32 num_vfs; 1175 u32 i, j; 1176 u32 val; 1177 u32 eol = 0x7ff; 1178 1179 /* get number of interrupts, queues, and vfs */ 1180 val = rd32(hw, I40E_GLPCI_CNF2); 1181 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1182 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1183 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1184 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1185 1186 val = rd32(hw, I40E_PFLAN_QALLOC); 1187 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1188 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1189 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1190 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1191 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1192 num_queues = (j - base_queue) + 1; 1193 else 1194 num_queues = 0; 1195 1196 val = rd32(hw, I40E_PF_VT_PFALLOC); 1197 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1198 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1199 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1200 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1201 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1202 num_vfs = (j - i) + 1; 1203 else 1204 num_vfs = 0; 1205 1206 /* stop all the interrupts */ 1207 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1208 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1209 for (i = 0; i < num_pf_int - 2; i++) 1210 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1211 1212 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1213 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1214 wr32(hw, I40E_PFINT_LNKLST0, val); 1215 for (i = 0; i < num_pf_int - 2; i++) 1216 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1217 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1218 for (i = 0; i < num_vfs; i++) 1219 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1220 for (i = 0; i < num_vf_int - 2; i++) 1221 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1222 1223 /* warn the HW of the coming Tx disables */ 1224 for (i = 0; i < num_queues; i++) { 1225 u32 abs_queue_idx = base_queue + i; 1226 u32 reg_block = 0; 1227 1228 if (abs_queue_idx >= 128) { 1229 reg_block = abs_queue_idx / 128; 1230 abs_queue_idx %= 128; 1231 } 1232 1233 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1234 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1235 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1236 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1237 1238 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1239 } 1240 i40e_usec_delay(400); 1241 1242 /* stop all the queues */ 1243 for (i = 0; i < num_queues; i++) { 1244 wr32(hw, I40E_QINT_TQCTL(i), 0); 1245 wr32(hw, I40E_QTX_ENA(i), 0); 1246 wr32(hw, I40E_QINT_RQCTL(i), 0); 1247 wr32(hw, I40E_QRX_ENA(i), 0); 1248 } 1249 1250 /* short wait for all queue disables to settle */ 1251 i40e_usec_delay(50); 1252 } 1253 1254 /** 1255 * i40e_clear_pxe_mode - clear pxe operations mode 1256 * @hw: pointer to the hw struct 1257 * 1258 * Make sure all PXE mode settings are cleared, including things 1259 * like descriptor fetch/write-back mode. 1260 **/ 1261 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1262 { 1263 if (i40e_check_asq_alive(hw)) 1264 i40e_aq_clear_pxe_mode(hw, NULL); 1265 } 1266 1267 /** 1268 * i40e_led_is_mine - helper to find matching led 1269 * @hw: pointer to the hw struct 1270 * @idx: index into GPIO registers 1271 * 1272 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1273 */ 1274 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1275 { 1276 u32 gpio_val = 0; 1277 u32 port; 1278 1279 if (!hw->func_caps.led[idx]) 1280 return 0; 1281 1282 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1283 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1284 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1285 1286 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1287 * if it is not our port then ignore 1288 */ 1289 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1290 (port != hw->port)) 1291 return 0; 1292 1293 return gpio_val; 1294 } 1295 1296 #define I40E_COMBINED_ACTIVITY 0xA 1297 #define I40E_FILTER_ACTIVITY 0xE 1298 #define I40E_LINK_ACTIVITY 0xC 1299 #define I40E_MAC_ACTIVITY 0xD 1300 #define I40E_LED0 22 1301 1302 /** 1303 * i40e_led_get - return current on/off mode 1304 * @hw: pointer to the hw struct 1305 * 1306 * The value returned is the 'mode' field as defined in the 1307 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1308 * values are variations of possible behaviors relating to 1309 * blink, link, and wire. 1310 **/ 1311 u32 i40e_led_get(struct i40e_hw *hw) 1312 { 1313 u32 current_mode = 0; 1314 u32 mode = 0; 1315 int i; 1316 1317 /* as per the documentation GPIO 22-29 are the LED 1318 * GPIO pins named LED0..LED7 1319 */ 1320 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1321 u32 gpio_val = i40e_led_is_mine(hw, i); 1322 1323 if (!gpio_val) 1324 continue; 1325 1326 /* ignore gpio LED src mode entries related to the activity 1327 * LEDs 1328 */ 1329 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1330 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1331 switch (current_mode) { 1332 case I40E_COMBINED_ACTIVITY: 1333 case I40E_FILTER_ACTIVITY: 1334 case I40E_MAC_ACTIVITY: 1335 continue; 1336 default: 1337 break; 1338 } 1339 1340 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1341 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1342 break; 1343 } 1344 1345 return mode; 1346 } 1347 1348 /** 1349 * i40e_led_set - set new on/off mode 1350 * @hw: pointer to the hw struct 1351 * @mode: 0=off, 0xf=on (else see manual for mode details) 1352 * @blink: TRUE if the LED should blink when on, FALSE if steady 1353 * 1354 * if this function is used to turn on the blink it should 1355 * be used to disable the blink when restoring the original state. 1356 **/ 1357 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1358 { 1359 u32 current_mode = 0; 1360 int i; 1361 1362 if (mode & 0xfffffff0) 1363 DEBUGOUT1("invalid mode passed in %X\n", mode); 1364 1365 /* as per the documentation GPIO 22-29 are the LED 1366 * GPIO pins named LED0..LED7 1367 */ 1368 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1369 u32 gpio_val = i40e_led_is_mine(hw, i); 1370 1371 if (!gpio_val) 1372 continue; 1373 1374 /* ignore gpio LED src mode entries related to the activity 1375 * LEDs 1376 */ 1377 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1378 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1379 switch (current_mode) { 1380 case I40E_COMBINED_ACTIVITY: 1381 case I40E_FILTER_ACTIVITY: 1382 case I40E_MAC_ACTIVITY: 1383 continue; 1384 default: 1385 break; 1386 } 1387 1388 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1389 /* this & is a bit of paranoia, but serves as a range check */ 1390 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1391 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1392 1393 if (mode == I40E_LINK_ACTIVITY) 1394 blink = FALSE; 1395 1396 if (blink) 1397 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1398 else 1399 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1400 1401 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1402 break; 1403 } 1404 } 1405 1406 /* Admin command wrappers */ 1407 1408 /** 1409 * i40e_aq_get_phy_capabilities 1410 * @hw: pointer to the hw struct 1411 * @abilities: structure for PHY capabilities to be filled 1412 * @qualified_modules: report Qualified Modules 1413 * @report_init: report init capabilities (active are default) 1414 * @cmd_details: pointer to command details structure or NULL 1415 * 1416 * Returns the various PHY abilities supported on the Port. 1417 **/ 1418 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1419 bool qualified_modules, bool report_init, 1420 struct i40e_aq_get_phy_abilities_resp *abilities, 1421 struct i40e_asq_cmd_details *cmd_details) 1422 { 1423 struct i40e_aq_desc desc; 1424 enum i40e_status_code status; 1425 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1426 1427 if (!abilities) 1428 return I40E_ERR_PARAM; 1429 1430 i40e_fill_default_direct_cmd_desc(&desc, 1431 i40e_aqc_opc_get_phy_abilities); 1432 1433 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1434 if (abilities_size > I40E_AQ_LARGE_BUF) 1435 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1436 1437 if (qualified_modules) 1438 desc.params.external.param0 |= 1439 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1440 1441 if (report_init) 1442 desc.params.external.param0 |= 1443 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1444 1445 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1446 cmd_details); 1447 1448 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1449 status = I40E_ERR_UNKNOWN_PHY; 1450 1451 if (report_init) 1452 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1453 1454 return status; 1455 } 1456 1457 /** 1458 * i40e_aq_set_phy_config 1459 * @hw: pointer to the hw struct 1460 * @config: structure with PHY configuration to be set 1461 * @cmd_details: pointer to command details structure or NULL 1462 * 1463 * Set the various PHY configuration parameters 1464 * supported on the Port.One or more of the Set PHY config parameters may be 1465 * ignored in an MFP mode as the PF may not have the privilege to set some 1466 * of the PHY Config parameters. This status will be indicated by the 1467 * command response. 1468 **/ 1469 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1470 struct i40e_aq_set_phy_config *config, 1471 struct i40e_asq_cmd_details *cmd_details) 1472 { 1473 struct i40e_aq_desc desc; 1474 struct i40e_aq_set_phy_config *cmd = 1475 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1476 enum i40e_status_code status; 1477 1478 if (!config) 1479 return I40E_ERR_PARAM; 1480 1481 i40e_fill_default_direct_cmd_desc(&desc, 1482 i40e_aqc_opc_set_phy_config); 1483 1484 *cmd = *config; 1485 1486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1487 1488 return status; 1489 } 1490 1491 /** 1492 * i40e_set_fc 1493 * @hw: pointer to the hw struct 1494 * 1495 * Set the requested flow control mode using set_phy_config. 1496 **/ 1497 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1498 bool atomic_restart) 1499 { 1500 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1501 struct i40e_aq_get_phy_abilities_resp abilities; 1502 struct i40e_aq_set_phy_config config; 1503 enum i40e_status_code status; 1504 u8 pause_mask = 0x0; 1505 1506 *aq_failures = 0x0; 1507 1508 switch (fc_mode) { 1509 case I40E_FC_FULL: 1510 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1511 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1512 break; 1513 case I40E_FC_RX_PAUSE: 1514 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1515 break; 1516 case I40E_FC_TX_PAUSE: 1517 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1518 break; 1519 default: 1520 break; 1521 } 1522 1523 /* Get the current phy config */ 1524 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1525 NULL); 1526 if (status) { 1527 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1528 return status; 1529 } 1530 1531 memset(&config, 0, sizeof(config)); 1532 /* clear the old pause settings */ 1533 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1534 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1535 /* set the new abilities */ 1536 config.abilities |= pause_mask; 1537 /* If the abilities have changed, then set the new config */ 1538 if (config.abilities != abilities.abilities) { 1539 /* Auto restart link so settings take effect */ 1540 if (atomic_restart) 1541 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1542 /* Copy over all the old settings */ 1543 config.phy_type = abilities.phy_type; 1544 config.link_speed = abilities.link_speed; 1545 config.eee_capability = abilities.eee_capability; 1546 config.eeer = abilities.eeer_val; 1547 config.low_power_ctrl = abilities.d3_lpan; 1548 status = i40e_aq_set_phy_config(hw, &config, NULL); 1549 1550 if (status) 1551 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1552 } 1553 /* Update the link info */ 1554 status = i40e_update_link_info(hw); 1555 if (status) { 1556 /* Wait a little bit (on 40G cards it sometimes takes a really 1557 * long time for link to come back from the atomic reset) 1558 * and try once more 1559 */ 1560 i40e_msec_delay(1000); 1561 status = i40e_update_link_info(hw); 1562 } 1563 if (status) 1564 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1565 1566 return status; 1567 } 1568 1569 /** 1570 * i40e_aq_set_mac_config 1571 * @hw: pointer to the hw struct 1572 * @max_frame_size: Maximum Frame Size to be supported by the port 1573 * @crc_en: Tell HW to append a CRC to outgoing frames 1574 * @pacing: Pacing configurations 1575 * @cmd_details: pointer to command details structure or NULL 1576 * 1577 * Configure MAC settings for frame size, jumbo frame support and the 1578 * addition of a CRC by the hardware. 1579 **/ 1580 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1581 u16 max_frame_size, 1582 bool crc_en, u16 pacing, 1583 struct i40e_asq_cmd_details *cmd_details) 1584 { 1585 struct i40e_aq_desc desc; 1586 struct i40e_aq_set_mac_config *cmd = 1587 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1588 enum i40e_status_code status; 1589 1590 if (max_frame_size == 0) 1591 return I40E_ERR_PARAM; 1592 1593 i40e_fill_default_direct_cmd_desc(&desc, 1594 i40e_aqc_opc_set_mac_config); 1595 1596 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1597 cmd->params = ((u8)pacing & 0x0F) << 3; 1598 if (crc_en) 1599 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1600 1601 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1602 1603 return status; 1604 } 1605 1606 /** 1607 * i40e_aq_clear_pxe_mode 1608 * @hw: pointer to the hw struct 1609 * @cmd_details: pointer to command details structure or NULL 1610 * 1611 * Tell the firmware that the driver is taking over from PXE 1612 **/ 1613 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1614 struct i40e_asq_cmd_details *cmd_details) 1615 { 1616 enum i40e_status_code status; 1617 struct i40e_aq_desc desc; 1618 struct i40e_aqc_clear_pxe *cmd = 1619 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1620 1621 i40e_fill_default_direct_cmd_desc(&desc, 1622 i40e_aqc_opc_clear_pxe_mode); 1623 1624 cmd->rx_cnt = 0x2; 1625 1626 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1627 1628 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1629 1630 return status; 1631 } 1632 1633 /** 1634 * i40e_aq_set_link_restart_an 1635 * @hw: pointer to the hw struct 1636 * @enable_link: if TRUE: enable link, if FALSE: disable link 1637 * @cmd_details: pointer to command details structure or NULL 1638 * 1639 * Sets up the link and restarts the Auto-Negotiation over the link. 1640 **/ 1641 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1642 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1643 { 1644 struct i40e_aq_desc desc; 1645 struct i40e_aqc_set_link_restart_an *cmd = 1646 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1647 enum i40e_status_code status; 1648 1649 i40e_fill_default_direct_cmd_desc(&desc, 1650 i40e_aqc_opc_set_link_restart_an); 1651 1652 cmd->command = I40E_AQ_PHY_RESTART_AN; 1653 if (enable_link) 1654 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1655 else 1656 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1657 1658 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1659 1660 return status; 1661 } 1662 1663 /** 1664 * i40e_aq_get_link_info 1665 * @hw: pointer to the hw struct 1666 * @enable_lse: enable/disable LinkStatusEvent reporting 1667 * @link: pointer to link status structure - optional 1668 * @cmd_details: pointer to command details structure or NULL 1669 * 1670 * Returns the link status of the adapter. 1671 **/ 1672 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1673 bool enable_lse, struct i40e_link_status *link, 1674 struct i40e_asq_cmd_details *cmd_details) 1675 { 1676 struct i40e_aq_desc desc; 1677 struct i40e_aqc_get_link_status *resp = 1678 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1679 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1680 enum i40e_status_code status; 1681 bool tx_pause, rx_pause; 1682 u16 command_flags; 1683 1684 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1685 1686 if (enable_lse) 1687 command_flags = I40E_AQ_LSE_ENABLE; 1688 else 1689 command_flags = I40E_AQ_LSE_DISABLE; 1690 resp->command_flags = CPU_TO_LE16(command_flags); 1691 1692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1693 1694 if (status != I40E_SUCCESS) 1695 goto aq_get_link_info_exit; 1696 1697 /* save off old link status information */ 1698 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1699 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1700 1701 /* update link status */ 1702 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1703 hw->phy.media_type = i40e_get_media_type(hw); 1704 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1705 hw_link_info->link_info = resp->link_info; 1706 hw_link_info->an_info = resp->an_info; 1707 hw_link_info->ext_info = resp->ext_info; 1708 hw_link_info->loopback = resp->loopback; 1709 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1710 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1711 1712 /* update fc info */ 1713 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1714 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1715 if (tx_pause & rx_pause) 1716 hw->fc.current_mode = I40E_FC_FULL; 1717 else if (tx_pause) 1718 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1719 else if (rx_pause) 1720 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1721 else 1722 hw->fc.current_mode = I40E_FC_NONE; 1723 1724 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1725 hw_link_info->crc_enable = TRUE; 1726 else 1727 hw_link_info->crc_enable = FALSE; 1728 1729 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE)) 1730 hw_link_info->lse_enable = TRUE; 1731 else 1732 hw_link_info->lse_enable = FALSE; 1733 1734 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1735 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1736 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1737 1738 /* save link status information */ 1739 if (link) 1740 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1741 I40E_NONDMA_TO_NONDMA); 1742 1743 /* flag cleared so helper functions don't call AQ again */ 1744 hw->phy.get_link_info = FALSE; 1745 1746 aq_get_link_info_exit: 1747 return status; 1748 } 1749 1750 /** 1751 * i40e_aq_set_phy_int_mask 1752 * @hw: pointer to the hw struct 1753 * @mask: interrupt mask to be set 1754 * @cmd_details: pointer to command details structure or NULL 1755 * 1756 * Set link interrupt mask. 1757 **/ 1758 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1759 u16 mask, 1760 struct i40e_asq_cmd_details *cmd_details) 1761 { 1762 struct i40e_aq_desc desc; 1763 struct i40e_aqc_set_phy_int_mask *cmd = 1764 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1765 enum i40e_status_code status; 1766 1767 i40e_fill_default_direct_cmd_desc(&desc, 1768 i40e_aqc_opc_set_phy_int_mask); 1769 1770 cmd->event_mask = CPU_TO_LE16(mask); 1771 1772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1773 1774 return status; 1775 } 1776 1777 /** 1778 * i40e_aq_get_local_advt_reg 1779 * @hw: pointer to the hw struct 1780 * @advt_reg: local AN advertisement register value 1781 * @cmd_details: pointer to command details structure or NULL 1782 * 1783 * Get the Local AN advertisement register value. 1784 **/ 1785 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1786 u64 *advt_reg, 1787 struct i40e_asq_cmd_details *cmd_details) 1788 { 1789 struct i40e_aq_desc desc; 1790 struct i40e_aqc_an_advt_reg *resp = 1791 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1792 enum i40e_status_code status; 1793 1794 i40e_fill_default_direct_cmd_desc(&desc, 1795 i40e_aqc_opc_get_local_advt_reg); 1796 1797 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1798 1799 if (status != I40E_SUCCESS) 1800 goto aq_get_local_advt_reg_exit; 1801 1802 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1803 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1804 1805 aq_get_local_advt_reg_exit: 1806 return status; 1807 } 1808 1809 /** 1810 * i40e_aq_set_local_advt_reg 1811 * @hw: pointer to the hw struct 1812 * @advt_reg: local AN advertisement register value 1813 * @cmd_details: pointer to command details structure or NULL 1814 * 1815 * Get the Local AN advertisement register value. 1816 **/ 1817 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 1818 u64 advt_reg, 1819 struct i40e_asq_cmd_details *cmd_details) 1820 { 1821 struct i40e_aq_desc desc; 1822 struct i40e_aqc_an_advt_reg *cmd = 1823 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1824 enum i40e_status_code status; 1825 1826 i40e_fill_default_direct_cmd_desc(&desc, 1827 i40e_aqc_opc_get_local_advt_reg); 1828 1829 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 1830 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 1831 1832 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1833 1834 return status; 1835 } 1836 1837 /** 1838 * i40e_aq_get_partner_advt 1839 * @hw: pointer to the hw struct 1840 * @advt_reg: AN partner advertisement register value 1841 * @cmd_details: pointer to command details structure or NULL 1842 * 1843 * Get the link partner AN advertisement register value. 1844 **/ 1845 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 1846 u64 *advt_reg, 1847 struct i40e_asq_cmd_details *cmd_details) 1848 { 1849 struct i40e_aq_desc desc; 1850 struct i40e_aqc_an_advt_reg *resp = 1851 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1852 enum i40e_status_code status; 1853 1854 i40e_fill_default_direct_cmd_desc(&desc, 1855 i40e_aqc_opc_get_partner_advt); 1856 1857 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1858 1859 if (status != I40E_SUCCESS) 1860 goto aq_get_partner_advt_exit; 1861 1862 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1863 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1864 1865 aq_get_partner_advt_exit: 1866 return status; 1867 } 1868 1869 /** 1870 * i40e_aq_set_lb_modes 1871 * @hw: pointer to the hw struct 1872 * @lb_modes: loopback mode to be set 1873 * @cmd_details: pointer to command details structure or NULL 1874 * 1875 * Sets loopback modes. 1876 **/ 1877 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 1878 u16 lb_modes, 1879 struct i40e_asq_cmd_details *cmd_details) 1880 { 1881 struct i40e_aq_desc desc; 1882 struct i40e_aqc_set_lb_mode *cmd = 1883 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 1884 enum i40e_status_code status; 1885 1886 i40e_fill_default_direct_cmd_desc(&desc, 1887 i40e_aqc_opc_set_lb_modes); 1888 1889 cmd->lb_mode = CPU_TO_LE16(lb_modes); 1890 1891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1892 1893 return status; 1894 } 1895 1896 /** 1897 * i40e_aq_set_phy_debug 1898 * @hw: pointer to the hw struct 1899 * @cmd_flags: debug command flags 1900 * @cmd_details: pointer to command details structure or NULL 1901 * 1902 * Reset the external PHY. 1903 **/ 1904 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1905 struct i40e_asq_cmd_details *cmd_details) 1906 { 1907 struct i40e_aq_desc desc; 1908 struct i40e_aqc_set_phy_debug *cmd = 1909 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1910 enum i40e_status_code status; 1911 1912 i40e_fill_default_direct_cmd_desc(&desc, 1913 i40e_aqc_opc_set_phy_debug); 1914 1915 cmd->command_flags = cmd_flags; 1916 1917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1918 1919 return status; 1920 } 1921 1922 /** 1923 * i40e_aq_add_vsi 1924 * @hw: pointer to the hw struct 1925 * @vsi_ctx: pointer to a vsi context struct 1926 * @cmd_details: pointer to command details structure or NULL 1927 * 1928 * Add a VSI context to the hardware. 1929 **/ 1930 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 1931 struct i40e_vsi_context *vsi_ctx, 1932 struct i40e_asq_cmd_details *cmd_details) 1933 { 1934 struct i40e_aq_desc desc; 1935 struct i40e_aqc_add_get_update_vsi *cmd = 1936 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1937 struct i40e_aqc_add_get_update_vsi_completion *resp = 1938 (struct i40e_aqc_add_get_update_vsi_completion *) 1939 &desc.params.raw; 1940 enum i40e_status_code status; 1941 1942 i40e_fill_default_direct_cmd_desc(&desc, 1943 i40e_aqc_opc_add_vsi); 1944 1945 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 1946 cmd->connection_type = vsi_ctx->connection_type; 1947 cmd->vf_id = vsi_ctx->vf_num; 1948 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 1949 1950 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1951 1952 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1953 sizeof(vsi_ctx->info), cmd_details); 1954 1955 if (status != I40E_SUCCESS) 1956 goto aq_add_vsi_exit; 1957 1958 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 1959 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 1960 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 1961 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 1962 1963 aq_add_vsi_exit: 1964 return status; 1965 } 1966 1967 /** 1968 * i40e_aq_set_default_vsi 1969 * @hw: pointer to the hw struct 1970 * @seid: vsi number 1971 * @cmd_details: pointer to command details structure or NULL 1972 **/ 1973 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 1974 u16 seid, 1975 struct i40e_asq_cmd_details *cmd_details) 1976 { 1977 struct i40e_aq_desc desc; 1978 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1979 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1980 &desc.params.raw; 1981 enum i40e_status_code status; 1982 1983 i40e_fill_default_direct_cmd_desc(&desc, 1984 i40e_aqc_opc_set_vsi_promiscuous_modes); 1985 1986 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1987 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 1988 cmd->seid = CPU_TO_LE16(seid); 1989 1990 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1991 1992 return status; 1993 } 1994 1995 /** 1996 * i40e_aq_set_vsi_unicast_promiscuous 1997 * @hw: pointer to the hw struct 1998 * @seid: vsi number 1999 * @set: set unicast promiscuous enable/disable 2000 * @cmd_details: pointer to command details structure or NULL 2001 **/ 2002 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2003 u16 seid, bool set, 2004 struct i40e_asq_cmd_details *cmd_details) 2005 { 2006 struct i40e_aq_desc desc; 2007 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2008 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2009 enum i40e_status_code status; 2010 u16 flags = 0; 2011 2012 i40e_fill_default_direct_cmd_desc(&desc, 2013 i40e_aqc_opc_set_vsi_promiscuous_modes); 2014 2015 if (set) 2016 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2017 2018 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2019 2020 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2021 2022 cmd->seid = CPU_TO_LE16(seid); 2023 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2024 2025 return status; 2026 } 2027 2028 /** 2029 * i40e_aq_set_vsi_multicast_promiscuous 2030 * @hw: pointer to the hw struct 2031 * @seid: vsi number 2032 * @set: set multicast promiscuous enable/disable 2033 * @cmd_details: pointer to command details structure or NULL 2034 **/ 2035 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2036 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2037 { 2038 struct i40e_aq_desc desc; 2039 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2040 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2041 enum i40e_status_code status; 2042 u16 flags = 0; 2043 2044 i40e_fill_default_direct_cmd_desc(&desc, 2045 i40e_aqc_opc_set_vsi_promiscuous_modes); 2046 2047 if (set) 2048 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2049 2050 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2051 2052 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2053 2054 cmd->seid = CPU_TO_LE16(seid); 2055 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2056 2057 return status; 2058 } 2059 2060 /** 2061 * i40e_aq_set_vsi_mc_promisc_on_vlan 2062 * @hw: pointer to the hw struct 2063 * @seid: vsi number 2064 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2065 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2066 * @cmd_details: pointer to command details structure or NULL 2067 **/ 2068 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2069 u16 seid, bool enable, u16 vid, 2070 struct i40e_asq_cmd_details *cmd_details) 2071 { 2072 struct i40e_aq_desc desc; 2073 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2074 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2075 enum i40e_status_code status; 2076 u16 flags = 0; 2077 2078 i40e_fill_default_direct_cmd_desc(&desc, 2079 i40e_aqc_opc_set_vsi_promiscuous_modes); 2080 2081 if (enable) 2082 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2083 2084 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2085 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2086 cmd->seid = CPU_TO_LE16(seid); 2087 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2088 2089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2090 2091 return status; 2092 } 2093 2094 /** 2095 * i40e_aq_set_vsi_uc_promisc_on_vlan 2096 * @hw: pointer to the hw struct 2097 * @seid: vsi number 2098 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2099 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2100 * @cmd_details: pointer to command details structure or NULL 2101 **/ 2102 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2103 u16 seid, bool enable, u16 vid, 2104 struct i40e_asq_cmd_details *cmd_details) 2105 { 2106 struct i40e_aq_desc desc; 2107 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2108 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2109 enum i40e_status_code status; 2110 u16 flags = 0; 2111 2112 i40e_fill_default_direct_cmd_desc(&desc, 2113 i40e_aqc_opc_set_vsi_promiscuous_modes); 2114 2115 if (enable) 2116 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2117 2118 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2119 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2120 cmd->seid = CPU_TO_LE16(seid); 2121 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2122 2123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2124 2125 return status; 2126 } 2127 2128 /** 2129 * i40e_aq_set_vsi_broadcast 2130 * @hw: pointer to the hw struct 2131 * @seid: vsi number 2132 * @set_filter: TRUE to set filter, FALSE to clear filter 2133 * @cmd_details: pointer to command details structure or NULL 2134 * 2135 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2136 **/ 2137 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2138 u16 seid, bool set_filter, 2139 struct i40e_asq_cmd_details *cmd_details) 2140 { 2141 struct i40e_aq_desc desc; 2142 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2143 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2144 enum i40e_status_code status; 2145 2146 i40e_fill_default_direct_cmd_desc(&desc, 2147 i40e_aqc_opc_set_vsi_promiscuous_modes); 2148 2149 if (set_filter) 2150 cmd->promiscuous_flags 2151 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2152 else 2153 cmd->promiscuous_flags 2154 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2155 2156 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2157 cmd->seid = CPU_TO_LE16(seid); 2158 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2159 2160 return status; 2161 } 2162 2163 /** 2164 * i40e_get_vsi_params - get VSI configuration info 2165 * @hw: pointer to the hw struct 2166 * @vsi_ctx: pointer to a vsi context struct 2167 * @cmd_details: pointer to command details structure or NULL 2168 **/ 2169 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2170 struct i40e_vsi_context *vsi_ctx, 2171 struct i40e_asq_cmd_details *cmd_details) 2172 { 2173 struct i40e_aq_desc desc; 2174 struct i40e_aqc_add_get_update_vsi *cmd = 2175 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2176 struct i40e_aqc_add_get_update_vsi_completion *resp = 2177 (struct i40e_aqc_add_get_update_vsi_completion *) 2178 &desc.params.raw; 2179 enum i40e_status_code status; 2180 2181 i40e_fill_default_direct_cmd_desc(&desc, 2182 i40e_aqc_opc_get_vsi_parameters); 2183 2184 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2185 2186 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2187 2188 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2189 sizeof(vsi_ctx->info), NULL); 2190 2191 if (status != I40E_SUCCESS) 2192 goto aq_get_vsi_params_exit; 2193 2194 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2195 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2196 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2197 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2198 2199 aq_get_vsi_params_exit: 2200 return status; 2201 } 2202 2203 /** 2204 * i40e_aq_update_vsi_params 2205 * @hw: pointer to the hw struct 2206 * @vsi_ctx: pointer to a vsi context struct 2207 * @cmd_details: pointer to command details structure or NULL 2208 * 2209 * Update a VSI context. 2210 **/ 2211 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2212 struct i40e_vsi_context *vsi_ctx, 2213 struct i40e_asq_cmd_details *cmd_details) 2214 { 2215 struct i40e_aq_desc desc; 2216 struct i40e_aqc_add_get_update_vsi *cmd = 2217 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2218 enum i40e_status_code status; 2219 2220 i40e_fill_default_direct_cmd_desc(&desc, 2221 i40e_aqc_opc_update_vsi_parameters); 2222 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2223 2224 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2225 2226 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2227 sizeof(vsi_ctx->info), cmd_details); 2228 2229 return status; 2230 } 2231 2232 /** 2233 * i40e_aq_get_switch_config 2234 * @hw: pointer to the hardware structure 2235 * @buf: pointer to the result buffer 2236 * @buf_size: length of input buffer 2237 * @start_seid: seid to start for the report, 0 == beginning 2238 * @cmd_details: pointer to command details structure or NULL 2239 * 2240 * Fill the buf with switch configuration returned from AdminQ command 2241 **/ 2242 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2243 struct i40e_aqc_get_switch_config_resp *buf, 2244 u16 buf_size, u16 *start_seid, 2245 struct i40e_asq_cmd_details *cmd_details) 2246 { 2247 struct i40e_aq_desc desc; 2248 struct i40e_aqc_switch_seid *scfg = 2249 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2250 enum i40e_status_code status; 2251 2252 i40e_fill_default_direct_cmd_desc(&desc, 2253 i40e_aqc_opc_get_switch_config); 2254 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2255 if (buf_size > I40E_AQ_LARGE_BUF) 2256 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2257 scfg->seid = CPU_TO_LE16(*start_seid); 2258 2259 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2260 *start_seid = LE16_TO_CPU(scfg->seid); 2261 2262 return status; 2263 } 2264 2265 /** 2266 * i40e_aq_get_firmware_version 2267 * @hw: pointer to the hw struct 2268 * @fw_major_version: firmware major version 2269 * @fw_minor_version: firmware minor version 2270 * @fw_build: firmware build number 2271 * @api_major_version: major queue version 2272 * @api_minor_version: minor queue version 2273 * @cmd_details: pointer to command details structure or NULL 2274 * 2275 * Get the firmware version from the admin queue commands 2276 **/ 2277 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2278 u16 *fw_major_version, u16 *fw_minor_version, 2279 u32 *fw_build, 2280 u16 *api_major_version, u16 *api_minor_version, 2281 struct i40e_asq_cmd_details *cmd_details) 2282 { 2283 struct i40e_aq_desc desc; 2284 struct i40e_aqc_get_version *resp = 2285 (struct i40e_aqc_get_version *)&desc.params.raw; 2286 enum i40e_status_code status; 2287 2288 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2289 2290 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2291 2292 if (status == I40E_SUCCESS) { 2293 if (fw_major_version != NULL) 2294 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2295 if (fw_minor_version != NULL) 2296 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2297 if (fw_build != NULL) 2298 *fw_build = LE32_TO_CPU(resp->fw_build); 2299 if (api_major_version != NULL) 2300 *api_major_version = LE16_TO_CPU(resp->api_major); 2301 if (api_minor_version != NULL) 2302 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2303 2304 /* A workaround to fix the API version in SW */ 2305 if (api_major_version && api_minor_version && 2306 fw_major_version && fw_minor_version && 2307 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2308 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2309 (*fw_major_version > 4))) 2310 *api_minor_version = 2; 2311 } 2312 2313 return status; 2314 } 2315 2316 /** 2317 * i40e_aq_send_driver_version 2318 * @hw: pointer to the hw struct 2319 * @dv: driver's major, minor version 2320 * @cmd_details: pointer to command details structure or NULL 2321 * 2322 * Send the driver version to the firmware 2323 **/ 2324 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2325 struct i40e_driver_version *dv, 2326 struct i40e_asq_cmd_details *cmd_details) 2327 { 2328 struct i40e_aq_desc desc; 2329 struct i40e_aqc_driver_version *cmd = 2330 (struct i40e_aqc_driver_version *)&desc.params.raw; 2331 enum i40e_status_code status; 2332 u16 len; 2333 2334 if (dv == NULL) 2335 return I40E_ERR_PARAM; 2336 2337 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2338 2339 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2340 cmd->driver_major_ver = dv->major_version; 2341 cmd->driver_minor_ver = dv->minor_version; 2342 cmd->driver_build_ver = dv->build_version; 2343 cmd->driver_subbuild_ver = dv->subbuild_version; 2344 2345 len = 0; 2346 while (len < sizeof(dv->driver_string) && 2347 (dv->driver_string[len] < 0x80) && 2348 dv->driver_string[len]) 2349 len++; 2350 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2351 len, cmd_details); 2352 2353 return status; 2354 } 2355 2356 /** 2357 * i40e_get_link_status - get status of the HW network link 2358 * @hw: pointer to the hw struct 2359 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2360 * 2361 * Variable link_up TRUE if link is up, FALSE if link is down. 2362 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2363 * 2364 * Side effect: LinkStatusEvent reporting becomes enabled 2365 **/ 2366 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2367 { 2368 enum i40e_status_code status = I40E_SUCCESS; 2369 2370 if (hw->phy.get_link_info) { 2371 status = i40e_update_link_info(hw); 2372 2373 if (status != I40E_SUCCESS) 2374 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2375 status); 2376 } 2377 2378 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2379 2380 return status; 2381 } 2382 2383 /** 2384 * i40e_updatelink_status - update status of the HW network link 2385 * @hw: pointer to the hw struct 2386 **/ 2387 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2388 { 2389 struct i40e_aq_get_phy_abilities_resp abilities; 2390 enum i40e_status_code status = I40E_SUCCESS; 2391 2392 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2393 if (status) 2394 return status; 2395 2396 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) { 2397 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2398 &abilities, NULL); 2399 if (status) 2400 return status; 2401 2402 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2403 sizeof(hw->phy.link_info.module_type)); 2404 } 2405 return status; 2406 } 2407 2408 2409 /** 2410 * i40e_get_link_speed 2411 * @hw: pointer to the hw struct 2412 * 2413 * Returns the link speed of the adapter. 2414 **/ 2415 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2416 { 2417 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2418 enum i40e_status_code status = I40E_SUCCESS; 2419 2420 if (hw->phy.get_link_info) { 2421 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2422 2423 if (status != I40E_SUCCESS) 2424 goto i40e_link_speed_exit; 2425 } 2426 2427 speed = hw->phy.link_info.link_speed; 2428 2429 i40e_link_speed_exit: 2430 return speed; 2431 } 2432 2433 /** 2434 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2435 * @hw: pointer to the hw struct 2436 * @uplink_seid: the MAC or other gizmo SEID 2437 * @downlink_seid: the VSI SEID 2438 * @enabled_tc: bitmap of TCs to be enabled 2439 * @default_port: TRUE for default port VSI, FALSE for control port 2440 * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support 2441 * @veb_seid: pointer to where to put the resulting VEB SEID 2442 * @cmd_details: pointer to command details structure or NULL 2443 * 2444 * This asks the FW to add a VEB between the uplink and downlink 2445 * elements. If the uplink SEID is 0, this will be a floating VEB. 2446 **/ 2447 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2448 u16 downlink_seid, u8 enabled_tc, 2449 bool default_port, bool enable_l2_filtering, 2450 u16 *veb_seid, 2451 struct i40e_asq_cmd_details *cmd_details) 2452 { 2453 struct i40e_aq_desc desc; 2454 struct i40e_aqc_add_veb *cmd = 2455 (struct i40e_aqc_add_veb *)&desc.params.raw; 2456 struct i40e_aqc_add_veb_completion *resp = 2457 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2458 enum i40e_status_code status; 2459 u16 veb_flags = 0; 2460 2461 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2462 if (!!uplink_seid != !!downlink_seid) 2463 return I40E_ERR_PARAM; 2464 2465 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2466 2467 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2468 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2469 cmd->enable_tcs = enabled_tc; 2470 if (!uplink_seid) 2471 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2472 if (default_port) 2473 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2474 else 2475 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2476 2477 if (enable_l2_filtering) 2478 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 2479 2480 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2481 2482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2483 2484 if (!status && veb_seid) 2485 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2486 2487 return status; 2488 } 2489 2490 /** 2491 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2492 * @hw: pointer to the hw struct 2493 * @veb_seid: the SEID of the VEB to query 2494 * @switch_id: the uplink switch id 2495 * @floating: set to TRUE if the VEB is floating 2496 * @statistic_index: index of the stats counter block for this VEB 2497 * @vebs_used: number of VEB's used by function 2498 * @vebs_free: total VEB's not reserved by any function 2499 * @cmd_details: pointer to command details structure or NULL 2500 * 2501 * This retrieves the parameters for a particular VEB, specified by 2502 * uplink_seid, and returns them to the caller. 2503 **/ 2504 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2505 u16 veb_seid, u16 *switch_id, 2506 bool *floating, u16 *statistic_index, 2507 u16 *vebs_used, u16 *vebs_free, 2508 struct i40e_asq_cmd_details *cmd_details) 2509 { 2510 struct i40e_aq_desc desc; 2511 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2512 (struct i40e_aqc_get_veb_parameters_completion *) 2513 &desc.params.raw; 2514 enum i40e_status_code status; 2515 2516 if (veb_seid == 0) 2517 return I40E_ERR_PARAM; 2518 2519 i40e_fill_default_direct_cmd_desc(&desc, 2520 i40e_aqc_opc_get_veb_parameters); 2521 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2522 2523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2524 if (status) 2525 goto get_veb_exit; 2526 2527 if (switch_id) 2528 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2529 if (statistic_index) 2530 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2531 if (vebs_used) 2532 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2533 if (vebs_free) 2534 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2535 if (floating) { 2536 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2537 2538 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2539 *floating = TRUE; 2540 else 2541 *floating = FALSE; 2542 } 2543 2544 get_veb_exit: 2545 return status; 2546 } 2547 2548 /** 2549 * i40e_aq_add_macvlan 2550 * @hw: pointer to the hw struct 2551 * @seid: VSI for the mac address 2552 * @mv_list: list of macvlans to be added 2553 * @count: length of the list 2554 * @cmd_details: pointer to command details structure or NULL 2555 * 2556 * Add MAC/VLAN addresses to the HW filtering 2557 **/ 2558 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2559 struct i40e_aqc_add_macvlan_element_data *mv_list, 2560 u16 count, struct i40e_asq_cmd_details *cmd_details) 2561 { 2562 struct i40e_aq_desc desc; 2563 struct i40e_aqc_macvlan *cmd = 2564 (struct i40e_aqc_macvlan *)&desc.params.raw; 2565 enum i40e_status_code status; 2566 u16 buf_size; 2567 2568 if (count == 0 || !mv_list || !hw) 2569 return I40E_ERR_PARAM; 2570 2571 buf_size = count * sizeof(*mv_list); 2572 2573 /* prep the rest of the request */ 2574 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2575 cmd->num_addresses = CPU_TO_LE16(count); 2576 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2577 cmd->seid[1] = 0; 2578 cmd->seid[2] = 0; 2579 2580 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2581 if (buf_size > I40E_AQ_LARGE_BUF) 2582 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2583 2584 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2585 cmd_details); 2586 2587 return status; 2588 } 2589 2590 /** 2591 * i40e_aq_remove_macvlan 2592 * @hw: pointer to the hw struct 2593 * @seid: VSI for the mac address 2594 * @mv_list: list of macvlans to be removed 2595 * @count: length of the list 2596 * @cmd_details: pointer to command details structure or NULL 2597 * 2598 * Remove MAC/VLAN addresses from the HW filtering 2599 **/ 2600 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2601 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2602 u16 count, struct i40e_asq_cmd_details *cmd_details) 2603 { 2604 struct i40e_aq_desc desc; 2605 struct i40e_aqc_macvlan *cmd = 2606 (struct i40e_aqc_macvlan *)&desc.params.raw; 2607 enum i40e_status_code status; 2608 u16 buf_size; 2609 2610 if (count == 0 || !mv_list || !hw) 2611 return I40E_ERR_PARAM; 2612 2613 buf_size = count * sizeof(*mv_list); 2614 2615 /* prep the rest of the request */ 2616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2617 cmd->num_addresses = CPU_TO_LE16(count); 2618 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2619 cmd->seid[1] = 0; 2620 cmd->seid[2] = 0; 2621 2622 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2623 if (buf_size > I40E_AQ_LARGE_BUF) 2624 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2625 2626 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2627 cmd_details); 2628 2629 return status; 2630 } 2631 2632 /** 2633 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 2634 * @hw: pointer to the hw struct 2635 * @seid: VSI for the vlan filters 2636 * @v_list: list of vlan filters to be added 2637 * @count: length of the list 2638 * @cmd_details: pointer to command details structure or NULL 2639 **/ 2640 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 2641 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2642 u8 count, struct i40e_asq_cmd_details *cmd_details) 2643 { 2644 struct i40e_aq_desc desc; 2645 struct i40e_aqc_macvlan *cmd = 2646 (struct i40e_aqc_macvlan *)&desc.params.raw; 2647 enum i40e_status_code status; 2648 u16 buf_size; 2649 2650 if (count == 0 || !v_list || !hw) 2651 return I40E_ERR_PARAM; 2652 2653 buf_size = count * sizeof(*v_list); 2654 2655 /* prep the rest of the request */ 2656 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 2657 cmd->num_addresses = CPU_TO_LE16(count); 2658 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2659 cmd->seid[1] = 0; 2660 cmd->seid[2] = 0; 2661 2662 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2663 if (buf_size > I40E_AQ_LARGE_BUF) 2664 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2665 2666 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2667 cmd_details); 2668 2669 return status; 2670 } 2671 2672 /** 2673 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 2674 * @hw: pointer to the hw struct 2675 * @seid: VSI for the vlan filters 2676 * @v_list: list of macvlans to be removed 2677 * @count: length of the list 2678 * @cmd_details: pointer to command details structure or NULL 2679 **/ 2680 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 2681 struct i40e_aqc_add_remove_vlan_element_data *v_list, 2682 u8 count, struct i40e_asq_cmd_details *cmd_details) 2683 { 2684 struct i40e_aq_desc desc; 2685 struct i40e_aqc_macvlan *cmd = 2686 (struct i40e_aqc_macvlan *)&desc.params.raw; 2687 enum i40e_status_code status; 2688 u16 buf_size; 2689 2690 if (count == 0 || !v_list || !hw) 2691 return I40E_ERR_PARAM; 2692 2693 buf_size = count * sizeof(*v_list); 2694 2695 /* prep the rest of the request */ 2696 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 2697 cmd->num_addresses = CPU_TO_LE16(count); 2698 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 2699 cmd->seid[1] = 0; 2700 cmd->seid[2] = 0; 2701 2702 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2703 if (buf_size > I40E_AQ_LARGE_BUF) 2704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2705 2706 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 2707 cmd_details); 2708 2709 return status; 2710 } 2711 2712 /** 2713 * i40e_aq_send_msg_to_vf 2714 * @hw: pointer to the hardware structure 2715 * @vfid: vf id to send msg 2716 * @v_opcode: opcodes for VF-PF communication 2717 * @v_retval: return error code 2718 * @msg: pointer to the msg buffer 2719 * @msglen: msg length 2720 * @cmd_details: pointer to command details 2721 * 2722 * send msg to vf 2723 **/ 2724 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2725 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2726 struct i40e_asq_cmd_details *cmd_details) 2727 { 2728 struct i40e_aq_desc desc; 2729 struct i40e_aqc_pf_vf_message *cmd = 2730 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2731 enum i40e_status_code status; 2732 2733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2734 cmd->id = CPU_TO_LE32(vfid); 2735 desc.cookie_high = CPU_TO_LE32(v_opcode); 2736 desc.cookie_low = CPU_TO_LE32(v_retval); 2737 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 2738 if (msglen) { 2739 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 2740 I40E_AQ_FLAG_RD)); 2741 if (msglen > I40E_AQ_LARGE_BUF) 2742 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2743 desc.datalen = CPU_TO_LE16(msglen); 2744 } 2745 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2746 2747 return status; 2748 } 2749 2750 /** 2751 * i40e_aq_debug_read_register 2752 * @hw: pointer to the hw struct 2753 * @reg_addr: register address 2754 * @reg_val: register value 2755 * @cmd_details: pointer to command details structure or NULL 2756 * 2757 * Read the register using the admin queue commands 2758 **/ 2759 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 2760 u32 reg_addr, u64 *reg_val, 2761 struct i40e_asq_cmd_details *cmd_details) 2762 { 2763 struct i40e_aq_desc desc; 2764 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2765 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2766 enum i40e_status_code status; 2767 2768 if (reg_val == NULL) 2769 return I40E_ERR_PARAM; 2770 2771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2772 2773 cmd_resp->address = CPU_TO_LE32(reg_addr); 2774 2775 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2776 2777 if (status == I40E_SUCCESS) { 2778 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 2779 (u64)LE32_TO_CPU(cmd_resp->value_low); 2780 } 2781 2782 return status; 2783 } 2784 2785 /** 2786 * i40e_aq_debug_write_register 2787 * @hw: pointer to the hw struct 2788 * @reg_addr: register address 2789 * @reg_val: register value 2790 * @cmd_details: pointer to command details structure or NULL 2791 * 2792 * Write to a register using the admin queue commands 2793 **/ 2794 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 2795 u32 reg_addr, u64 reg_val, 2796 struct i40e_asq_cmd_details *cmd_details) 2797 { 2798 struct i40e_aq_desc desc; 2799 struct i40e_aqc_debug_reg_read_write *cmd = 2800 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2801 enum i40e_status_code status; 2802 2803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2804 2805 cmd->address = CPU_TO_LE32(reg_addr); 2806 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 2807 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 2808 2809 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2810 2811 return status; 2812 } 2813 2814 /** 2815 * i40e_aq_get_hmc_resource_profile 2816 * @hw: pointer to the hw struct 2817 * @profile: type of profile the HMC is to be set as 2818 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2819 * @cmd_details: pointer to command details structure or NULL 2820 * 2821 * query the HMC profile of the device. 2822 **/ 2823 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw, 2824 enum i40e_aq_hmc_profile *profile, 2825 u8 *pe_vf_enabled_count, 2826 struct i40e_asq_cmd_details *cmd_details) 2827 { 2828 struct i40e_aq_desc desc; 2829 struct i40e_aq_get_set_hmc_resource_profile *resp = 2830 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2831 enum i40e_status_code status; 2832 2833 i40e_fill_default_direct_cmd_desc(&desc, 2834 i40e_aqc_opc_query_hmc_resource_profile); 2835 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2836 2837 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile & 2838 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK); 2839 *pe_vf_enabled_count = resp->pe_vf_enabled & 2840 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK; 2841 2842 return status; 2843 } 2844 2845 /** 2846 * i40e_aq_set_hmc_resource_profile 2847 * @hw: pointer to the hw struct 2848 * @profile: type of profile the HMC is to be set as 2849 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2850 * @cmd_details: pointer to command details structure or NULL 2851 * 2852 * set the HMC profile of the device. 2853 **/ 2854 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2855 enum i40e_aq_hmc_profile profile, 2856 u8 pe_vf_enabled_count, 2857 struct i40e_asq_cmd_details *cmd_details) 2858 { 2859 struct i40e_aq_desc desc; 2860 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2861 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2862 enum i40e_status_code status; 2863 2864 i40e_fill_default_direct_cmd_desc(&desc, 2865 i40e_aqc_opc_set_hmc_resource_profile); 2866 2867 cmd->pm_profile = (u8)profile; 2868 cmd->pe_vf_enabled = pe_vf_enabled_count; 2869 2870 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2871 2872 return status; 2873 } 2874 2875 /** 2876 * i40e_aq_request_resource 2877 * @hw: pointer to the hw struct 2878 * @resource: resource id 2879 * @access: access type 2880 * @sdp_number: resource number 2881 * @timeout: the maximum time in ms that the driver may hold the resource 2882 * @cmd_details: pointer to command details structure or NULL 2883 * 2884 * requests common resource using the admin queue commands 2885 **/ 2886 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 2887 enum i40e_aq_resources_ids resource, 2888 enum i40e_aq_resource_access_type access, 2889 u8 sdp_number, u64 *timeout, 2890 struct i40e_asq_cmd_details *cmd_details) 2891 { 2892 struct i40e_aq_desc desc; 2893 struct i40e_aqc_request_resource *cmd_resp = 2894 (struct i40e_aqc_request_resource *)&desc.params.raw; 2895 enum i40e_status_code status; 2896 2897 DEBUGFUNC("i40e_aq_request_resource"); 2898 2899 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2900 2901 cmd_resp->resource_id = CPU_TO_LE16(resource); 2902 cmd_resp->access_type = CPU_TO_LE16(access); 2903 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 2904 2905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2906 /* The completion specifies the maximum time in ms that the driver 2907 * may hold the resource in the Timeout field. 2908 * If the resource is held by someone else, the command completes with 2909 * busy return value and the timeout field indicates the maximum time 2910 * the current owner of the resource has to free it. 2911 */ 2912 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2913 *timeout = LE32_TO_CPU(cmd_resp->timeout); 2914 2915 return status; 2916 } 2917 2918 /** 2919 * i40e_aq_release_resource 2920 * @hw: pointer to the hw struct 2921 * @resource: resource id 2922 * @sdp_number: resource number 2923 * @cmd_details: pointer to command details structure or NULL 2924 * 2925 * release common resource using the admin queue commands 2926 **/ 2927 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 2928 enum i40e_aq_resources_ids resource, 2929 u8 sdp_number, 2930 struct i40e_asq_cmd_details *cmd_details) 2931 { 2932 struct i40e_aq_desc desc; 2933 struct i40e_aqc_request_resource *cmd = 2934 (struct i40e_aqc_request_resource *)&desc.params.raw; 2935 enum i40e_status_code status; 2936 2937 DEBUGFUNC("i40e_aq_release_resource"); 2938 2939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2940 2941 cmd->resource_id = CPU_TO_LE16(resource); 2942 cmd->resource_number = CPU_TO_LE32(sdp_number); 2943 2944 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2945 2946 return status; 2947 } 2948 2949 /** 2950 * i40e_aq_read_nvm 2951 * @hw: pointer to the hw struct 2952 * @module_pointer: module pointer location in words from the NVM beginning 2953 * @offset: byte offset from the module beginning 2954 * @length: length of the section to be read (in bytes from the offset) 2955 * @data: command buffer (size [bytes] = length) 2956 * @last_command: tells if this is the last command in a series 2957 * @cmd_details: pointer to command details structure or NULL 2958 * 2959 * Read the NVM using the admin queue commands 2960 **/ 2961 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2962 u32 offset, u16 length, void *data, 2963 bool last_command, 2964 struct i40e_asq_cmd_details *cmd_details) 2965 { 2966 struct i40e_aq_desc desc; 2967 struct i40e_aqc_nvm_update *cmd = 2968 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2969 enum i40e_status_code status; 2970 2971 DEBUGFUNC("i40e_aq_read_nvm"); 2972 2973 /* In offset the highest byte must be zeroed. */ 2974 if (offset & 0xFF000000) { 2975 status = I40E_ERR_PARAM; 2976 goto i40e_aq_read_nvm_exit; 2977 } 2978 2979 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2980 2981 /* If this is the last command in a series, set the proper flag. */ 2982 if (last_command) 2983 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2984 cmd->module_pointer = module_pointer; 2985 cmd->offset = CPU_TO_LE32(offset); 2986 cmd->length = CPU_TO_LE16(length); 2987 2988 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2989 if (length > I40E_AQ_LARGE_BUF) 2990 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2991 2992 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2993 2994 i40e_aq_read_nvm_exit: 2995 return status; 2996 } 2997 2998 /** 2999 * i40e_aq_read_nvm_config - read an nvm config block 3000 * @hw: pointer to the hw struct 3001 * @cmd_flags: NVM access admin command bits 3002 * @field_id: field or feature id 3003 * @data: buffer for result 3004 * @buf_size: buffer size 3005 * @element_count: pointer to count of elements read by FW 3006 * @cmd_details: pointer to command details structure or NULL 3007 **/ 3008 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3009 u8 cmd_flags, u32 field_id, void *data, 3010 u16 buf_size, u16 *element_count, 3011 struct i40e_asq_cmd_details *cmd_details) 3012 { 3013 struct i40e_aq_desc desc; 3014 struct i40e_aqc_nvm_config_read *cmd = 3015 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3016 enum i40e_status_code status; 3017 3018 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3019 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3020 if (buf_size > I40E_AQ_LARGE_BUF) 3021 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3022 3023 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3024 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3025 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3026 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3027 else 3028 cmd->element_id_msw = 0; 3029 3030 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3031 3032 if (!status && element_count) 3033 *element_count = LE16_TO_CPU(cmd->element_count); 3034 3035 return status; 3036 } 3037 3038 /** 3039 * i40e_aq_write_nvm_config - write an nvm config block 3040 * @hw: pointer to the hw struct 3041 * @cmd_flags: NVM access admin command bits 3042 * @data: buffer for result 3043 * @buf_size: buffer size 3044 * @element_count: count of elements to be written 3045 * @cmd_details: pointer to command details structure or NULL 3046 **/ 3047 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3048 u8 cmd_flags, void *data, u16 buf_size, 3049 u16 element_count, 3050 struct i40e_asq_cmd_details *cmd_details) 3051 { 3052 struct i40e_aq_desc desc; 3053 struct i40e_aqc_nvm_config_write *cmd = 3054 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3055 enum i40e_status_code status; 3056 3057 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3058 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3059 if (buf_size > I40E_AQ_LARGE_BUF) 3060 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3061 3062 cmd->element_count = CPU_TO_LE16(element_count); 3063 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3064 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3065 3066 return status; 3067 } 3068 3069 /** 3070 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3071 * @hw: pointer to the hw struct 3072 * @cmd_details: pointer to command details structure or NULL 3073 **/ 3074 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3075 void *buff, u16 buff_size, 3076 struct i40e_asq_cmd_details *cmd_details) 3077 { 3078 struct i40e_aq_desc desc; 3079 enum i40e_status_code status; 3080 3081 3082 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3083 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3084 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3085 status = I40E_ERR_NOT_IMPLEMENTED; 3086 3087 return status; 3088 } 3089 3090 /** 3091 * i40e_aq_erase_nvm 3092 * @hw: pointer to the hw struct 3093 * @module_pointer: module pointer location in words from the NVM beginning 3094 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3095 * @length: length of the section to be erased (expressed in 4 KB) 3096 * @last_command: tells if this is the last command in a series 3097 * @cmd_details: pointer to command details structure or NULL 3098 * 3099 * Erase the NVM sector using the admin queue commands 3100 **/ 3101 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3102 u32 offset, u16 length, bool last_command, 3103 struct i40e_asq_cmd_details *cmd_details) 3104 { 3105 struct i40e_aq_desc desc; 3106 struct i40e_aqc_nvm_update *cmd = 3107 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3108 enum i40e_status_code status; 3109 3110 DEBUGFUNC("i40e_aq_erase_nvm"); 3111 3112 /* In offset the highest byte must be zeroed. */ 3113 if (offset & 0xFF000000) { 3114 status = I40E_ERR_PARAM; 3115 goto i40e_aq_erase_nvm_exit; 3116 } 3117 3118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3119 3120 /* If this is the last command in a series, set the proper flag. */ 3121 if (last_command) 3122 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3123 cmd->module_pointer = module_pointer; 3124 cmd->offset = CPU_TO_LE32(offset); 3125 cmd->length = CPU_TO_LE16(length); 3126 3127 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3128 3129 i40e_aq_erase_nvm_exit: 3130 return status; 3131 } 3132 3133 /** 3134 * i40e_parse_discover_capabilities 3135 * @hw: pointer to the hw struct 3136 * @buff: pointer to a buffer containing device/function capability records 3137 * @cap_count: number of capability records in the list 3138 * @list_type_opc: type of capabilities list to parse 3139 * 3140 * Parse the device/function capabilities list. 3141 **/ 3142 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3143 u32 cap_count, 3144 enum i40e_admin_queue_opc list_type_opc) 3145 { 3146 struct i40e_aqc_list_capabilities_element_resp *cap; 3147 u32 valid_functions, num_functions; 3148 u32 number, logical_id, phys_id; 3149 struct i40e_hw_capabilities *p; 3150 u8 major_rev; 3151 u32 i = 0; 3152 u16 id; 3153 3154 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3155 3156 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3157 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3158 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3159 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3160 else 3161 return; 3162 3163 for (i = 0; i < cap_count; i++, cap++) { 3164 id = LE16_TO_CPU(cap->id); 3165 number = LE32_TO_CPU(cap->number); 3166 logical_id = LE32_TO_CPU(cap->logical_id); 3167 phys_id = LE32_TO_CPU(cap->phys_id); 3168 major_rev = cap->major_rev; 3169 3170 switch (id) { 3171 case I40E_AQ_CAP_ID_SWITCH_MODE: 3172 p->switch_mode = number; 3173 break; 3174 case I40E_AQ_CAP_ID_MNG_MODE: 3175 p->management_mode = number; 3176 break; 3177 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3178 p->npar_enable = number; 3179 break; 3180 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3181 p->os2bmc = number; 3182 break; 3183 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3184 p->valid_functions = number; 3185 break; 3186 case I40E_AQ_CAP_ID_SRIOV: 3187 if (number == 1) 3188 p->sr_iov_1_1 = TRUE; 3189 break; 3190 case I40E_AQ_CAP_ID_VF: 3191 p->num_vfs = number; 3192 p->vf_base_id = logical_id; 3193 break; 3194 case I40E_AQ_CAP_ID_VMDQ: 3195 if (number == 1) 3196 p->vmdq = TRUE; 3197 break; 3198 case I40E_AQ_CAP_ID_8021QBG: 3199 if (number == 1) 3200 p->evb_802_1_qbg = TRUE; 3201 break; 3202 case I40E_AQ_CAP_ID_8021QBR: 3203 if (number == 1) 3204 p->evb_802_1_qbh = TRUE; 3205 break; 3206 case I40E_AQ_CAP_ID_VSI: 3207 p->num_vsis = number; 3208 break; 3209 case I40E_AQ_CAP_ID_DCB: 3210 if (number == 1) { 3211 p->dcb = TRUE; 3212 p->enabled_tcmap = logical_id; 3213 p->maxtc = phys_id; 3214 } 3215 break; 3216 case I40E_AQ_CAP_ID_FCOE: 3217 if (number == 1) 3218 p->fcoe = TRUE; 3219 break; 3220 case I40E_AQ_CAP_ID_ISCSI: 3221 if (number == 1) 3222 p->iscsi = TRUE; 3223 break; 3224 case I40E_AQ_CAP_ID_RSS: 3225 p->rss = TRUE; 3226 p->rss_table_size = number; 3227 p->rss_table_entry_width = logical_id; 3228 break; 3229 case I40E_AQ_CAP_ID_RXQ: 3230 p->num_rx_qp = number; 3231 p->base_queue = phys_id; 3232 break; 3233 case I40E_AQ_CAP_ID_TXQ: 3234 p->num_tx_qp = number; 3235 p->base_queue = phys_id; 3236 break; 3237 case I40E_AQ_CAP_ID_MSIX: 3238 p->num_msix_vectors = number; 3239 break; 3240 case I40E_AQ_CAP_ID_VF_MSIX: 3241 p->num_msix_vectors_vf = number; 3242 break; 3243 case I40E_AQ_CAP_ID_FLEX10: 3244 if (major_rev == 1) { 3245 if (number == 1) { 3246 p->flex10_enable = TRUE; 3247 p->flex10_capable = TRUE; 3248 } 3249 } else { 3250 /* Capability revision >= 2 */ 3251 if (number & 1) 3252 p->flex10_enable = TRUE; 3253 if (number & 2) 3254 p->flex10_capable = TRUE; 3255 } 3256 p->flex10_mode = logical_id; 3257 p->flex10_status = phys_id; 3258 break; 3259 case I40E_AQ_CAP_ID_CEM: 3260 if (number == 1) 3261 p->mgmt_cem = TRUE; 3262 break; 3263 case I40E_AQ_CAP_ID_IWARP: 3264 if (number == 1) 3265 p->iwarp = TRUE; 3266 break; 3267 case I40E_AQ_CAP_ID_LED: 3268 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3269 p->led[phys_id] = TRUE; 3270 break; 3271 case I40E_AQ_CAP_ID_SDP: 3272 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3273 p->sdp[phys_id] = TRUE; 3274 break; 3275 case I40E_AQ_CAP_ID_MDIO: 3276 if (number == 1) { 3277 p->mdio_port_num = phys_id; 3278 p->mdio_port_mode = logical_id; 3279 } 3280 break; 3281 case I40E_AQ_CAP_ID_1588: 3282 if (number == 1) 3283 p->ieee_1588 = TRUE; 3284 break; 3285 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3286 p->fd = TRUE; 3287 p->fd_filters_guaranteed = number; 3288 p->fd_filters_best_effort = logical_id; 3289 break; 3290 case I40E_AQ_CAP_ID_WSR_PROT: 3291 p->wr_csr_prot = (u64)number; 3292 p->wr_csr_prot |= (u64)logical_id << 32; 3293 break; 3294 default: 3295 break; 3296 } 3297 } 3298 3299 if (p->fcoe) 3300 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3301 3302 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3303 p->fcoe = FALSE; 3304 3305 /* count the enabled ports (aka the "not disabled" ports) */ 3306 hw->num_ports = 0; 3307 for (i = 0; i < 4; i++) { 3308 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3309 u64 port_cfg = 0; 3310 3311 /* use AQ read to get the physical register offset instead 3312 * of the port relative offset 3313 */ 3314 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3315 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3316 hw->num_ports++; 3317 } 3318 3319 valid_functions = p->valid_functions; 3320 num_functions = 0; 3321 while (valid_functions) { 3322 if (valid_functions & 1) 3323 num_functions++; 3324 valid_functions >>= 1; 3325 } 3326 3327 /* partition id is 1-based, and functions are evenly spread 3328 * across the ports as partitions 3329 */ 3330 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3331 hw->num_partitions = num_functions / hw->num_ports; 3332 3333 /* additional HW specific goodies that might 3334 * someday be HW version specific 3335 */ 3336 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3337 } 3338 3339 /** 3340 * i40e_aq_discover_capabilities 3341 * @hw: pointer to the hw struct 3342 * @buff: a virtual buffer to hold the capabilities 3343 * @buff_size: Size of the virtual buffer 3344 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3345 * @list_type_opc: capabilities type to discover - pass in the command opcode 3346 * @cmd_details: pointer to command details structure or NULL 3347 * 3348 * Get the device capabilities descriptions from the firmware 3349 **/ 3350 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3351 void *buff, u16 buff_size, u16 *data_size, 3352 enum i40e_admin_queue_opc list_type_opc, 3353 struct i40e_asq_cmd_details *cmd_details) 3354 { 3355 struct i40e_aqc_list_capabilites *cmd; 3356 struct i40e_aq_desc desc; 3357 enum i40e_status_code status = I40E_SUCCESS; 3358 3359 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3360 3361 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3362 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3363 status = I40E_ERR_PARAM; 3364 goto exit; 3365 } 3366 3367 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3368 3369 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3370 if (buff_size > I40E_AQ_LARGE_BUF) 3371 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3372 3373 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3374 *data_size = LE16_TO_CPU(desc.datalen); 3375 3376 if (status) 3377 goto exit; 3378 3379 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 3380 list_type_opc); 3381 3382 exit: 3383 return status; 3384 } 3385 3386 /** 3387 * i40e_aq_update_nvm 3388 * @hw: pointer to the hw struct 3389 * @module_pointer: module pointer location in words from the NVM beginning 3390 * @offset: byte offset from the module beginning 3391 * @length: length of the section to be written (in bytes from the offset) 3392 * @data: command buffer (size [bytes] = length) 3393 * @last_command: tells if this is the last command in a series 3394 * @cmd_details: pointer to command details structure or NULL 3395 * 3396 * Update the NVM using the admin queue commands 3397 **/ 3398 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3399 u32 offset, u16 length, void *data, 3400 bool last_command, 3401 struct i40e_asq_cmd_details *cmd_details) 3402 { 3403 struct i40e_aq_desc desc; 3404 struct i40e_aqc_nvm_update *cmd = 3405 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3406 enum i40e_status_code status; 3407 3408 DEBUGFUNC("i40e_aq_update_nvm"); 3409 3410 /* In offset the highest byte must be zeroed. */ 3411 if (offset & 0xFF000000) { 3412 status = I40E_ERR_PARAM; 3413 goto i40e_aq_update_nvm_exit; 3414 } 3415 3416 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3417 3418 /* If this is the last command in a series, set the proper flag. */ 3419 if (last_command) 3420 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3421 cmd->module_pointer = module_pointer; 3422 cmd->offset = CPU_TO_LE32(offset); 3423 cmd->length = CPU_TO_LE16(length); 3424 3425 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3426 if (length > I40E_AQ_LARGE_BUF) 3427 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3428 3429 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3430 3431 i40e_aq_update_nvm_exit: 3432 return status; 3433 } 3434 3435 /** 3436 * i40e_aq_get_lldp_mib 3437 * @hw: pointer to the hw struct 3438 * @bridge_type: type of bridge requested 3439 * @mib_type: Local, Remote or both Local and Remote MIBs 3440 * @buff: pointer to a user supplied buffer to store the MIB block 3441 * @buff_size: size of the buffer (in bytes) 3442 * @local_len : length of the returned Local LLDP MIB 3443 * @remote_len: length of the returned Remote LLDP MIB 3444 * @cmd_details: pointer to command details structure or NULL 3445 * 3446 * Requests the complete LLDP MIB (entire packet). 3447 **/ 3448 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3449 u8 mib_type, void *buff, u16 buff_size, 3450 u16 *local_len, u16 *remote_len, 3451 struct i40e_asq_cmd_details *cmd_details) 3452 { 3453 struct i40e_aq_desc desc; 3454 struct i40e_aqc_lldp_get_mib *cmd = 3455 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3456 struct i40e_aqc_lldp_get_mib *resp = 3457 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3458 enum i40e_status_code status; 3459 3460 if (buff_size == 0 || !buff) 3461 return I40E_ERR_PARAM; 3462 3463 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3464 /* Indirect Command */ 3465 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3466 3467 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3468 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3469 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3470 3471 desc.datalen = CPU_TO_LE16(buff_size); 3472 3473 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3474 if (buff_size > I40E_AQ_LARGE_BUF) 3475 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3476 3477 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3478 if (!status) { 3479 if (local_len != NULL) 3480 *local_len = LE16_TO_CPU(resp->local_len); 3481 if (remote_len != NULL) 3482 *remote_len = LE16_TO_CPU(resp->remote_len); 3483 } 3484 3485 return status; 3486 } 3487 3488 /** 3489 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3490 * @hw: pointer to the hw struct 3491 * @mib_type: Local, Remote or both Local and Remote MIBs 3492 * @buff: pointer to a user supplied buffer to store the MIB block 3493 * @buff_size: size of the buffer (in bytes) 3494 * @cmd_details: pointer to command details structure or NULL 3495 * 3496 * Set the LLDP MIB. 3497 **/ 3498 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3499 u8 mib_type, void *buff, u16 buff_size, 3500 struct i40e_asq_cmd_details *cmd_details) 3501 { 3502 struct i40e_aq_desc desc; 3503 struct i40e_aqc_lldp_set_local_mib *cmd = 3504 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3505 enum i40e_status_code status; 3506 3507 if (buff_size == 0 || !buff) 3508 return I40E_ERR_PARAM; 3509 3510 i40e_fill_default_direct_cmd_desc(&desc, 3511 i40e_aqc_opc_lldp_set_local_mib); 3512 /* Indirect Command */ 3513 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3514 if (buff_size > I40E_AQ_LARGE_BUF) 3515 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3516 desc.datalen = CPU_TO_LE16(buff_size); 3517 3518 cmd->type = mib_type; 3519 cmd->length = CPU_TO_LE16(buff_size); 3520 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff)); 3521 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 3522 3523 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3524 return status; 3525 } 3526 3527 /** 3528 * i40e_aq_cfg_lldp_mib_change_event 3529 * @hw: pointer to the hw struct 3530 * @enable_update: Enable or Disable event posting 3531 * @cmd_details: pointer to command details structure or NULL 3532 * 3533 * Enable or Disable posting of an event on ARQ when LLDP MIB 3534 * associated with the interface changes 3535 **/ 3536 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3537 bool enable_update, 3538 struct i40e_asq_cmd_details *cmd_details) 3539 { 3540 struct i40e_aq_desc desc; 3541 struct i40e_aqc_lldp_update_mib *cmd = 3542 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3543 enum i40e_status_code status; 3544 3545 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3546 3547 if (!enable_update) 3548 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3549 3550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3551 3552 return status; 3553 } 3554 3555 /** 3556 * i40e_aq_add_lldp_tlv 3557 * @hw: pointer to the hw struct 3558 * @bridge_type: type of bridge 3559 * @buff: buffer with TLV to add 3560 * @buff_size: length of the buffer 3561 * @tlv_len: length of the TLV to be added 3562 * @mib_len: length of the LLDP MIB returned in response 3563 * @cmd_details: pointer to command details structure or NULL 3564 * 3565 * Add the specified TLV to LLDP Local MIB for the given bridge type, 3566 * it is responsibility of the caller to make sure that the TLV is not 3567 * already present in the LLDPDU. 3568 * In return firmware will write the complete LLDP MIB with the newly 3569 * added TLV in the response buffer. 3570 **/ 3571 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 3572 void *buff, u16 buff_size, u16 tlv_len, 3573 u16 *mib_len, 3574 struct i40e_asq_cmd_details *cmd_details) 3575 { 3576 struct i40e_aq_desc desc; 3577 struct i40e_aqc_lldp_add_tlv *cmd = 3578 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3579 enum i40e_status_code status; 3580 3581 if (buff_size == 0 || !buff || tlv_len == 0) 3582 return I40E_ERR_PARAM; 3583 3584 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 3585 3586 /* Indirect Command */ 3587 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3588 if (buff_size > I40E_AQ_LARGE_BUF) 3589 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3590 desc.datalen = CPU_TO_LE16(buff_size); 3591 3592 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3593 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3594 cmd->len = CPU_TO_LE16(tlv_len); 3595 3596 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3597 if (!status) { 3598 if (mib_len != NULL) 3599 *mib_len = LE16_TO_CPU(desc.datalen); 3600 } 3601 3602 return status; 3603 } 3604 3605 /** 3606 * i40e_aq_update_lldp_tlv 3607 * @hw: pointer to the hw struct 3608 * @bridge_type: type of bridge 3609 * @buff: buffer with TLV to update 3610 * @buff_size: size of the buffer holding original and updated TLVs 3611 * @old_len: Length of the Original TLV 3612 * @new_len: Length of the Updated TLV 3613 * @offset: offset of the updated TLV in the buff 3614 * @mib_len: length of the returned LLDP MIB 3615 * @cmd_details: pointer to command details structure or NULL 3616 * 3617 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 3618 * Firmware will place the complete LLDP MIB in response buffer with the 3619 * updated TLV. 3620 **/ 3621 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 3622 u8 bridge_type, void *buff, u16 buff_size, 3623 u16 old_len, u16 new_len, u16 offset, 3624 u16 *mib_len, 3625 struct i40e_asq_cmd_details *cmd_details) 3626 { 3627 struct i40e_aq_desc desc; 3628 struct i40e_aqc_lldp_update_tlv *cmd = 3629 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 3630 enum i40e_status_code status; 3631 3632 if (buff_size == 0 || !buff || offset == 0 || 3633 old_len == 0 || new_len == 0) 3634 return I40E_ERR_PARAM; 3635 3636 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 3637 3638 /* Indirect Command */ 3639 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3640 if (buff_size > I40E_AQ_LARGE_BUF) 3641 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3642 desc.datalen = CPU_TO_LE16(buff_size); 3643 3644 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3645 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3646 cmd->old_len = CPU_TO_LE16(old_len); 3647 cmd->new_offset = CPU_TO_LE16(offset); 3648 cmd->new_len = CPU_TO_LE16(new_len); 3649 3650 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3651 if (!status) { 3652 if (mib_len != NULL) 3653 *mib_len = LE16_TO_CPU(desc.datalen); 3654 } 3655 3656 return status; 3657 } 3658 3659 /** 3660 * i40e_aq_delete_lldp_tlv 3661 * @hw: pointer to the hw struct 3662 * @bridge_type: type of bridge 3663 * @buff: pointer to a user supplied buffer that has the TLV 3664 * @buff_size: length of the buffer 3665 * @tlv_len: length of the TLV to be deleted 3666 * @mib_len: length of the returned LLDP MIB 3667 * @cmd_details: pointer to command details structure or NULL 3668 * 3669 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 3670 * The firmware places the entire LLDP MIB in the response buffer. 3671 **/ 3672 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 3673 u8 bridge_type, void *buff, u16 buff_size, 3674 u16 tlv_len, u16 *mib_len, 3675 struct i40e_asq_cmd_details *cmd_details) 3676 { 3677 struct i40e_aq_desc desc; 3678 struct i40e_aqc_lldp_add_tlv *cmd = 3679 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 3680 enum i40e_status_code status; 3681 3682 if (buff_size == 0 || !buff) 3683 return I40E_ERR_PARAM; 3684 3685 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 3686 3687 /* Indirect Command */ 3688 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3689 if (buff_size > I40E_AQ_LARGE_BUF) 3690 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3691 desc.datalen = CPU_TO_LE16(buff_size); 3692 cmd->len = CPU_TO_LE16(tlv_len); 3693 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3694 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3695 3696 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3697 if (!status) { 3698 if (mib_len != NULL) 3699 *mib_len = LE16_TO_CPU(desc.datalen); 3700 } 3701 3702 return status; 3703 } 3704 3705 /** 3706 * i40e_aq_stop_lldp 3707 * @hw: pointer to the hw struct 3708 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3709 * @cmd_details: pointer to command details structure or NULL 3710 * 3711 * Stop or Shutdown the embedded LLDP Agent 3712 **/ 3713 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3714 struct i40e_asq_cmd_details *cmd_details) 3715 { 3716 struct i40e_aq_desc desc; 3717 struct i40e_aqc_lldp_stop *cmd = 3718 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3719 enum i40e_status_code status; 3720 3721 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3722 3723 if (shutdown_agent) 3724 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3725 3726 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3727 3728 return status; 3729 } 3730 3731 /** 3732 * i40e_aq_start_lldp 3733 * @hw: pointer to the hw struct 3734 * @cmd_details: pointer to command details structure or NULL 3735 * 3736 * Start the embedded LLDP Agent on all ports. 3737 **/ 3738 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 3739 struct i40e_asq_cmd_details *cmd_details) 3740 { 3741 struct i40e_aq_desc desc; 3742 struct i40e_aqc_lldp_start *cmd = 3743 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3744 enum i40e_status_code status; 3745 3746 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3747 3748 cmd->command = I40E_AQ_LLDP_AGENT_START; 3749 3750 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3751 3752 return status; 3753 } 3754 3755 /** 3756 * i40e_aq_get_cee_dcb_config 3757 * @hw: pointer to the hw struct 3758 * @buff: response buffer that stores CEE operational configuration 3759 * @buff_size: size of the buffer passed 3760 * @cmd_details: pointer to command details structure or NULL 3761 * 3762 * Get CEE DCBX mode operational configuration from firmware 3763 **/ 3764 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3765 void *buff, u16 buff_size, 3766 struct i40e_asq_cmd_details *cmd_details) 3767 { 3768 struct i40e_aq_desc desc; 3769 enum i40e_status_code status; 3770 3771 if (buff_size == 0 || !buff) 3772 return I40E_ERR_PARAM; 3773 3774 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3775 3776 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3777 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3778 cmd_details); 3779 3780 return status; 3781 } 3782 3783 /** 3784 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 3785 * @hw: pointer to the hw struct 3786 * @start_agent: True if DCBx Agent needs to be Started 3787 * False if DCBx Agent needs to be Stopped 3788 * @cmd_details: pointer to command details structure or NULL 3789 * 3790 * Start/Stop the embedded dcbx Agent 3791 **/ 3792 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 3793 bool start_agent, 3794 struct i40e_asq_cmd_details *cmd_details) 3795 { 3796 struct i40e_aq_desc desc; 3797 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 3798 (struct i40e_aqc_lldp_stop_start_specific_agent *) 3799 &desc.params.raw; 3800 enum i40e_status_code status; 3801 3802 i40e_fill_default_direct_cmd_desc(&desc, 3803 i40e_aqc_opc_lldp_stop_start_spec_agent); 3804 3805 if (start_agent) 3806 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 3807 3808 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3809 3810 return status; 3811 } 3812 3813 /** 3814 * i40e_aq_add_udp_tunnel 3815 * @hw: pointer to the hw struct 3816 * @udp_port: the UDP port to add 3817 * @header_len: length of the tunneling header length in DWords 3818 * @protocol_index: protocol index type 3819 * @filter_index: pointer to filter index 3820 * @cmd_details: pointer to command details structure or NULL 3821 **/ 3822 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3823 u16 udp_port, u8 protocol_index, 3824 u8 *filter_index, 3825 struct i40e_asq_cmd_details *cmd_details) 3826 { 3827 struct i40e_aq_desc desc; 3828 struct i40e_aqc_add_udp_tunnel *cmd = 3829 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3830 struct i40e_aqc_del_udp_tunnel_completion *resp = 3831 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3832 enum i40e_status_code status; 3833 3834 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3835 3836 cmd->udp_port = CPU_TO_LE16(udp_port); 3837 cmd->protocol_type = protocol_index; 3838 3839 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3840 3841 if (!status && filter_index) 3842 *filter_index = resp->index; 3843 3844 return status; 3845 } 3846 3847 /** 3848 * i40e_aq_del_udp_tunnel 3849 * @hw: pointer to the hw struct 3850 * @index: filter index 3851 * @cmd_details: pointer to command details structure or NULL 3852 **/ 3853 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3854 struct i40e_asq_cmd_details *cmd_details) 3855 { 3856 struct i40e_aq_desc desc; 3857 struct i40e_aqc_remove_udp_tunnel *cmd = 3858 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3859 enum i40e_status_code status; 3860 3861 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3862 3863 cmd->index = index; 3864 3865 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3866 3867 return status; 3868 } 3869 3870 /** 3871 * i40e_aq_get_switch_resource_alloc (0x0204) 3872 * @hw: pointer to the hw struct 3873 * @num_entries: pointer to u8 to store the number of resource entries returned 3874 * @buf: pointer to a user supplied buffer. This buffer must be large enough 3875 * to store the resource information for all resource types. Each 3876 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 3877 * @count: size, in bytes, of the buffer provided 3878 * @cmd_details: pointer to command details structure or NULL 3879 * 3880 * Query the resources allocated to a function. 3881 **/ 3882 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 3883 u8 *num_entries, 3884 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 3885 u16 count, 3886 struct i40e_asq_cmd_details *cmd_details) 3887 { 3888 struct i40e_aq_desc desc; 3889 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 3890 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 3891 enum i40e_status_code status; 3892 u16 length = count * sizeof(*buf); 3893 3894 i40e_fill_default_direct_cmd_desc(&desc, 3895 i40e_aqc_opc_get_switch_resource_alloc); 3896 3897 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3898 if (length > I40E_AQ_LARGE_BUF) 3899 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3900 3901 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 3902 3903 if (!status && num_entries) 3904 *num_entries = cmd_resp->num_entries; 3905 3906 return status; 3907 } 3908 3909 /** 3910 * i40e_aq_delete_element - Delete switch element 3911 * @hw: pointer to the hw struct 3912 * @seid: the SEID to delete from the switch 3913 * @cmd_details: pointer to command details structure or NULL 3914 * 3915 * This deletes a switch element from the switch. 3916 **/ 3917 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3918 struct i40e_asq_cmd_details *cmd_details) 3919 { 3920 struct i40e_aq_desc desc; 3921 struct i40e_aqc_switch_seid *cmd = 3922 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3923 enum i40e_status_code status; 3924 3925 if (seid == 0) 3926 return I40E_ERR_PARAM; 3927 3928 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3929 3930 cmd->seid = CPU_TO_LE16(seid); 3931 3932 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3933 3934 return status; 3935 } 3936 3937 /** 3938 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port 3939 * @hw: pointer to the hw struct 3940 * @flags: component flags 3941 * @mac_seid: uplink seid (MAC SEID) 3942 * @vsi_seid: connected vsi seid 3943 * @ret_seid: seid of create pv component 3944 * 3945 * This instantiates an i40e port virtualizer with specified flags. 3946 * Depending on specified flags the port virtualizer can act as a 3947 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 3948 */ 3949 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 3950 u16 mac_seid, u16 vsi_seid, 3951 u16 *ret_seid) 3952 { 3953 struct i40e_aq_desc desc; 3954 struct i40e_aqc_add_update_pv *cmd = 3955 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 3956 struct i40e_aqc_add_update_pv_completion *resp = 3957 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 3958 enum i40e_status_code status; 3959 3960 if (vsi_seid == 0) 3961 return I40E_ERR_PARAM; 3962 3963 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 3964 cmd->command_flags = CPU_TO_LE16(flags); 3965 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 3966 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 3967 3968 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3969 if (!status && ret_seid) 3970 *ret_seid = LE16_TO_CPU(resp->pv_seid); 3971 3972 return status; 3973 } 3974 3975 /** 3976 * i40e_aq_add_tag - Add an S/E-tag 3977 * @hw: pointer to the hw struct 3978 * @direct_to_queue: should s-tag direct flow to a specific queue 3979 * @vsi_seid: VSI SEID to use this tag 3980 * @tag: value of the tag 3981 * @queue_num: queue number, only valid is direct_to_queue is TRUE 3982 * @tags_used: return value, number of tags in use by this PF 3983 * @tags_free: return value, number of unallocated tags 3984 * @cmd_details: pointer to command details structure or NULL 3985 * 3986 * This associates an S- or E-tag to a VSI in the switch complex. It returns 3987 * the number of tags allocated by the PF, and the number of unallocated 3988 * tags available. 3989 **/ 3990 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 3991 u16 vsi_seid, u16 tag, u16 queue_num, 3992 u16 *tags_used, u16 *tags_free, 3993 struct i40e_asq_cmd_details *cmd_details) 3994 { 3995 struct i40e_aq_desc desc; 3996 struct i40e_aqc_add_tag *cmd = 3997 (struct i40e_aqc_add_tag *)&desc.params.raw; 3998 struct i40e_aqc_add_remove_tag_completion *resp = 3999 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4000 enum i40e_status_code status; 4001 4002 if (vsi_seid == 0) 4003 return I40E_ERR_PARAM; 4004 4005 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4006 4007 cmd->seid = CPU_TO_LE16(vsi_seid); 4008 cmd->tag = CPU_TO_LE16(tag); 4009 if (direct_to_queue) { 4010 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4011 cmd->queue_number = CPU_TO_LE16(queue_num); 4012 } 4013 4014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4015 4016 if (!status) { 4017 if (tags_used != NULL) 4018 *tags_used = LE16_TO_CPU(resp->tags_used); 4019 if (tags_free != NULL) 4020 *tags_free = LE16_TO_CPU(resp->tags_free); 4021 } 4022 4023 return status; 4024 } 4025 4026 /** 4027 * i40e_aq_remove_tag - Remove an S- or E-tag 4028 * @hw: pointer to the hw struct 4029 * @vsi_seid: VSI SEID this tag is associated with 4030 * @tag: value of the S-tag to delete 4031 * @tags_used: return value, number of tags in use by this PF 4032 * @tags_free: return value, number of unallocated tags 4033 * @cmd_details: pointer to command details structure or NULL 4034 * 4035 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4036 * the number of tags allocated by the PF, and the number of unallocated 4037 * tags available. 4038 **/ 4039 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4040 u16 tag, u16 *tags_used, u16 *tags_free, 4041 struct i40e_asq_cmd_details *cmd_details) 4042 { 4043 struct i40e_aq_desc desc; 4044 struct i40e_aqc_remove_tag *cmd = 4045 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4046 struct i40e_aqc_add_remove_tag_completion *resp = 4047 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4048 enum i40e_status_code status; 4049 4050 if (vsi_seid == 0) 4051 return I40E_ERR_PARAM; 4052 4053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4054 4055 cmd->seid = CPU_TO_LE16(vsi_seid); 4056 cmd->tag = CPU_TO_LE16(tag); 4057 4058 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4059 4060 if (!status) { 4061 if (tags_used != NULL) 4062 *tags_used = LE16_TO_CPU(resp->tags_used); 4063 if (tags_free != NULL) 4064 *tags_free = LE16_TO_CPU(resp->tags_free); 4065 } 4066 4067 return status; 4068 } 4069 4070 /** 4071 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4072 * @hw: pointer to the hw struct 4073 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4074 * @etag: value of E-tag to add 4075 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4076 * @buf: address of indirect buffer 4077 * @tags_used: return value, number of E-tags in use by this port 4078 * @tags_free: return value, number of unallocated M-tags 4079 * @cmd_details: pointer to command details structure or NULL 4080 * 4081 * This associates a multicast E-tag to a port virtualizer. It will return 4082 * the number of tags allocated by the PF, and the number of unallocated 4083 * tags available. 4084 * 4085 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4086 * num_tags_in_buf long. 4087 **/ 4088 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4089 u16 etag, u8 num_tags_in_buf, void *buf, 4090 u16 *tags_used, u16 *tags_free, 4091 struct i40e_asq_cmd_details *cmd_details) 4092 { 4093 struct i40e_aq_desc desc; 4094 struct i40e_aqc_add_remove_mcast_etag *cmd = 4095 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4096 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4097 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4098 enum i40e_status_code status; 4099 u16 length = sizeof(u16) * num_tags_in_buf; 4100 4101 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4102 return I40E_ERR_PARAM; 4103 4104 i40e_fill_default_direct_cmd_desc(&desc, 4105 i40e_aqc_opc_add_multicast_etag); 4106 4107 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4108 cmd->etag = CPU_TO_LE16(etag); 4109 cmd->num_unicast_etags = num_tags_in_buf; 4110 4111 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4112 if (length > I40E_AQ_LARGE_BUF) 4113 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4114 4115 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4116 4117 if (!status) { 4118 if (tags_used != NULL) 4119 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4120 if (tags_free != NULL) 4121 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4122 } 4123 4124 return status; 4125 } 4126 4127 /** 4128 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4129 * @hw: pointer to the hw struct 4130 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4131 * @etag: value of the E-tag to remove 4132 * @tags_used: return value, number of tags in use by this port 4133 * @tags_free: return value, number of unallocated tags 4134 * @cmd_details: pointer to command details structure or NULL 4135 * 4136 * This deletes an E-tag from the port virtualizer. It will return 4137 * the number of tags allocated by the port, and the number of unallocated 4138 * tags available. 4139 **/ 4140 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4141 u16 etag, u16 *tags_used, u16 *tags_free, 4142 struct i40e_asq_cmd_details *cmd_details) 4143 { 4144 struct i40e_aq_desc desc; 4145 struct i40e_aqc_add_remove_mcast_etag *cmd = 4146 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4147 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4148 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4149 enum i40e_status_code status; 4150 4151 4152 if (pv_seid == 0) 4153 return I40E_ERR_PARAM; 4154 4155 i40e_fill_default_direct_cmd_desc(&desc, 4156 i40e_aqc_opc_remove_multicast_etag); 4157 4158 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4159 cmd->etag = CPU_TO_LE16(etag); 4160 4161 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4162 4163 if (!status) { 4164 if (tags_used != NULL) 4165 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4166 if (tags_free != NULL) 4167 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4168 } 4169 4170 return status; 4171 } 4172 4173 /** 4174 * i40e_aq_update_tag - Update an S/E-tag 4175 * @hw: pointer to the hw struct 4176 * @vsi_seid: VSI SEID using this S-tag 4177 * @old_tag: old tag value 4178 * @new_tag: new tag value 4179 * @tags_used: return value, number of tags in use by this PF 4180 * @tags_free: return value, number of unallocated tags 4181 * @cmd_details: pointer to command details structure or NULL 4182 * 4183 * This updates the value of the tag currently attached to this VSI 4184 * in the switch complex. It will return the number of tags allocated 4185 * by the PF, and the number of unallocated tags available. 4186 **/ 4187 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4188 u16 old_tag, u16 new_tag, u16 *tags_used, 4189 u16 *tags_free, 4190 struct i40e_asq_cmd_details *cmd_details) 4191 { 4192 struct i40e_aq_desc desc; 4193 struct i40e_aqc_update_tag *cmd = 4194 (struct i40e_aqc_update_tag *)&desc.params.raw; 4195 struct i40e_aqc_update_tag_completion *resp = 4196 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4197 enum i40e_status_code status; 4198 4199 if (vsi_seid == 0) 4200 return I40E_ERR_PARAM; 4201 4202 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4203 4204 cmd->seid = CPU_TO_LE16(vsi_seid); 4205 cmd->old_tag = CPU_TO_LE16(old_tag); 4206 cmd->new_tag = CPU_TO_LE16(new_tag); 4207 4208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4209 4210 if (!status) { 4211 if (tags_used != NULL) 4212 *tags_used = LE16_TO_CPU(resp->tags_used); 4213 if (tags_free != NULL) 4214 *tags_free = LE16_TO_CPU(resp->tags_free); 4215 } 4216 4217 return status; 4218 } 4219 4220 /** 4221 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4222 * @hw: pointer to the hw struct 4223 * @tcmap: TC map for request/release any ignore PFC condition 4224 * @request: request or release ignore PFC condition 4225 * @tcmap_ret: return TCs for which PFC is currently ignored 4226 * @cmd_details: pointer to command details structure or NULL 4227 * 4228 * This sends out request/release to ignore PFC condition for a TC. 4229 * It will return the TCs for which PFC is currently ignored. 4230 **/ 4231 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4232 bool request, u8 *tcmap_ret, 4233 struct i40e_asq_cmd_details *cmd_details) 4234 { 4235 struct i40e_aq_desc desc; 4236 struct i40e_aqc_pfc_ignore *cmd_resp = 4237 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4238 enum i40e_status_code status; 4239 4240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4241 4242 if (request) 4243 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4244 4245 cmd_resp->tc_bitmap = tcmap; 4246 4247 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4248 4249 if (!status) { 4250 if (tcmap_ret != NULL) 4251 *tcmap_ret = cmd_resp->tc_bitmap; 4252 } 4253 4254 return status; 4255 } 4256 4257 /** 4258 * i40e_aq_dcb_updated - DCB Updated Command 4259 * @hw: pointer to the hw struct 4260 * @cmd_details: pointer to command details structure or NULL 4261 * 4262 * When LLDP is handled in PF this command is used by the PF 4263 * to notify EMP that a DCB setting is modified. 4264 * When LLDP is handled in EMP this command is used by the PF 4265 * to notify EMP whenever one of the following parameters get 4266 * modified: 4267 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4268 * - PCIRTT in PRTDCB_GENC.PCIRTT 4269 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4270 * EMP will return when the shared RPB settings have been 4271 * recomputed and modified. The retval field in the descriptor 4272 * will be set to 0 when RPB is modified. 4273 **/ 4274 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4275 struct i40e_asq_cmd_details *cmd_details) 4276 { 4277 struct i40e_aq_desc desc; 4278 enum i40e_status_code status; 4279 4280 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4281 4282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4283 4284 return status; 4285 } 4286 4287 /** 4288 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4289 * @hw: pointer to the hw struct 4290 * @seid: defines the SEID of the switch for which the stats are requested 4291 * @vlan_id: the VLAN ID for which the statistics are requested 4292 * @stat_index: index of the statistics counters block assigned to this VLAN 4293 * @cmd_details: pointer to command details structure or NULL 4294 * 4295 * XL710 supports 128 smonVlanStats counters.This command is used to 4296 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4297 * switch. 4298 **/ 4299 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4300 u16 vlan_id, u16 *stat_index, 4301 struct i40e_asq_cmd_details *cmd_details) 4302 { 4303 struct i40e_aq_desc desc; 4304 struct i40e_aqc_add_remove_statistics *cmd_resp = 4305 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4306 enum i40e_status_code status; 4307 4308 if ((seid == 0) || (stat_index == NULL)) 4309 return I40E_ERR_PARAM; 4310 4311 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 4312 4313 cmd_resp->seid = CPU_TO_LE16(seid); 4314 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 4315 4316 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4317 4318 if (!status && stat_index) 4319 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 4320 4321 return status; 4322 } 4323 4324 /** 4325 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 4326 * @hw: pointer to the hw struct 4327 * @seid: defines the SEID of the switch for which the stats are requested 4328 * @vlan_id: the VLAN ID for which the statistics are requested 4329 * @stat_index: index of the statistics counters block assigned to this VLAN 4330 * @cmd_details: pointer to command details structure or NULL 4331 * 4332 * XL710 supports 128 smonVlanStats counters.This command is used to 4333 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 4334 * switch. 4335 **/ 4336 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 4337 u16 vlan_id, u16 stat_index, 4338 struct i40e_asq_cmd_details *cmd_details) 4339 { 4340 struct i40e_aq_desc desc; 4341 struct i40e_aqc_add_remove_statistics *cmd = 4342 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4343 enum i40e_status_code status; 4344 4345 if (seid == 0) 4346 return I40E_ERR_PARAM; 4347 4348 i40e_fill_default_direct_cmd_desc(&desc, 4349 i40e_aqc_opc_remove_statistics); 4350 4351 cmd->seid = CPU_TO_LE16(seid); 4352 cmd->vlan = CPU_TO_LE16(vlan_id); 4353 cmd->stat_index = CPU_TO_LE16(stat_index); 4354 4355 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4356 4357 return status; 4358 } 4359 4360 /** 4361 * i40e_aq_set_port_parameters - set physical port parameters. 4362 * @hw: pointer to the hw struct 4363 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 4364 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 4365 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 4366 * @double_vlan: if set double VLAN is enabled 4367 * @cmd_details: pointer to command details structure or NULL 4368 **/ 4369 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 4370 u16 bad_frame_vsi, bool save_bad_pac, 4371 bool pad_short_pac, bool double_vlan, 4372 struct i40e_asq_cmd_details *cmd_details) 4373 { 4374 struct i40e_aqc_set_port_parameters *cmd; 4375 enum i40e_status_code status; 4376 struct i40e_aq_desc desc; 4377 u16 command_flags = 0; 4378 4379 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 4380 4381 i40e_fill_default_direct_cmd_desc(&desc, 4382 i40e_aqc_opc_set_port_parameters); 4383 4384 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 4385 if (save_bad_pac) 4386 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 4387 if (pad_short_pac) 4388 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 4389 if (double_vlan) 4390 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 4391 cmd->command_flags = CPU_TO_LE16(command_flags); 4392 4393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4394 4395 return status; 4396 } 4397 4398 /** 4399 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 4400 * @hw: pointer to the hw struct 4401 * @seid: seid for the physical port/switching component/vsi 4402 * @buff: Indirect buffer to hold data parameters and response 4403 * @buff_size: Indirect buffer size 4404 * @opcode: Tx scheduler AQ command opcode 4405 * @cmd_details: pointer to command details structure or NULL 4406 * 4407 * Generic command handler for Tx scheduler AQ commands 4408 **/ 4409 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 4410 void *buff, u16 buff_size, 4411 enum i40e_admin_queue_opc opcode, 4412 struct i40e_asq_cmd_details *cmd_details) 4413 { 4414 struct i40e_aq_desc desc; 4415 struct i40e_aqc_tx_sched_ind *cmd = 4416 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4417 enum i40e_status_code status; 4418 bool cmd_param_flag = FALSE; 4419 4420 switch (opcode) { 4421 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 4422 case i40e_aqc_opc_configure_vsi_tc_bw: 4423 case i40e_aqc_opc_enable_switching_comp_ets: 4424 case i40e_aqc_opc_modify_switching_comp_ets: 4425 case i40e_aqc_opc_disable_switching_comp_ets: 4426 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 4427 case i40e_aqc_opc_configure_switching_comp_bw_config: 4428 cmd_param_flag = TRUE; 4429 break; 4430 case i40e_aqc_opc_query_vsi_bw_config: 4431 case i40e_aqc_opc_query_vsi_ets_sla_config: 4432 case i40e_aqc_opc_query_switching_comp_ets_config: 4433 case i40e_aqc_opc_query_port_ets_config: 4434 case i40e_aqc_opc_query_switching_comp_bw_config: 4435 cmd_param_flag = FALSE; 4436 break; 4437 default: 4438 return I40E_ERR_PARAM; 4439 } 4440 4441 i40e_fill_default_direct_cmd_desc(&desc, opcode); 4442 4443 /* Indirect command */ 4444 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4445 if (cmd_param_flag) 4446 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 4447 if (buff_size > I40E_AQ_LARGE_BUF) 4448 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4449 4450 desc.datalen = CPU_TO_LE16(buff_size); 4451 4452 cmd->vsi_seid = CPU_TO_LE16(seid); 4453 4454 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4455 4456 return status; 4457 } 4458 4459 /** 4460 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 4461 * @hw: pointer to the hw struct 4462 * @seid: VSI seid 4463 * @credit: BW limit credits (0 = disabled) 4464 * @max_credit: Max BW limit credits 4465 * @cmd_details: pointer to command details structure or NULL 4466 **/ 4467 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 4468 u16 seid, u16 credit, u8 max_credit, 4469 struct i40e_asq_cmd_details *cmd_details) 4470 { 4471 struct i40e_aq_desc desc; 4472 struct i40e_aqc_configure_vsi_bw_limit *cmd = 4473 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 4474 enum i40e_status_code status; 4475 4476 i40e_fill_default_direct_cmd_desc(&desc, 4477 i40e_aqc_opc_configure_vsi_bw_limit); 4478 4479 cmd->vsi_seid = CPU_TO_LE16(seid); 4480 cmd->credit = CPU_TO_LE16(credit); 4481 cmd->max_credit = max_credit; 4482 4483 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4484 4485 return status; 4486 } 4487 4488 /** 4489 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 4490 * @hw: pointer to the hw struct 4491 * @seid: switching component seid 4492 * @credit: BW limit credits (0 = disabled) 4493 * @max_bw: Max BW limit credits 4494 * @cmd_details: pointer to command details structure or NULL 4495 **/ 4496 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 4497 u16 seid, u16 credit, u8 max_bw, 4498 struct i40e_asq_cmd_details *cmd_details) 4499 { 4500 struct i40e_aq_desc desc; 4501 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 4502 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 4503 enum i40e_status_code status; 4504 4505 i40e_fill_default_direct_cmd_desc(&desc, 4506 i40e_aqc_opc_configure_switching_comp_bw_limit); 4507 4508 cmd->seid = CPU_TO_LE16(seid); 4509 cmd->credit = CPU_TO_LE16(credit); 4510 cmd->max_bw = max_bw; 4511 4512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4513 4514 return status; 4515 } 4516 4517 /** 4518 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 4519 * @hw: pointer to the hw struct 4520 * @seid: VSI seid 4521 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4522 * @cmd_details: pointer to command details structure or NULL 4523 **/ 4524 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 4525 u16 seid, 4526 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 4527 struct i40e_asq_cmd_details *cmd_details) 4528 { 4529 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4530 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 4531 cmd_details); 4532 } 4533 4534 /** 4535 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 4536 * @hw: pointer to the hw struct 4537 * @seid: VSI seid 4538 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 4539 * @cmd_details: pointer to command details structure or NULL 4540 **/ 4541 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 4542 u16 seid, 4543 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 4544 struct i40e_asq_cmd_details *cmd_details) 4545 { 4546 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4547 i40e_aqc_opc_configure_vsi_tc_bw, 4548 cmd_details); 4549 } 4550 4551 /** 4552 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 4553 * @hw: pointer to the hw struct 4554 * @seid: seid of the switching component 4555 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 4556 * @cmd_details: pointer to command details structure or NULL 4557 **/ 4558 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 4559 struct i40e_hw *hw, u16 seid, 4560 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 4561 struct i40e_asq_cmd_details *cmd_details) 4562 { 4563 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4564 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 4565 cmd_details); 4566 } 4567 4568 /** 4569 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4570 * @hw: pointer to the hw struct 4571 * @seid: seid of the VSI 4572 * @bw_data: Buffer to hold VSI BW configuration 4573 * @cmd_details: pointer to command details structure or NULL 4574 **/ 4575 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4576 u16 seid, 4577 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4578 struct i40e_asq_cmd_details *cmd_details) 4579 { 4580 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4581 i40e_aqc_opc_query_vsi_bw_config, 4582 cmd_details); 4583 } 4584 4585 /** 4586 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4587 * @hw: pointer to the hw struct 4588 * @seid: seid of the VSI 4589 * @bw_data: Buffer to hold VSI BW configuration per TC 4590 * @cmd_details: pointer to command details structure or NULL 4591 **/ 4592 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4593 u16 seid, 4594 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4595 struct i40e_asq_cmd_details *cmd_details) 4596 { 4597 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4598 i40e_aqc_opc_query_vsi_ets_sla_config, 4599 cmd_details); 4600 } 4601 4602 /** 4603 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4604 * @hw: pointer to the hw struct 4605 * @seid: seid of the switching component 4606 * @bw_data: Buffer to hold switching component's per TC BW config 4607 * @cmd_details: pointer to command details structure or NULL 4608 **/ 4609 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4610 u16 seid, 4611 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4612 struct i40e_asq_cmd_details *cmd_details) 4613 { 4614 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4615 i40e_aqc_opc_query_switching_comp_ets_config, 4616 cmd_details); 4617 } 4618 4619 /** 4620 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4621 * @hw: pointer to the hw struct 4622 * @seid: seid of the VSI or switching component connected to Physical Port 4623 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4624 * @cmd_details: pointer to command details structure or NULL 4625 **/ 4626 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4627 u16 seid, 4628 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4629 struct i40e_asq_cmd_details *cmd_details) 4630 { 4631 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4632 i40e_aqc_opc_query_port_ets_config, 4633 cmd_details); 4634 } 4635 4636 /** 4637 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4638 * @hw: pointer to the hw struct 4639 * @seid: seid of the switching component 4640 * @bw_data: Buffer to hold switching component's BW configuration 4641 * @cmd_details: pointer to command details structure or NULL 4642 **/ 4643 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4644 u16 seid, 4645 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4646 struct i40e_asq_cmd_details *cmd_details) 4647 { 4648 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4649 i40e_aqc_opc_query_switching_comp_bw_config, 4650 cmd_details); 4651 } 4652 4653 /** 4654 * i40e_validate_filter_settings 4655 * @hw: pointer to the hardware structure 4656 * @settings: Filter control settings 4657 * 4658 * Check and validate the filter control settings passed. 4659 * The function checks for the valid filter/context sizes being 4660 * passed for FCoE and PE. 4661 * 4662 * Returns I40E_SUCCESS if the values passed are valid and within 4663 * range else returns an error. 4664 **/ 4665 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 4666 struct i40e_filter_control_settings *settings) 4667 { 4668 u32 fcoe_cntx_size, fcoe_filt_size; 4669 u32 pe_cntx_size, pe_filt_size; 4670 u32 fcoe_fmax; 4671 4672 u32 val; 4673 4674 /* Validate FCoE settings passed */ 4675 switch (settings->fcoe_filt_num) { 4676 case I40E_HASH_FILTER_SIZE_1K: 4677 case I40E_HASH_FILTER_SIZE_2K: 4678 case I40E_HASH_FILTER_SIZE_4K: 4679 case I40E_HASH_FILTER_SIZE_8K: 4680 case I40E_HASH_FILTER_SIZE_16K: 4681 case I40E_HASH_FILTER_SIZE_32K: 4682 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4683 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4684 break; 4685 default: 4686 return I40E_ERR_PARAM; 4687 } 4688 4689 switch (settings->fcoe_cntx_num) { 4690 case I40E_DMA_CNTX_SIZE_512: 4691 case I40E_DMA_CNTX_SIZE_1K: 4692 case I40E_DMA_CNTX_SIZE_2K: 4693 case I40E_DMA_CNTX_SIZE_4K: 4694 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4695 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4696 break; 4697 default: 4698 return I40E_ERR_PARAM; 4699 } 4700 4701 /* Validate PE settings passed */ 4702 switch (settings->pe_filt_num) { 4703 case I40E_HASH_FILTER_SIZE_1K: 4704 case I40E_HASH_FILTER_SIZE_2K: 4705 case I40E_HASH_FILTER_SIZE_4K: 4706 case I40E_HASH_FILTER_SIZE_8K: 4707 case I40E_HASH_FILTER_SIZE_16K: 4708 case I40E_HASH_FILTER_SIZE_32K: 4709 case I40E_HASH_FILTER_SIZE_64K: 4710 case I40E_HASH_FILTER_SIZE_128K: 4711 case I40E_HASH_FILTER_SIZE_256K: 4712 case I40E_HASH_FILTER_SIZE_512K: 4713 case I40E_HASH_FILTER_SIZE_1M: 4714 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4715 pe_filt_size <<= (u32)settings->pe_filt_num; 4716 break; 4717 default: 4718 return I40E_ERR_PARAM; 4719 } 4720 4721 switch (settings->pe_cntx_num) { 4722 case I40E_DMA_CNTX_SIZE_512: 4723 case I40E_DMA_CNTX_SIZE_1K: 4724 case I40E_DMA_CNTX_SIZE_2K: 4725 case I40E_DMA_CNTX_SIZE_4K: 4726 case I40E_DMA_CNTX_SIZE_8K: 4727 case I40E_DMA_CNTX_SIZE_16K: 4728 case I40E_DMA_CNTX_SIZE_32K: 4729 case I40E_DMA_CNTX_SIZE_64K: 4730 case I40E_DMA_CNTX_SIZE_128K: 4731 case I40E_DMA_CNTX_SIZE_256K: 4732 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4733 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4734 break; 4735 default: 4736 return I40E_ERR_PARAM; 4737 } 4738 4739 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4740 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4741 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4742 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4743 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4744 return I40E_ERR_INVALID_SIZE; 4745 4746 return I40E_SUCCESS; 4747 } 4748 4749 /** 4750 * i40e_set_filter_control 4751 * @hw: pointer to the hardware structure 4752 * @settings: Filter control settings 4753 * 4754 * Set the Queue Filters for PE/FCoE and enable filters required 4755 * for a single PF. It is expected that these settings are programmed 4756 * at the driver initialization time. 4757 **/ 4758 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 4759 struct i40e_filter_control_settings *settings) 4760 { 4761 enum i40e_status_code ret = I40E_SUCCESS; 4762 u32 hash_lut_size = 0; 4763 u32 val; 4764 4765 if (!settings) 4766 return I40E_ERR_PARAM; 4767 4768 /* Validate the input settings */ 4769 ret = i40e_validate_filter_settings(hw, settings); 4770 if (ret) 4771 return ret; 4772 4773 /* Read the PF Queue Filter control register */ 4774 val = rd32(hw, I40E_PFQF_CTL_0); 4775 4776 /* Program required PE hash buckets for the PF */ 4777 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4778 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4779 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4780 /* Program required PE contexts for the PF */ 4781 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4782 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4783 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4784 4785 /* Program required FCoE hash buckets for the PF */ 4786 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4787 val |= ((u32)settings->fcoe_filt_num << 4788 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4789 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4790 /* Program required FCoE DDP contexts for the PF */ 4791 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4792 val |= ((u32)settings->fcoe_cntx_num << 4793 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4794 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4795 4796 /* Program Hash LUT size for the PF */ 4797 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4798 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4799 hash_lut_size = 1; 4800 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4801 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4802 4803 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4804 if (settings->enable_fdir) 4805 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4806 if (settings->enable_ethtype) 4807 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4808 if (settings->enable_macvlan) 4809 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4810 4811 wr32(hw, I40E_PFQF_CTL_0, val); 4812 4813 return I40E_SUCCESS; 4814 } 4815 4816 /** 4817 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4818 * @hw: pointer to the hw struct 4819 * @mac_addr: MAC address to use in the filter 4820 * @ethtype: Ethertype to use in the filter 4821 * @flags: Flags that needs to be applied to the filter 4822 * @vsi_seid: seid of the control VSI 4823 * @queue: VSI queue number to send the packet to 4824 * @is_add: Add control packet filter if True else remove 4825 * @stats: Structure to hold information on control filter counts 4826 * @cmd_details: pointer to command details structure or NULL 4827 * 4828 * This command will Add or Remove control packet filter for a control VSI. 4829 * In return it will update the total number of perfect filter count in 4830 * the stats member. 4831 **/ 4832 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4833 u8 *mac_addr, u16 ethtype, u16 flags, 4834 u16 vsi_seid, u16 queue, bool is_add, 4835 struct i40e_control_filter_stats *stats, 4836 struct i40e_asq_cmd_details *cmd_details) 4837 { 4838 struct i40e_aq_desc desc; 4839 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4840 (struct i40e_aqc_add_remove_control_packet_filter *) 4841 &desc.params.raw; 4842 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4843 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4844 &desc.params.raw; 4845 enum i40e_status_code status; 4846 4847 if (vsi_seid == 0) 4848 return I40E_ERR_PARAM; 4849 4850 if (is_add) { 4851 i40e_fill_default_direct_cmd_desc(&desc, 4852 i40e_aqc_opc_add_control_packet_filter); 4853 cmd->queue = CPU_TO_LE16(queue); 4854 } else { 4855 i40e_fill_default_direct_cmd_desc(&desc, 4856 i40e_aqc_opc_remove_control_packet_filter); 4857 } 4858 4859 if (mac_addr) 4860 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 4861 I40E_NONDMA_TO_NONDMA); 4862 4863 cmd->etype = CPU_TO_LE16(ethtype); 4864 cmd->flags = CPU_TO_LE16(flags); 4865 cmd->seid = CPU_TO_LE16(vsi_seid); 4866 4867 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4868 4869 if (!status && stats) { 4870 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 4871 stats->etype_used = LE16_TO_CPU(resp->etype_used); 4872 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 4873 stats->etype_free = LE16_TO_CPU(resp->etype_free); 4874 } 4875 4876 return status; 4877 } 4878 4879 /** 4880 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4881 * @hw: pointer to the hw struct 4882 * @seid: VSI seid to add ethertype filter from 4883 **/ 4884 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4885 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4886 u16 seid) 4887 { 4888 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4889 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4890 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4891 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4892 enum i40e_status_code status; 4893 4894 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4895 seid, 0, TRUE, NULL, 4896 NULL); 4897 if (status) 4898 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4899 } 4900 4901 /** 4902 * i40e_aq_add_cloud_filters 4903 * @hw: pointer to the hardware structure 4904 * @seid: VSI seid to add cloud filters from 4905 * @filters: Buffer which contains the filters to be added 4906 * @filter_count: number of filters contained in the buffer 4907 * 4908 * Set the cloud filters for a given VSI. The contents of the 4909 * i40e_aqc_add_remove_cloud_filters_element_data are filled 4910 * in by the caller of the function. 4911 * 4912 **/ 4913 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 4914 u16 seid, 4915 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4916 u8 filter_count) 4917 { 4918 struct i40e_aq_desc desc; 4919 struct i40e_aqc_add_remove_cloud_filters *cmd = 4920 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4921 u16 buff_len; 4922 enum i40e_status_code status; 4923 4924 i40e_fill_default_direct_cmd_desc(&desc, 4925 i40e_aqc_opc_add_cloud_filters); 4926 4927 buff_len = filter_count * sizeof(*filters); 4928 desc.datalen = CPU_TO_LE16(buff_len); 4929 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4930 cmd->num_filters = filter_count; 4931 cmd->seid = CPU_TO_LE16(seid); 4932 4933 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4934 4935 return status; 4936 } 4937 4938 /** 4939 * i40e_aq_remove_cloud_filters 4940 * @hw: pointer to the hardware structure 4941 * @seid: VSI seid to remove cloud filters from 4942 * @filters: Buffer which contains the filters to be removed 4943 * @filter_count: number of filters contained in the buffer 4944 * 4945 * Remove the cloud filters for a given VSI. The contents of the 4946 * i40e_aqc_add_remove_cloud_filters_element_data are filled 4947 * in by the caller of the function. 4948 * 4949 **/ 4950 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 4951 u16 seid, 4952 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 4953 u8 filter_count) 4954 { 4955 struct i40e_aq_desc desc; 4956 struct i40e_aqc_add_remove_cloud_filters *cmd = 4957 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 4958 enum i40e_status_code status; 4959 u16 buff_len; 4960 4961 i40e_fill_default_direct_cmd_desc(&desc, 4962 i40e_aqc_opc_remove_cloud_filters); 4963 4964 buff_len = filter_count * sizeof(*filters); 4965 desc.datalen = CPU_TO_LE16(buff_len); 4966 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4967 cmd->num_filters = filter_count; 4968 cmd->seid = CPU_TO_LE16(seid); 4969 4970 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 4971 4972 return status; 4973 } 4974 4975 /** 4976 * i40e_aq_alternate_write 4977 * @hw: pointer to the hardware structure 4978 * @reg_addr0: address of first dword to be read 4979 * @reg_val0: value to be written under 'reg_addr0' 4980 * @reg_addr1: address of second dword to be read 4981 * @reg_val1: value to be written under 'reg_addr1' 4982 * 4983 * Write one or two dwords to alternate structure. Fields are indicated 4984 * by 'reg_addr0' and 'reg_addr1' register numbers. 4985 * 4986 **/ 4987 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 4988 u32 reg_addr0, u32 reg_val0, 4989 u32 reg_addr1, u32 reg_val1) 4990 { 4991 struct i40e_aq_desc desc; 4992 struct i40e_aqc_alternate_write *cmd_resp = 4993 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4994 enum i40e_status_code status; 4995 4996 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 4997 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 4998 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 4999 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5000 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5001 5002 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5003 5004 return status; 5005 } 5006 5007 /** 5008 * i40e_aq_alternate_write_indirect 5009 * @hw: pointer to the hardware structure 5010 * @addr: address of a first register to be modified 5011 * @dw_count: number of alternate structure fields to write 5012 * @buffer: pointer to the command buffer 5013 * 5014 * Write 'dw_count' dwords from 'buffer' to alternate structure 5015 * starting at 'addr'. 5016 * 5017 **/ 5018 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5019 u32 addr, u32 dw_count, void *buffer) 5020 { 5021 struct i40e_aq_desc desc; 5022 struct i40e_aqc_alternate_ind_write *cmd_resp = 5023 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5024 enum i40e_status_code status; 5025 5026 if (buffer == NULL) 5027 return I40E_ERR_PARAM; 5028 5029 /* Indirect command */ 5030 i40e_fill_default_direct_cmd_desc(&desc, 5031 i40e_aqc_opc_alternate_write_indirect); 5032 5033 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5034 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5035 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5036 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5037 5038 cmd_resp->address = CPU_TO_LE32(addr); 5039 cmd_resp->length = CPU_TO_LE32(dw_count); 5040 5041 status = i40e_asq_send_command(hw, &desc, buffer, 5042 I40E_LO_DWORD(4*dw_count), NULL); 5043 5044 return status; 5045 } 5046 5047 /** 5048 * i40e_aq_alternate_read 5049 * @hw: pointer to the hardware structure 5050 * @reg_addr0: address of first dword to be read 5051 * @reg_val0: pointer for data read from 'reg_addr0' 5052 * @reg_addr1: address of second dword to be read 5053 * @reg_val1: pointer for data read from 'reg_addr1' 5054 * 5055 * Read one or two dwords from alternate structure. Fields are indicated 5056 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5057 * is not passed then only register at 'reg_addr0' is read. 5058 * 5059 **/ 5060 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5061 u32 reg_addr0, u32 *reg_val0, 5062 u32 reg_addr1, u32 *reg_val1) 5063 { 5064 struct i40e_aq_desc desc; 5065 struct i40e_aqc_alternate_write *cmd_resp = 5066 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5067 enum i40e_status_code status; 5068 5069 if (reg_val0 == NULL) 5070 return I40E_ERR_PARAM; 5071 5072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5073 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5074 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5075 5076 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5077 5078 if (status == I40E_SUCCESS) { 5079 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5080 5081 if (reg_val1 != NULL) 5082 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5083 } 5084 5085 return status; 5086 } 5087 5088 /** 5089 * i40e_aq_alternate_read_indirect 5090 * @hw: pointer to the hardware structure 5091 * @addr: address of the alternate structure field 5092 * @dw_count: number of alternate structure fields to read 5093 * @buffer: pointer to the command buffer 5094 * 5095 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5096 * place them in 'buffer'. The buffer should be allocated by caller. 5097 * 5098 **/ 5099 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5100 u32 addr, u32 dw_count, void *buffer) 5101 { 5102 struct i40e_aq_desc desc; 5103 struct i40e_aqc_alternate_ind_write *cmd_resp = 5104 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5105 enum i40e_status_code status; 5106 5107 if (buffer == NULL) 5108 return I40E_ERR_PARAM; 5109 5110 /* Indirect command */ 5111 i40e_fill_default_direct_cmd_desc(&desc, 5112 i40e_aqc_opc_alternate_read_indirect); 5113 5114 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5115 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5116 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5117 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5118 5119 cmd_resp->address = CPU_TO_LE32(addr); 5120 cmd_resp->length = CPU_TO_LE32(dw_count); 5121 5122 status = i40e_asq_send_command(hw, &desc, buffer, 5123 I40E_LO_DWORD(4*dw_count), NULL); 5124 5125 return status; 5126 } 5127 5128 /** 5129 * i40e_aq_alternate_clear 5130 * @hw: pointer to the HW structure. 5131 * 5132 * Clear the alternate structures of the port from which the function 5133 * is called. 5134 * 5135 **/ 5136 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5137 { 5138 struct i40e_aq_desc desc; 5139 enum i40e_status_code status; 5140 5141 i40e_fill_default_direct_cmd_desc(&desc, 5142 i40e_aqc_opc_alternate_clear_port); 5143 5144 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5145 5146 return status; 5147 } 5148 5149 /** 5150 * i40e_aq_alternate_write_done 5151 * @hw: pointer to the HW structure. 5152 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5153 * @reset_needed: indicates the SW should trigger GLOBAL reset 5154 * 5155 * Indicates to the FW that alternate structures have been changed. 5156 * 5157 **/ 5158 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5159 u8 bios_mode, bool *reset_needed) 5160 { 5161 struct i40e_aq_desc desc; 5162 struct i40e_aqc_alternate_write_done *cmd = 5163 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5164 enum i40e_status_code status; 5165 5166 if (reset_needed == NULL) 5167 return I40E_ERR_PARAM; 5168 5169 i40e_fill_default_direct_cmd_desc(&desc, 5170 i40e_aqc_opc_alternate_write_done); 5171 5172 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5173 5174 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5175 if (!status && reset_needed) 5176 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5177 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5178 5179 return status; 5180 } 5181 5182 /** 5183 * i40e_aq_set_oem_mode 5184 * @hw: pointer to the HW structure. 5185 * @oem_mode: the OEM mode to be used 5186 * 5187 * Sets the device to a specific operating mode. Currently the only supported 5188 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5189 * 5190 **/ 5191 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5192 u8 oem_mode) 5193 { 5194 struct i40e_aq_desc desc; 5195 struct i40e_aqc_alternate_write_done *cmd = 5196 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5197 enum i40e_status_code status; 5198 5199 i40e_fill_default_direct_cmd_desc(&desc, 5200 i40e_aqc_opc_alternate_set_mode); 5201 5202 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5203 5204 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5205 5206 return status; 5207 } 5208 5209 /** 5210 * i40e_aq_resume_port_tx 5211 * @hw: pointer to the hardware structure 5212 * @cmd_details: pointer to command details structure or NULL 5213 * 5214 * Resume port's Tx traffic 5215 **/ 5216 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5217 struct i40e_asq_cmd_details *cmd_details) 5218 { 5219 struct i40e_aq_desc desc; 5220 enum i40e_status_code status; 5221 5222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5223 5224 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5225 5226 return status; 5227 } 5228 5229 /** 5230 * i40e_set_pci_config_data - store PCI bus info 5231 * @hw: pointer to hardware structure 5232 * @link_status: the link status word from PCI config space 5233 * 5234 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5235 **/ 5236 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5237 { 5238 hw->bus.type = i40e_bus_type_pci_express; 5239 5240 switch (link_status & I40E_PCI_LINK_WIDTH) { 5241 case I40E_PCI_LINK_WIDTH_1: 5242 hw->bus.width = i40e_bus_width_pcie_x1; 5243 break; 5244 case I40E_PCI_LINK_WIDTH_2: 5245 hw->bus.width = i40e_bus_width_pcie_x2; 5246 break; 5247 case I40E_PCI_LINK_WIDTH_4: 5248 hw->bus.width = i40e_bus_width_pcie_x4; 5249 break; 5250 case I40E_PCI_LINK_WIDTH_8: 5251 hw->bus.width = i40e_bus_width_pcie_x8; 5252 break; 5253 default: 5254 hw->bus.width = i40e_bus_width_unknown; 5255 break; 5256 } 5257 5258 switch (link_status & I40E_PCI_LINK_SPEED) { 5259 case I40E_PCI_LINK_SPEED_2500: 5260 hw->bus.speed = i40e_bus_speed_2500; 5261 break; 5262 case I40E_PCI_LINK_SPEED_5000: 5263 hw->bus.speed = i40e_bus_speed_5000; 5264 break; 5265 case I40E_PCI_LINK_SPEED_8000: 5266 hw->bus.speed = i40e_bus_speed_8000; 5267 break; 5268 default: 5269 hw->bus.speed = i40e_bus_speed_unknown; 5270 break; 5271 } 5272 } 5273 5274 /** 5275 * i40e_aq_debug_dump 5276 * @hw: pointer to the hardware structure 5277 * @cluster_id: specific cluster to dump 5278 * @table_id: table id within cluster 5279 * @start_index: index of line in the block to read 5280 * @buff_size: dump buffer size 5281 * @buff: dump buffer 5282 * @ret_buff_size: actual buffer size returned 5283 * @ret_next_table: next block to read 5284 * @ret_next_index: next index to read 5285 * 5286 * Dump internal FW/HW data for debug purposes. 5287 * 5288 **/ 5289 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 5290 u8 table_id, u32 start_index, u16 buff_size, 5291 void *buff, u16 *ret_buff_size, 5292 u8 *ret_next_table, u32 *ret_next_index, 5293 struct i40e_asq_cmd_details *cmd_details) 5294 { 5295 struct i40e_aq_desc desc; 5296 struct i40e_aqc_debug_dump_internals *cmd = 5297 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5298 struct i40e_aqc_debug_dump_internals *resp = 5299 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5300 enum i40e_status_code status; 5301 5302 if (buff_size == 0 || !buff) 5303 return I40E_ERR_PARAM; 5304 5305 i40e_fill_default_direct_cmd_desc(&desc, 5306 i40e_aqc_opc_debug_dump_internals); 5307 /* Indirect Command */ 5308 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5309 if (buff_size > I40E_AQ_LARGE_BUF) 5310 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5311 5312 cmd->cluster_id = cluster_id; 5313 cmd->table_id = table_id; 5314 cmd->idx = CPU_TO_LE32(start_index); 5315 5316 desc.datalen = CPU_TO_LE16(buff_size); 5317 5318 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5319 if (!status) { 5320 if (ret_buff_size != NULL) 5321 *ret_buff_size = LE16_TO_CPU(desc.datalen); 5322 if (ret_next_table != NULL) 5323 *ret_next_table = resp->table_id; 5324 if (ret_next_index != NULL) 5325 *ret_next_index = LE32_TO_CPU(resp->idx); 5326 } 5327 5328 return status; 5329 } 5330 5331 /** 5332 * i40e_read_bw_from_alt_ram 5333 * @hw: pointer to the hardware structure 5334 * @max_bw: pointer for max_bw read 5335 * @min_bw: pointer for min_bw read 5336 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 5337 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 5338 * 5339 * Read bw from the alternate ram for the given pf 5340 **/ 5341 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 5342 u32 *max_bw, u32 *min_bw, 5343 bool *min_valid, bool *max_valid) 5344 { 5345 enum i40e_status_code status; 5346 u32 max_bw_addr, min_bw_addr; 5347 5348 /* Calculate the address of the min/max bw registers */ 5349 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5350 I40E_ALT_STRUCT_MAX_BW_OFFSET + 5351 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5352 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5353 I40E_ALT_STRUCT_MIN_BW_OFFSET + 5354 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5355 5356 /* Read the bandwidths from alt ram */ 5357 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 5358 min_bw_addr, min_bw); 5359 5360 if (*min_bw & I40E_ALT_BW_VALID_MASK) 5361 *min_valid = TRUE; 5362 else 5363 *min_valid = FALSE; 5364 5365 if (*max_bw & I40E_ALT_BW_VALID_MASK) 5366 *max_valid = TRUE; 5367 else 5368 *max_valid = FALSE; 5369 5370 return status; 5371 } 5372 5373 /** 5374 * i40e_aq_configure_partition_bw 5375 * @hw: pointer to the hardware structure 5376 * @bw_data: Buffer holding valid pfs and bw limits 5377 * @cmd_details: pointer to command details 5378 * 5379 * Configure partitions guaranteed/max bw 5380 **/ 5381 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 5382 struct i40e_aqc_configure_partition_bw_data *bw_data, 5383 struct i40e_asq_cmd_details *cmd_details) 5384 { 5385 enum i40e_status_code status; 5386 struct i40e_aq_desc desc; 5387 u16 bwd_size = sizeof(*bw_data); 5388 5389 i40e_fill_default_direct_cmd_desc(&desc, 5390 i40e_aqc_opc_configure_partition_bw); 5391 5392 /* Indirect command */ 5393 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5394 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5395 5396 if (bwd_size > I40E_AQ_LARGE_BUF) 5397 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5398 5399 desc.datalen = CPU_TO_LE16(bwd_size); 5400 5401 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 5402 5403 return status; 5404 } 5405 5406 /** 5407 * i40e_aq_send_msg_to_pf 5408 * @hw: pointer to the hardware structure 5409 * @v_opcode: opcodes for VF-PF communication 5410 * @v_retval: return error code 5411 * @msg: pointer to the msg buffer 5412 * @msglen: msg length 5413 * @cmd_details: pointer to command details 5414 * 5415 * Send message to PF driver using admin queue. By default, this message 5416 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 5417 * completion before returning. 5418 **/ 5419 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 5420 enum i40e_virtchnl_ops v_opcode, 5421 enum i40e_status_code v_retval, 5422 u8 *msg, u16 msglen, 5423 struct i40e_asq_cmd_details *cmd_details) 5424 { 5425 struct i40e_aq_desc desc; 5426 struct i40e_asq_cmd_details details; 5427 enum i40e_status_code status; 5428 5429 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 5430 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 5431 desc.cookie_high = CPU_TO_LE32(v_opcode); 5432 desc.cookie_low = CPU_TO_LE32(v_retval); 5433 if (msglen) { 5434 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 5435 | I40E_AQ_FLAG_RD)); 5436 if (msglen > I40E_AQ_LARGE_BUF) 5437 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5438 desc.datalen = CPU_TO_LE16(msglen); 5439 } 5440 if (!cmd_details) { 5441 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 5442 details.async = TRUE; 5443 cmd_details = &details; 5444 } 5445 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 5446 msglen, cmd_details); 5447 return status; 5448 } 5449 5450 /** 5451 * i40e_vf_parse_hw_config 5452 * @hw: pointer to the hardware structure 5453 * @msg: pointer to the virtual channel VF resource structure 5454 * 5455 * Given a VF resource message from the PF, populate the hw struct 5456 * with appropriate information. 5457 **/ 5458 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 5459 struct i40e_virtchnl_vf_resource *msg) 5460 { 5461 struct i40e_virtchnl_vsi_resource *vsi_res; 5462 int i; 5463 5464 vsi_res = &msg->vsi_res[0]; 5465 5466 hw->dev_caps.num_vsis = msg->num_vsis; 5467 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 5468 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 5469 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 5470 hw->dev_caps.dcb = msg->vf_offload_flags & 5471 I40E_VIRTCHNL_VF_OFFLOAD_L2; 5472 hw->dev_caps.fcoe = (msg->vf_offload_flags & 5473 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; 5474 hw->dev_caps.iwarp = (msg->vf_offload_flags & 5475 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 5476 for (i = 0; i < msg->num_vsis; i++) { 5477 if (vsi_res->vsi_type == I40E_VSI_SRIOV) { 5478 i40e_memcpy(hw->mac.perm_addr, 5479 vsi_res->default_mac_addr, 5480 I40E_ETH_LENGTH_OF_ADDRESS, 5481 I40E_NONDMA_TO_NONDMA); 5482 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 5483 I40E_ETH_LENGTH_OF_ADDRESS, 5484 I40E_NONDMA_TO_NONDMA); 5485 } 5486 vsi_res++; 5487 } 5488 } 5489 5490 /** 5491 * i40e_vf_reset 5492 * @hw: pointer to the hardware structure 5493 * 5494 * Send a VF_RESET message to the PF. Does not wait for response from PF 5495 * as none will be forthcoming. Immediately after calling this function, 5496 * the admin queue should be shut down and (optionally) reinitialized. 5497 **/ 5498 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 5499 { 5500 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, 5501 I40E_SUCCESS, NULL, 0, NULL); 5502 } 5503