1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_ADMINQ_CMD_H_ 36 #define _I40E_ADMINQ_CMD_H_ 37 38 /* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 #define I40E_FW_API_VERSION_MAJOR 0x0001 45 #define I40E_FW_API_VERSION_MINOR 0x0005 46 47 struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69 }; 70 71 /* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76 /* command flags and offsets*/ 77 #define I40E_AQ_FLAG_DD_SHIFT 0 78 #define I40E_AQ_FLAG_CMP_SHIFT 1 79 #define I40E_AQ_FLAG_ERR_SHIFT 2 80 #define I40E_AQ_FLAG_VFE_SHIFT 3 81 #define I40E_AQ_FLAG_LB_SHIFT 9 82 #define I40E_AQ_FLAG_RD_SHIFT 10 83 #define I40E_AQ_FLAG_VFC_SHIFT 11 84 #define I40E_AQ_FLAG_BUF_SHIFT 12 85 #define I40E_AQ_FLAG_SI_SHIFT 13 86 #define I40E_AQ_FLAG_EI_SHIFT 14 87 #define I40E_AQ_FLAG_FE_SHIFT 15 88 89 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101 /* error codes */ 102 enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126 }; 127 128 /* Admin Queue command opcodes */ 129 enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* Proxy commands */ 144 i40e_aqc_opc_set_proxy_config = 0x0104, 145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146 147 /* LAA */ 148 i40e_aqc_opc_mac_address_read = 0x0107, 149 i40e_aqc_opc_mac_address_write = 0x0108, 150 151 /* PXE */ 152 i40e_aqc_opc_clear_pxe_mode = 0x0110, 153 154 /* WoL commands */ 155 i40e_aqc_opc_set_wol_filter = 0x0120, 156 i40e_aqc_opc_get_wake_reason = 0x0121, 157 i40e_aqc_opc_clear_all_wol_filters = 0x025E, 158 159 /* internal switch commands */ 160 i40e_aqc_opc_get_switch_config = 0x0200, 161 i40e_aqc_opc_add_statistics = 0x0201, 162 i40e_aqc_opc_remove_statistics = 0x0202, 163 i40e_aqc_opc_set_port_parameters = 0x0203, 164 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 165 i40e_aqc_opc_set_switch_config = 0x0205, 166 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 167 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 168 169 i40e_aqc_opc_add_vsi = 0x0210, 170 i40e_aqc_opc_update_vsi_parameters = 0x0211, 171 i40e_aqc_opc_get_vsi_parameters = 0x0212, 172 173 i40e_aqc_opc_add_pv = 0x0220, 174 i40e_aqc_opc_update_pv_parameters = 0x0221, 175 i40e_aqc_opc_get_pv_parameters = 0x0222, 176 177 i40e_aqc_opc_add_veb = 0x0230, 178 i40e_aqc_opc_update_veb_parameters = 0x0231, 179 i40e_aqc_opc_get_veb_parameters = 0x0232, 180 181 i40e_aqc_opc_delete_element = 0x0243, 182 183 i40e_aqc_opc_add_macvlan = 0x0250, 184 i40e_aqc_opc_remove_macvlan = 0x0251, 185 i40e_aqc_opc_add_vlan = 0x0252, 186 i40e_aqc_opc_remove_vlan = 0x0253, 187 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 188 i40e_aqc_opc_add_tag = 0x0255, 189 i40e_aqc_opc_remove_tag = 0x0256, 190 i40e_aqc_opc_add_multicast_etag = 0x0257, 191 i40e_aqc_opc_remove_multicast_etag = 0x0258, 192 i40e_aqc_opc_update_tag = 0x0259, 193 i40e_aqc_opc_add_control_packet_filter = 0x025A, 194 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 195 i40e_aqc_opc_add_cloud_filters = 0x025C, 196 i40e_aqc_opc_remove_cloud_filters = 0x025D, 197 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 198 199 i40e_aqc_opc_add_mirror_rule = 0x0260, 200 i40e_aqc_opc_delete_mirror_rule = 0x0261, 201 202 /* DCB commands */ 203 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 204 i40e_aqc_opc_dcb_updated = 0x0302, 205 206 /* TX scheduler */ 207 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 208 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 209 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 210 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 211 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 212 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 213 214 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 215 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 216 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 217 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 218 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 219 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 220 i40e_aqc_opc_query_port_ets_config = 0x0419, 221 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 222 i40e_aqc_opc_suspend_port_tx = 0x041B, 223 i40e_aqc_opc_resume_port_tx = 0x041C, 224 i40e_aqc_opc_configure_partition_bw = 0x041D, 225 /* hmc */ 226 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 227 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 228 229 /* phy commands*/ 230 i40e_aqc_opc_get_phy_abilities = 0x0600, 231 i40e_aqc_opc_set_phy_config = 0x0601, 232 i40e_aqc_opc_set_mac_config = 0x0603, 233 i40e_aqc_opc_set_link_restart_an = 0x0605, 234 i40e_aqc_opc_get_link_status = 0x0607, 235 i40e_aqc_opc_set_phy_int_mask = 0x0613, 236 i40e_aqc_opc_get_local_advt_reg = 0x0614, 237 i40e_aqc_opc_set_local_advt_reg = 0x0615, 238 i40e_aqc_opc_get_partner_advt = 0x0616, 239 i40e_aqc_opc_set_lb_modes = 0x0618, 240 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 241 i40e_aqc_opc_set_phy_debug = 0x0622, 242 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 243 i40e_aqc_opc_run_phy_activity = 0x0626, 244 245 /* NVM commands */ 246 i40e_aqc_opc_nvm_read = 0x0701, 247 i40e_aqc_opc_nvm_erase = 0x0702, 248 i40e_aqc_opc_nvm_update = 0x0703, 249 i40e_aqc_opc_nvm_config_read = 0x0704, 250 i40e_aqc_opc_nvm_config_write = 0x0705, 251 i40e_aqc_opc_oem_post_update = 0x0720, 252 i40e_aqc_opc_thermal_sensor = 0x0721, 253 254 /* virtualization commands */ 255 i40e_aqc_opc_send_msg_to_pf = 0x0801, 256 i40e_aqc_opc_send_msg_to_vf = 0x0802, 257 i40e_aqc_opc_send_msg_to_peer = 0x0803, 258 259 /* alternate structure */ 260 i40e_aqc_opc_alternate_write = 0x0900, 261 i40e_aqc_opc_alternate_write_indirect = 0x0901, 262 i40e_aqc_opc_alternate_read = 0x0902, 263 i40e_aqc_opc_alternate_read_indirect = 0x0903, 264 i40e_aqc_opc_alternate_write_done = 0x0904, 265 i40e_aqc_opc_alternate_set_mode = 0x0905, 266 i40e_aqc_opc_alternate_clear_port = 0x0906, 267 268 /* LLDP commands */ 269 i40e_aqc_opc_lldp_get_mib = 0x0A00, 270 i40e_aqc_opc_lldp_update_mib = 0x0A01, 271 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 272 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 273 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 274 i40e_aqc_opc_lldp_stop = 0x0A05, 275 i40e_aqc_opc_lldp_start = 0x0A06, 276 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 277 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 278 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 279 280 /* Tunnel commands */ 281 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 282 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 283 i40e_aqc_opc_set_rss_key = 0x0B02, 284 i40e_aqc_opc_set_rss_lut = 0x0B03, 285 i40e_aqc_opc_get_rss_key = 0x0B04, 286 i40e_aqc_opc_get_rss_lut = 0x0B05, 287 288 /* Async Events */ 289 i40e_aqc_opc_event_lan_overflow = 0x1001, 290 291 /* OEM commands */ 292 i40e_aqc_opc_oem_parameter_change = 0xFE00, 293 i40e_aqc_opc_oem_device_status_change = 0xFE01, 294 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 295 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 296 297 /* debug commands */ 298 i40e_aqc_opc_debug_read_reg = 0xFF03, 299 i40e_aqc_opc_debug_write_reg = 0xFF04, 300 i40e_aqc_opc_debug_modify_reg = 0xFF07, 301 i40e_aqc_opc_debug_dump_internals = 0xFF08, 302 }; 303 304 /* command structures and indirect data structures */ 305 306 /* Structure naming conventions: 307 * - no suffix for direct command descriptor structures 308 * - _data for indirect sent data 309 * - _resp for indirect return data (data which is both will use _data) 310 * - _completion for direct return data 311 * - _element_ for repeated elements (may also be _data or _resp) 312 * 313 * Command structures are expected to overlay the params.raw member of the basic 314 * descriptor, and as such cannot exceed 16 bytes in length. 315 */ 316 317 /* This macro is used to generate a compilation error if a structure 318 * is not exactly the correct length. It gives a divide by zero error if the 319 * structure is not of the correct size, otherwise it creates an enum that is 320 * never used. 321 */ 322 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 323 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 324 325 /* This macro is used extensively to ensure that command structures are 16 326 * bytes in length as they have to map to the raw array of that size. 327 */ 328 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 329 330 /* internal (0x00XX) commands */ 331 332 /* Get version (direct 0x0001) */ 333 struct i40e_aqc_get_version { 334 __le32 rom_ver; 335 __le32 fw_build; 336 __le16 fw_major; 337 __le16 fw_minor; 338 __le16 api_major; 339 __le16 api_minor; 340 }; 341 342 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 343 344 /* Send driver version (indirect 0x0002) */ 345 struct i40e_aqc_driver_version { 346 u8 driver_major_ver; 347 u8 driver_minor_ver; 348 u8 driver_build_ver; 349 u8 driver_subbuild_ver; 350 u8 reserved[4]; 351 __le32 address_high; 352 __le32 address_low; 353 }; 354 355 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 356 357 /* Queue Shutdown (direct 0x0003) */ 358 struct i40e_aqc_queue_shutdown { 359 __le32 driver_unloading; 360 #define I40E_AQ_DRIVER_UNLOADING 0x1 361 u8 reserved[12]; 362 }; 363 364 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 365 366 /* Set PF context (0x0004, direct) */ 367 struct i40e_aqc_set_pf_context { 368 u8 pf_id; 369 u8 reserved[15]; 370 }; 371 372 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 373 374 /* Request resource ownership (direct 0x0008) 375 * Release resource ownership (direct 0x0009) 376 */ 377 #define I40E_AQ_RESOURCE_NVM 1 378 #define I40E_AQ_RESOURCE_SDP 2 379 #define I40E_AQ_RESOURCE_ACCESS_READ 1 380 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 381 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 382 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 383 384 struct i40e_aqc_request_resource { 385 __le16 resource_id; 386 __le16 access_type; 387 __le32 timeout; 388 __le32 resource_number; 389 u8 reserved[4]; 390 }; 391 392 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 393 394 /* Get function capabilities (indirect 0x000A) 395 * Get device capabilities (indirect 0x000B) 396 */ 397 struct i40e_aqc_list_capabilites { 398 u8 command_flags; 399 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 400 u8 pf_index; 401 u8 reserved[2]; 402 __le32 count; 403 __le32 addr_high; 404 __le32 addr_low; 405 }; 406 407 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 408 409 struct i40e_aqc_list_capabilities_element_resp { 410 __le16 id; 411 u8 major_rev; 412 u8 minor_rev; 413 __le32 number; 414 __le32 logical_id; 415 __le32 phys_id; 416 u8 reserved[16]; 417 }; 418 419 /* list of caps */ 420 421 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 422 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 423 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 424 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 425 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 426 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 427 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 428 #define I40E_AQ_CAP_ID_SRIOV 0x0012 429 #define I40E_AQ_CAP_ID_VF 0x0013 430 #define I40E_AQ_CAP_ID_VMDQ 0x0014 431 #define I40E_AQ_CAP_ID_8021QBG 0x0015 432 #define I40E_AQ_CAP_ID_8021QBR 0x0016 433 #define I40E_AQ_CAP_ID_VSI 0x0017 434 #define I40E_AQ_CAP_ID_DCB 0x0018 435 #define I40E_AQ_CAP_ID_FCOE 0x0021 436 #define I40E_AQ_CAP_ID_ISCSI 0x0022 437 #define I40E_AQ_CAP_ID_RSS 0x0040 438 #define I40E_AQ_CAP_ID_RXQ 0x0041 439 #define I40E_AQ_CAP_ID_TXQ 0x0042 440 #define I40E_AQ_CAP_ID_MSIX 0x0043 441 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 442 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 443 #define I40E_AQ_CAP_ID_1588 0x0046 444 #define I40E_AQ_CAP_ID_IWARP 0x0051 445 #define I40E_AQ_CAP_ID_LED 0x0061 446 #define I40E_AQ_CAP_ID_SDP 0x0062 447 #define I40E_AQ_CAP_ID_MDIO 0x0063 448 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 449 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 450 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 451 #define I40E_AQ_CAP_ID_CEM 0x00F2 452 453 /* Set CPPM Configuration (direct 0x0103) */ 454 struct i40e_aqc_cppm_configuration { 455 __le16 command_flags; 456 #define I40E_AQ_CPPM_EN_LTRC 0x0800 457 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 458 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 459 #define I40E_AQ_CPPM_EN_HPTC 0x4000 460 #define I40E_AQ_CPPM_EN_DMARC 0x8000 461 __le16 ttlx; 462 __le32 dmacr; 463 __le16 dmcth; 464 u8 hptc; 465 u8 reserved; 466 __le32 pfltrc; 467 }; 468 469 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 470 471 /* Set ARP Proxy command / response (indirect 0x0104) */ 472 struct i40e_aqc_arp_proxy_data { 473 __le16 command_flags; 474 #define I40E_AQ_ARP_INIT_IPV4 0x0800 475 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 476 #define I40E_AQ_ARP_ENA 0x2000 477 #define I40E_AQ_ARP_ADD_IPV4 0x4000 478 #define I40E_AQ_ARP_DEL_IPV4 0x8000 479 __le16 table_id; 480 __le32 enabled_offloads; 481 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 482 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 483 __le32 ip_addr; 484 u8 mac_addr[6]; 485 u8 reserved[2]; 486 }; 487 488 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 489 490 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 491 struct i40e_aqc_ns_proxy_data { 492 __le16 table_idx_mac_addr_0; 493 __le16 table_idx_mac_addr_1; 494 __le16 table_idx_ipv6_0; 495 __le16 table_idx_ipv6_1; 496 __le16 control; 497 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 498 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 499 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 500 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 501 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 502 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 503 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 504 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 505 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 506 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 507 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 508 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 509 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 510 u8 mac_addr_0[6]; 511 u8 mac_addr_1[6]; 512 u8 local_mac_addr[6]; 513 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 514 u8 ipv6_addr_1[16]; 515 }; 516 517 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 518 519 /* Manage LAA Command (0x0106) - obsolete */ 520 struct i40e_aqc_mng_laa { 521 __le16 command_flags; 522 #define I40E_AQ_LAA_FLAG_WR 0x8000 523 u8 reserved[2]; 524 __le32 sal; 525 __le16 sah; 526 u8 reserved2[6]; 527 }; 528 529 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 530 531 /* Manage MAC Address Read Command (indirect 0x0107) */ 532 struct i40e_aqc_mac_address_read { 533 __le16 command_flags; 534 #define I40E_AQC_LAN_ADDR_VALID 0x10 535 #define I40E_AQC_SAN_ADDR_VALID 0x20 536 #define I40E_AQC_PORT_ADDR_VALID 0x40 537 #define I40E_AQC_WOL_ADDR_VALID 0x80 538 #define I40E_AQC_MC_MAG_EN_VALID 0x100 539 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 540 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 541 u8 reserved[6]; 542 __le32 addr_high; 543 __le32 addr_low; 544 }; 545 546 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 547 548 struct i40e_aqc_mac_address_read_data { 549 u8 pf_lan_mac[6]; 550 u8 pf_san_mac[6]; 551 u8 port_mac[6]; 552 u8 pf_wol_mac[6]; 553 }; 554 555 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 556 557 /* Manage MAC Address Write Command (0x0108) */ 558 struct i40e_aqc_mac_address_write { 559 __le16 command_flags; 560 #define I40E_AQC_MC_MAG_EN 0x0100 561 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 562 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 563 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 564 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 565 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 566 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 567 568 __le16 mac_sah; 569 __le32 mac_sal; 570 u8 reserved[8]; 571 }; 572 573 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 574 575 /* PXE commands (0x011x) */ 576 577 /* Clear PXE Command and response (direct 0x0110) */ 578 struct i40e_aqc_clear_pxe { 579 u8 rx_cnt; 580 u8 reserved[15]; 581 }; 582 583 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 584 585 /* Set WoL Filter (0x0120) */ 586 587 struct i40e_aqc_set_wol_filter { 588 __le16 filter_index; 589 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 590 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 591 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 592 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 593 594 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 595 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 596 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 597 __le16 cmd_flags; 598 #define I40E_AQC_SET_WOL_FILTER 0x8000 599 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 600 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 601 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 602 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 603 __le16 valid_flags; 604 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 605 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 606 u8 reserved[2]; 607 __le32 address_high; 608 __le32 address_low; 609 }; 610 611 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 612 613 struct i40e_aqc_set_wol_filter_data { 614 u8 filter[128]; 615 u8 mask[16]; 616 }; 617 618 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 619 620 /* Get Wake Reason (0x0121) */ 621 622 struct i40e_aqc_get_wake_reason_completion { 623 u8 reserved_1[2]; 624 __le16 wake_reason; 625 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 626 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 627 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 628 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 630 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 631 u8 reserved_2[12]; 632 }; 633 634 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 635 636 /* Switch configuration commands (0x02xx) */ 637 638 /* Used by many indirect commands that only pass an seid and a buffer in the 639 * command 640 */ 641 struct i40e_aqc_switch_seid { 642 __le16 seid; 643 u8 reserved[6]; 644 __le32 addr_high; 645 __le32 addr_low; 646 }; 647 648 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 649 650 /* Get Switch Configuration command (indirect 0x0200) 651 * uses i40e_aqc_switch_seid for the descriptor 652 */ 653 struct i40e_aqc_get_switch_config_header_resp { 654 __le16 num_reported; 655 __le16 num_total; 656 u8 reserved[12]; 657 }; 658 659 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 660 661 struct i40e_aqc_switch_config_element_resp { 662 u8 element_type; 663 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 664 #define I40E_AQ_SW_ELEM_TYPE_PF 2 665 #define I40E_AQ_SW_ELEM_TYPE_VF 3 666 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 667 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 668 #define I40E_AQ_SW_ELEM_TYPE_PV 16 669 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 670 #define I40E_AQ_SW_ELEM_TYPE_PA 18 671 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 672 u8 revision; 673 #define I40E_AQ_SW_ELEM_REV_1 1 674 __le16 seid; 675 __le16 uplink_seid; 676 __le16 downlink_seid; 677 u8 reserved[3]; 678 u8 connection_type; 679 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 680 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 681 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 682 __le16 scheduler_id; 683 __le16 element_info; 684 }; 685 686 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 687 688 /* Get Switch Configuration (indirect 0x0200) 689 * an array of elements are returned in the response buffer 690 * the first in the array is the header, remainder are elements 691 */ 692 struct i40e_aqc_get_switch_config_resp { 693 struct i40e_aqc_get_switch_config_header_resp header; 694 struct i40e_aqc_switch_config_element_resp element[1]; 695 }; 696 697 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 698 699 /* Add Statistics (direct 0x0201) 700 * Remove Statistics (direct 0x0202) 701 */ 702 struct i40e_aqc_add_remove_statistics { 703 __le16 seid; 704 __le16 vlan; 705 __le16 stat_index; 706 u8 reserved[10]; 707 }; 708 709 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 710 711 /* Set Port Parameters command (direct 0x0203) */ 712 struct i40e_aqc_set_port_parameters { 713 __le16 command_flags; 714 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 715 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 716 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 717 __le16 bad_frame_vsi; 718 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 719 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 720 __le16 default_seid; /* reserved for command */ 721 u8 reserved[10]; 722 }; 723 724 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 725 726 /* Get Switch Resource Allocation (indirect 0x0204) */ 727 struct i40e_aqc_get_switch_resource_alloc { 728 u8 num_entries; /* reserved for command */ 729 u8 reserved[7]; 730 __le32 addr_high; 731 __le32 addr_low; 732 }; 733 734 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 735 736 /* expect an array of these structs in the response buffer */ 737 struct i40e_aqc_switch_resource_alloc_element_resp { 738 u8 resource_type; 739 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 740 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 741 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 742 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 743 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 744 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 745 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 746 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 747 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 748 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 749 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 750 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 751 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 752 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 753 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 754 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 755 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 756 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 757 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 758 u8 reserved1; 759 __le16 guaranteed; 760 __le16 total; 761 __le16 used; 762 __le16 total_unalloced; 763 u8 reserved2[6]; 764 }; 765 766 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 767 768 /* Set Switch Configuration (direct 0x0205) */ 769 struct i40e_aqc_set_switch_config { 770 __le16 flags; 771 /* flags used for both fields below */ 772 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 773 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 774 __le16 valid_flags; 775 u8 reserved[12]; 776 }; 777 778 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 779 780 /* Read Receive control registers (direct 0x0206) 781 * Write Receive control registers (direct 0x0207) 782 * used for accessing Rx control registers that can be 783 * slow and need special handling when under high Rx load 784 */ 785 struct i40e_aqc_rx_ctl_reg_read_write { 786 __le32 reserved1; 787 __le32 address; 788 __le32 reserved2; 789 __le32 value; 790 }; 791 792 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 793 794 /* Add VSI (indirect 0x0210) 795 * this indirect command uses struct i40e_aqc_vsi_properties_data 796 * as the indirect buffer (128 bytes) 797 * 798 * Update VSI (indirect 0x211) 799 * uses the same data structure as Add VSI 800 * 801 * Get VSI (indirect 0x0212) 802 * uses the same completion and data structure as Add VSI 803 */ 804 struct i40e_aqc_add_get_update_vsi { 805 __le16 uplink_seid; 806 u8 connection_type; 807 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 808 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 809 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 810 u8 reserved1; 811 u8 vf_id; 812 u8 reserved2; 813 __le16 vsi_flags; 814 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 815 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 816 #define I40E_AQ_VSI_TYPE_VF 0x0 817 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 818 #define I40E_AQ_VSI_TYPE_PF 0x2 819 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 820 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 821 __le32 addr_high; 822 __le32 addr_low; 823 }; 824 825 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 826 827 struct i40e_aqc_add_get_update_vsi_completion { 828 __le16 seid; 829 __le16 vsi_number; 830 __le16 vsi_used; 831 __le16 vsi_free; 832 __le32 addr_high; 833 __le32 addr_low; 834 }; 835 836 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 837 838 struct i40e_aqc_vsi_properties_data { 839 /* first 96 byte are written by SW */ 840 __le16 valid_sections; 841 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 842 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 843 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 844 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 845 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 846 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 847 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 848 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 849 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 850 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 851 /* switch section */ 852 __le16 switch_id; /* 12bit id combined with flags below */ 853 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 854 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 855 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 856 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 857 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 858 u8 sw_reserved[2]; 859 /* security section */ 860 u8 sec_flags; 861 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 862 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 863 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 864 u8 sec_reserved; 865 /* VLAN section */ 866 __le16 pvid; /* VLANS include priority bits */ 867 __le16 fcoe_pvid; 868 u8 port_vlan_flags; 869 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 870 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 871 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 872 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 873 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 874 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 875 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 876 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 877 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 878 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 879 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 880 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 881 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 882 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 883 u8 pvlan_reserved[3]; 884 /* ingress egress up sections */ 885 __le32 ingress_table; /* bitmap, 3 bits per up */ 886 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 887 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 888 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 889 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 890 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 891 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 892 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 893 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 894 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 895 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 896 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 897 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 898 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 899 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 900 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 901 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 902 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 903 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 904 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 905 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 906 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 907 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 908 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 909 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 910 __le32 egress_table; /* same defines as for ingress table */ 911 /* cascaded PV section */ 912 __le16 cas_pv_tag; 913 u8 cas_pv_flags; 914 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 915 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 916 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 917 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 918 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 919 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 920 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 921 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 922 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 923 u8 cas_pv_reserved; 924 /* queue mapping section */ 925 __le16 mapping_flags; 926 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 927 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 928 __le16 queue_mapping[16]; 929 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 930 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 931 __le16 tc_mapping[8]; 932 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 933 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 934 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 935 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 936 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 937 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 938 /* queueing option section */ 939 u8 queueing_opt_flags; 940 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 941 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 942 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 943 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 944 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 945 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 946 u8 queueing_opt_reserved[3]; 947 /* scheduler section */ 948 u8 up_enable_bits; 949 u8 sched_reserved; 950 /* outer up section */ 951 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 952 u8 cmd_reserved[8]; 953 /* last 32 bytes are written by FW */ 954 __le16 qs_handle[8]; 955 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 956 __le16 stat_counter_idx; 957 __le16 sched_id; 958 u8 resp_reserved[12]; 959 }; 960 961 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 962 963 /* Add Port Virtualizer (direct 0x0220) 964 * also used for update PV (direct 0x0221) but only flags are used 965 * (IS_CTRL_PORT only works on add PV) 966 */ 967 struct i40e_aqc_add_update_pv { 968 __le16 command_flags; 969 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 970 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 971 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 972 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 973 __le16 uplink_seid; 974 __le16 connected_seid; 975 u8 reserved[10]; 976 }; 977 978 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 979 980 struct i40e_aqc_add_update_pv_completion { 981 /* reserved for update; for add also encodes error if rc == ENOSPC */ 982 __le16 pv_seid; 983 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 984 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 985 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 986 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 987 u8 reserved[14]; 988 }; 989 990 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 991 992 /* Get PV Params (direct 0x0222) 993 * uses i40e_aqc_switch_seid for the descriptor 994 */ 995 996 struct i40e_aqc_get_pv_params_completion { 997 __le16 seid; 998 __le16 default_stag; 999 __le16 pv_flags; /* same flags as add_pv */ 1000 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1001 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1002 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1003 u8 reserved[8]; 1004 __le16 default_port_seid; 1005 }; 1006 1007 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1008 1009 /* Add VEB (direct 0x0230) */ 1010 struct i40e_aqc_add_veb { 1011 __le16 uplink_seid; 1012 __le16 downlink_seid; 1013 __le16 veb_flags; 1014 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1015 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1016 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1017 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1018 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1019 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1020 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1021 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1022 u8 enable_tcs; 1023 u8 reserved[9]; 1024 }; 1025 1026 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1027 1028 struct i40e_aqc_add_veb_completion { 1029 u8 reserved[6]; 1030 __le16 switch_seid; 1031 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1032 __le16 veb_seid; 1033 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1034 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1035 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1036 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1037 __le16 statistic_index; 1038 __le16 vebs_used; 1039 __le16 vebs_free; 1040 }; 1041 1042 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1043 1044 /* Get VEB Parameters (direct 0x0232) 1045 * uses i40e_aqc_switch_seid for the descriptor 1046 */ 1047 struct i40e_aqc_get_veb_parameters_completion { 1048 __le16 seid; 1049 __le16 switch_id; 1050 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1051 __le16 statistic_index; 1052 __le16 vebs_used; 1053 __le16 vebs_free; 1054 u8 reserved[4]; 1055 }; 1056 1057 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1058 1059 /* Delete Element (direct 0x0243) 1060 * uses the generic i40e_aqc_switch_seid 1061 */ 1062 1063 /* Add MAC-VLAN (indirect 0x0250) */ 1064 1065 /* used for the command for most vlan commands */ 1066 struct i40e_aqc_macvlan { 1067 __le16 num_addresses; 1068 __le16 seid[3]; 1069 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1070 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1071 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1072 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1073 __le32 addr_high; 1074 __le32 addr_low; 1075 }; 1076 1077 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1078 1079 /* indirect data for command and response */ 1080 struct i40e_aqc_add_macvlan_element_data { 1081 u8 mac_addr[6]; 1082 __le16 vlan_tag; 1083 __le16 flags; 1084 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1085 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1086 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1087 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1088 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1089 __le16 queue_number; 1090 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1091 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1092 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1093 /* response section */ 1094 u8 match_method; 1095 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1096 #define I40E_AQC_MM_HASH_MATCH 0x02 1097 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1098 u8 reserved1[3]; 1099 }; 1100 1101 struct i40e_aqc_add_remove_macvlan_completion { 1102 __le16 perfect_mac_used; 1103 __le16 perfect_mac_free; 1104 __le16 unicast_hash_free; 1105 __le16 multicast_hash_free; 1106 __le32 addr_high; 1107 __le32 addr_low; 1108 }; 1109 1110 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1111 1112 /* Remove MAC-VLAN (indirect 0x0251) 1113 * uses i40e_aqc_macvlan for the descriptor 1114 * data points to an array of num_addresses of elements 1115 */ 1116 1117 struct i40e_aqc_remove_macvlan_element_data { 1118 u8 mac_addr[6]; 1119 __le16 vlan_tag; 1120 u8 flags; 1121 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1122 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1123 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1124 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1125 u8 reserved[3]; 1126 /* reply section */ 1127 u8 error_code; 1128 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1129 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1130 u8 reply_reserved[3]; 1131 }; 1132 1133 /* Add VLAN (indirect 0x0252) 1134 * Remove VLAN (indirect 0x0253) 1135 * use the generic i40e_aqc_macvlan for the command 1136 */ 1137 struct i40e_aqc_add_remove_vlan_element_data { 1138 __le16 vlan_tag; 1139 u8 vlan_flags; 1140 /* flags for add VLAN */ 1141 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1142 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1143 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1144 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1145 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1146 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1147 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1148 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1149 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1150 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1151 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1152 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1153 /* flags for remove VLAN */ 1154 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1155 u8 reserved; 1156 u8 result; 1157 /* flags for add VLAN */ 1158 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1159 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1160 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1161 /* flags for remove VLAN */ 1162 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1163 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1164 u8 reserved1[3]; 1165 }; 1166 1167 struct i40e_aqc_add_remove_vlan_completion { 1168 u8 reserved[4]; 1169 __le16 vlans_used; 1170 __le16 vlans_free; 1171 __le32 addr_high; 1172 __le32 addr_low; 1173 }; 1174 1175 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1176 struct i40e_aqc_set_vsi_promiscuous_modes { 1177 __le16 promiscuous_flags; 1178 __le16 valid_flags; 1179 /* flags used for both fields above */ 1180 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1181 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1182 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1183 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1184 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1185 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1186 __le16 seid; 1187 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1188 __le16 vlan_tag; 1189 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1190 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1191 u8 reserved[8]; 1192 }; 1193 1194 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1195 1196 /* Add S/E-tag command (direct 0x0255) 1197 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1198 */ 1199 struct i40e_aqc_add_tag { 1200 __le16 flags; 1201 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1202 __le16 seid; 1203 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1204 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1205 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1206 __le16 tag; 1207 __le16 queue_number; 1208 u8 reserved[8]; 1209 }; 1210 1211 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1212 1213 struct i40e_aqc_add_remove_tag_completion { 1214 u8 reserved[12]; 1215 __le16 tags_used; 1216 __le16 tags_free; 1217 }; 1218 1219 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1220 1221 /* Remove S/E-tag command (direct 0x0256) 1222 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1223 */ 1224 struct i40e_aqc_remove_tag { 1225 __le16 seid; 1226 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1227 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1228 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1229 __le16 tag; 1230 u8 reserved[12]; 1231 }; 1232 1233 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1234 1235 /* Add multicast E-Tag (direct 0x0257) 1236 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1237 * and no external data 1238 */ 1239 struct i40e_aqc_add_remove_mcast_etag { 1240 __le16 pv_seid; 1241 __le16 etag; 1242 u8 num_unicast_etags; 1243 u8 reserved[3]; 1244 __le32 addr_high; /* address of array of 2-byte s-tags */ 1245 __le32 addr_low; 1246 }; 1247 1248 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1249 1250 struct i40e_aqc_add_remove_mcast_etag_completion { 1251 u8 reserved[4]; 1252 __le16 mcast_etags_used; 1253 __le16 mcast_etags_free; 1254 __le32 addr_high; 1255 __le32 addr_low; 1256 1257 }; 1258 1259 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1260 1261 /* Update S/E-Tag (direct 0x0259) */ 1262 struct i40e_aqc_update_tag { 1263 __le16 seid; 1264 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1265 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1266 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1267 __le16 old_tag; 1268 __le16 new_tag; 1269 u8 reserved[10]; 1270 }; 1271 1272 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1273 1274 struct i40e_aqc_update_tag_completion { 1275 u8 reserved[12]; 1276 __le16 tags_used; 1277 __le16 tags_free; 1278 }; 1279 1280 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1281 1282 /* Add Control Packet filter (direct 0x025A) 1283 * Remove Control Packet filter (direct 0x025B) 1284 * uses the i40e_aqc_add_oveb_cloud, 1285 * and the generic direct completion structure 1286 */ 1287 struct i40e_aqc_add_remove_control_packet_filter { 1288 u8 mac[6]; 1289 __le16 etype; 1290 __le16 flags; 1291 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1292 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1293 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1294 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1295 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1296 __le16 seid; 1297 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1298 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1299 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1300 __le16 queue; 1301 u8 reserved[2]; 1302 }; 1303 1304 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1305 1306 struct i40e_aqc_add_remove_control_packet_filter_completion { 1307 __le16 mac_etype_used; 1308 __le16 etype_used; 1309 __le16 mac_etype_free; 1310 __le16 etype_free; 1311 u8 reserved[8]; 1312 }; 1313 1314 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1315 1316 /* Add Cloud filters (indirect 0x025C) 1317 * Remove Cloud filters (indirect 0x025D) 1318 * uses the i40e_aqc_add_remove_cloud_filters, 1319 * and the generic indirect completion structure 1320 */ 1321 struct i40e_aqc_add_remove_cloud_filters { 1322 u8 num_filters; 1323 u8 reserved; 1324 __le16 seid; 1325 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1326 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1327 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1328 u8 reserved2[4]; 1329 __le32 addr_high; 1330 __le32 addr_low; 1331 }; 1332 1333 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1334 1335 struct i40e_aqc_add_remove_cloud_filters_element_data { 1336 u8 outer_mac[6]; 1337 u8 inner_mac[6]; 1338 __le16 inner_vlan; 1339 union { 1340 struct { 1341 u8 reserved[12]; 1342 u8 data[4]; 1343 } v4; 1344 struct { 1345 u8 data[16]; 1346 } v6; 1347 } ipaddr; 1348 __le16 flags; 1349 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1350 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1351 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1352 /* 0x0000 reserved */ 1353 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1354 /* 0x0002 reserved */ 1355 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1356 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1357 /* 0x0005 reserved */ 1358 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1359 /* 0x0007 reserved */ 1360 /* 0x0008 reserved */ 1361 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1362 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1363 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1364 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1365 1366 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1367 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1368 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1369 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1370 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1371 1372 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1373 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1374 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1375 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1376 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1377 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1378 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1379 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1380 1381 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1382 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1383 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1384 1385 __le32 tenant_id; 1386 u8 reserved[4]; 1387 __le16 queue_number; 1388 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1389 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1390 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1391 u8 reserved2[14]; 1392 /* response section */ 1393 u8 allocation_result; 1394 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1395 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1396 u8 response_reserved[7]; 1397 }; 1398 1399 struct i40e_aqc_remove_cloud_filters_completion { 1400 __le16 perfect_ovlan_used; 1401 __le16 perfect_ovlan_free; 1402 __le16 vlan_used; 1403 __le16 vlan_free; 1404 __le32 addr_high; 1405 __le32 addr_low; 1406 }; 1407 1408 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1409 1410 /* Add Mirror Rule (indirect or direct 0x0260) 1411 * Delete Mirror Rule (indirect or direct 0x0261) 1412 * note: some rule types (4,5) do not use an external buffer. 1413 * take care to set the flags correctly. 1414 */ 1415 struct i40e_aqc_add_delete_mirror_rule { 1416 __le16 seid; 1417 __le16 rule_type; 1418 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1419 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1420 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1421 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1422 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1423 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1424 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1425 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1426 __le16 num_entries; 1427 __le16 destination; /* VSI for add, rule id for delete */ 1428 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1429 __le32 addr_low; 1430 }; 1431 1432 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1433 1434 struct i40e_aqc_add_delete_mirror_rule_completion { 1435 u8 reserved[2]; 1436 __le16 rule_id; /* only used on add */ 1437 __le16 mirror_rules_used; 1438 __le16 mirror_rules_free; 1439 __le32 addr_high; 1440 __le32 addr_low; 1441 }; 1442 1443 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1444 1445 /* DCB 0x03xx*/ 1446 1447 /* PFC Ignore (direct 0x0301) 1448 * the command and response use the same descriptor structure 1449 */ 1450 struct i40e_aqc_pfc_ignore { 1451 u8 tc_bitmap; 1452 u8 command_flags; /* unused on response */ 1453 #define I40E_AQC_PFC_IGNORE_SET 0x80 1454 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1455 u8 reserved[14]; 1456 }; 1457 1458 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1459 1460 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1461 * with no parameters 1462 */ 1463 1464 /* TX scheduler 0x04xx */ 1465 1466 /* Almost all the indirect commands use 1467 * this generic struct to pass the SEID in param0 1468 */ 1469 struct i40e_aqc_tx_sched_ind { 1470 __le16 vsi_seid; 1471 u8 reserved[6]; 1472 __le32 addr_high; 1473 __le32 addr_low; 1474 }; 1475 1476 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1477 1478 /* Several commands respond with a set of queue set handles */ 1479 struct i40e_aqc_qs_handles_resp { 1480 __le16 qs_handles[8]; 1481 }; 1482 1483 /* Configure VSI BW limits (direct 0x0400) */ 1484 struct i40e_aqc_configure_vsi_bw_limit { 1485 __le16 vsi_seid; 1486 u8 reserved[2]; 1487 __le16 credit; 1488 u8 reserved1[2]; 1489 u8 max_credit; /* 0-3, limit = 2^max */ 1490 u8 reserved2[7]; 1491 }; 1492 1493 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1494 1495 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1496 * responds with i40e_aqc_qs_handles_resp 1497 */ 1498 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1499 u8 tc_valid_bits; 1500 u8 reserved[15]; 1501 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1502 1503 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1504 __le16 tc_bw_max[2]; 1505 u8 reserved1[28]; 1506 }; 1507 1508 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1509 1510 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1511 * responds with i40e_aqc_qs_handles_resp 1512 */ 1513 struct i40e_aqc_configure_vsi_tc_bw_data { 1514 u8 tc_valid_bits; 1515 u8 reserved[3]; 1516 u8 tc_bw_credits[8]; 1517 u8 reserved1[4]; 1518 __le16 qs_handles[8]; 1519 }; 1520 1521 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1522 1523 /* Query vsi bw configuration (indirect 0x0408) */ 1524 struct i40e_aqc_query_vsi_bw_config_resp { 1525 u8 tc_valid_bits; 1526 u8 tc_suspended_bits; 1527 u8 reserved[14]; 1528 __le16 qs_handles[8]; 1529 u8 reserved1[4]; 1530 __le16 port_bw_limit; 1531 u8 reserved2[2]; 1532 u8 max_bw; /* 0-3, limit = 2^max */ 1533 u8 reserved3[23]; 1534 }; 1535 1536 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1537 1538 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1539 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1540 u8 tc_valid_bits; 1541 u8 reserved[3]; 1542 u8 share_credits[8]; 1543 __le16 credits[8]; 1544 1545 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1546 __le16 tc_bw_max[2]; 1547 }; 1548 1549 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1550 1551 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1552 struct i40e_aqc_configure_switching_comp_bw_limit { 1553 __le16 seid; 1554 u8 reserved[2]; 1555 __le16 credit; 1556 u8 reserved1[2]; 1557 u8 max_bw; /* 0-3, limit = 2^max */ 1558 u8 reserved2[7]; 1559 }; 1560 1561 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1562 1563 /* Enable Physical Port ETS (indirect 0x0413) 1564 * Modify Physical Port ETS (indirect 0x0414) 1565 * Disable Physical Port ETS (indirect 0x0415) 1566 */ 1567 struct i40e_aqc_configure_switching_comp_ets_data { 1568 u8 reserved[4]; 1569 u8 tc_valid_bits; 1570 u8 seepage; 1571 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1572 u8 tc_strict_priority_flags; 1573 u8 reserved1[17]; 1574 u8 tc_bw_share_credits[8]; 1575 u8 reserved2[96]; 1576 }; 1577 1578 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1579 1580 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1581 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1582 u8 tc_valid_bits; 1583 u8 reserved[15]; 1584 __le16 tc_bw_credit[8]; 1585 1586 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1587 __le16 tc_bw_max[2]; 1588 u8 reserved1[28]; 1589 }; 1590 1591 I40E_CHECK_STRUCT_LEN(0x40, 1592 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1593 1594 /* Configure Switching Component Bandwidth Allocation per Tc 1595 * (indirect 0x0417) 1596 */ 1597 struct i40e_aqc_configure_switching_comp_bw_config_data { 1598 u8 tc_valid_bits; 1599 u8 reserved[2]; 1600 u8 absolute_credits; /* bool */ 1601 u8 tc_bw_share_credits[8]; 1602 u8 reserved1[20]; 1603 }; 1604 1605 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1606 1607 /* Query Switching Component Configuration (indirect 0x0418) */ 1608 struct i40e_aqc_query_switching_comp_ets_config_resp { 1609 u8 tc_valid_bits; 1610 u8 reserved[35]; 1611 __le16 port_bw_limit; 1612 u8 reserved1[2]; 1613 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1614 u8 reserved2[23]; 1615 }; 1616 1617 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1618 1619 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1620 struct i40e_aqc_query_port_ets_config_resp { 1621 u8 reserved[4]; 1622 u8 tc_valid_bits; 1623 u8 reserved1; 1624 u8 tc_strict_priority_bits; 1625 u8 reserved2; 1626 u8 tc_bw_share_credits[8]; 1627 __le16 tc_bw_limits[8]; 1628 1629 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1630 __le16 tc_bw_max[2]; 1631 u8 reserved3[32]; 1632 }; 1633 1634 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1635 1636 /* Query Switching Component Bandwidth Allocation per Traffic Type 1637 * (indirect 0x041A) 1638 */ 1639 struct i40e_aqc_query_switching_comp_bw_config_resp { 1640 u8 tc_valid_bits; 1641 u8 reserved[2]; 1642 u8 absolute_credits_enable; /* bool */ 1643 u8 tc_bw_share_credits[8]; 1644 __le16 tc_bw_limits[8]; 1645 1646 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1647 __le16 tc_bw_max[2]; 1648 }; 1649 1650 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1651 1652 /* Suspend/resume port TX traffic 1653 * (direct 0x041B and 0x041C) uses the generic SEID struct 1654 */ 1655 1656 /* Configure partition BW 1657 * (indirect 0x041D) 1658 */ 1659 struct i40e_aqc_configure_partition_bw_data { 1660 __le16 pf_valid_bits; 1661 u8 min_bw[16]; /* guaranteed bandwidth */ 1662 u8 max_bw[16]; /* bandwidth limit */ 1663 }; 1664 1665 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1666 1667 /* Get and set the active HMC resource profile and status. 1668 * (direct 0x0500) and (direct 0x0501) 1669 */ 1670 struct i40e_aq_get_set_hmc_resource_profile { 1671 u8 pm_profile; 1672 u8 pe_vf_enabled; 1673 u8 reserved[14]; 1674 }; 1675 1676 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1677 1678 enum i40e_aq_hmc_profile { 1679 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1680 I40E_HMC_PROFILE_DEFAULT = 1, 1681 I40E_HMC_PROFILE_FAVOR_VF = 2, 1682 I40E_HMC_PROFILE_EQUAL = 3, 1683 }; 1684 1685 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1686 1687 /* set in param0 for get phy abilities to report qualified modules */ 1688 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1689 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1690 1691 enum i40e_aq_phy_type { 1692 I40E_PHY_TYPE_SGMII = 0x0, 1693 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1694 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1695 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1696 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1697 I40E_PHY_TYPE_XAUI = 0x5, 1698 I40E_PHY_TYPE_XFI = 0x6, 1699 I40E_PHY_TYPE_SFI = 0x7, 1700 I40E_PHY_TYPE_XLAUI = 0x8, 1701 I40E_PHY_TYPE_XLPPI = 0x9, 1702 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1703 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1704 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1705 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1706 I40E_PHY_TYPE_100BASE_TX = 0x11, 1707 I40E_PHY_TYPE_1000BASE_T = 0x12, 1708 I40E_PHY_TYPE_10GBASE_T = 0x13, 1709 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1710 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1711 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1712 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1713 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1714 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1715 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1716 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1717 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1718 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1719 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1720 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1721 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1722 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1723 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1724 I40E_PHY_TYPE_MAX 1725 }; 1726 1727 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1728 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1729 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1730 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1731 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1732 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1733 1734 enum i40e_aq_link_speed { 1735 I40E_LINK_SPEED_UNKNOWN = 0, 1736 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1737 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1738 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1739 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1740 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1741 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1742 }; 1743 1744 struct i40e_aqc_module_desc { 1745 u8 oui[3]; 1746 u8 reserved1; 1747 u8 part_number[16]; 1748 u8 revision[4]; 1749 u8 reserved2[8]; 1750 }; 1751 1752 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1753 1754 struct i40e_aq_get_phy_abilities_resp { 1755 __le32 phy_type; /* bitmap using the above enum for offsets */ 1756 u8 link_speed; /* bitmap using the above enum bit patterns */ 1757 u8 abilities; 1758 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1759 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1760 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1761 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1762 #define I40E_AQ_PHY_AN_ENABLED 0x10 1763 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1764 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1765 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1766 __le16 eee_capability; 1767 #define I40E_AQ_EEE_100BASE_TX 0x0002 1768 #define I40E_AQ_EEE_1000BASE_T 0x0004 1769 #define I40E_AQ_EEE_10GBASE_T 0x0008 1770 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1771 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1772 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1773 __le32 eeer_val; 1774 u8 d3_lpan; 1775 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1776 u8 phy_type_ext; 1777 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1778 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1779 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1780 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1781 u8 fec_cfg_curr_mod_ext_info; 1782 #define I40E_AQ_ENABLE_FEC_KR 0x01 1783 #define I40E_AQ_ENABLE_FEC_RS 0x02 1784 #define I40E_AQ_REQUEST_FEC_KR 0x04 1785 #define I40E_AQ_REQUEST_FEC_RS 0x08 1786 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1787 #define I40E_AQ_FEC 1788 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1789 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1790 1791 u8 ext_comp_code; 1792 u8 phy_id[4]; 1793 u8 module_type[3]; 1794 u8 qualified_module_count; 1795 #define I40E_AQ_PHY_MAX_QMS 16 1796 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1797 }; 1798 1799 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1800 1801 /* Set PHY Config (direct 0x0601) */ 1802 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1803 __le32 phy_type; 1804 u8 link_speed; 1805 u8 abilities; 1806 /* bits 0-2 use the values from get_phy_abilities_resp */ 1807 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1808 #define I40E_AQ_PHY_ENABLE_AN 0x10 1809 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1810 __le16 eee_capability; 1811 __le32 eeer; 1812 u8 low_power_ctrl; 1813 u8 phy_type_ext; 1814 u8 fec_config; 1815 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1816 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1817 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1818 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1819 #define I40E_AQ_SET_FEC_AUTO BIT(4) 1820 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1821 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1822 u8 reserved; 1823 }; 1824 1825 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1826 1827 /* Set MAC Config command data structure (direct 0x0603) */ 1828 struct i40e_aq_set_mac_config { 1829 __le16 max_frame_size; 1830 u8 params; 1831 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1832 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1833 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1834 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1835 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1836 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1837 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1838 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1839 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1840 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1841 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1842 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1843 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1844 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1845 u8 tx_timer_priority; /* bitmap */ 1846 __le16 tx_timer_value; 1847 __le16 fc_refresh_threshold; 1848 u8 reserved[8]; 1849 }; 1850 1851 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1852 1853 /* Restart Auto-Negotiation (direct 0x605) */ 1854 struct i40e_aqc_set_link_restart_an { 1855 u8 command; 1856 #define I40E_AQ_PHY_RESTART_AN 0x02 1857 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1858 u8 reserved[15]; 1859 }; 1860 1861 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1862 1863 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1864 struct i40e_aqc_get_link_status { 1865 __le16 command_flags; /* only field set on command */ 1866 #define I40E_AQ_LSE_MASK 0x3 1867 #define I40E_AQ_LSE_NOP 0x0 1868 #define I40E_AQ_LSE_DISABLE 0x2 1869 #define I40E_AQ_LSE_ENABLE 0x3 1870 /* only response uses this flag */ 1871 #define I40E_AQ_LSE_IS_ENABLED 0x1 1872 u8 phy_type; /* i40e_aq_phy_type */ 1873 u8 link_speed; /* i40e_aq_link_speed */ 1874 u8 link_info; 1875 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1876 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1877 #define I40E_AQ_LINK_FAULT 0x02 1878 #define I40E_AQ_LINK_FAULT_TX 0x04 1879 #define I40E_AQ_LINK_FAULT_RX 0x08 1880 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1881 #define I40E_AQ_LINK_UP_PORT 0x20 1882 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1883 #define I40E_AQ_SIGNAL_DETECT 0x80 1884 u8 an_info; 1885 #define I40E_AQ_AN_COMPLETED 0x01 1886 #define I40E_AQ_LP_AN_ABILITY 0x02 1887 #define I40E_AQ_PD_FAULT 0x04 1888 #define I40E_AQ_FEC_EN 0x08 1889 #define I40E_AQ_PHY_LOW_POWER 0x10 1890 #define I40E_AQ_LINK_PAUSE_TX 0x20 1891 #define I40E_AQ_LINK_PAUSE_RX 0x40 1892 #define I40E_AQ_QUALIFIED_MODULE 0x80 1893 u8 ext_info; 1894 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1895 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1896 #define I40E_AQ_LINK_TX_SHIFT 0x02 1897 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1898 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1899 #define I40E_AQ_LINK_TX_DRAINED 0x01 1900 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1901 #define I40E_AQ_LINK_FORCED_40G 0x10 1902 /* 25G Error Codes */ 1903 #define I40E_AQ_25G_NO_ERR 0X00 1904 #define I40E_AQ_25G_NOT_PRESENT 0X01 1905 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 1906 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1907 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1908 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 1909 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1910 __le16 max_frame_size; 1911 u8 config; 1912 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 1913 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 1914 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1915 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1916 u8 power_desc; 1917 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 1918 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 1919 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 1920 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 1921 #define I40E_AQ_PWR_CLASS_MASK 0x03 1922 u8 reserved[4]; 1923 }; 1924 1925 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1926 1927 /* Set event mask command (direct 0x613) */ 1928 struct i40e_aqc_set_phy_int_mask { 1929 u8 reserved[8]; 1930 __le16 event_mask; 1931 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1932 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1933 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1934 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1935 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1936 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1937 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1938 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1939 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1940 u8 reserved1[6]; 1941 }; 1942 1943 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1944 1945 /* Get Local AN advt register (direct 0x0614) 1946 * Set Local AN advt register (direct 0x0615) 1947 * Get Link Partner AN advt register (direct 0x0616) 1948 */ 1949 struct i40e_aqc_an_advt_reg { 1950 __le32 local_an_reg0; 1951 __le16 local_an_reg1; 1952 u8 reserved[10]; 1953 }; 1954 1955 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1956 1957 /* Set Loopback mode (0x0618) */ 1958 struct i40e_aqc_set_lb_mode { 1959 __le16 lb_mode; 1960 #define I40E_AQ_LB_PHY_LOCAL 0x01 1961 #define I40E_AQ_LB_PHY_REMOTE 0x02 1962 #define I40E_AQ_LB_MAC_LOCAL 0x04 1963 u8 reserved[14]; 1964 }; 1965 1966 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1967 1968 /* Set PHY Debug command (0x0622) */ 1969 struct i40e_aqc_set_phy_debug { 1970 u8 command_flags; 1971 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1972 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1973 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1974 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1975 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1976 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1977 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1978 /* Disable link manageability on a single port */ 1979 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1980 /* Disable link manageability on all ports needs both bits 4 and 5 */ 1981 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 1982 u8 reserved[15]; 1983 }; 1984 1985 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1986 1987 enum i40e_aq_phy_reg_type { 1988 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1989 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1990 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1991 }; 1992 1993 /* Run PHY Activity (0x0626) */ 1994 struct i40e_aqc_run_phy_activity { 1995 __le16 activity_id; 1996 u8 flags; 1997 u8 reserved1; 1998 __le32 control; 1999 __le32 data; 2000 u8 reserved2[4]; 2001 }; 2002 2003 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2004 2005 /* NVM Read command (indirect 0x0701) 2006 * NVM Erase commands (direct 0x0702) 2007 * NVM Update commands (indirect 0x0703) 2008 */ 2009 struct i40e_aqc_nvm_update { 2010 u8 command_flags; 2011 #define I40E_AQ_NVM_LAST_CMD 0x01 2012 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2013 u8 module_pointer; 2014 __le16 length; 2015 __le32 offset; 2016 __le32 addr_high; 2017 __le32 addr_low; 2018 }; 2019 2020 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2021 2022 /* NVM Config Read (indirect 0x0704) */ 2023 struct i40e_aqc_nvm_config_read { 2024 __le16 cmd_flags; 2025 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2026 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2027 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2028 __le16 element_count; 2029 __le16 element_id; /* Feature/field ID */ 2030 __le16 element_id_msw; /* MSWord of field ID */ 2031 __le32 address_high; 2032 __le32 address_low; 2033 }; 2034 2035 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2036 2037 /* NVM Config Write (indirect 0x0705) */ 2038 struct i40e_aqc_nvm_config_write { 2039 __le16 cmd_flags; 2040 __le16 element_count; 2041 u8 reserved[4]; 2042 __le32 address_high; 2043 __le32 address_low; 2044 }; 2045 2046 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2047 2048 /* Used for 0x0704 as well as for 0x0705 commands */ 2049 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2050 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2051 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2052 #define I40E_AQ_ANVM_FEATURE 0 2053 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2054 struct i40e_aqc_nvm_config_data_feature { 2055 __le16 feature_id; 2056 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2057 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2058 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2059 __le16 feature_options; 2060 __le16 feature_selection; 2061 }; 2062 2063 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2064 2065 struct i40e_aqc_nvm_config_data_immediate_field { 2066 __le32 field_id; 2067 __le32 field_value; 2068 __le16 field_options; 2069 __le16 reserved; 2070 }; 2071 2072 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2073 2074 /* OEM Post Update (indirect 0x0720) 2075 * no command data struct used 2076 */ 2077 struct i40e_aqc_nvm_oem_post_update { 2078 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2079 u8 sel_data; 2080 u8 reserved[7]; 2081 }; 2082 2083 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2084 2085 struct i40e_aqc_nvm_oem_post_update_buffer { 2086 u8 str_len; 2087 u8 dev_addr; 2088 __le16 eeprom_addr; 2089 u8 data[36]; 2090 }; 2091 2092 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2093 2094 /* Thermal Sensor (indirect 0x0721) 2095 * read or set thermal sensor configs and values 2096 * takes a sensor and command specific data buffer, not detailed here 2097 */ 2098 struct i40e_aqc_thermal_sensor { 2099 u8 sensor_action; 2100 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2101 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2102 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2103 u8 reserved[7]; 2104 __le32 addr_high; 2105 __le32 addr_low; 2106 }; 2107 2108 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2109 2110 /* Send to PF command (indirect 0x0801) id is only used by PF 2111 * Send to VF command (indirect 0x0802) id is only used by PF 2112 * Send to Peer PF command (indirect 0x0803) 2113 */ 2114 struct i40e_aqc_pf_vf_message { 2115 __le32 id; 2116 u8 reserved[4]; 2117 __le32 addr_high; 2118 __le32 addr_low; 2119 }; 2120 2121 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2122 2123 /* Alternate structure */ 2124 2125 /* Direct write (direct 0x0900) 2126 * Direct read (direct 0x0902) 2127 */ 2128 struct i40e_aqc_alternate_write { 2129 __le32 address0; 2130 __le32 data0; 2131 __le32 address1; 2132 __le32 data1; 2133 }; 2134 2135 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2136 2137 /* Indirect write (indirect 0x0901) 2138 * Indirect read (indirect 0x0903) 2139 */ 2140 2141 struct i40e_aqc_alternate_ind_write { 2142 __le32 address; 2143 __le32 length; 2144 __le32 addr_high; 2145 __le32 addr_low; 2146 }; 2147 2148 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2149 2150 /* Done alternate write (direct 0x0904) 2151 * uses i40e_aq_desc 2152 */ 2153 struct i40e_aqc_alternate_write_done { 2154 __le16 cmd_flags; 2155 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2156 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2157 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2158 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2159 u8 reserved[14]; 2160 }; 2161 2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2163 2164 /* Set OEM mode (direct 0x0905) */ 2165 struct i40e_aqc_alternate_set_mode { 2166 __le32 mode; 2167 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2168 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2169 u8 reserved[12]; 2170 }; 2171 2172 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2173 2174 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2175 2176 /* async events 0x10xx */ 2177 2178 /* Lan Queue Overflow Event (direct, 0x1001) */ 2179 struct i40e_aqc_lan_overflow { 2180 __le32 prtdcb_rupto; 2181 __le32 otx_ctl; 2182 u8 reserved[8]; 2183 }; 2184 2185 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2186 2187 /* Get LLDP MIB (indirect 0x0A00) */ 2188 struct i40e_aqc_lldp_get_mib { 2189 u8 type; 2190 u8 reserved1; 2191 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2192 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2193 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2194 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2195 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2196 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2197 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2198 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2199 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2200 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2201 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2202 __le16 local_len; 2203 __le16 remote_len; 2204 u8 reserved2[2]; 2205 __le32 addr_high; 2206 __le32 addr_low; 2207 }; 2208 2209 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2210 2211 /* Configure LLDP MIB Change Event (direct 0x0A01) 2212 * also used for the event (with type in the command field) 2213 */ 2214 struct i40e_aqc_lldp_update_mib { 2215 u8 command; 2216 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2217 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2218 u8 reserved[7]; 2219 __le32 addr_high; 2220 __le32 addr_low; 2221 }; 2222 2223 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2224 2225 /* Add LLDP TLV (indirect 0x0A02) 2226 * Delete LLDP TLV (indirect 0x0A04) 2227 */ 2228 struct i40e_aqc_lldp_add_tlv { 2229 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2230 u8 reserved1[1]; 2231 __le16 len; 2232 u8 reserved2[4]; 2233 __le32 addr_high; 2234 __le32 addr_low; 2235 }; 2236 2237 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2238 2239 /* Update LLDP TLV (indirect 0x0A03) */ 2240 struct i40e_aqc_lldp_update_tlv { 2241 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2242 u8 reserved; 2243 __le16 old_len; 2244 __le16 new_offset; 2245 __le16 new_len; 2246 __le32 addr_high; 2247 __le32 addr_low; 2248 }; 2249 2250 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2251 2252 /* Stop LLDP (direct 0x0A05) */ 2253 struct i40e_aqc_lldp_stop { 2254 u8 command; 2255 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2256 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2257 u8 reserved[15]; 2258 }; 2259 2260 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2261 2262 /* Start LLDP (direct 0x0A06) */ 2263 2264 struct i40e_aqc_lldp_start { 2265 u8 command; 2266 #define I40E_AQ_LLDP_AGENT_START 0x1 2267 u8 reserved[15]; 2268 }; 2269 2270 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2271 2272 /* Get CEE DCBX Oper Config (0x0A07) 2273 * uses the generic descriptor struct 2274 * returns below as indirect response 2275 */ 2276 2277 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2278 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2279 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2280 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2281 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2282 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2283 2284 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2285 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2286 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2287 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2288 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2289 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2290 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2291 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2292 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2293 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2294 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2295 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2296 2297 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2298 * word boundary layout issues, which the Linux compilers silently deal 2299 * with by adding padding, making the actual struct larger than designed. 2300 * However, the FW compiler for the NIC is less lenient and complains 2301 * about the struct. Hence, the struct defined here has an extra byte in 2302 * fields reserved3 and reserved4 to directly acknowledge that padding, 2303 * and the new length is used in the length check macro. 2304 */ 2305 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2306 u8 reserved1; 2307 u8 oper_num_tc; 2308 u8 oper_prio_tc[4]; 2309 u8 reserved2; 2310 u8 oper_tc_bw[8]; 2311 u8 oper_pfc_en; 2312 u8 reserved3[2]; 2313 __le16 oper_app_prio; 2314 u8 reserved4[2]; 2315 __le16 tlv_status; 2316 }; 2317 2318 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2319 2320 struct i40e_aqc_get_cee_dcb_cfg_resp { 2321 u8 oper_num_tc; 2322 u8 oper_prio_tc[4]; 2323 u8 oper_tc_bw[8]; 2324 u8 oper_pfc_en; 2325 __le16 oper_app_prio; 2326 __le32 tlv_status; 2327 u8 reserved[12]; 2328 }; 2329 2330 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2331 2332 /* Set Local LLDP MIB (indirect 0x0A08) 2333 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2334 */ 2335 struct i40e_aqc_lldp_set_local_mib { 2336 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2337 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2338 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2339 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2340 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2341 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2342 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2343 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2344 u8 type; 2345 u8 reserved0; 2346 __le16 length; 2347 u8 reserved1[4]; 2348 __le32 address_high; 2349 __le32 address_low; 2350 }; 2351 2352 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2353 2354 struct i40e_aqc_lldp_set_local_mib_resp { 2355 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2356 u8 status; 2357 u8 reserved[15]; 2358 }; 2359 2360 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2361 2362 /* Stop/Start LLDP Agent (direct 0x0A09) 2363 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2364 */ 2365 struct i40e_aqc_lldp_stop_start_specific_agent { 2366 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2367 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2368 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2369 u8 command; 2370 u8 reserved[15]; 2371 }; 2372 2373 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2374 2375 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2376 struct i40e_aqc_add_udp_tunnel { 2377 __le16 udp_port; 2378 u8 reserved0[3]; 2379 u8 protocol_type; 2380 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2381 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2382 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2383 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2384 u8 reserved1[10]; 2385 }; 2386 2387 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2388 2389 struct i40e_aqc_add_udp_tunnel_completion { 2390 __le16 udp_port; 2391 u8 filter_entry_index; 2392 u8 multiple_pfs; 2393 #define I40E_AQC_SINGLE_PF 0x0 2394 #define I40E_AQC_MULTIPLE_PFS 0x1 2395 u8 total_filters; 2396 u8 reserved[11]; 2397 }; 2398 2399 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2400 2401 /* remove UDP Tunnel command (0x0B01) */ 2402 struct i40e_aqc_remove_udp_tunnel { 2403 u8 reserved[2]; 2404 u8 index; /* 0 to 15 */ 2405 u8 reserved2[13]; 2406 }; 2407 2408 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2409 2410 struct i40e_aqc_del_udp_tunnel_completion { 2411 __le16 udp_port; 2412 u8 index; /* 0 to 15 */ 2413 u8 multiple_pfs; 2414 u8 total_filters_used; 2415 u8 reserved1[11]; 2416 }; 2417 2418 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2419 2420 struct i40e_aqc_get_set_rss_key { 2421 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2422 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2423 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2424 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2425 __le16 vsi_id; 2426 u8 reserved[6]; 2427 __le32 addr_high; 2428 __le32 addr_low; 2429 }; 2430 2431 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2432 2433 struct i40e_aqc_get_set_rss_key_data { 2434 u8 standard_rss_key[0x28]; 2435 u8 extended_hash_key[0xc]; 2436 }; 2437 2438 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2439 2440 struct i40e_aqc_get_set_rss_lut { 2441 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2442 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2443 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2444 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2445 __le16 vsi_id; 2446 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2447 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2448 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2449 2450 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2451 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2452 __le16 flags; 2453 u8 reserved[4]; 2454 __le32 addr_high; 2455 __le32 addr_low; 2456 }; 2457 2458 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2459 2460 /* tunnel key structure 0x0B10 */ 2461 2462 struct i40e_aqc_tunnel_key_structure { 2463 u8 key1_off; 2464 u8 key2_off; 2465 u8 key1_len; /* 0 to 15 */ 2466 u8 key2_len; /* 0 to 15 */ 2467 u8 flags; 2468 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2469 /* response flags */ 2470 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2471 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2472 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2473 u8 network_key_index; 2474 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2475 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2476 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2477 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2478 u8 reserved[10]; 2479 }; 2480 2481 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2482 2483 /* OEM mode commands (direct 0xFE0x) */ 2484 struct i40e_aqc_oem_param_change { 2485 __le32 param_type; 2486 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2487 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2488 #define I40E_AQ_OEM_PARAM_MAC 2 2489 __le32 param_value1; 2490 __le16 param_value2; 2491 u8 reserved[6]; 2492 }; 2493 2494 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2495 2496 struct i40e_aqc_oem_state_change { 2497 __le32 state; 2498 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2499 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2500 u8 reserved[12]; 2501 }; 2502 2503 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2504 2505 /* Initialize OCSD (0xFE02, direct) */ 2506 struct i40e_aqc_opc_oem_ocsd_initialize { 2507 u8 type_status; 2508 u8 reserved1[3]; 2509 __le32 ocsd_memory_block_addr_high; 2510 __le32 ocsd_memory_block_addr_low; 2511 __le32 requested_update_interval; 2512 }; 2513 2514 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2515 2516 /* Initialize OCBB (0xFE03, direct) */ 2517 struct i40e_aqc_opc_oem_ocbb_initialize { 2518 u8 type_status; 2519 u8 reserved1[3]; 2520 __le32 ocbb_memory_block_addr_high; 2521 __le32 ocbb_memory_block_addr_low; 2522 u8 reserved2[4]; 2523 }; 2524 2525 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2526 2527 /* debug commands */ 2528 2529 /* get device id (0xFF00) uses the generic structure */ 2530 2531 /* set test more (0xFF01, internal) */ 2532 2533 struct i40e_acq_set_test_mode { 2534 u8 mode; 2535 #define I40E_AQ_TEST_PARTIAL 0 2536 #define I40E_AQ_TEST_FULL 1 2537 #define I40E_AQ_TEST_NVM 2 2538 u8 reserved[3]; 2539 u8 command; 2540 #define I40E_AQ_TEST_OPEN 0 2541 #define I40E_AQ_TEST_CLOSE 1 2542 #define I40E_AQ_TEST_INC 2 2543 u8 reserved2[3]; 2544 __le32 address_high; 2545 __le32 address_low; 2546 }; 2547 2548 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2549 2550 /* Debug Read Register command (0xFF03) 2551 * Debug Write Register command (0xFF04) 2552 */ 2553 struct i40e_aqc_debug_reg_read_write { 2554 __le32 reserved; 2555 __le32 address; 2556 __le32 value_high; 2557 __le32 value_low; 2558 }; 2559 2560 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2561 2562 /* Scatter/gather Reg Read (indirect 0xFF05) 2563 * Scatter/gather Reg Write (indirect 0xFF06) 2564 */ 2565 2566 /* i40e_aq_desc is used for the command */ 2567 struct i40e_aqc_debug_reg_sg_element_data { 2568 __le32 address; 2569 __le32 value; 2570 }; 2571 2572 /* Debug Modify register (direct 0xFF07) */ 2573 struct i40e_aqc_debug_modify_reg { 2574 __le32 address; 2575 __le32 value; 2576 __le32 clear_mask; 2577 __le32 set_mask; 2578 }; 2579 2580 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2581 2582 /* dump internal data (0xFF08, indirect) */ 2583 2584 #define I40E_AQ_CLUSTER_ID_AUX 0 2585 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2586 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2587 #define I40E_AQ_CLUSTER_ID_HMC 3 2588 #define I40E_AQ_CLUSTER_ID_MAC0 4 2589 #define I40E_AQ_CLUSTER_ID_MAC1 5 2590 #define I40E_AQ_CLUSTER_ID_MAC2 6 2591 #define I40E_AQ_CLUSTER_ID_MAC3 7 2592 #define I40E_AQ_CLUSTER_ID_DCB 8 2593 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2594 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2595 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2596 2597 struct i40e_aqc_debug_dump_internals { 2598 u8 cluster_id; 2599 u8 table_id; 2600 __le16 data_size; 2601 __le32 idx; 2602 __le32 address_high; 2603 __le32 address_low; 2604 }; 2605 2606 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2607 2608 struct i40e_aqc_debug_modify_internals { 2609 u8 cluster_id; 2610 u8 cluster_specific_params[7]; 2611 __le32 address_high; 2612 __le32 address_low; 2613 }; 2614 2615 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2616 2617 #endif /* _I40E_ADMINQ_CMD_H_ */ 2618