1 /****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 34 #ifndef _I40E_ADMINQ_CMD_H_ 35 #define _I40E_ADMINQ_CMD_H_ 36 37 /* This header file defines the i40e Admin Queue commands and is shared between 38 * i40e Firmware and Software. 39 * 40 * This file needs to comply with the Linux Kernel coding style. 41 */ 42 43 44 #define I40E_FW_API_VERSION_MAJOR 0x0001 45 #define I40E_FW_API_VERSION_MINOR_X722 0x000C 46 #define I40E_FW_API_VERSION_MINOR_X710 0x000F 47 48 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 49 I40E_FW_API_VERSION_MINOR_X710 : \ 50 I40E_FW_API_VERSION_MINOR_X722) 51 52 /* API version 1.7 implements additional link and PHY-specific APIs */ 53 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 54 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */ 55 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009 56 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 57 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 58 /* API version 1.10 for X722 devices adds ability to request FEC encoding */ 59 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A 60 61 struct i40e_aq_desc { 62 __le16 flags; 63 __le16 opcode; 64 __le16 datalen; 65 __le16 retval; 66 __le32 cookie_high; 67 __le32 cookie_low; 68 union { 69 struct { 70 __le32 param0; 71 __le32 param1; 72 __le32 param2; 73 __le32 param3; 74 } internal; 75 struct { 76 __le32 param0; 77 __le32 param1; 78 __le32 addr_high; 79 __le32 addr_low; 80 } external; 81 u8 raw[16]; 82 } params; 83 }; 84 85 /* Flags sub-structure 86 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 87 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 88 */ 89 90 /* command flags and offsets*/ 91 #define I40E_AQ_FLAG_DD_SHIFT 0 92 #define I40E_AQ_FLAG_CMP_SHIFT 1 93 #define I40E_AQ_FLAG_ERR_SHIFT 2 94 #define I40E_AQ_FLAG_VFE_SHIFT 3 95 #define I40E_AQ_FLAG_LB_SHIFT 9 96 #define I40E_AQ_FLAG_RD_SHIFT 10 97 #define I40E_AQ_FLAG_VFC_SHIFT 11 98 #define I40E_AQ_FLAG_BUF_SHIFT 12 99 #define I40E_AQ_FLAG_SI_SHIFT 13 100 #define I40E_AQ_FLAG_EI_SHIFT 14 101 #define I40E_AQ_FLAG_FE_SHIFT 15 102 103 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 104 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 105 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 106 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 107 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 108 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 109 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 110 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 111 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 112 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 113 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 114 115 /* error codes */ 116 enum i40e_admin_queue_err { 117 I40E_AQ_RC_OK = 0, /* success */ 118 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 119 I40E_AQ_RC_ENOENT = 2, /* No such element */ 120 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 121 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 122 I40E_AQ_RC_EIO = 5, /* I/O error */ 123 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 124 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 125 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 126 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 127 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 128 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 129 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 130 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 131 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 132 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 133 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 134 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 135 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 136 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 137 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 138 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 139 I40E_AQ_RC_EFBIG = 22, /* File too large */ 140 }; 141 142 /* Admin Queue command opcodes */ 143 enum i40e_admin_queue_opc { 144 /* aq commands */ 145 i40e_aqc_opc_get_version = 0x0001, 146 i40e_aqc_opc_driver_version = 0x0002, 147 i40e_aqc_opc_queue_shutdown = 0x0003, 148 i40e_aqc_opc_set_pf_context = 0x0004, 149 150 /* resource ownership */ 151 i40e_aqc_opc_request_resource = 0x0008, 152 i40e_aqc_opc_release_resource = 0x0009, 153 154 i40e_aqc_opc_list_func_capabilities = 0x000A, 155 i40e_aqc_opc_list_dev_capabilities = 0x000B, 156 157 /* Proxy commands */ 158 i40e_aqc_opc_set_proxy_config = 0x0104, 159 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 160 161 /* LAA */ 162 i40e_aqc_opc_mac_address_read = 0x0107, 163 i40e_aqc_opc_mac_address_write = 0x0108, 164 165 /* PXE */ 166 i40e_aqc_opc_clear_pxe_mode = 0x0110, 167 168 /* WoL commands */ 169 i40e_aqc_opc_set_wol_filter = 0x0120, 170 i40e_aqc_opc_get_wake_reason = 0x0121, 171 i40e_aqc_opc_clear_all_wol_filters = 0x025E, 172 173 /* internal switch commands */ 174 i40e_aqc_opc_get_switch_config = 0x0200, 175 i40e_aqc_opc_add_statistics = 0x0201, 176 i40e_aqc_opc_remove_statistics = 0x0202, 177 i40e_aqc_opc_set_port_parameters = 0x0203, 178 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 179 i40e_aqc_opc_set_switch_config = 0x0205, 180 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 181 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 182 183 i40e_aqc_opc_add_vsi = 0x0210, 184 i40e_aqc_opc_update_vsi_parameters = 0x0211, 185 i40e_aqc_opc_get_vsi_parameters = 0x0212, 186 187 i40e_aqc_opc_add_pv = 0x0220, 188 i40e_aqc_opc_update_pv_parameters = 0x0221, 189 i40e_aqc_opc_get_pv_parameters = 0x0222, 190 191 i40e_aqc_opc_add_veb = 0x0230, 192 i40e_aqc_opc_update_veb_parameters = 0x0231, 193 i40e_aqc_opc_get_veb_parameters = 0x0232, 194 195 i40e_aqc_opc_delete_element = 0x0243, 196 197 i40e_aqc_opc_add_macvlan = 0x0250, 198 i40e_aqc_opc_remove_macvlan = 0x0251, 199 i40e_aqc_opc_add_vlan = 0x0252, 200 i40e_aqc_opc_remove_vlan = 0x0253, 201 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 202 i40e_aqc_opc_add_tag = 0x0255, 203 i40e_aqc_opc_remove_tag = 0x0256, 204 i40e_aqc_opc_add_multicast_etag = 0x0257, 205 i40e_aqc_opc_remove_multicast_etag = 0x0258, 206 i40e_aqc_opc_update_tag = 0x0259, 207 i40e_aqc_opc_add_control_packet_filter = 0x025A, 208 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 209 i40e_aqc_opc_add_cloud_filters = 0x025C, 210 i40e_aqc_opc_remove_cloud_filters = 0x025D, 211 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 212 i40e_aqc_opc_replace_cloud_filters = 0x025F, 213 214 i40e_aqc_opc_add_mirror_rule = 0x0260, 215 i40e_aqc_opc_delete_mirror_rule = 0x0261, 216 217 /* DCB commands */ 218 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 219 i40e_aqc_opc_dcb_updated = 0x0302, 220 i40e_aqc_opc_set_dcb_parameters = 0x0303, 221 222 /* TX scheduler */ 223 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 224 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 225 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 226 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 227 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 228 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 229 230 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 231 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 232 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 233 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 234 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 235 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 236 i40e_aqc_opc_query_port_ets_config = 0x0419, 237 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 238 i40e_aqc_opc_suspend_port_tx = 0x041B, 239 i40e_aqc_opc_resume_port_tx = 0x041C, 240 i40e_aqc_opc_configure_partition_bw = 0x041D, 241 /* hmc */ 242 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 243 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 244 245 /* phy commands*/ 246 i40e_aqc_opc_get_phy_abilities = 0x0600, 247 i40e_aqc_opc_set_phy_config = 0x0601, 248 i40e_aqc_opc_set_mac_config = 0x0603, 249 i40e_aqc_opc_set_link_restart_an = 0x0605, 250 i40e_aqc_opc_get_link_status = 0x0607, 251 i40e_aqc_opc_set_phy_int_mask = 0x0613, 252 i40e_aqc_opc_get_local_advt_reg = 0x0614, 253 i40e_aqc_opc_set_local_advt_reg = 0x0615, 254 i40e_aqc_opc_get_partner_advt = 0x0616, 255 i40e_aqc_opc_set_lb_modes = 0x0618, 256 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 257 i40e_aqc_opc_set_phy_debug = 0x0622, 258 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 259 i40e_aqc_opc_run_phy_activity = 0x0626, 260 i40e_aqc_opc_set_phy_register = 0x0628, 261 i40e_aqc_opc_get_phy_register = 0x0629, 262 263 /* NVM commands */ 264 i40e_aqc_opc_nvm_read = 0x0701, 265 i40e_aqc_opc_nvm_erase = 0x0702, 266 i40e_aqc_opc_nvm_update = 0x0703, 267 i40e_aqc_opc_nvm_config_read = 0x0704, 268 i40e_aqc_opc_nvm_config_write = 0x0705, 269 i40e_aqc_opc_nvm_update_in_process = 0x0706, 270 i40e_aqc_opc_rollback_revision_update = 0x0707, 271 i40e_aqc_opc_oem_post_update = 0x0720, 272 i40e_aqc_opc_thermal_sensor = 0x0721, 273 274 /* virtualization commands */ 275 i40e_aqc_opc_send_msg_to_pf = 0x0801, 276 i40e_aqc_opc_send_msg_to_vf = 0x0802, 277 i40e_aqc_opc_send_msg_to_peer = 0x0803, 278 279 /* alternate structure */ 280 i40e_aqc_opc_alternate_write = 0x0900, 281 i40e_aqc_opc_alternate_write_indirect = 0x0901, 282 i40e_aqc_opc_alternate_read = 0x0902, 283 i40e_aqc_opc_alternate_read_indirect = 0x0903, 284 i40e_aqc_opc_alternate_write_done = 0x0904, 285 i40e_aqc_opc_alternate_set_mode = 0x0905, 286 i40e_aqc_opc_alternate_clear_port = 0x0906, 287 288 /* LLDP commands */ 289 i40e_aqc_opc_lldp_get_mib = 0x0A00, 290 i40e_aqc_opc_lldp_update_mib = 0x0A01, 291 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 292 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 293 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 294 i40e_aqc_opc_lldp_stop = 0x0A05, 295 i40e_aqc_opc_lldp_start = 0x0A06, 296 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 297 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 298 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 299 i40e_aqc_opc_lldp_restore = 0x0A0A, 300 301 /* Tunnel commands */ 302 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 303 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 304 i40e_aqc_opc_set_rss_key = 0x0B02, 305 i40e_aqc_opc_set_rss_lut = 0x0B03, 306 i40e_aqc_opc_get_rss_key = 0x0B04, 307 i40e_aqc_opc_get_rss_lut = 0x0B05, 308 309 /* Async Events */ 310 i40e_aqc_opc_event_lan_overflow = 0x1001, 311 312 /* OEM commands */ 313 i40e_aqc_opc_oem_parameter_change = 0xFE00, 314 i40e_aqc_opc_oem_device_status_change = 0xFE01, 315 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 316 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 317 318 /* debug commands */ 319 i40e_aqc_opc_debug_read_reg = 0xFF03, 320 i40e_aqc_opc_debug_write_reg = 0xFF04, 321 i40e_aqc_opc_debug_modify_reg = 0xFF07, 322 i40e_aqc_opc_debug_dump_internals = 0xFF08, 323 }; 324 325 /* command structures and indirect data structures */ 326 327 /* Structure naming conventions: 328 * - no suffix for direct command descriptor structures 329 * - _data for indirect sent data 330 * - _resp for indirect return data (data which is both will use _data) 331 * - _completion for direct return data 332 * - _element_ for repeated elements (may also be _data or _resp) 333 * 334 * Command structures are expected to overlay the params.raw member of the basic 335 * descriptor, and as such cannot exceed 16 bytes in length. 336 */ 337 338 /* This macro is used to generate a compilation error if a structure 339 * is not exactly the correct length. It gives a divide by zero error if the 340 * structure is not of the correct size, otherwise it creates an enum that is 341 * never used. 342 */ 343 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 344 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 345 346 /* This macro is used extensively to ensure that command structures are 16 347 * bytes in length as they have to map to the raw array of that size. 348 */ 349 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 350 351 /* internal (0x00XX) commands */ 352 353 /* Get version (direct 0x0001) */ 354 struct i40e_aqc_get_version { 355 __le32 rom_ver; 356 __le32 fw_build; 357 __le16 fw_major; 358 __le16 fw_minor; 359 __le16 api_major; 360 __le16 api_minor; 361 }; 362 363 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 364 365 /* Send driver version (indirect 0x0002) */ 366 struct i40e_aqc_driver_version { 367 u8 driver_major_ver; 368 u8 driver_minor_ver; 369 u8 driver_build_ver; 370 u8 driver_subbuild_ver; 371 u8 reserved[4]; 372 __le32 address_high; 373 __le32 address_low; 374 }; 375 376 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 377 378 /* Queue Shutdown (direct 0x0003) */ 379 struct i40e_aqc_queue_shutdown { 380 __le32 driver_unloading; 381 #define I40E_AQ_DRIVER_UNLOADING 0x1 382 u8 reserved[12]; 383 }; 384 385 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 386 387 /* Set PF context (0x0004, direct) */ 388 struct i40e_aqc_set_pf_context { 389 u8 pf_id; 390 u8 reserved[15]; 391 }; 392 393 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 394 395 /* Request resource ownership (direct 0x0008) 396 * Release resource ownership (direct 0x0009) 397 */ 398 #define I40E_AQ_RESOURCE_NVM 1 399 #define I40E_AQ_RESOURCE_SDP 2 400 #define I40E_AQ_RESOURCE_ACCESS_READ 1 401 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 402 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 403 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 404 405 struct i40e_aqc_request_resource { 406 __le16 resource_id; 407 __le16 access_type; 408 __le32 timeout; 409 __le32 resource_number; 410 u8 reserved[4]; 411 }; 412 413 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 414 415 /* Get function capabilities (indirect 0x000A) 416 * Get device capabilities (indirect 0x000B) 417 */ 418 struct i40e_aqc_list_capabilites { 419 u8 command_flags; 420 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 421 u8 pf_index; 422 u8 reserved[2]; 423 __le32 count; 424 __le32 addr_high; 425 __le32 addr_low; 426 }; 427 428 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 429 430 struct i40e_aqc_list_capabilities_element_resp { 431 __le16 id; 432 u8 major_rev; 433 u8 minor_rev; 434 __le32 number; 435 __le32 logical_id; 436 __le32 phys_id; 437 u8 reserved[16]; 438 }; 439 440 /* list of caps */ 441 442 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 443 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 444 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 445 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 446 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 447 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 448 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 449 #define I40E_AQ_CAP_ID_SRIOV 0x0012 450 #define I40E_AQ_CAP_ID_VF 0x0013 451 #define I40E_AQ_CAP_ID_VMDQ 0x0014 452 #define I40E_AQ_CAP_ID_8021QBG 0x0015 453 #define I40E_AQ_CAP_ID_8021QBR 0x0016 454 #define I40E_AQ_CAP_ID_VSI 0x0017 455 #define I40E_AQ_CAP_ID_DCB 0x0018 456 #define I40E_AQ_CAP_ID_FCOE 0x0021 457 #define I40E_AQ_CAP_ID_ISCSI 0x0022 458 #define I40E_AQ_CAP_ID_RSS 0x0040 459 #define I40E_AQ_CAP_ID_RXQ 0x0041 460 #define I40E_AQ_CAP_ID_TXQ 0x0042 461 #define I40E_AQ_CAP_ID_MSIX 0x0043 462 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 463 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 464 #define I40E_AQ_CAP_ID_1588 0x0046 465 #define I40E_AQ_CAP_ID_IWARP 0x0051 466 #define I40E_AQ_CAP_ID_LED 0x0061 467 #define I40E_AQ_CAP_ID_SDP 0x0062 468 #define I40E_AQ_CAP_ID_MDIO 0x0063 469 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 470 #define I40E_AQ_CAP_ID_DIS_UNUSED_PORTS 0x0067 471 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 472 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 473 #define I40E_AQ_CAP_ID_CEM 0x00F2 474 475 /* Set CPPM Configuration (direct 0x0103) */ 476 struct i40e_aqc_cppm_configuration { 477 __le16 command_flags; 478 #define I40E_AQ_CPPM_EN_LTRC 0x0800 479 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 480 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 481 #define I40E_AQ_CPPM_EN_HPTC 0x4000 482 #define I40E_AQ_CPPM_EN_DMARC 0x8000 483 __le16 ttlx; 484 __le32 dmacr; 485 __le16 dmcth; 486 u8 hptc; 487 u8 reserved; 488 __le32 pfltrc; 489 }; 490 491 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 492 493 /* Set ARP Proxy command / response (indirect 0x0104) */ 494 struct i40e_aqc_arp_proxy_data { 495 __le16 command_flags; 496 #define I40E_AQ_ARP_INIT_IPV4 0x0800 497 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 498 #define I40E_AQ_ARP_ENA 0x2000 499 #define I40E_AQ_ARP_ADD_IPV4 0x4000 500 #define I40E_AQ_ARP_DEL_IPV4 0x8000 501 __le16 table_id; 502 __le32 enabled_offloads; 503 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 504 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 505 __le32 ip_addr; 506 u8 mac_addr[6]; 507 u8 reserved[2]; 508 }; 509 510 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 511 512 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 513 struct i40e_aqc_ns_proxy_data { 514 __le16 table_idx_mac_addr_0; 515 __le16 table_idx_mac_addr_1; 516 __le16 table_idx_ipv6_0; 517 __le16 table_idx_ipv6_1; 518 __le16 control; 519 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 520 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 521 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 522 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 523 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 524 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 525 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 526 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 527 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 528 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 529 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 530 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 531 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 532 u8 mac_addr_0[6]; 533 u8 mac_addr_1[6]; 534 u8 local_mac_addr[6]; 535 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 536 u8 ipv6_addr_1[16]; 537 }; 538 539 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 540 541 /* Manage LAA Command (0x0106) - obsolete */ 542 struct i40e_aqc_mng_laa { 543 __le16 command_flags; 544 #define I40E_AQ_LAA_FLAG_WR 0x8000 545 u8 reserved[2]; 546 __le32 sal; 547 __le16 sah; 548 u8 reserved2[6]; 549 }; 550 551 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 552 553 /* Manage MAC Address Read Command (indirect 0x0107) */ 554 struct i40e_aqc_mac_address_read { 555 __le16 command_flags; 556 #define I40E_AQC_LAN_ADDR_VALID 0x10 557 #define I40E_AQC_SAN_ADDR_VALID 0x20 558 #define I40E_AQC_PORT_ADDR_VALID 0x40 559 #define I40E_AQC_WOL_ADDR_VALID 0x80 560 #define I40E_AQC_MC_MAG_EN_VALID 0x100 561 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 562 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 563 u8 reserved[6]; 564 __le32 addr_high; 565 __le32 addr_low; 566 }; 567 568 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 569 570 struct i40e_aqc_mac_address_read_data { 571 u8 pf_lan_mac[6]; 572 u8 pf_san_mac[6]; 573 u8 port_mac[6]; 574 u8 pf_wol_mac[6]; 575 }; 576 577 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 578 579 /* Manage MAC Address Write Command (0x0108) */ 580 struct i40e_aqc_mac_address_write { 581 __le16 command_flags; 582 #define I40E_AQC_MC_MAG_EN 0x0100 583 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 584 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 585 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 586 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 587 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 588 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 589 590 __le16 mac_sah; 591 __le32 mac_sal; 592 u8 reserved[8]; 593 }; 594 595 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 596 597 /* PXE commands (0x011x) */ 598 599 /* Clear PXE Command and response (direct 0x0110) */ 600 struct i40e_aqc_clear_pxe { 601 u8 rx_cnt; 602 u8 reserved[15]; 603 }; 604 605 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 606 607 /* Set WoL Filter (0x0120) */ 608 609 struct i40e_aqc_set_wol_filter { 610 __le16 filter_index; 611 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 612 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 613 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 614 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 615 616 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 617 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 618 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 619 __le16 cmd_flags; 620 #define I40E_AQC_SET_WOL_FILTER 0x8000 621 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 622 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 623 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 624 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 625 __le16 valid_flags; 626 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 627 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 628 u8 reserved[2]; 629 __le32 address_high; 630 __le32 address_low; 631 }; 632 633 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 634 635 struct i40e_aqc_set_wol_filter_data { 636 u8 filter[128]; 637 u8 mask[16]; 638 }; 639 640 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 641 642 /* Get Wake Reason (0x0121) */ 643 644 struct i40e_aqc_get_wake_reason_completion { 645 u8 reserved_1[2]; 646 __le16 wake_reason; 647 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 648 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 649 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 650 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 651 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 652 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 653 u8 reserved_2[12]; 654 }; 655 656 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 657 658 /* Switch configuration commands (0x02xx) */ 659 660 /* Used by many indirect commands that only pass an seid and a buffer in the 661 * command 662 */ 663 struct i40e_aqc_switch_seid { 664 __le16 seid; 665 u8 reserved[6]; 666 __le32 addr_high; 667 __le32 addr_low; 668 }; 669 670 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 671 672 /* Get Switch Configuration command (indirect 0x0200) 673 * uses i40e_aqc_switch_seid for the descriptor 674 */ 675 struct i40e_aqc_get_switch_config_header_resp { 676 __le16 num_reported; 677 __le16 num_total; 678 u8 reserved[12]; 679 }; 680 681 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 682 683 struct i40e_aqc_switch_config_element_resp { 684 u8 element_type; 685 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 686 #define I40E_AQ_SW_ELEM_TYPE_PF 2 687 #define I40E_AQ_SW_ELEM_TYPE_VF 3 688 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 689 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 690 #define I40E_AQ_SW_ELEM_TYPE_PV 16 691 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 692 #define I40E_AQ_SW_ELEM_TYPE_PA 18 693 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 694 u8 revision; 695 #define I40E_AQ_SW_ELEM_REV_1 1 696 __le16 seid; 697 __le16 uplink_seid; 698 __le16 downlink_seid; 699 u8 reserved[3]; 700 u8 connection_type; 701 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 702 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 703 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 704 __le16 scheduler_id; 705 __le16 element_info; 706 }; 707 708 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 709 710 /* Get Switch Configuration (indirect 0x0200) 711 * an array of elements are returned in the response buffer 712 * the first in the array is the header, remainder are elements 713 */ 714 struct i40e_aqc_get_switch_config_resp { 715 struct i40e_aqc_get_switch_config_header_resp header; 716 struct i40e_aqc_switch_config_element_resp element[1]; 717 }; 718 719 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 720 721 /* Add Statistics (direct 0x0201) 722 * Remove Statistics (direct 0x0202) 723 */ 724 struct i40e_aqc_add_remove_statistics { 725 __le16 seid; 726 __le16 vlan; 727 __le16 stat_index; 728 u8 reserved[10]; 729 }; 730 731 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 732 733 /* Set Port Parameters command (direct 0x0203) */ 734 struct i40e_aqc_set_port_parameters { 735 __le16 command_flags; 736 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 737 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 738 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 739 __le16 bad_frame_vsi; 740 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 741 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 742 __le16 default_seid; /* reserved for command */ 743 u8 reserved[10]; 744 }; 745 746 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 747 748 /* Get Switch Resource Allocation (indirect 0x0204) */ 749 struct i40e_aqc_get_switch_resource_alloc { 750 u8 num_entries; /* reserved for command */ 751 u8 reserved[7]; 752 __le32 addr_high; 753 __le32 addr_low; 754 }; 755 756 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 757 758 /* expect an array of these structs in the response buffer */ 759 struct i40e_aqc_switch_resource_alloc_element_resp { 760 u8 resource_type; 761 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 762 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 763 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 764 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 765 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 766 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 767 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 768 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 769 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 770 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 771 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 772 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 773 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 774 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 775 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 776 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 777 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 778 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 779 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 780 u8 reserved1; 781 __le16 guaranteed; 782 __le16 total; 783 __le16 used; 784 __le16 total_unalloced; 785 u8 reserved2[6]; 786 }; 787 788 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 789 790 /* Set Switch Configuration (direct 0x0205) */ 791 struct i40e_aqc_set_switch_config { 792 __le16 flags; 793 /* flags used for both fields below */ 794 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 795 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 796 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 797 #define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008 798 __le16 valid_flags; 799 /* The ethertype in switch_tag is dropped on ingress and used 800 * internally by the switch. Set this to zero for the default 801 * of 0x88a8 (802.1ad). Should be zero for firmware API 802 * versions lower than 1.7. 803 */ 804 __le16 switch_tag; 805 /* The ethertypes in first_tag and second_tag are used to 806 * match the outer and inner VLAN tags (respectively) when HW 807 * double VLAN tagging is enabled via the set port parameters 808 * AQ command. Otherwise these are both ignored. Set them to 809 * zero for their defaults of 0x8100 (802.1Q). Should be zero 810 * for firmware API versions lower than 1.7. 811 */ 812 __le16 first_tag; 813 __le16 second_tag; 814 /* Next byte is split into following: 815 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 816 * Bit 6 : 0 : Destination Port, 1: source port 817 * Bit 5..4 : L4 type 818 * 0: rsvd 819 * 1: TCP 820 * 2: UDP 821 * 3: Both TCP and UDP 822 * Bits 3:0 Mode 823 * 0: default mode 824 * 1: L4 port only mode 825 * 2: non-tunneled mode 826 * 3: tunneled mode 827 */ 828 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 829 830 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 831 832 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 833 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 834 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 835 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 836 837 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 838 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 839 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 840 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 841 u8 mode; 842 u8 rsvd5[5]; 843 }; 844 845 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 846 847 /* Read Receive control registers (direct 0x0206) 848 * Write Receive control registers (direct 0x0207) 849 * used for accessing Rx control registers that can be 850 * slow and need special handling when under high Rx load 851 */ 852 struct i40e_aqc_rx_ctl_reg_read_write { 853 __le32 reserved1; 854 __le32 address; 855 __le32 reserved2; 856 __le32 value; 857 }; 858 859 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 860 861 /* Add VSI (indirect 0x0210) 862 * this indirect command uses struct i40e_aqc_vsi_properties_data 863 * as the indirect buffer (128 bytes) 864 * 865 * Update VSI (indirect 0x211) 866 * uses the same data structure as Add VSI 867 * 868 * Get VSI (indirect 0x0212) 869 * uses the same completion and data structure as Add VSI 870 */ 871 struct i40e_aqc_add_get_update_vsi { 872 __le16 uplink_seid; 873 u8 connection_type; 874 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 875 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 876 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 877 u8 reserved1; 878 u8 vf_id; 879 u8 reserved2; 880 __le16 vsi_flags; 881 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 882 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 883 #define I40E_AQ_VSI_TYPE_VF 0x0 884 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 885 #define I40E_AQ_VSI_TYPE_PF 0x2 886 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 887 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 888 __le32 addr_high; 889 __le32 addr_low; 890 }; 891 892 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 893 894 struct i40e_aqc_add_get_update_vsi_completion { 895 __le16 seid; 896 __le16 vsi_number; 897 __le16 vsi_used; 898 __le16 vsi_free; 899 __le32 addr_high; 900 __le32 addr_low; 901 }; 902 903 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 904 905 struct i40e_aqc_vsi_properties_data { 906 /* first 96 byte are written by SW */ 907 __le16 valid_sections; 908 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 909 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 910 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 911 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 912 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 913 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 914 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 915 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 916 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 917 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 918 /* switch section */ 919 __le16 switch_id; /* 12bit id combined with flags below */ 920 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 921 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 922 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 923 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 924 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 925 u8 sw_reserved[2]; 926 /* security section */ 927 u8 sec_flags; 928 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 929 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 930 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 931 u8 sec_reserved; 932 /* VLAN section */ 933 __le16 pvid; /* VLANS include priority bits */ 934 __le16 outer_vlan; 935 u8 port_vlan_flags; 936 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 937 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 938 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 939 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 940 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 941 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 942 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 943 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 944 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 945 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 946 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 947 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 948 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 949 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 950 u8 outer_vlan_flags; 951 #define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00 952 #define I40E_AQ_VSI_OVLAN_MODE_MASK (0x03 << \ 953 I40E_AQ_VSI_OVLAN_MODE_SHIFT) 954 #define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED 0x01 955 #define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02 956 #define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03 957 #define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04 958 #define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03 959 #define I40E_AQ_VSI_OVLAN_EMOD_MASK (0x03 <<\ 960 I40E_AQ_VSI_OVLAN_EMOD_SHIFT) 961 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL 0x00 962 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01 963 #define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL 0x02 964 #define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03 965 #define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04 966 967 u8 pvlan_reserved[2]; 968 /* ingress egress up sections */ 969 __le32 ingress_table; /* bitmap, 3 bits per up */ 970 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 971 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 972 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 973 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 974 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 975 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 976 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 977 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 978 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 979 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 980 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 981 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 982 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 983 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 984 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 985 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 986 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 987 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 988 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 989 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 990 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 991 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 992 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 993 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 994 __le32 egress_table; /* same defines as for ingress table */ 995 /* cascaded PV section */ 996 __le16 cas_pv_tag; 997 u8 cas_pv_flags; 998 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 999 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 1000 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 1001 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 1002 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 1003 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 1004 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 1005 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 1006 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 1007 u8 cas_pv_reserved; 1008 /* queue mapping section */ 1009 __le16 mapping_flags; 1010 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 1011 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 1012 __le16 queue_mapping[16]; 1013 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 1014 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 1015 __le16 tc_mapping[8]; 1016 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 1017 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 1018 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 1019 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 1020 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 1021 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 1022 /* queueing option section */ 1023 u8 queueing_opt_flags; 1024 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 1025 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 1026 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 1027 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 1028 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 1029 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 1030 u8 queueing_opt_reserved[3]; 1031 /* scheduler section */ 1032 u8 up_enable_bits; 1033 u8 sched_reserved; 1034 /* outer up section */ 1035 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1036 u8 cmd_reserved[8]; 1037 /* last 32 bytes are written by FW */ 1038 __le16 qs_handle[8]; 1039 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1040 __le16 stat_counter_idx; 1041 __le16 sched_id; 1042 u8 resp_reserved[12]; 1043 }; 1044 1045 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1046 1047 /* Add Port Virtualizer (direct 0x0220) 1048 * also used for update PV (direct 0x0221) but only flags are used 1049 * (IS_CTRL_PORT only works on add PV) 1050 */ 1051 struct i40e_aqc_add_update_pv { 1052 __le16 command_flags; 1053 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1054 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1055 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1056 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1057 __le16 uplink_seid; 1058 __le16 connected_seid; 1059 u8 reserved[10]; 1060 }; 1061 1062 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1063 1064 struct i40e_aqc_add_update_pv_completion { 1065 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1066 __le16 pv_seid; 1067 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1068 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1069 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1070 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1071 u8 reserved[14]; 1072 }; 1073 1074 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1075 1076 /* Get PV Params (direct 0x0222) 1077 * uses i40e_aqc_switch_seid for the descriptor 1078 */ 1079 1080 struct i40e_aqc_get_pv_params_completion { 1081 __le16 seid; 1082 __le16 default_stag; 1083 __le16 pv_flags; /* same flags as add_pv */ 1084 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1085 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1086 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1087 u8 reserved[8]; 1088 __le16 default_port_seid; 1089 }; 1090 1091 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1092 1093 /* Add VEB (direct 0x0230) */ 1094 struct i40e_aqc_add_veb { 1095 __le16 uplink_seid; 1096 __le16 downlink_seid; 1097 __le16 veb_flags; 1098 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1099 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1100 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1101 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1102 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1103 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1104 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1105 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1106 u8 enable_tcs; 1107 u8 reserved[9]; 1108 }; 1109 1110 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1111 1112 struct i40e_aqc_add_veb_completion { 1113 u8 reserved[6]; 1114 __le16 switch_seid; 1115 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1116 __le16 veb_seid; 1117 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1118 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1119 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1120 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1121 __le16 statistic_index; 1122 __le16 vebs_used; 1123 __le16 vebs_free; 1124 }; 1125 1126 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1127 1128 /* Get VEB Parameters (direct 0x0232) 1129 * uses i40e_aqc_switch_seid for the descriptor 1130 */ 1131 struct i40e_aqc_get_veb_parameters_completion { 1132 __le16 seid; 1133 __le16 switch_id; 1134 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1135 __le16 statistic_index; 1136 __le16 vebs_used; 1137 __le16 vebs_free; 1138 u8 reserved[4]; 1139 }; 1140 1141 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1142 1143 /* Delete Element (direct 0x0243) 1144 * uses the generic i40e_aqc_switch_seid 1145 */ 1146 1147 /* Add MAC-VLAN (indirect 0x0250) */ 1148 1149 /* used for the command for most vlan commands */ 1150 struct i40e_aqc_macvlan { 1151 __le16 num_addresses; 1152 __le16 seid[3]; 1153 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1154 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1155 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1156 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1157 __le32 addr_high; 1158 __le32 addr_low; 1159 }; 1160 1161 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1162 1163 /* indirect data for command and response */ 1164 struct i40e_aqc_add_macvlan_element_data { 1165 u8 mac_addr[6]; 1166 __le16 vlan_tag; 1167 __le16 flags; 1168 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1169 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1170 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1171 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1172 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1173 __le16 queue_number; 1174 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1175 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1176 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1177 /* response section */ 1178 u8 match_method; 1179 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1180 #define I40E_AQC_MM_HASH_MATCH 0x02 1181 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1182 u8 reserved1[3]; 1183 }; 1184 1185 struct i40e_aqc_add_remove_macvlan_completion { 1186 __le16 perfect_mac_used; 1187 __le16 perfect_mac_free; 1188 __le16 unicast_hash_free; 1189 __le16 multicast_hash_free; 1190 __le32 addr_high; 1191 __le32 addr_low; 1192 }; 1193 1194 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1195 1196 /* Remove MAC-VLAN (indirect 0x0251) 1197 * uses i40e_aqc_macvlan for the descriptor 1198 * data points to an array of num_addresses of elements 1199 */ 1200 1201 struct i40e_aqc_remove_macvlan_element_data { 1202 u8 mac_addr[6]; 1203 __le16 vlan_tag; 1204 u8 flags; 1205 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1206 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1207 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1208 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1209 u8 reserved[3]; 1210 /* reply section */ 1211 u8 error_code; 1212 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1213 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1214 u8 reply_reserved[3]; 1215 }; 1216 1217 /* Add VLAN (indirect 0x0252) 1218 * Remove VLAN (indirect 0x0253) 1219 * use the generic i40e_aqc_macvlan for the command 1220 */ 1221 struct i40e_aqc_add_remove_vlan_element_data { 1222 __le16 vlan_tag; 1223 u8 vlan_flags; 1224 /* flags for add VLAN */ 1225 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1226 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1227 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1228 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1229 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1230 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1231 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1232 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1233 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1234 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1235 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1236 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1237 /* flags for remove VLAN */ 1238 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1239 u8 reserved; 1240 u8 result; 1241 /* flags for add VLAN */ 1242 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1243 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1244 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1245 /* flags for remove VLAN */ 1246 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1247 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1248 u8 reserved1[3]; 1249 }; 1250 1251 struct i40e_aqc_add_remove_vlan_completion { 1252 u8 reserved[4]; 1253 __le16 vlans_used; 1254 __le16 vlans_free; 1255 __le32 addr_high; 1256 __le32 addr_low; 1257 }; 1258 1259 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1260 struct i40e_aqc_set_vsi_promiscuous_modes { 1261 __le16 promiscuous_flags; 1262 __le16 valid_flags; 1263 /* flags used for both fields above */ 1264 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1265 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1266 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1267 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1268 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1269 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000 1270 __le16 seid; 1271 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1272 __le16 vlan_tag; 1273 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1274 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1275 u8 reserved[8]; 1276 }; 1277 1278 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1279 1280 /* Add S/E-tag command (direct 0x0255) 1281 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1282 */ 1283 struct i40e_aqc_add_tag { 1284 __le16 flags; 1285 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1286 __le16 seid; 1287 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1288 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1289 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1290 __le16 tag; 1291 __le16 queue_number; 1292 u8 reserved[8]; 1293 }; 1294 1295 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1296 1297 struct i40e_aqc_add_remove_tag_completion { 1298 u8 reserved[12]; 1299 __le16 tags_used; 1300 __le16 tags_free; 1301 }; 1302 1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1304 1305 /* Remove S/E-tag command (direct 0x0256) 1306 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1307 */ 1308 struct i40e_aqc_remove_tag { 1309 __le16 seid; 1310 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1311 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1312 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1313 __le16 tag; 1314 u8 reserved[12]; 1315 }; 1316 1317 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1318 1319 /* Add multicast E-Tag (direct 0x0257) 1320 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1321 * and no external data 1322 */ 1323 struct i40e_aqc_add_remove_mcast_etag { 1324 __le16 pv_seid; 1325 __le16 etag; 1326 u8 num_unicast_etags; 1327 u8 reserved[3]; 1328 __le32 addr_high; /* address of array of 2-byte s-tags */ 1329 __le32 addr_low; 1330 }; 1331 1332 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1333 1334 struct i40e_aqc_add_remove_mcast_etag_completion { 1335 u8 reserved[4]; 1336 __le16 mcast_etags_used; 1337 __le16 mcast_etags_free; 1338 __le32 addr_high; 1339 __le32 addr_low; 1340 1341 }; 1342 1343 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1344 1345 /* Update S/E-Tag (direct 0x0259) */ 1346 struct i40e_aqc_update_tag { 1347 __le16 seid; 1348 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1349 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1350 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1351 __le16 old_tag; 1352 __le16 new_tag; 1353 u8 reserved[10]; 1354 }; 1355 1356 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1357 1358 struct i40e_aqc_update_tag_completion { 1359 u8 reserved[12]; 1360 __le16 tags_used; 1361 __le16 tags_free; 1362 }; 1363 1364 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1365 1366 /* Add Control Packet filter (direct 0x025A) 1367 * Remove Control Packet filter (direct 0x025B) 1368 * uses the i40e_aqc_add_oveb_cloud, 1369 * and the generic direct completion structure 1370 */ 1371 struct i40e_aqc_add_remove_control_packet_filter { 1372 u8 mac[6]; 1373 __le16 etype; 1374 __le16 flags; 1375 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1376 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1377 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1378 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1379 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1380 __le16 seid; 1381 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1382 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1383 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1384 __le16 queue; 1385 u8 reserved[2]; 1386 }; 1387 1388 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1389 1390 struct i40e_aqc_add_remove_control_packet_filter_completion { 1391 __le16 mac_etype_used; 1392 __le16 etype_used; 1393 __le16 mac_etype_free; 1394 __le16 etype_free; 1395 u8 reserved[8]; 1396 }; 1397 1398 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1399 1400 /* Add Cloud filters (indirect 0x025C) 1401 * Remove Cloud filters (indirect 0x025D) 1402 * uses the i40e_aqc_add_remove_cloud_filters, 1403 * and the generic indirect completion structure 1404 */ 1405 struct i40e_aqc_add_remove_cloud_filters { 1406 u8 num_filters; 1407 u8 reserved; 1408 __le16 seid; 1409 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1410 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1411 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1412 u8 big_buffer_flag; 1413 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1 1414 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1415 u8 reserved2[3]; 1416 __le32 addr_high; 1417 __le32 addr_low; 1418 }; 1419 1420 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1421 1422 struct i40e_aqc_cloud_filters_element_data { 1423 u8 outer_mac[6]; 1424 u8 inner_mac[6]; 1425 __le16 inner_vlan; 1426 union { 1427 struct { 1428 u8 reserved[12]; 1429 u8 data[4]; 1430 } v4; 1431 struct { 1432 u8 data[16]; 1433 } v6; 1434 struct { 1435 __le16 data[8]; 1436 } raw_v6; 1437 } ipaddr; 1438 __le16 flags; 1439 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1440 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1441 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1442 /* 0x0000 reserved */ 1443 /* 0x0001 reserved */ 1444 /* 0x0002 reserved */ 1445 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1446 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1447 /* 0x0005 reserved */ 1448 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1449 /* 0x0007 reserved */ 1450 /* 0x0008 reserved */ 1451 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1452 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1453 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1454 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1455 #define I40E_AQC_ADD_CLOUD_FILTER_OIP1 0x0010 1456 #define I40E_AQC_ADD_CLOUD_FILTER_OIP2 0x0012 1457 /* 0x000D reserved */ 1458 /* 0x000E reserved */ 1459 /* 0x000F reserved */ 1460 /* 0x0010 to 0x0017 is for custom filters */ 1461 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1462 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1463 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1464 1465 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1466 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1467 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1468 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1469 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1470 1471 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1472 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1473 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1474 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1475 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1476 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1477 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1478 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1479 1480 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1481 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1482 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1483 1484 __le32 tenant_id; 1485 u8 reserved[4]; 1486 __le16 queue_number; 1487 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1488 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1489 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1490 u8 reserved2[14]; 1491 /* response section */ 1492 u8 allocation_result; 1493 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1494 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1495 u8 response_reserved[7]; 1496 }; 1497 1498 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when 1499 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. 1500 */ 1501 struct i40e_aqc_add_rm_cloud_filt_elem_ext { 1502 struct i40e_aqc_cloud_filters_element_data element; 1503 u16 general_fields[32]; 1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1514 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1515 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1516 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1517 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1518 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1519 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1520 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1521 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1522 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1523 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1524 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1525 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1526 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1527 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1528 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1529 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1530 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1531 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1532 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1533 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1534 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1535 }; 1536 1537 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1538 1539 /* i40e_aqc_cloud_filters_element_bb is used when 1540 * I40E_AQC_CLOUD_CMD_BB flag is set. 1541 */ 1542 struct i40e_aqc_cloud_filters_element_bb { 1543 struct i40e_aqc_cloud_filters_element_data element; 1544 u16 general_fields[32]; 1545 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1546 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1547 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1548 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1549 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1550 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1551 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1552 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1553 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1554 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1555 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1556 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1557 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1558 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1559 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1560 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1561 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1562 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1563 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1564 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1565 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1566 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1567 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1568 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1569 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1570 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1571 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1572 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1573 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1574 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1575 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1576 }; 1577 1578 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1579 1580 struct i40e_aqc_remove_cloud_filters_completion { 1581 __le16 perfect_ovlan_used; 1582 __le16 perfect_ovlan_free; 1583 __le16 vlan_used; 1584 __le16 vlan_free; 1585 __le32 addr_high; 1586 __le32 addr_low; 1587 }; 1588 1589 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1590 1591 /* Replace filter Command 0x025F 1592 * uses the i40e_aqc_replace_cloud_filters, 1593 * and the generic indirect completion structure 1594 */ 1595 struct i40e_filter_data { 1596 u8 filter_type; 1597 u8 input[3]; 1598 }; 1599 1600 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1601 1602 struct i40e_aqc_replace_cloud_filters_cmd { 1603 u8 valid_flags; 1604 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1605 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1606 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1607 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1608 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1609 u8 old_filter_type; 1610 u8 new_filter_type; 1611 u8 tr_bit; 1612 u8 tr_bit2; 1613 u8 reserved[3]; 1614 __le32 addr_high; 1615 __le32 addr_low; 1616 }; 1617 1618 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1619 1620 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1621 u8 data[32]; 1622 /* Filter type INPUT codes*/ 1623 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1624 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL) 1625 1626 /* Field Vector offsets */ 1627 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1628 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1629 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1630 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1631 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1632 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1633 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1634 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1635 /* big FLU */ 1636 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1637 /* big FLU */ 1638 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1639 1640 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1641 struct i40e_filter_data filters[8]; 1642 }; 1643 1644 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1645 1646 /* Add Mirror Rule (indirect or direct 0x0260) 1647 * Delete Mirror Rule (indirect or direct 0x0261) 1648 * note: some rule types (4,5) do not use an external buffer. 1649 * take care to set the flags correctly. 1650 */ 1651 struct i40e_aqc_add_delete_mirror_rule { 1652 __le16 seid; 1653 __le16 rule_type; 1654 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1655 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1656 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1657 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1658 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1659 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1660 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1661 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1662 __le16 num_entries; 1663 __le16 destination; /* VSI for add, rule id for delete */ 1664 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1665 __le32 addr_low; 1666 }; 1667 1668 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1669 1670 struct i40e_aqc_add_delete_mirror_rule_completion { 1671 u8 reserved[2]; 1672 __le16 rule_id; /* only used on add */ 1673 __le16 mirror_rules_used; 1674 __le16 mirror_rules_free; 1675 __le32 addr_high; 1676 __le32 addr_low; 1677 }; 1678 1679 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1680 1681 /* DCB 0x03xx*/ 1682 1683 /* PFC Ignore (direct 0x0301) 1684 * the command and response use the same descriptor structure 1685 */ 1686 struct i40e_aqc_pfc_ignore { 1687 u8 tc_bitmap; 1688 u8 command_flags; /* unused on response */ 1689 #define I40E_AQC_PFC_IGNORE_SET 0x80 1690 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1691 u8 reserved[14]; 1692 }; 1693 1694 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1695 1696 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1697 * with no parameters 1698 */ 1699 1700 /* TX scheduler 0x04xx */ 1701 1702 /* Almost all the indirect commands use 1703 * this generic struct to pass the SEID in param0 1704 */ 1705 struct i40e_aqc_tx_sched_ind { 1706 __le16 vsi_seid; 1707 u8 reserved[6]; 1708 __le32 addr_high; 1709 __le32 addr_low; 1710 }; 1711 1712 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1713 1714 /* Several commands respond with a set of queue set handles */ 1715 struct i40e_aqc_qs_handles_resp { 1716 __le16 qs_handles[8]; 1717 }; 1718 1719 /* Configure VSI BW limits (direct 0x0400) */ 1720 struct i40e_aqc_configure_vsi_bw_limit { 1721 __le16 vsi_seid; 1722 u8 reserved[2]; 1723 __le16 credit; 1724 u8 reserved1[2]; 1725 u8 max_credit; /* 0-3, limit = 2^max */ 1726 u8 reserved2[7]; 1727 }; 1728 1729 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1730 1731 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1732 * responds with i40e_aqc_qs_handles_resp 1733 */ 1734 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1735 u8 tc_valid_bits; 1736 u8 reserved[15]; 1737 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1738 1739 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1740 __le16 tc_bw_max[2]; 1741 u8 reserved1[28]; 1742 }; 1743 1744 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1745 1746 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1747 * responds with i40e_aqc_qs_handles_resp 1748 */ 1749 struct i40e_aqc_configure_vsi_tc_bw_data { 1750 u8 tc_valid_bits; 1751 u8 reserved[3]; 1752 u8 tc_bw_credits[8]; 1753 u8 reserved1[4]; 1754 __le16 qs_handles[8]; 1755 }; 1756 1757 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1758 1759 /* Query vsi bw configuration (indirect 0x0408) */ 1760 struct i40e_aqc_query_vsi_bw_config_resp { 1761 u8 tc_valid_bits; 1762 u8 tc_suspended_bits; 1763 u8 reserved[14]; 1764 __le16 qs_handles[8]; 1765 u8 reserved1[4]; 1766 __le16 port_bw_limit; 1767 u8 reserved2[2]; 1768 u8 max_bw; /* 0-3, limit = 2^max */ 1769 u8 reserved3[23]; 1770 }; 1771 1772 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1773 1774 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1775 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1776 u8 tc_valid_bits; 1777 u8 reserved[3]; 1778 u8 share_credits[8]; 1779 __le16 credits[8]; 1780 1781 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1782 __le16 tc_bw_max[2]; 1783 }; 1784 1785 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1786 1787 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1788 struct i40e_aqc_configure_switching_comp_bw_limit { 1789 __le16 seid; 1790 u8 reserved[2]; 1791 __le16 credit; 1792 u8 reserved1[2]; 1793 u8 max_bw; /* 0-3, limit = 2^max */ 1794 u8 reserved2[7]; 1795 }; 1796 1797 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1798 1799 /* Enable Physical Port ETS (indirect 0x0413) 1800 * Modify Physical Port ETS (indirect 0x0414) 1801 * Disable Physical Port ETS (indirect 0x0415) 1802 */ 1803 struct i40e_aqc_configure_switching_comp_ets_data { 1804 u8 reserved[4]; 1805 u8 tc_valid_bits; 1806 u8 seepage; 1807 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1808 u8 tc_strict_priority_flags; 1809 u8 reserved1[17]; 1810 u8 tc_bw_share_credits[8]; 1811 u8 reserved2[96]; 1812 }; 1813 1814 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1815 1816 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1817 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1818 u8 tc_valid_bits; 1819 u8 reserved[15]; 1820 __le16 tc_bw_credit[8]; 1821 1822 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1823 __le16 tc_bw_max[2]; 1824 u8 reserved1[28]; 1825 }; 1826 1827 I40E_CHECK_STRUCT_LEN(0x40, 1828 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1829 1830 /* Configure Switching Component Bandwidth Allocation per Tc 1831 * (indirect 0x0417) 1832 */ 1833 struct i40e_aqc_configure_switching_comp_bw_config_data { 1834 u8 tc_valid_bits; 1835 u8 reserved[2]; 1836 u8 absolute_credits; /* bool */ 1837 u8 tc_bw_share_credits[8]; 1838 u8 reserved1[20]; 1839 }; 1840 1841 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1842 1843 /* Query Switching Component Configuration (indirect 0x0418) */ 1844 struct i40e_aqc_query_switching_comp_ets_config_resp { 1845 u8 tc_valid_bits; 1846 u8 reserved[35]; 1847 __le16 port_bw_limit; 1848 u8 reserved1[2]; 1849 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1850 u8 reserved2[23]; 1851 }; 1852 1853 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1854 1855 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1856 struct i40e_aqc_query_port_ets_config_resp { 1857 u8 reserved[4]; 1858 u8 tc_valid_bits; 1859 u8 reserved1; 1860 u8 tc_strict_priority_bits; 1861 u8 reserved2; 1862 u8 tc_bw_share_credits[8]; 1863 __le16 tc_bw_limits[8]; 1864 1865 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1866 __le16 tc_bw_max[2]; 1867 u8 reserved3[32]; 1868 }; 1869 1870 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1871 1872 /* Query Switching Component Bandwidth Allocation per Traffic Type 1873 * (indirect 0x041A) 1874 */ 1875 struct i40e_aqc_query_switching_comp_bw_config_resp { 1876 u8 tc_valid_bits; 1877 u8 reserved[2]; 1878 u8 absolute_credits_enable; /* bool */ 1879 u8 tc_bw_share_credits[8]; 1880 __le16 tc_bw_limits[8]; 1881 1882 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1883 __le16 tc_bw_max[2]; 1884 }; 1885 1886 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1887 1888 /* Suspend/resume port TX traffic 1889 * (direct 0x041B and 0x041C) uses the generic SEID struct 1890 */ 1891 1892 /* Configure partition BW 1893 * (indirect 0x041D) 1894 */ 1895 struct i40e_aqc_configure_partition_bw_data { 1896 __le16 pf_valid_bits; 1897 u8 min_bw[16]; /* guaranteed bandwidth */ 1898 u8 max_bw[16]; /* bandwidth limit */ 1899 }; 1900 1901 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1902 1903 /* Get and set the active HMC resource profile and status. 1904 * (direct 0x0500) and (direct 0x0501) 1905 */ 1906 struct i40e_aq_get_set_hmc_resource_profile { 1907 u8 pm_profile; 1908 u8 pe_vf_enabled; 1909 u8 reserved[14]; 1910 }; 1911 1912 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1913 1914 enum i40e_aq_hmc_profile { 1915 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1916 I40E_HMC_PROFILE_DEFAULT = 1, 1917 I40E_HMC_PROFILE_FAVOR_VF = 2, 1918 I40E_HMC_PROFILE_EQUAL = 3, 1919 }; 1920 1921 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1922 1923 /* set in param0 for get phy abilities to report qualified modules */ 1924 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1925 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1926 1927 enum i40e_aq_phy_type { 1928 I40E_PHY_TYPE_SGMII = 0x0, 1929 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1930 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1931 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1932 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1933 I40E_PHY_TYPE_XAUI = 0x5, 1934 I40E_PHY_TYPE_XFI = 0x6, 1935 I40E_PHY_TYPE_SFI = 0x7, 1936 I40E_PHY_TYPE_XLAUI = 0x8, 1937 I40E_PHY_TYPE_XLPPI = 0x9, 1938 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1939 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1940 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1941 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1942 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1943 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1944 I40E_PHY_TYPE_100BASE_TX = 0x11, 1945 I40E_PHY_TYPE_1000BASE_T = 0x12, 1946 I40E_PHY_TYPE_10GBASE_T = 0x13, 1947 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1948 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1949 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1950 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1951 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1952 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1953 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1954 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1955 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1956 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1957 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1958 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1959 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1960 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1961 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1962 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1963 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1964 I40E_PHY_TYPE_2_5GBASE_T = 0x26, 1965 I40E_PHY_TYPE_5GBASE_T = 0x27, 1966 I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30, 1967 I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31, 1968 I40E_PHY_TYPE_MAX, 1969 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1970 I40E_PHY_TYPE_EMPTY = 0xFE, 1971 I40E_PHY_TYPE_DEFAULT = 0xFF, 1972 }; 1973 1974 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1975 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1976 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1977 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1978 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1979 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1980 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1981 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1982 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1983 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1984 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1985 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1986 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1987 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1988 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1989 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1990 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1991 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1992 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1993 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1994 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1995 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1996 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1997 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1998 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1999 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 2000 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 2001 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 2002 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 2003 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 2004 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 2005 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 2006 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 2007 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 2008 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 2009 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 2010 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 2011 BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 2012 2013 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 2014 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 2015 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 2016 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 2017 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 2018 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 2019 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 2020 #define I40E_LINK_SPEED_5GB_SHIFT 0x7 2021 2022 enum i40e_aq_link_speed { 2023 I40E_LINK_SPEED_UNKNOWN = 0, 2024 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 2025 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 2026 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 2027 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 2028 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 2029 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 2030 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 2031 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 2032 }; 2033 2034 struct i40e_aqc_module_desc { 2035 u8 oui[3]; 2036 u8 reserved1; 2037 u8 part_number[16]; 2038 u8 revision[4]; 2039 u8 reserved2[8]; 2040 }; 2041 2042 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 2043 2044 struct i40e_aq_get_phy_abilities_resp { 2045 __le32 phy_type; /* bitmap using the above enum for offsets */ 2046 u8 link_speed; /* bitmap using the above enum bit patterns */ 2047 u8 abilities; 2048 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 2049 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 2050 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 2051 #define I40E_AQ_PHY_LINK_ENABLED 0x08 2052 #define I40E_AQ_PHY_AN_ENABLED 0x10 2053 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 2054 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 2055 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 2056 __le16 eee_capability; 2057 #define I40E_AQ_EEE_AUTO 0x0001 2058 #define I40E_AQ_EEE_100BASE_TX 0x0002 2059 #define I40E_AQ_EEE_1000BASE_T 0x0004 2060 #define I40E_AQ_EEE_10GBASE_T 0x0008 2061 #define I40E_AQ_EEE_1000BASE_KX 0x0010 2062 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 2063 #define I40E_AQ_EEE_10GBASE_KR 0x0040 2064 #define I40E_AQ_EEE_2_5GBASE_T 0x0100 2065 #define I40E_AQ_EEE_5GBASE_T 0x0200 2066 __le32 eeer_val; 2067 u8 d3_lpan; 2068 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 2069 u8 phy_type_ext; 2070 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 2071 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 2072 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2073 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2074 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 2075 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 2076 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 2077 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 2078 u8 fec_cfg_curr_mod_ext_info; 2079 #define I40E_AQ_ENABLE_FEC_KR 0x01 2080 #define I40E_AQ_ENABLE_FEC_RS 0x02 2081 #define I40E_AQ_REQUEST_FEC_KR 0x04 2082 #define I40E_AQ_REQUEST_FEC_RS 0x08 2083 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 2084 #define I40E_AQ_FEC 2085 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 2086 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 2087 2088 u8 ext_comp_code; 2089 u8 phy_id[4]; 2090 u8 module_type[3]; 2091 u8 qualified_module_count; 2092 #define I40E_AQ_PHY_MAX_QMS 16 2093 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2094 }; 2095 2096 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2097 2098 /* Set PHY Config (direct 0x0601) */ 2099 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2100 __le32 phy_type; 2101 u8 link_speed; 2102 u8 abilities; 2103 /* bits 0-2 use the values from get_phy_abilities_resp */ 2104 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2105 #define I40E_AQ_PHY_ENABLE_AN 0x10 2106 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2107 __le16 eee_capability; 2108 __le32 eeer; 2109 u8 low_power_ctrl; 2110 u8 phy_type_ext; 2111 u8 fec_config; 2112 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2113 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2114 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2115 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2116 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2117 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2118 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2119 u8 reserved; 2120 }; 2121 2122 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2123 2124 /* Set MAC Config command data structure (direct 0x0603) */ 2125 struct i40e_aq_set_mac_config { 2126 __le16 max_frame_size; 2127 u8 params; 2128 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2129 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2130 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2131 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2132 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2133 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2134 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2135 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2136 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2137 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2138 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2139 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2140 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2141 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2142 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80 2143 u8 tx_timer_priority; /* bitmap */ 2144 __le16 tx_timer_value; 2145 __le16 fc_refresh_threshold; 2146 u8 reserved[8]; 2147 }; 2148 2149 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2150 2151 /* Restart Auto-Negotiation (direct 0x605) */ 2152 struct i40e_aqc_set_link_restart_an { 2153 u8 command; 2154 #define I40E_AQ_PHY_RESTART_AN 0x02 2155 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2156 u8 reserved[15]; 2157 }; 2158 2159 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2160 2161 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2162 struct i40e_aqc_get_link_status { 2163 __le16 command_flags; /* only field set on command */ 2164 #define I40E_AQ_LSE_MASK 0x3 2165 #define I40E_AQ_LSE_NOP 0x0 2166 #define I40E_AQ_LSE_DISABLE 0x2 2167 #define I40E_AQ_LSE_ENABLE 0x3 2168 /* only response uses this flag */ 2169 #define I40E_AQ_LSE_IS_ENABLED 0x1 2170 u8 phy_type; /* i40e_aq_phy_type */ 2171 u8 link_speed; /* i40e_aq_link_speed */ 2172 u8 link_info; 2173 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2174 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2175 #define I40E_AQ_LINK_FAULT 0x02 2176 #define I40E_AQ_LINK_FAULT_TX 0x04 2177 #define I40E_AQ_LINK_FAULT_RX 0x08 2178 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2179 #define I40E_AQ_LINK_UP_PORT 0x20 2180 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2181 #define I40E_AQ_SIGNAL_DETECT 0x80 2182 u8 an_info; 2183 #define I40E_AQ_AN_COMPLETED 0x01 2184 #define I40E_AQ_LP_AN_ABILITY 0x02 2185 #define I40E_AQ_PD_FAULT 0x04 2186 #define I40E_AQ_FEC_EN 0x08 2187 #define I40E_AQ_PHY_LOW_POWER 0x10 2188 #define I40E_AQ_LINK_PAUSE_TX 0x20 2189 #define I40E_AQ_LINK_PAUSE_RX 0x40 2190 #define I40E_AQ_QUALIFIED_MODULE 0x80 2191 u8 ext_info; 2192 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2193 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2194 #define I40E_AQ_LINK_TX_SHIFT 0x02 2195 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2196 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2197 #define I40E_AQ_LINK_TX_DRAINED 0x01 2198 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2199 #define I40E_AQ_LINK_FORCED_40G 0x10 2200 /* 25G Error Codes */ 2201 #define I40E_AQ_25G_NO_ERR 0X00 2202 #define I40E_AQ_25G_NOT_PRESENT 0X01 2203 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2204 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2205 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2206 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2207 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2208 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2209 #define I40E_AQ_LOOPBACK_MASK 0x07 2210 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2211 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2212 __le16 max_frame_size; 2213 u8 config; 2214 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2215 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2216 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2217 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2218 union { 2219 struct { 2220 u8 power_desc; 2221 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2222 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2223 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2224 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2225 #define I40E_AQ_PWR_CLASS_MASK 0x03 2226 u8 reserved[4]; 2227 }; 2228 struct { 2229 u8 link_type[4]; 2230 u8 link_type_ext; 2231 }; 2232 }; 2233 }; 2234 2235 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2236 2237 /* Set event mask command (direct 0x613) */ 2238 struct i40e_aqc_set_phy_int_mask { 2239 u8 reserved[8]; 2240 __le16 event_mask; 2241 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2242 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2243 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2244 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2245 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2246 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2247 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2248 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2249 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2250 u8 reserved1[6]; 2251 }; 2252 2253 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2254 2255 /* Get Local AN advt register (direct 0x0614) 2256 * Set Local AN advt register (direct 0x0615) 2257 * Get Link Partner AN advt register (direct 0x0616) 2258 */ 2259 struct i40e_aqc_an_advt_reg { 2260 __le32 local_an_reg0; 2261 __le16 local_an_reg1; 2262 u8 reserved[10]; 2263 }; 2264 2265 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2266 2267 /* Set Loopback mode (0x0618) */ 2268 struct i40e_aqc_set_lb_mode { 2269 u8 lb_level; 2270 #define I40E_AQ_LB_NONE 0 2271 #define I40E_AQ_LB_MAC 1 2272 #define I40E_AQ_LB_SERDES 2 2273 #define I40E_AQ_LB_PHY_INT 3 2274 #define I40E_AQ_LB_PHY_EXT 4 2275 #define I40E_AQ_LB_BASE_T_PCS 5 2276 #define I40E_AQ_LB_BASE_T_EXT 6 2277 #define I40E_AQ_LB_PHY_LOCAL 0x01 2278 #define I40E_AQ_LB_PHY_REMOTE 0x02 2279 #define I40E_AQ_LB_MAC_LOCAL 0x04 2280 u8 lb_type; 2281 #define I40E_AQ_LB_LOCAL 0 2282 #define I40E_AQ_LB_FAR 0x01 2283 u8 speed; 2284 #define I40E_AQ_LB_SPEED_NONE 0 2285 #define I40E_AQ_LB_SPEED_1G 1 2286 #define I40E_AQ_LB_SPEED_10G 2 2287 #define I40E_AQ_LB_SPEED_40G 3 2288 #define I40E_AQ_LB_SPEED_20G 4 2289 u8 force_speed; 2290 u8 reserved[12]; 2291 }; 2292 2293 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2294 2295 /* Set PHY Debug command (0x0622) */ 2296 struct i40e_aqc_set_phy_debug { 2297 u8 command_flags; 2298 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2299 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2300 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2301 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2302 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2303 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2304 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2305 /* Disable link manageability on a single port */ 2306 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2307 /* Disable link manageability on all ports needs both bits 4 and 5 */ 2308 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2309 u8 reserved[15]; 2310 }; 2311 2312 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2313 2314 enum i40e_aq_phy_reg_type { 2315 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2316 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2317 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2318 }; 2319 2320 #pragma pack(1) 2321 /* Run PHY Activity (0x0626) */ 2322 struct i40e_aqc_run_phy_activity { 2323 u8 cmd_flags; 2324 __le16 activity_id; 2325 #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10 2326 u8 reserved; 2327 union { 2328 struct { 2329 __le32 dnl_opcode; 2330 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a 2331 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b 2332 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b 2333 __le32 data; 2334 u8 reserved2[4]; 2335 } cmd; 2336 struct { 2337 __le32 cmd_status; 2338 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4 2339 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF 2340 __le32 data0; 2341 __le32 data1; 2342 } resp; 2343 } params; 2344 }; 2345 #pragma pack() 2346 2347 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2348 2349 /* Set PHY Register command (0x0628) */ 2350 /* Get PHY Register command (0x0629) */ 2351 struct i40e_aqc_phy_register_access { 2352 u8 phy_interface; 2353 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2354 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2355 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2356 u8 dev_addres; 2357 u8 cmd_flags; 2358 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01 2359 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02 2360 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2 2361 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \ 2362 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) 2363 u8 reserved1; 2364 __le32 reg_address; 2365 __le32 reg_value; 2366 u8 reserved2[4]; 2367 }; 2368 2369 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2370 2371 /* NVM Read command (indirect 0x0701) 2372 * NVM Erase commands (direct 0x0702) 2373 * NVM Update commands (indirect 0x0703) 2374 */ 2375 struct i40e_aqc_nvm_update { 2376 u8 command_flags; 2377 #define I40E_AQ_NVM_LAST_CMD 0x01 2378 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2379 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2380 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2381 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2382 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2383 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2384 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2385 u8 module_pointer; 2386 __le16 length; 2387 __le32 offset; 2388 __le32 addr_high; 2389 __le32 addr_low; 2390 }; 2391 2392 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2393 2394 /* NVM Config Read (indirect 0x0704) */ 2395 struct i40e_aqc_nvm_config_read { 2396 __le16 cmd_flags; 2397 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2398 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2399 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2400 __le16 element_count; 2401 __le16 element_id; /* Feature/field ID */ 2402 __le16 element_id_msw; /* MSWord of field ID */ 2403 __le32 address_high; 2404 __le32 address_low; 2405 }; 2406 2407 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2408 2409 /* NVM Config Write (indirect 0x0705) */ 2410 struct i40e_aqc_nvm_config_write { 2411 __le16 cmd_flags; 2412 __le16 element_count; 2413 u8 reserved[4]; 2414 __le32 address_high; 2415 __le32 address_low; 2416 }; 2417 2418 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2419 2420 /* Used for 0x0704 as well as for 0x0705 commands */ 2421 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2422 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2423 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2424 #define I40E_AQ_ANVM_FEATURE 0 2425 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2426 struct i40e_aqc_nvm_config_data_feature { 2427 __le16 feature_id; 2428 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2429 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2430 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2431 __le16 feature_options; 2432 __le16 feature_selection; 2433 }; 2434 2435 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2436 2437 /* NVM Update in Process (direct 0x0706) */ 2438 struct i40e_aqc_nvm_update_in_process { 2439 u8 command; 2440 #define I40E_AQ_UPDATE_FLOW_END 0x0 2441 #define I40E_AQ_UPDATE_FLOW_START 0x1 2442 u8 reserved[15]; 2443 }; 2444 2445 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update_in_process); 2446 2447 struct i40e_aqc_nvm_config_data_immediate_field { 2448 __le32 field_id; 2449 __le32 field_value; 2450 __le16 field_options; 2451 __le16 reserved; 2452 }; 2453 2454 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2455 2456 /* Minimal Rollback Revision Update (direct 0x0707) */ 2457 struct i40e_aqc_rollback_revision_update { 2458 u8 optin_mode; /* bool */ 2459 #define I40E_AQ_RREV_OPTIN_MODE 0x01 2460 u8 module_selected; 2461 #define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 2462 #define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 2463 #define I40E_AQ_RREV_MODULE_OPTION_ROM 2 2464 #define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 2465 #define I40E_AQ_RREV_MODULE_PE_IMAGE 4 2466 #define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION 5 2467 #define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION 6 2468 #define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION 7 2469 #define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION 8 2470 u8 reserved1[2]; 2471 u32 min_rrev; 2472 u8 reserved2[8]; 2473 }; 2474 2475 I40E_CHECK_CMD_LENGTH(i40e_aqc_rollback_revision_update); 2476 2477 /* OEM Post Update (indirect 0x0720) 2478 * no command data struct used 2479 */ 2480 struct i40e_aqc_nvm_oem_post_update { 2481 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2482 u8 sel_data; 2483 u8 reserved[7]; 2484 }; 2485 2486 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2487 2488 struct i40e_aqc_nvm_oem_post_update_buffer { 2489 u8 str_len; 2490 u8 dev_addr; 2491 __le16 eeprom_addr; 2492 u8 data[36]; 2493 }; 2494 2495 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2496 2497 /* Thermal Sensor (indirect 0x0721) 2498 * read or set thermal sensor configs and values 2499 * takes a sensor and command specific data buffer, not detailed here 2500 */ 2501 struct i40e_aqc_thermal_sensor { 2502 u8 sensor_action; 2503 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2504 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2505 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2506 u8 reserved[7]; 2507 __le32 addr_high; 2508 __le32 addr_low; 2509 }; 2510 2511 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2512 2513 /* Send to PF command (indirect 0x0801) id is only used by PF 2514 * Send to VF command (indirect 0x0802) id is only used by PF 2515 * Send to Peer PF command (indirect 0x0803) 2516 */ 2517 struct i40e_aqc_pf_vf_message { 2518 __le32 id; 2519 u8 reserved[4]; 2520 __le32 addr_high; 2521 __le32 addr_low; 2522 }; 2523 2524 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2525 2526 /* Alternate structure */ 2527 2528 /* Direct write (direct 0x0900) 2529 * Direct read (direct 0x0902) 2530 */ 2531 struct i40e_aqc_alternate_write { 2532 __le32 address0; 2533 __le32 data0; 2534 __le32 address1; 2535 __le32 data1; 2536 }; 2537 2538 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2539 2540 /* Indirect write (indirect 0x0901) 2541 * Indirect read (indirect 0x0903) 2542 */ 2543 2544 struct i40e_aqc_alternate_ind_write { 2545 __le32 address; 2546 __le32 length; 2547 __le32 addr_high; 2548 __le32 addr_low; 2549 }; 2550 2551 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2552 2553 /* Done alternate write (direct 0x0904) 2554 * uses i40e_aq_desc 2555 */ 2556 struct i40e_aqc_alternate_write_done { 2557 __le16 cmd_flags; 2558 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2559 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2560 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2561 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2562 u8 reserved[14]; 2563 }; 2564 2565 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2566 2567 /* Set OEM mode (direct 0x0905) */ 2568 struct i40e_aqc_alternate_set_mode { 2569 __le32 mode; 2570 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2571 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2572 u8 reserved[12]; 2573 }; 2574 2575 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2576 2577 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2578 2579 /* async events 0x10xx */ 2580 2581 /* Lan Queue Overflow Event (direct, 0x1001) */ 2582 struct i40e_aqc_lan_overflow { 2583 __le32 prtdcb_rupto; 2584 __le32 otx_ctl; 2585 u8 reserved[8]; 2586 }; 2587 2588 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2589 2590 /* Get LLDP MIB (indirect 0x0A00) */ 2591 struct i40e_aqc_lldp_get_mib { 2592 u8 type; 2593 u8 reserved1; 2594 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2595 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2596 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2597 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2598 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2599 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2600 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2601 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2602 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2603 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2604 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2605 __le16 local_len; 2606 __le16 remote_len; 2607 u8 reserved2[2]; 2608 __le32 addr_high; 2609 __le32 addr_low; 2610 }; 2611 2612 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2613 2614 /* Configure LLDP MIB Change Event (direct 0x0A01) 2615 * also used for the event (with type in the command field) 2616 */ 2617 struct i40e_aqc_lldp_update_mib { 2618 u8 command; 2619 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2620 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2621 u8 reserved[7]; 2622 __le32 addr_high; 2623 __le32 addr_low; 2624 }; 2625 2626 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2627 2628 /* Add LLDP TLV (indirect 0x0A02) 2629 * Delete LLDP TLV (indirect 0x0A04) 2630 */ 2631 struct i40e_aqc_lldp_add_tlv { 2632 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2633 u8 reserved1[1]; 2634 __le16 len; 2635 u8 reserved2[4]; 2636 __le32 addr_high; 2637 __le32 addr_low; 2638 }; 2639 2640 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2641 2642 /* Update LLDP TLV (indirect 0x0A03) */ 2643 struct i40e_aqc_lldp_update_tlv { 2644 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2645 u8 reserved; 2646 __le16 old_len; 2647 __le16 new_offset; 2648 __le16 new_len; 2649 __le32 addr_high; 2650 __le32 addr_low; 2651 }; 2652 2653 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2654 2655 /* Stop LLDP (direct 0x0A05) */ 2656 struct i40e_aqc_lldp_stop { 2657 u8 command; 2658 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2659 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2660 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2661 u8 reserved[15]; 2662 }; 2663 2664 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2665 2666 /* Start LLDP (direct 0x0A06) */ 2667 struct i40e_aqc_lldp_start { 2668 u8 command; 2669 #define I40E_AQ_LLDP_AGENT_START 0x1 2670 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 2671 u8 reserved[15]; 2672 }; 2673 2674 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2675 2676 /* Set DCB (direct 0x0303) */ 2677 struct i40e_aqc_set_dcb_parameters { 2678 u8 command; 2679 #define I40E_AQ_DCB_SET_AGENT 0x1 2680 #define I40E_DCB_VALID 0x1 2681 u8 valid_flags; 2682 u8 reserved[14]; 2683 }; 2684 2685 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2686 2687 /* Get CEE DCBX Oper Config (0x0A07) 2688 * uses the generic descriptor struct 2689 * returns below as indirect response 2690 */ 2691 2692 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2693 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2694 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2695 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2696 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2697 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2698 2699 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2700 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2701 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2702 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2703 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2704 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2705 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2706 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2707 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2708 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2709 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2710 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2711 2712 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2713 * word boundary layout issues, which the Linux compilers silently deal 2714 * with by adding padding, making the actual struct larger than designed. 2715 * However, the FW compiler for the NIC is less lenient and complains 2716 * about the struct. Hence, the struct defined here has an extra byte in 2717 * fields reserved3 and reserved4 to directly acknowledge that padding, 2718 * and the new length is used in the length check macro. 2719 */ 2720 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2721 u8 reserved1; 2722 u8 oper_num_tc; 2723 u8 oper_prio_tc[4]; 2724 u8 reserved2; 2725 u8 oper_tc_bw[8]; 2726 u8 oper_pfc_en; 2727 u8 reserved3[2]; 2728 __le16 oper_app_prio; 2729 u8 reserved4[2]; 2730 __le16 tlv_status; 2731 }; 2732 2733 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2734 2735 struct i40e_aqc_get_cee_dcb_cfg_resp { 2736 u8 oper_num_tc; 2737 u8 oper_prio_tc[4]; 2738 u8 oper_tc_bw[8]; 2739 u8 oper_pfc_en; 2740 __le16 oper_app_prio; 2741 __le32 tlv_status; 2742 u8 reserved[12]; 2743 }; 2744 2745 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2746 2747 /* Set Local LLDP MIB (indirect 0x0A08) 2748 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2749 */ 2750 struct i40e_aqc_lldp_set_local_mib { 2751 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2752 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2753 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2754 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2755 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2756 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2757 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2758 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2759 u8 type; 2760 u8 reserved0; 2761 __le16 length; 2762 u8 reserved1[4]; 2763 __le32 address_high; 2764 __le32 address_low; 2765 }; 2766 2767 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2768 2769 struct i40e_aqc_lldp_set_local_mib_resp { 2770 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2771 u8 status; 2772 u8 reserved[15]; 2773 }; 2774 2775 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2776 2777 /* Stop/Start LLDP Agent (direct 0x0A09) 2778 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2779 */ 2780 struct i40e_aqc_lldp_stop_start_specific_agent { 2781 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2782 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2783 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2784 u8 command; 2785 u8 reserved[15]; 2786 }; 2787 2788 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2789 2790 /* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2791 struct i40e_aqc_lldp_restore { 2792 u8 command; 2793 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2794 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2795 u8 reserved[15]; 2796 }; 2797 2798 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2799 2800 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2801 struct i40e_aqc_add_udp_tunnel { 2802 __le16 udp_port; 2803 u8 reserved0[3]; 2804 u8 protocol_type; 2805 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2806 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2807 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2808 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2809 u8 reserved1[10]; 2810 }; 2811 2812 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2813 2814 struct i40e_aqc_add_udp_tunnel_completion { 2815 __le16 udp_port; 2816 u8 filter_entry_index; 2817 u8 multiple_pfs; 2818 #define I40E_AQC_SINGLE_PF 0x0 2819 #define I40E_AQC_MULTIPLE_PFS 0x1 2820 u8 total_filters; 2821 u8 reserved[11]; 2822 }; 2823 2824 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2825 2826 /* remove UDP Tunnel command (0x0B01) */ 2827 struct i40e_aqc_remove_udp_tunnel { 2828 u8 reserved[2]; 2829 u8 index; /* 0 to 15 */ 2830 u8 reserved2[13]; 2831 }; 2832 2833 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2834 2835 struct i40e_aqc_del_udp_tunnel_completion { 2836 __le16 udp_port; 2837 u8 index; /* 0 to 15 */ 2838 u8 multiple_pfs; 2839 u8 total_filters_used; 2840 u8 reserved1[11]; 2841 }; 2842 2843 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2844 2845 struct i40e_aqc_get_set_rss_key { 2846 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2847 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2848 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2849 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2850 __le16 vsi_id; 2851 u8 reserved[6]; 2852 __le32 addr_high; 2853 __le32 addr_low; 2854 }; 2855 2856 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2857 2858 struct i40e_aqc_get_set_rss_key_data { 2859 u8 standard_rss_key[0x28]; 2860 u8 extended_hash_key[0xc]; 2861 }; 2862 2863 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2864 2865 struct i40e_aqc_get_set_rss_lut { 2866 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2867 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2868 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2869 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2870 __le16 vsi_id; 2871 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2872 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2873 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2874 2875 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2876 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2877 __le16 flags; 2878 u8 reserved[4]; 2879 __le32 addr_high; 2880 __le32 addr_low; 2881 }; 2882 2883 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2884 2885 /* tunnel key structure 0x0B10 */ 2886 2887 struct i40e_aqc_tunnel_key_structure { 2888 u8 key1_off; 2889 u8 key2_off; 2890 u8 key1_len; /* 0 to 15 */ 2891 u8 key2_len; /* 0 to 15 */ 2892 u8 flags; 2893 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2894 /* response flags */ 2895 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2896 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2897 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2898 u8 network_key_index; 2899 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2900 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2901 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2902 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2903 u8 reserved[10]; 2904 }; 2905 2906 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2907 2908 /* OEM mode commands (direct 0xFE0x) */ 2909 struct i40e_aqc_oem_param_change { 2910 __le32 param_type; 2911 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2912 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2913 #define I40E_AQ_OEM_PARAM_MAC 2 2914 __le32 param_value1; 2915 __le16 param_value2; 2916 u8 reserved[6]; 2917 }; 2918 2919 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2920 2921 struct i40e_aqc_oem_state_change { 2922 __le32 state; 2923 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2924 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2925 u8 reserved[12]; 2926 }; 2927 2928 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2929 2930 /* Initialize OCSD (0xFE02, direct) */ 2931 struct i40e_aqc_opc_oem_ocsd_initialize { 2932 u8 type_status; 2933 u8 reserved1[3]; 2934 __le32 ocsd_memory_block_addr_high; 2935 __le32 ocsd_memory_block_addr_low; 2936 __le32 requested_update_interval; 2937 }; 2938 2939 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2940 2941 /* Initialize OCBB (0xFE03, direct) */ 2942 struct i40e_aqc_opc_oem_ocbb_initialize { 2943 u8 type_status; 2944 u8 reserved1[3]; 2945 __le32 ocbb_memory_block_addr_high; 2946 __le32 ocbb_memory_block_addr_low; 2947 u8 reserved2[4]; 2948 }; 2949 2950 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2951 2952 /* debug commands */ 2953 2954 /* get device id (0xFF00) uses the generic structure */ 2955 2956 /* set test more (0xFF01, internal) */ 2957 2958 struct i40e_acq_set_test_mode { 2959 u8 mode; 2960 #define I40E_AQ_TEST_PARTIAL 0 2961 #define I40E_AQ_TEST_FULL 1 2962 #define I40E_AQ_TEST_NVM 2 2963 u8 reserved[3]; 2964 u8 command; 2965 #define I40E_AQ_TEST_OPEN 0 2966 #define I40E_AQ_TEST_CLOSE 1 2967 #define I40E_AQ_TEST_INC 2 2968 u8 reserved2[3]; 2969 __le32 address_high; 2970 __le32 address_low; 2971 }; 2972 2973 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2974 2975 /* Debug Read Register command (0xFF03) 2976 * Debug Write Register command (0xFF04) 2977 */ 2978 struct i40e_aqc_debug_reg_read_write { 2979 __le32 reserved; 2980 __le32 address; 2981 __le32 value_high; 2982 __le32 value_low; 2983 }; 2984 2985 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2986 2987 /* Scatter/gather Reg Read (indirect 0xFF05) 2988 * Scatter/gather Reg Write (indirect 0xFF06) 2989 */ 2990 2991 /* i40e_aq_desc is used for the command */ 2992 struct i40e_aqc_debug_reg_sg_element_data { 2993 __le32 address; 2994 __le32 value; 2995 }; 2996 2997 /* Debug Modify register (direct 0xFF07) */ 2998 struct i40e_aqc_debug_modify_reg { 2999 __le32 address; 3000 __le32 value; 3001 __le32 clear_mask; 3002 __le32 set_mask; 3003 }; 3004 3005 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 3006 3007 /* dump internal data (0xFF08, indirect) */ 3008 3009 #define I40E_AQ_CLUSTER_ID_AUX 0 3010 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 3011 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 3012 #define I40E_AQ_CLUSTER_ID_HMC 3 3013 #define I40E_AQ_CLUSTER_ID_MAC0 4 3014 #define I40E_AQ_CLUSTER_ID_MAC1 5 3015 #define I40E_AQ_CLUSTER_ID_MAC2 6 3016 #define I40E_AQ_CLUSTER_ID_MAC3 7 3017 #define I40E_AQ_CLUSTER_ID_DCB 8 3018 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 3019 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 3020 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 3021 3022 struct i40e_aqc_debug_dump_internals { 3023 u8 cluster_id; 3024 u8 table_id; 3025 __le16 data_size; 3026 __le32 idx; 3027 __le32 address_high; 3028 __le32 address_low; 3029 }; 3030 3031 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 3032 3033 struct i40e_aqc_debug_modify_internals { 3034 u8 cluster_id; 3035 u8 cluster_specific_params[7]; 3036 __le32 address_high; 3037 __le32 address_low; 3038 }; 3039 3040 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 3041 3042 #endif /* _I40E_ADMINQ_CMD_H_ */ 3043