1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_ADMINQ_CMD_H_ 36 #define _I40E_ADMINQ_CMD_H_ 37 38 /* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 #define I40E_FW_API_VERSION_MAJOR 0x0001 45 #define I40E_FW_API_VERSION_MINOR 0x0004 46 47 struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69 }; 70 71 /* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76 /* command flags and offsets*/ 77 #define I40E_AQ_FLAG_DD_SHIFT 0 78 #define I40E_AQ_FLAG_CMP_SHIFT 1 79 #define I40E_AQ_FLAG_ERR_SHIFT 2 80 #define I40E_AQ_FLAG_VFE_SHIFT 3 81 #define I40E_AQ_FLAG_LB_SHIFT 9 82 #define I40E_AQ_FLAG_RD_SHIFT 10 83 #define I40E_AQ_FLAG_VFC_SHIFT 11 84 #define I40E_AQ_FLAG_BUF_SHIFT 12 85 #define I40E_AQ_FLAG_SI_SHIFT 13 86 #define I40E_AQ_FLAG_EI_SHIFT 14 87 #define I40E_AQ_FLAG_FE_SHIFT 15 88 89 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101 /* error codes */ 102 enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126 }; 127 128 /* Admin Queue command opcodes */ 129 enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* LAA */ 144 i40e_aqc_opc_mac_address_read = 0x0107, 145 i40e_aqc_opc_mac_address_write = 0x0108, 146 147 /* PXE */ 148 i40e_aqc_opc_clear_pxe_mode = 0x0110, 149 150 /* internal switch commands */ 151 i40e_aqc_opc_get_switch_config = 0x0200, 152 i40e_aqc_opc_add_statistics = 0x0201, 153 i40e_aqc_opc_remove_statistics = 0x0202, 154 i40e_aqc_opc_set_port_parameters = 0x0203, 155 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156 157 i40e_aqc_opc_add_vsi = 0x0210, 158 i40e_aqc_opc_update_vsi_parameters = 0x0211, 159 i40e_aqc_opc_get_vsi_parameters = 0x0212, 160 161 i40e_aqc_opc_add_pv = 0x0220, 162 i40e_aqc_opc_update_pv_parameters = 0x0221, 163 i40e_aqc_opc_get_pv_parameters = 0x0222, 164 165 i40e_aqc_opc_add_veb = 0x0230, 166 i40e_aqc_opc_update_veb_parameters = 0x0231, 167 i40e_aqc_opc_get_veb_parameters = 0x0232, 168 169 i40e_aqc_opc_delete_element = 0x0243, 170 171 i40e_aqc_opc_add_macvlan = 0x0250, 172 i40e_aqc_opc_remove_macvlan = 0x0251, 173 i40e_aqc_opc_add_vlan = 0x0252, 174 i40e_aqc_opc_remove_vlan = 0x0253, 175 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 176 i40e_aqc_opc_add_tag = 0x0255, 177 i40e_aqc_opc_remove_tag = 0x0256, 178 i40e_aqc_opc_add_multicast_etag = 0x0257, 179 i40e_aqc_opc_remove_multicast_etag = 0x0258, 180 i40e_aqc_opc_update_tag = 0x0259, 181 i40e_aqc_opc_add_control_packet_filter = 0x025A, 182 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 183 i40e_aqc_opc_add_cloud_filters = 0x025C, 184 i40e_aqc_opc_remove_cloud_filters = 0x025D, 185 186 i40e_aqc_opc_add_mirror_rule = 0x0260, 187 i40e_aqc_opc_delete_mirror_rule = 0x0261, 188 189 /* DCB commands */ 190 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 191 i40e_aqc_opc_dcb_updated = 0x0302, 192 193 /* TX scheduler */ 194 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 195 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 196 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 197 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 198 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 199 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 200 201 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 202 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 203 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 204 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 205 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 206 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 207 i40e_aqc_opc_query_port_ets_config = 0x0419, 208 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 209 i40e_aqc_opc_suspend_port_tx = 0x041B, 210 i40e_aqc_opc_resume_port_tx = 0x041C, 211 i40e_aqc_opc_configure_partition_bw = 0x041D, 212 213 /* hmc */ 214 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 215 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 216 217 /* phy commands*/ 218 i40e_aqc_opc_get_phy_abilities = 0x0600, 219 i40e_aqc_opc_set_phy_config = 0x0601, 220 i40e_aqc_opc_set_mac_config = 0x0603, 221 i40e_aqc_opc_set_link_restart_an = 0x0605, 222 i40e_aqc_opc_get_link_status = 0x0607, 223 i40e_aqc_opc_set_phy_int_mask = 0x0613, 224 i40e_aqc_opc_get_local_advt_reg = 0x0614, 225 i40e_aqc_opc_set_local_advt_reg = 0x0615, 226 i40e_aqc_opc_get_partner_advt = 0x0616, 227 i40e_aqc_opc_set_lb_modes = 0x0618, 228 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 229 i40e_aqc_opc_set_phy_debug = 0x0622, 230 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 231 232 /* NVM commands */ 233 i40e_aqc_opc_nvm_read = 0x0701, 234 i40e_aqc_opc_nvm_erase = 0x0702, 235 i40e_aqc_opc_nvm_update = 0x0703, 236 i40e_aqc_opc_nvm_config_read = 0x0704, 237 i40e_aqc_opc_nvm_config_write = 0x0705, 238 i40e_aqc_opc_oem_post_update = 0x0720, 239 240 /* virtualization commands */ 241 i40e_aqc_opc_send_msg_to_pf = 0x0801, 242 i40e_aqc_opc_send_msg_to_vf = 0x0802, 243 i40e_aqc_opc_send_msg_to_peer = 0x0803, 244 245 /* alternate structure */ 246 i40e_aqc_opc_alternate_write = 0x0900, 247 i40e_aqc_opc_alternate_write_indirect = 0x0901, 248 i40e_aqc_opc_alternate_read = 0x0902, 249 i40e_aqc_opc_alternate_read_indirect = 0x0903, 250 i40e_aqc_opc_alternate_write_done = 0x0904, 251 i40e_aqc_opc_alternate_set_mode = 0x0905, 252 i40e_aqc_opc_alternate_clear_port = 0x0906, 253 254 /* LLDP commands */ 255 i40e_aqc_opc_lldp_get_mib = 0x0A00, 256 i40e_aqc_opc_lldp_update_mib = 0x0A01, 257 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 258 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 259 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 260 i40e_aqc_opc_lldp_stop = 0x0A05, 261 i40e_aqc_opc_lldp_start = 0x0A06, 262 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 263 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 264 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 265 266 /* Tunnel commands */ 267 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 268 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 269 270 /* Proxy commands */ 271 i40e_aqc_opc_set_proxy_config = 0x0104, 272 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 273 274 /* Async Events */ 275 i40e_aqc_opc_event_lan_overflow = 0x1001, 276 277 /* OEM commands */ 278 i40e_aqc_opc_oem_parameter_change = 0xFE00, 279 i40e_aqc_opc_oem_device_status_change = 0xFE01, 280 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 281 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 282 283 /* debug commands */ 284 i40e_aqc_opc_debug_read_reg = 0xFF03, 285 i40e_aqc_opc_debug_write_reg = 0xFF04, 286 i40e_aqc_opc_debug_modify_reg = 0xFF07, 287 i40e_aqc_opc_debug_dump_internals = 0xFF08, 288 }; 289 290 /* command structures and indirect data structures */ 291 292 /* Structure naming conventions: 293 * - no suffix for direct command descriptor structures 294 * - _data for indirect sent data 295 * - _resp for indirect return data (data which is both will use _data) 296 * - _completion for direct return data 297 * - _element_ for repeated elements (may also be _data or _resp) 298 * 299 * Command structures are expected to overlay the params.raw member of the basic 300 * descriptor, and as such cannot exceed 16 bytes in length. 301 */ 302 303 /* This macro is used to generate a compilation error if a structure 304 * is not exactly the correct length. It gives a divide by zero error if the 305 * structure is not of the correct size, otherwise it creates an enum that is 306 * never used. 307 */ 308 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 309 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 310 311 /* This macro is used extensively to ensure that command structures are 16 312 * bytes in length as they have to map to the raw array of that size. 313 */ 314 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 315 316 /* internal (0x00XX) commands */ 317 318 /* Get version (direct 0x0001) */ 319 struct i40e_aqc_get_version { 320 __le32 rom_ver; 321 __le32 fw_build; 322 __le16 fw_major; 323 __le16 fw_minor; 324 __le16 api_major; 325 __le16 api_minor; 326 }; 327 328 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 329 330 /* Send driver version (indirect 0x0002) */ 331 struct i40e_aqc_driver_version { 332 u8 driver_major_ver; 333 u8 driver_minor_ver; 334 u8 driver_build_ver; 335 u8 driver_subbuild_ver; 336 u8 reserved[4]; 337 __le32 address_high; 338 __le32 address_low; 339 }; 340 341 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 342 343 /* Queue Shutdown (direct 0x0003) */ 344 struct i40e_aqc_queue_shutdown { 345 __le32 driver_unloading; 346 #define I40E_AQ_DRIVER_UNLOADING 0x1 347 u8 reserved[12]; 348 }; 349 350 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 351 352 /* Set PF context (0x0004, direct) */ 353 struct i40e_aqc_set_pf_context { 354 u8 pf_id; 355 u8 reserved[15]; 356 }; 357 358 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 359 360 /* Request resource ownership (direct 0x0008) 361 * Release resource ownership (direct 0x0009) 362 */ 363 #define I40E_AQ_RESOURCE_NVM 1 364 #define I40E_AQ_RESOURCE_SDP 2 365 #define I40E_AQ_RESOURCE_ACCESS_READ 1 366 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 367 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 368 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 369 370 struct i40e_aqc_request_resource { 371 __le16 resource_id; 372 __le16 access_type; 373 __le32 timeout; 374 __le32 resource_number; 375 u8 reserved[4]; 376 }; 377 378 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 379 380 /* Get function capabilities (indirect 0x000A) 381 * Get device capabilities (indirect 0x000B) 382 */ 383 struct i40e_aqc_list_capabilites { 384 u8 command_flags; 385 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 386 u8 pf_index; 387 u8 reserved[2]; 388 __le32 count; 389 __le32 addr_high; 390 __le32 addr_low; 391 }; 392 393 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 394 395 struct i40e_aqc_list_capabilities_element_resp { 396 __le16 id; 397 u8 major_rev; 398 u8 minor_rev; 399 __le32 number; 400 __le32 logical_id; 401 __le32 phys_id; 402 u8 reserved[16]; 403 }; 404 405 /* list of caps */ 406 407 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 408 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 409 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 410 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 411 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 412 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 413 #define I40E_AQ_CAP_ID_SRIOV 0x0012 414 #define I40E_AQ_CAP_ID_VF 0x0013 415 #define I40E_AQ_CAP_ID_VMDQ 0x0014 416 #define I40E_AQ_CAP_ID_8021QBG 0x0015 417 #define I40E_AQ_CAP_ID_8021QBR 0x0016 418 #define I40E_AQ_CAP_ID_VSI 0x0017 419 #define I40E_AQ_CAP_ID_DCB 0x0018 420 #define I40E_AQ_CAP_ID_FCOE 0x0021 421 #define I40E_AQ_CAP_ID_ISCSI 0x0022 422 #define I40E_AQ_CAP_ID_RSS 0x0040 423 #define I40E_AQ_CAP_ID_RXQ 0x0041 424 #define I40E_AQ_CAP_ID_TXQ 0x0042 425 #define I40E_AQ_CAP_ID_MSIX 0x0043 426 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 427 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 428 #define I40E_AQ_CAP_ID_1588 0x0046 429 #define I40E_AQ_CAP_ID_IWARP 0x0051 430 #define I40E_AQ_CAP_ID_LED 0x0061 431 #define I40E_AQ_CAP_ID_SDP 0x0062 432 #define I40E_AQ_CAP_ID_MDIO 0x0063 433 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 434 #define I40E_AQ_CAP_ID_CEM 0x00F2 435 436 /* Set CPPM Configuration (direct 0x0103) */ 437 struct i40e_aqc_cppm_configuration { 438 __le16 command_flags; 439 #define I40E_AQ_CPPM_EN_LTRC 0x0800 440 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 441 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 442 #define I40E_AQ_CPPM_EN_HPTC 0x4000 443 #define I40E_AQ_CPPM_EN_DMARC 0x8000 444 __le16 ttlx; 445 __le32 dmacr; 446 __le16 dmcth; 447 u8 hptc; 448 u8 reserved; 449 __le32 pfltrc; 450 }; 451 452 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 453 454 /* Set ARP Proxy command / response (indirect 0x0104) */ 455 struct i40e_aqc_arp_proxy_data { 456 __le16 command_flags; 457 #define I40E_AQ_ARP_INIT_IPV4 0x0008 458 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 459 #define I40E_AQ_ARP_ENA 0x0020 460 #define I40E_AQ_ARP_ADD_IPV4 0x0040 461 #define I40E_AQ_ARP_DEL_IPV4 0x0080 462 __le16 table_id; 463 __le32 pfpm_proxyfc; 464 __le32 ip_addr; 465 u8 mac_addr[6]; 466 u8 reserved[2]; 467 }; 468 469 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 470 471 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 472 struct i40e_aqc_ns_proxy_data { 473 __le16 table_idx_mac_addr_0; 474 __le16 table_idx_mac_addr_1; 475 __le16 table_idx_ipv6_0; 476 __le16 table_idx_ipv6_1; 477 __le16 control; 478 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 479 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 480 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 481 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 482 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 483 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 484 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 485 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 486 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 487 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 488 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 489 u8 mac_addr_0[6]; 490 u8 mac_addr_1[6]; 491 u8 local_mac_addr[6]; 492 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 493 u8 ipv6_addr_1[16]; 494 }; 495 496 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 497 498 /* Manage LAA Command (0x0106) - obsolete */ 499 struct i40e_aqc_mng_laa { 500 __le16 command_flags; 501 #define I40E_AQ_LAA_FLAG_WR 0x8000 502 u8 reserved[2]; 503 __le32 sal; 504 __le16 sah; 505 u8 reserved2[6]; 506 }; 507 508 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 509 510 /* Manage MAC Address Read Command (indirect 0x0107) */ 511 struct i40e_aqc_mac_address_read { 512 __le16 command_flags; 513 #define I40E_AQC_LAN_ADDR_VALID 0x10 514 #define I40E_AQC_SAN_ADDR_VALID 0x20 515 #define I40E_AQC_PORT_ADDR_VALID 0x40 516 #define I40E_AQC_WOL_ADDR_VALID 0x80 517 #define I40E_AQC_MC_MAG_EN_VALID 0x100 518 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 519 u8 reserved[6]; 520 __le32 addr_high; 521 __le32 addr_low; 522 }; 523 524 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 525 526 struct i40e_aqc_mac_address_read_data { 527 u8 pf_lan_mac[6]; 528 u8 pf_san_mac[6]; 529 u8 port_mac[6]; 530 u8 pf_wol_mac[6]; 531 }; 532 533 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 534 535 /* Manage MAC Address Write Command (0x0108) */ 536 struct i40e_aqc_mac_address_write { 537 __le16 command_flags; 538 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 539 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 540 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 541 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 542 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 543 544 __le16 mac_sah; 545 __le32 mac_sal; 546 u8 reserved[8]; 547 }; 548 549 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 550 551 /* PXE commands (0x011x) */ 552 553 /* Clear PXE Command and response (direct 0x0110) */ 554 struct i40e_aqc_clear_pxe { 555 u8 rx_cnt; 556 u8 reserved[15]; 557 }; 558 559 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 560 561 /* Switch configuration commands (0x02xx) */ 562 563 /* Used by many indirect commands that only pass an seid and a buffer in the 564 * command 565 */ 566 struct i40e_aqc_switch_seid { 567 __le16 seid; 568 u8 reserved[6]; 569 __le32 addr_high; 570 __le32 addr_low; 571 }; 572 573 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 574 575 /* Get Switch Configuration command (indirect 0x0200) 576 * uses i40e_aqc_switch_seid for the descriptor 577 */ 578 struct i40e_aqc_get_switch_config_header_resp { 579 __le16 num_reported; 580 __le16 num_total; 581 u8 reserved[12]; 582 }; 583 584 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 585 586 struct i40e_aqc_switch_config_element_resp { 587 u8 element_type; 588 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 589 #define I40E_AQ_SW_ELEM_TYPE_PF 2 590 #define I40E_AQ_SW_ELEM_TYPE_VF 3 591 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 592 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 593 #define I40E_AQ_SW_ELEM_TYPE_PV 16 594 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 595 #define I40E_AQ_SW_ELEM_TYPE_PA 18 596 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 597 u8 revision; 598 #define I40E_AQ_SW_ELEM_REV_1 1 599 __le16 seid; 600 __le16 uplink_seid; 601 __le16 downlink_seid; 602 u8 reserved[3]; 603 u8 connection_type; 604 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 605 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 606 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 607 __le16 scheduler_id; 608 __le16 element_info; 609 }; 610 611 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 612 613 /* Get Switch Configuration (indirect 0x0200) 614 * an array of elements are returned in the response buffer 615 * the first in the array is the header, remainder are elements 616 */ 617 struct i40e_aqc_get_switch_config_resp { 618 struct i40e_aqc_get_switch_config_header_resp header; 619 struct i40e_aqc_switch_config_element_resp element[1]; 620 }; 621 622 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 623 624 /* Add Statistics (direct 0x0201) 625 * Remove Statistics (direct 0x0202) 626 */ 627 struct i40e_aqc_add_remove_statistics { 628 __le16 seid; 629 __le16 vlan; 630 __le16 stat_index; 631 u8 reserved[10]; 632 }; 633 634 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 635 636 /* Set Port Parameters command (direct 0x0203) */ 637 struct i40e_aqc_set_port_parameters { 638 __le16 command_flags; 639 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 640 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 641 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 642 __le16 bad_frame_vsi; 643 __le16 default_seid; /* reserved for command */ 644 u8 reserved[10]; 645 }; 646 647 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 648 649 /* Get Switch Resource Allocation (indirect 0x0204) */ 650 struct i40e_aqc_get_switch_resource_alloc { 651 u8 num_entries; /* reserved for command */ 652 u8 reserved[7]; 653 __le32 addr_high; 654 __le32 addr_low; 655 }; 656 657 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 658 659 /* expect an array of these structs in the response buffer */ 660 struct i40e_aqc_switch_resource_alloc_element_resp { 661 u8 resource_type; 662 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 663 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 664 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 665 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 666 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 667 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 668 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 669 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 670 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 671 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 672 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 673 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 674 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 675 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 676 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 677 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 678 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 679 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 680 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 681 u8 reserved1; 682 __le16 guaranteed; 683 __le16 total; 684 __le16 used; 685 __le16 total_unalloced; 686 u8 reserved2[6]; 687 }; 688 689 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 690 691 /* Add VSI (indirect 0x0210) 692 * this indirect command uses struct i40e_aqc_vsi_properties_data 693 * as the indirect buffer (128 bytes) 694 * 695 * Update VSI (indirect 0x211) 696 * uses the same data structure as Add VSI 697 * 698 * Get VSI (indirect 0x0212) 699 * uses the same completion and data structure as Add VSI 700 */ 701 struct i40e_aqc_add_get_update_vsi { 702 __le16 uplink_seid; 703 u8 connection_type; 704 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 705 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 706 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 707 u8 reserved1; 708 u8 vf_id; 709 u8 reserved2; 710 __le16 vsi_flags; 711 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 712 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 713 #define I40E_AQ_VSI_TYPE_VF 0x0 714 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 715 #define I40E_AQ_VSI_TYPE_PF 0x2 716 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 717 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 718 __le32 addr_high; 719 __le32 addr_low; 720 }; 721 722 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 723 724 struct i40e_aqc_add_get_update_vsi_completion { 725 __le16 seid; 726 __le16 vsi_number; 727 __le16 vsi_used; 728 __le16 vsi_free; 729 __le32 addr_high; 730 __le32 addr_low; 731 }; 732 733 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 734 735 struct i40e_aqc_vsi_properties_data { 736 /* first 96 byte are written by SW */ 737 __le16 valid_sections; 738 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 739 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 740 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 741 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 742 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 743 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 744 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 745 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 746 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 747 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 748 /* switch section */ 749 __le16 switch_id; /* 12bit id combined with flags below */ 750 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 751 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 752 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 753 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 754 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 755 u8 sw_reserved[2]; 756 /* security section */ 757 u8 sec_flags; 758 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 759 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 760 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 761 u8 sec_reserved; 762 /* VLAN section */ 763 __le16 pvid; /* VLANS include priority bits */ 764 __le16 fcoe_pvid; 765 u8 port_vlan_flags; 766 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 767 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 768 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 769 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 770 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 771 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 772 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 773 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 774 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 775 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 776 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 777 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 778 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 779 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 780 u8 pvlan_reserved[3]; 781 /* ingress egress up sections */ 782 __le32 ingress_table; /* bitmap, 3 bits per up */ 783 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 784 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 785 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 786 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 787 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 788 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 789 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 790 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 791 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 792 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 793 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 794 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 795 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 796 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 797 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 798 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 799 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 800 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 801 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 802 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 803 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 804 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 805 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 806 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 807 __le32 egress_table; /* same defines as for ingress table */ 808 /* cascaded PV section */ 809 __le16 cas_pv_tag; 810 u8 cas_pv_flags; 811 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 812 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 813 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 814 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 815 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 816 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 817 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 818 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 819 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 820 u8 cas_pv_reserved; 821 /* queue mapping section */ 822 __le16 mapping_flags; 823 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 824 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 825 __le16 queue_mapping[16]; 826 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 827 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 828 __le16 tc_mapping[8]; 829 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 830 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 831 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 832 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 833 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 834 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 835 /* queueing option section */ 836 u8 queueing_opt_flags; 837 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 838 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 839 u8 queueing_opt_reserved[3]; 840 /* scheduler section */ 841 u8 up_enable_bits; 842 u8 sched_reserved; 843 /* outer up section */ 844 __le32 outer_up_table; /* same structure and defines as ingress table */ 845 u8 cmd_reserved[8]; 846 /* last 32 bytes are written by FW */ 847 __le16 qs_handle[8]; 848 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 849 __le16 stat_counter_idx; 850 __le16 sched_id; 851 u8 resp_reserved[12]; 852 }; 853 854 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 855 856 /* Add Port Virtualizer (direct 0x0220) 857 * also used for update PV (direct 0x0221) but only flags are used 858 * (IS_CTRL_PORT only works on add PV) 859 */ 860 struct i40e_aqc_add_update_pv { 861 __le16 command_flags; 862 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 863 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 864 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 865 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 866 __le16 uplink_seid; 867 __le16 connected_seid; 868 u8 reserved[10]; 869 }; 870 871 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 872 873 struct i40e_aqc_add_update_pv_completion { 874 /* reserved for update; for add also encodes error if rc == ENOSPC */ 875 __le16 pv_seid; 876 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 877 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 878 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 879 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 880 u8 reserved[14]; 881 }; 882 883 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 884 885 /* Get PV Params (direct 0x0222) 886 * uses i40e_aqc_switch_seid for the descriptor 887 */ 888 889 struct i40e_aqc_get_pv_params_completion { 890 __le16 seid; 891 __le16 default_stag; 892 __le16 pv_flags; /* same flags as add_pv */ 893 #define I40E_AQC_GET_PV_PV_TYPE 0x1 894 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 895 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 896 u8 reserved[8]; 897 __le16 default_port_seid; 898 }; 899 900 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 901 902 /* Add VEB (direct 0x0230) */ 903 struct i40e_aqc_add_veb { 904 __le16 uplink_seid; 905 __le16 downlink_seid; 906 __le16 veb_flags; 907 #define I40E_AQC_ADD_VEB_FLOATING 0x1 908 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 909 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 910 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 911 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 912 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 913 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 914 u8 enable_tcs; 915 u8 reserved[9]; 916 }; 917 918 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 919 920 struct i40e_aqc_add_veb_completion { 921 u8 reserved[6]; 922 __le16 switch_seid; 923 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 924 __le16 veb_seid; 925 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 926 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 927 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 928 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 929 __le16 statistic_index; 930 __le16 vebs_used; 931 __le16 vebs_free; 932 }; 933 934 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 935 936 /* Get VEB Parameters (direct 0x0232) 937 * uses i40e_aqc_switch_seid for the descriptor 938 */ 939 struct i40e_aqc_get_veb_parameters_completion { 940 __le16 seid; 941 __le16 switch_id; 942 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 943 __le16 statistic_index; 944 __le16 vebs_used; 945 __le16 vebs_free; 946 u8 reserved[4]; 947 }; 948 949 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 950 951 /* Delete Element (direct 0x0243) 952 * uses the generic i40e_aqc_switch_seid 953 */ 954 955 /* Add MAC-VLAN (indirect 0x0250) */ 956 957 /* used for the command for most vlan commands */ 958 struct i40e_aqc_macvlan { 959 __le16 num_addresses; 960 __le16 seid[3]; 961 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 962 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 963 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 964 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 965 __le32 addr_high; 966 __le32 addr_low; 967 }; 968 969 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 970 971 /* indirect data for command and response */ 972 struct i40e_aqc_add_macvlan_element_data { 973 u8 mac_addr[6]; 974 __le16 vlan_tag; 975 __le16 flags; 976 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 977 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 978 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 979 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 980 __le16 queue_number; 981 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 982 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 983 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 984 /* response section */ 985 u8 match_method; 986 #define I40E_AQC_MM_PERFECT_MATCH 0x01 987 #define I40E_AQC_MM_HASH_MATCH 0x02 988 #define I40E_AQC_MM_ERR_NO_RES 0xFF 989 u8 reserved1[3]; 990 }; 991 992 struct i40e_aqc_add_remove_macvlan_completion { 993 __le16 perfect_mac_used; 994 __le16 perfect_mac_free; 995 __le16 unicast_hash_free; 996 __le16 multicast_hash_free; 997 __le32 addr_high; 998 __le32 addr_low; 999 }; 1000 1001 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1002 1003 /* Remove MAC-VLAN (indirect 0x0251) 1004 * uses i40e_aqc_macvlan for the descriptor 1005 * data points to an array of num_addresses of elements 1006 */ 1007 1008 struct i40e_aqc_remove_macvlan_element_data { 1009 u8 mac_addr[6]; 1010 __le16 vlan_tag; 1011 u8 flags; 1012 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1013 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1014 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1015 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1016 u8 reserved[3]; 1017 /* reply section */ 1018 u8 error_code; 1019 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1020 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1021 u8 reply_reserved[3]; 1022 }; 1023 1024 /* Add VLAN (indirect 0x0252) 1025 * Remove VLAN (indirect 0x0253) 1026 * use the generic i40e_aqc_macvlan for the command 1027 */ 1028 struct i40e_aqc_add_remove_vlan_element_data { 1029 __le16 vlan_tag; 1030 u8 vlan_flags; 1031 /* flags for add VLAN */ 1032 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1033 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1034 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1035 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1036 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1037 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1038 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1039 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1040 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1041 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1042 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1043 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1044 /* flags for remove VLAN */ 1045 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1046 u8 reserved; 1047 u8 result; 1048 /* flags for add VLAN */ 1049 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1050 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1051 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1052 /* flags for remove VLAN */ 1053 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1054 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1055 u8 reserved1[3]; 1056 }; 1057 1058 struct i40e_aqc_add_remove_vlan_completion { 1059 u8 reserved[4]; 1060 __le16 vlans_used; 1061 __le16 vlans_free; 1062 __le32 addr_high; 1063 __le32 addr_low; 1064 }; 1065 1066 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1067 struct i40e_aqc_set_vsi_promiscuous_modes { 1068 __le16 promiscuous_flags; 1069 __le16 valid_flags; 1070 /* flags used for both fields above */ 1071 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1072 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1073 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1074 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1075 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1076 __le16 seid; 1077 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1078 __le16 vlan_tag; 1079 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1080 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1081 u8 reserved[8]; 1082 }; 1083 1084 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1085 1086 /* Add S/E-tag command (direct 0x0255) 1087 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1088 */ 1089 struct i40e_aqc_add_tag { 1090 __le16 flags; 1091 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1092 __le16 seid; 1093 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1094 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1095 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1096 __le16 tag; 1097 __le16 queue_number; 1098 u8 reserved[8]; 1099 }; 1100 1101 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1102 1103 struct i40e_aqc_add_remove_tag_completion { 1104 u8 reserved[12]; 1105 __le16 tags_used; 1106 __le16 tags_free; 1107 }; 1108 1109 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1110 1111 /* Remove S/E-tag command (direct 0x0256) 1112 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1113 */ 1114 struct i40e_aqc_remove_tag { 1115 __le16 seid; 1116 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1117 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1118 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1119 __le16 tag; 1120 u8 reserved[12]; 1121 }; 1122 1123 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1124 1125 /* Add multicast E-Tag (direct 0x0257) 1126 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1127 * and no external data 1128 */ 1129 struct i40e_aqc_add_remove_mcast_etag { 1130 __le16 pv_seid; 1131 __le16 etag; 1132 u8 num_unicast_etags; 1133 u8 reserved[3]; 1134 __le32 addr_high; /* address of array of 2-byte s-tags */ 1135 __le32 addr_low; 1136 }; 1137 1138 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1139 1140 struct i40e_aqc_add_remove_mcast_etag_completion { 1141 u8 reserved[4]; 1142 __le16 mcast_etags_used; 1143 __le16 mcast_etags_free; 1144 __le32 addr_high; 1145 __le32 addr_low; 1146 1147 }; 1148 1149 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1150 1151 /* Update S/E-Tag (direct 0x0259) */ 1152 struct i40e_aqc_update_tag { 1153 __le16 seid; 1154 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1155 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1156 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1157 __le16 old_tag; 1158 __le16 new_tag; 1159 u8 reserved[10]; 1160 }; 1161 1162 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1163 1164 struct i40e_aqc_update_tag_completion { 1165 u8 reserved[12]; 1166 __le16 tags_used; 1167 __le16 tags_free; 1168 }; 1169 1170 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1171 1172 /* Add Control Packet filter (direct 0x025A) 1173 * Remove Control Packet filter (direct 0x025B) 1174 * uses the i40e_aqc_add_oveb_cloud, 1175 * and the generic direct completion structure 1176 */ 1177 struct i40e_aqc_add_remove_control_packet_filter { 1178 u8 mac[6]; 1179 __le16 etype; 1180 __le16 flags; 1181 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1182 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1183 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1184 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1185 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1186 __le16 seid; 1187 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1188 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1189 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1190 __le16 queue; 1191 u8 reserved[2]; 1192 }; 1193 1194 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1195 1196 struct i40e_aqc_add_remove_control_packet_filter_completion { 1197 __le16 mac_etype_used; 1198 __le16 etype_used; 1199 __le16 mac_etype_free; 1200 __le16 etype_free; 1201 u8 reserved[8]; 1202 }; 1203 1204 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1205 1206 /* Add Cloud filters (indirect 0x025C) 1207 * Remove Cloud filters (indirect 0x025D) 1208 * uses the i40e_aqc_add_remove_cloud_filters, 1209 * and the generic indirect completion structure 1210 */ 1211 struct i40e_aqc_add_remove_cloud_filters { 1212 u8 num_filters; 1213 u8 reserved; 1214 __le16 seid; 1215 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1216 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1217 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1218 u8 reserved2[4]; 1219 __le32 addr_high; 1220 __le32 addr_low; 1221 }; 1222 1223 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1224 1225 struct i40e_aqc_add_remove_cloud_filters_element_data { 1226 u8 outer_mac[6]; 1227 u8 inner_mac[6]; 1228 __le16 inner_vlan; 1229 union { 1230 struct { 1231 u8 reserved[12]; 1232 u8 data[4]; 1233 } v4; 1234 struct { 1235 u8 data[16]; 1236 } v6; 1237 } ipaddr; 1238 __le16 flags; 1239 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1240 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1241 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1242 /* 0x0000 reserved */ 1243 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1244 /* 0x0002 reserved */ 1245 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1246 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1247 /* 0x0005 reserved */ 1248 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1249 /* 0x0007 reserved */ 1250 /* 0x0008 reserved */ 1251 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1252 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1253 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1254 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1255 1256 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1257 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1258 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1259 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1260 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1261 1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1263 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1264 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1265 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1266 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1267 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1268 1269 __le32 tenant_id; 1270 u8 reserved[4]; 1271 __le16 queue_number; 1272 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1273 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1274 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1275 u8 reserved2[14]; 1276 /* response section */ 1277 u8 allocation_result; 1278 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1279 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1280 u8 response_reserved[7]; 1281 }; 1282 1283 struct i40e_aqc_remove_cloud_filters_completion { 1284 __le16 perfect_ovlan_used; 1285 __le16 perfect_ovlan_free; 1286 __le16 vlan_used; 1287 __le16 vlan_free; 1288 __le32 addr_high; 1289 __le32 addr_low; 1290 }; 1291 1292 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1293 1294 /* Add Mirror Rule (indirect or direct 0x0260) 1295 * Delete Mirror Rule (indirect or direct 0x0261) 1296 * note: some rule types (4,5) do not use an external buffer. 1297 * take care to set the flags correctly. 1298 */ 1299 struct i40e_aqc_add_delete_mirror_rule { 1300 __le16 seid; 1301 __le16 rule_type; 1302 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1303 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1304 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1305 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1306 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1307 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1308 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1309 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1310 __le16 num_entries; 1311 __le16 destination; /* VSI for add, rule id for delete */ 1312 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1313 __le32 addr_low; 1314 }; 1315 1316 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1317 1318 struct i40e_aqc_add_delete_mirror_rule_completion { 1319 u8 reserved[2]; 1320 __le16 rule_id; /* only used on add */ 1321 __le16 mirror_rules_used; 1322 __le16 mirror_rules_free; 1323 __le32 addr_high; 1324 __le32 addr_low; 1325 }; 1326 1327 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1328 1329 /* DCB 0x03xx*/ 1330 1331 /* PFC Ignore (direct 0x0301) 1332 * the command and response use the same descriptor structure 1333 */ 1334 struct i40e_aqc_pfc_ignore { 1335 u8 tc_bitmap; 1336 u8 command_flags; /* unused on response */ 1337 #define I40E_AQC_PFC_IGNORE_SET 0x80 1338 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1339 u8 reserved[14]; 1340 }; 1341 1342 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1343 1344 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1345 * with no parameters 1346 */ 1347 1348 /* TX scheduler 0x04xx */ 1349 1350 /* Almost all the indirect commands use 1351 * this generic struct to pass the SEID in param0 1352 */ 1353 struct i40e_aqc_tx_sched_ind { 1354 __le16 vsi_seid; 1355 u8 reserved[6]; 1356 __le32 addr_high; 1357 __le32 addr_low; 1358 }; 1359 1360 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1361 1362 /* Several commands respond with a set of queue set handles */ 1363 struct i40e_aqc_qs_handles_resp { 1364 __le16 qs_handles[8]; 1365 }; 1366 1367 /* Configure VSI BW limits (direct 0x0400) */ 1368 struct i40e_aqc_configure_vsi_bw_limit { 1369 __le16 vsi_seid; 1370 u8 reserved[2]; 1371 __le16 credit; 1372 u8 reserved1[2]; 1373 u8 max_credit; /* 0-3, limit = 2^max */ 1374 u8 reserved2[7]; 1375 }; 1376 1377 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1378 1379 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1380 * responds with i40e_aqc_qs_handles_resp 1381 */ 1382 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1383 u8 tc_valid_bits; 1384 u8 reserved[15]; 1385 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1386 1387 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1388 __le16 tc_bw_max[2]; 1389 u8 reserved1[28]; 1390 }; 1391 1392 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1393 1394 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1395 * responds with i40e_aqc_qs_handles_resp 1396 */ 1397 struct i40e_aqc_configure_vsi_tc_bw_data { 1398 u8 tc_valid_bits; 1399 u8 reserved[3]; 1400 u8 tc_bw_credits[8]; 1401 u8 reserved1[4]; 1402 __le16 qs_handles[8]; 1403 }; 1404 1405 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1406 1407 /* Query vsi bw configuration (indirect 0x0408) */ 1408 struct i40e_aqc_query_vsi_bw_config_resp { 1409 u8 tc_valid_bits; 1410 u8 tc_suspended_bits; 1411 u8 reserved[14]; 1412 __le16 qs_handles[8]; 1413 u8 reserved1[4]; 1414 __le16 port_bw_limit; 1415 u8 reserved2[2]; 1416 u8 max_bw; /* 0-3, limit = 2^max */ 1417 u8 reserved3[23]; 1418 }; 1419 1420 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1421 1422 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1423 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1424 u8 tc_valid_bits; 1425 u8 reserved[3]; 1426 u8 share_credits[8]; 1427 __le16 credits[8]; 1428 1429 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1430 __le16 tc_bw_max[2]; 1431 }; 1432 1433 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1434 1435 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1436 struct i40e_aqc_configure_switching_comp_bw_limit { 1437 __le16 seid; 1438 u8 reserved[2]; 1439 __le16 credit; 1440 u8 reserved1[2]; 1441 u8 max_bw; /* 0-3, limit = 2^max */ 1442 u8 reserved2[7]; 1443 }; 1444 1445 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1446 1447 /* Enable Physical Port ETS (indirect 0x0413) 1448 * Modify Physical Port ETS (indirect 0x0414) 1449 * Disable Physical Port ETS (indirect 0x0415) 1450 */ 1451 struct i40e_aqc_configure_switching_comp_ets_data { 1452 u8 reserved[4]; 1453 u8 tc_valid_bits; 1454 u8 seepage; 1455 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1456 u8 tc_strict_priority_flags; 1457 u8 reserved1[17]; 1458 u8 tc_bw_share_credits[8]; 1459 u8 reserved2[96]; 1460 }; 1461 1462 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1463 1464 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1465 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1466 u8 tc_valid_bits; 1467 u8 reserved[15]; 1468 __le16 tc_bw_credit[8]; 1469 1470 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1471 __le16 tc_bw_max[2]; 1472 u8 reserved1[28]; 1473 }; 1474 1475 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1476 1477 /* Configure Switching Component Bandwidth Allocation per Tc 1478 * (indirect 0x0417) 1479 */ 1480 struct i40e_aqc_configure_switching_comp_bw_config_data { 1481 u8 tc_valid_bits; 1482 u8 reserved[2]; 1483 u8 absolute_credits; /* bool */ 1484 u8 tc_bw_share_credits[8]; 1485 u8 reserved1[20]; 1486 }; 1487 1488 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1489 1490 /* Query Switching Component Configuration (indirect 0x0418) */ 1491 struct i40e_aqc_query_switching_comp_ets_config_resp { 1492 u8 tc_valid_bits; 1493 u8 reserved[35]; 1494 __le16 port_bw_limit; 1495 u8 reserved1[2]; 1496 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1497 u8 reserved2[23]; 1498 }; 1499 1500 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1501 1502 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1503 struct i40e_aqc_query_port_ets_config_resp { 1504 u8 reserved[4]; 1505 u8 tc_valid_bits; 1506 u8 reserved1; 1507 u8 tc_strict_priority_bits; 1508 u8 reserved2; 1509 u8 tc_bw_share_credits[8]; 1510 __le16 tc_bw_limits[8]; 1511 1512 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1513 __le16 tc_bw_max[2]; 1514 u8 reserved3[32]; 1515 }; 1516 1517 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1518 1519 /* Query Switching Component Bandwidth Allocation per Traffic Type 1520 * (indirect 0x041A) 1521 */ 1522 struct i40e_aqc_query_switching_comp_bw_config_resp { 1523 u8 tc_valid_bits; 1524 u8 reserved[2]; 1525 u8 absolute_credits_enable; /* bool */ 1526 u8 tc_bw_share_credits[8]; 1527 __le16 tc_bw_limits[8]; 1528 1529 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1530 __le16 tc_bw_max[2]; 1531 }; 1532 1533 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1534 1535 /* Suspend/resume port TX traffic 1536 * (direct 0x041B and 0x041C) uses the generic SEID struct 1537 */ 1538 1539 /* Configure partition BW 1540 * (indirect 0x041D) 1541 */ 1542 struct i40e_aqc_configure_partition_bw_data { 1543 __le16 pf_valid_bits; 1544 u8 min_bw[16]; /* guaranteed bandwidth */ 1545 u8 max_bw[16]; /* bandwidth limit */ 1546 }; 1547 1548 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1549 1550 /* Get and set the active HMC resource profile and status. 1551 * (direct 0x0500) and (direct 0x0501) 1552 */ 1553 struct i40e_aq_get_set_hmc_resource_profile { 1554 u8 pm_profile; 1555 u8 pe_vf_enabled; 1556 u8 reserved[14]; 1557 }; 1558 1559 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1560 1561 enum i40e_aq_hmc_profile { 1562 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1563 I40E_HMC_PROFILE_DEFAULT = 1, 1564 I40E_HMC_PROFILE_FAVOR_VF = 2, 1565 I40E_HMC_PROFILE_EQUAL = 3, 1566 }; 1567 1568 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1569 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1570 1571 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1572 1573 /* set in param0 for get phy abilities to report qualified modules */ 1574 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1575 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1576 1577 enum i40e_aq_phy_type { 1578 I40E_PHY_TYPE_SGMII = 0x0, 1579 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1580 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1581 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1582 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1583 I40E_PHY_TYPE_XAUI = 0x5, 1584 I40E_PHY_TYPE_XFI = 0x6, 1585 I40E_PHY_TYPE_SFI = 0x7, 1586 I40E_PHY_TYPE_XLAUI = 0x8, 1587 I40E_PHY_TYPE_XLPPI = 0x9, 1588 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1589 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1590 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1591 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1592 I40E_PHY_TYPE_100BASE_TX = 0x11, 1593 I40E_PHY_TYPE_1000BASE_T = 0x12, 1594 I40E_PHY_TYPE_10GBASE_T = 0x13, 1595 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1596 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1597 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1598 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1599 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1600 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1601 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1602 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1603 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1604 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1605 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1606 I40E_PHY_TYPE_MAX 1607 }; 1608 1609 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1610 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1611 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1612 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1613 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1614 1615 enum i40e_aq_link_speed { 1616 I40E_LINK_SPEED_UNKNOWN = 0, 1617 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1618 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1619 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1620 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1621 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1622 }; 1623 1624 struct i40e_aqc_module_desc { 1625 u8 oui[3]; 1626 u8 reserved1; 1627 u8 part_number[16]; 1628 u8 revision[4]; 1629 u8 reserved2[8]; 1630 }; 1631 1632 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1633 1634 struct i40e_aq_get_phy_abilities_resp { 1635 __le32 phy_type; /* bitmap using the above enum for offsets */ 1636 u8 link_speed; /* bitmap using the above enum bit patterns */ 1637 u8 abilities; 1638 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1639 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1640 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1641 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1642 #define I40E_AQ_PHY_AN_ENABLED 0x10 1643 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1644 __le16 eee_capability; 1645 #define I40E_AQ_EEE_100BASE_TX 0x0002 1646 #define I40E_AQ_EEE_1000BASE_T 0x0004 1647 #define I40E_AQ_EEE_10GBASE_T 0x0008 1648 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1649 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1650 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1651 __le32 eeer_val; 1652 u8 d3_lpan; 1653 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1654 u8 reserved[3]; 1655 u8 phy_id[4]; 1656 u8 module_type[3]; 1657 u8 qualified_module_count; 1658 #define I40E_AQ_PHY_MAX_QMS 16 1659 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1660 }; 1661 1662 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1663 1664 /* Set PHY Config (direct 0x0601) */ 1665 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1666 __le32 phy_type; 1667 u8 link_speed; 1668 u8 abilities; 1669 /* bits 0-2 use the values from get_phy_abilities_resp */ 1670 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1671 #define I40E_AQ_PHY_ENABLE_AN 0x10 1672 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1673 __le16 eee_capability; 1674 __le32 eeer; 1675 u8 low_power_ctrl; 1676 u8 reserved[3]; 1677 }; 1678 1679 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1680 1681 /* Set MAC Config command data structure (direct 0x0603) */ 1682 struct i40e_aq_set_mac_config { 1683 __le16 max_frame_size; 1684 u8 params; 1685 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1694 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1695 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1696 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1697 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1698 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1699 u8 tx_timer_priority; /* bitmap */ 1700 __le16 tx_timer_value; 1701 __le16 fc_refresh_threshold; 1702 u8 reserved[8]; 1703 }; 1704 1705 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1706 1707 /* Restart Auto-Negotiation (direct 0x605) */ 1708 struct i40e_aqc_set_link_restart_an { 1709 u8 command; 1710 #define I40E_AQ_PHY_RESTART_AN 0x02 1711 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1712 u8 reserved[15]; 1713 }; 1714 1715 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1716 1717 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1718 struct i40e_aqc_get_link_status { 1719 __le16 command_flags; /* only field set on command */ 1720 #define I40E_AQ_LSE_MASK 0x3 1721 #define I40E_AQ_LSE_NOP 0x0 1722 #define I40E_AQ_LSE_DISABLE 0x2 1723 #define I40E_AQ_LSE_ENABLE 0x3 1724 /* only response uses this flag */ 1725 #define I40E_AQ_LSE_IS_ENABLED 0x1 1726 u8 phy_type; /* i40e_aq_phy_type */ 1727 u8 link_speed; /* i40e_aq_link_speed */ 1728 u8 link_info; 1729 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1730 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1731 #define I40E_AQ_LINK_FAULT 0x02 1732 #define I40E_AQ_LINK_FAULT_TX 0x04 1733 #define I40E_AQ_LINK_FAULT_RX 0x08 1734 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1735 #define I40E_AQ_LINK_UP_PORT 0x20 1736 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1737 #define I40E_AQ_SIGNAL_DETECT 0x80 1738 u8 an_info; 1739 #define I40E_AQ_AN_COMPLETED 0x01 1740 #define I40E_AQ_LP_AN_ABILITY 0x02 1741 #define I40E_AQ_PD_FAULT 0x04 1742 #define I40E_AQ_FEC_EN 0x08 1743 #define I40E_AQ_PHY_LOW_POWER 0x10 1744 #define I40E_AQ_LINK_PAUSE_TX 0x20 1745 #define I40E_AQ_LINK_PAUSE_RX 0x40 1746 #define I40E_AQ_QUALIFIED_MODULE 0x80 1747 u8 ext_info; 1748 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1749 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1750 #define I40E_AQ_LINK_TX_SHIFT 0x02 1751 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1752 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1753 #define I40E_AQ_LINK_TX_DRAINED 0x01 1754 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1755 #define I40E_AQ_LINK_FORCED_40G 0x10 1756 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1757 __le16 max_frame_size; 1758 u8 config; 1759 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1760 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1761 u8 reserved[5]; 1762 }; 1763 1764 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1765 1766 /* Set event mask command (direct 0x613) */ 1767 struct i40e_aqc_set_phy_int_mask { 1768 u8 reserved[8]; 1769 __le16 event_mask; 1770 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1771 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1772 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1773 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1774 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1775 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1776 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1777 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1778 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1779 u8 reserved1[6]; 1780 }; 1781 1782 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1783 1784 /* Get Local AN advt register (direct 0x0614) 1785 * Set Local AN advt register (direct 0x0615) 1786 * Get Link Partner AN advt register (direct 0x0616) 1787 */ 1788 struct i40e_aqc_an_advt_reg { 1789 __le32 local_an_reg0; 1790 __le16 local_an_reg1; 1791 u8 reserved[10]; 1792 }; 1793 1794 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1795 1796 /* Set Loopback mode (0x0618) */ 1797 struct i40e_aqc_set_lb_mode { 1798 __le16 lb_mode; 1799 #define I40E_AQ_LB_PHY_LOCAL 0x01 1800 #define I40E_AQ_LB_PHY_REMOTE 0x02 1801 #define I40E_AQ_LB_MAC_LOCAL 0x04 1802 u8 reserved[14]; 1803 }; 1804 1805 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1806 1807 /* Set PHY Debug command (0x0622) */ 1808 struct i40e_aqc_set_phy_debug { 1809 u8 command_flags; 1810 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1811 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1812 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1813 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1814 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1815 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1816 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1817 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1818 u8 reserved[15]; 1819 }; 1820 1821 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1822 1823 enum i40e_aq_phy_reg_type { 1824 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1825 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1826 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1827 }; 1828 1829 /* NVM Read command (indirect 0x0701) 1830 * NVM Erase commands (direct 0x0702) 1831 * NVM Update commands (indirect 0x0703) 1832 */ 1833 struct i40e_aqc_nvm_update { 1834 u8 command_flags; 1835 #define I40E_AQ_NVM_LAST_CMD 0x01 1836 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1837 u8 module_pointer; 1838 __le16 length; 1839 __le32 offset; 1840 __le32 addr_high; 1841 __le32 addr_low; 1842 }; 1843 1844 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1845 1846 /* NVM Config Read (indirect 0x0704) */ 1847 struct i40e_aqc_nvm_config_read { 1848 __le16 cmd_flags; 1849 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1850 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1851 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1852 __le16 element_count; 1853 __le16 element_id; /* Feature/field ID */ 1854 __le16 element_id_msw; /* MSWord of field ID */ 1855 __le32 address_high; 1856 __le32 address_low; 1857 }; 1858 1859 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1860 1861 /* NVM Config Write (indirect 0x0705) */ 1862 struct i40e_aqc_nvm_config_write { 1863 __le16 cmd_flags; 1864 __le16 element_count; 1865 u8 reserved[4]; 1866 __le32 address_high; 1867 __le32 address_low; 1868 }; 1869 1870 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1871 1872 /* Used for 0x0704 as well as for 0x0705 commands */ 1873 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1874 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1875 #define I40E_AQ_ANVM_FEATURE 0 1876 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1877 struct i40e_aqc_nvm_config_data_feature { 1878 __le16 feature_id; 1879 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1880 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1881 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1882 __le16 feature_options; 1883 __le16 feature_selection; 1884 }; 1885 1886 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1887 1888 struct i40e_aqc_nvm_config_data_immediate_field { 1889 __le32 field_id; 1890 __le32 field_value; 1891 __le16 field_options; 1892 __le16 reserved; 1893 }; 1894 1895 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1896 1897 /* OEM Post Update (indirect 0x0720) 1898 * no command data struct used 1899 */ 1900 struct i40e_aqc_nvm_oem_post_update { 1901 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1902 u8 sel_data; 1903 u8 reserved[7]; 1904 }; 1905 1906 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1907 1908 struct i40e_aqc_nvm_oem_post_update_buffer { 1909 u8 str_len; 1910 u8 dev_addr; 1911 __le16 eeprom_addr; 1912 u8 data[36]; 1913 }; 1914 1915 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1916 1917 /* Send to PF command (indirect 0x0801) id is only used by PF 1918 * Send to VF command (indirect 0x0802) id is only used by PF 1919 * Send to Peer PF command (indirect 0x0803) 1920 */ 1921 struct i40e_aqc_pf_vf_message { 1922 __le32 id; 1923 u8 reserved[4]; 1924 __le32 addr_high; 1925 __le32 addr_low; 1926 }; 1927 1928 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1929 1930 /* Alternate structure */ 1931 1932 /* Direct write (direct 0x0900) 1933 * Direct read (direct 0x0902) 1934 */ 1935 struct i40e_aqc_alternate_write { 1936 __le32 address0; 1937 __le32 data0; 1938 __le32 address1; 1939 __le32 data1; 1940 }; 1941 1942 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1943 1944 /* Indirect write (indirect 0x0901) 1945 * Indirect read (indirect 0x0903) 1946 */ 1947 1948 struct i40e_aqc_alternate_ind_write { 1949 __le32 address; 1950 __le32 length; 1951 __le32 addr_high; 1952 __le32 addr_low; 1953 }; 1954 1955 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1956 1957 /* Done alternate write (direct 0x0904) 1958 * uses i40e_aq_desc 1959 */ 1960 struct i40e_aqc_alternate_write_done { 1961 __le16 cmd_flags; 1962 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1963 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1964 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1965 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1966 u8 reserved[14]; 1967 }; 1968 1969 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1970 1971 /* Set OEM mode (direct 0x0905) */ 1972 struct i40e_aqc_alternate_set_mode { 1973 __le32 mode; 1974 #define I40E_AQ_ALTERNATE_MODE_NONE 0 1975 #define I40E_AQ_ALTERNATE_MODE_OEM 1 1976 u8 reserved[12]; 1977 }; 1978 1979 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1980 1981 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1982 1983 /* async events 0x10xx */ 1984 1985 /* Lan Queue Overflow Event (direct, 0x1001) */ 1986 struct i40e_aqc_lan_overflow { 1987 __le32 prtdcb_rupto; 1988 __le32 otx_ctl; 1989 u8 reserved[8]; 1990 }; 1991 1992 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1993 1994 /* Get LLDP MIB (indirect 0x0A00) */ 1995 struct i40e_aqc_lldp_get_mib { 1996 u8 type; 1997 u8 reserved1; 1998 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1999 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2000 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2001 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2002 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2003 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2004 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2005 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2006 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2007 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2008 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2009 __le16 local_len; 2010 __le16 remote_len; 2011 u8 reserved2[2]; 2012 __le32 addr_high; 2013 __le32 addr_low; 2014 }; 2015 2016 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2017 2018 /* Configure LLDP MIB Change Event (direct 0x0A01) 2019 * also used for the event (with type in the command field) 2020 */ 2021 struct i40e_aqc_lldp_update_mib { 2022 u8 command; 2023 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2024 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2025 u8 reserved[7]; 2026 __le32 addr_high; 2027 __le32 addr_low; 2028 }; 2029 2030 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2031 2032 /* Add LLDP TLV (indirect 0x0A02) 2033 * Delete LLDP TLV (indirect 0x0A04) 2034 */ 2035 struct i40e_aqc_lldp_add_tlv { 2036 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2037 u8 reserved1[1]; 2038 __le16 len; 2039 u8 reserved2[4]; 2040 __le32 addr_high; 2041 __le32 addr_low; 2042 }; 2043 2044 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2045 2046 /* Update LLDP TLV (indirect 0x0A03) */ 2047 struct i40e_aqc_lldp_update_tlv { 2048 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2049 u8 reserved; 2050 __le16 old_len; 2051 __le16 new_offset; 2052 __le16 new_len; 2053 __le32 addr_high; 2054 __le32 addr_low; 2055 }; 2056 2057 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2058 2059 /* Stop LLDP (direct 0x0A05) */ 2060 struct i40e_aqc_lldp_stop { 2061 u8 command; 2062 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2063 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2064 u8 reserved[15]; 2065 }; 2066 2067 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2068 2069 /* Start LLDP (direct 0x0A06) */ 2070 2071 struct i40e_aqc_lldp_start { 2072 u8 command; 2073 #define I40E_AQ_LLDP_AGENT_START 0x1 2074 u8 reserved[15]; 2075 }; 2076 2077 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2078 2079 /* Get CEE DCBX Oper Config (0x0A07) 2080 * uses the generic descriptor struct 2081 * returns below as indirect response 2082 */ 2083 2084 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2085 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2086 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2087 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2088 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2089 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2090 2091 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2092 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2093 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2094 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2095 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2096 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2097 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2098 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2099 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2100 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2101 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2102 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2103 2104 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2105 * word boundary layout issues, which the Linux compilers silently deal 2106 * with by adding padding, making the actual struct larger than designed. 2107 * However, the FW compiler for the NIC is less lenient and complains 2108 * about the struct. Hence, the struct defined here has an extra byte in 2109 * fields reserved3 and reserved4 to directly acknowledge that padding, 2110 * and the new length is used in the length check macro. 2111 */ 2112 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2113 u8 reserved1; 2114 u8 oper_num_tc; 2115 u8 oper_prio_tc[4]; 2116 u8 reserved2; 2117 u8 oper_tc_bw[8]; 2118 u8 oper_pfc_en; 2119 u8 reserved3[2]; 2120 __le16 oper_app_prio; 2121 u8 reserved4[2]; 2122 __le16 tlv_status; 2123 }; 2124 2125 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2126 2127 struct i40e_aqc_get_cee_dcb_cfg_resp { 2128 u8 oper_num_tc; 2129 u8 oper_prio_tc[4]; 2130 u8 oper_tc_bw[8]; 2131 u8 oper_pfc_en; 2132 __le16 oper_app_prio; 2133 __le32 tlv_status; 2134 u8 reserved[12]; 2135 }; 2136 2137 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2138 2139 /* Set Local LLDP MIB (indirect 0x0A08) 2140 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2141 */ 2142 struct i40e_aqc_lldp_set_local_mib { 2143 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2144 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2145 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2146 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2147 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2148 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2149 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2150 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2151 u8 type; 2152 u8 reserved0; 2153 __le16 length; 2154 u8 reserved1[4]; 2155 __le32 address_high; 2156 __le32 address_low; 2157 }; 2158 2159 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2160 2161 struct i40e_aqc_lldp_set_local_mib_resp { 2162 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2163 u8 status; 2164 u8 reserved[15]; 2165 }; 2166 2167 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2168 2169 /* Stop/Start LLDP Agent (direct 0x0A09) 2170 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2171 */ 2172 struct i40e_aqc_lldp_stop_start_specific_agent { 2173 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2174 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2175 u8 command; 2176 u8 reserved[15]; 2177 }; 2178 2179 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2180 2181 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2182 struct i40e_aqc_add_udp_tunnel { 2183 __le16 udp_port; 2184 u8 reserved0[3]; 2185 u8 protocol_type; 2186 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2187 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2188 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2189 u8 reserved1[10]; 2190 }; 2191 2192 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2193 2194 struct i40e_aqc_add_udp_tunnel_completion { 2195 __le16 udp_port; 2196 u8 filter_entry_index; 2197 u8 multiple_pfs; 2198 #define I40E_AQC_SINGLE_PF 0x0 2199 #define I40E_AQC_MULTIPLE_PFS 0x1 2200 u8 total_filters; 2201 u8 reserved[11]; 2202 }; 2203 2204 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2205 2206 /* remove UDP Tunnel command (0x0B01) */ 2207 struct i40e_aqc_remove_udp_tunnel { 2208 u8 reserved[2]; 2209 u8 index; /* 0 to 15 */ 2210 u8 reserved2[13]; 2211 }; 2212 2213 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2214 2215 struct i40e_aqc_del_udp_tunnel_completion { 2216 __le16 udp_port; 2217 u8 index; /* 0 to 15 */ 2218 u8 multiple_pfs; 2219 u8 total_filters_used; 2220 u8 reserved1[11]; 2221 }; 2222 2223 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2224 2225 /* tunnel key structure 0x0B10 */ 2226 2227 struct i40e_aqc_tunnel_key_structure { 2228 u8 key1_off; 2229 u8 key2_off; 2230 u8 key1_len; /* 0 to 15 */ 2231 u8 key2_len; /* 0 to 15 */ 2232 u8 flags; 2233 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2234 /* response flags */ 2235 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2236 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2237 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2238 u8 network_key_index; 2239 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2240 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2241 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2242 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2243 u8 reserved[10]; 2244 }; 2245 2246 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2247 2248 /* OEM mode commands (direct 0xFE0x) */ 2249 struct i40e_aqc_oem_param_change { 2250 __le32 param_type; 2251 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2252 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2253 #define I40E_AQ_OEM_PARAM_MAC 2 2254 __le32 param_value1; 2255 __le16 param_value2; 2256 u8 reserved[6]; 2257 }; 2258 2259 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2260 2261 struct i40e_aqc_oem_state_change { 2262 __le32 state; 2263 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2264 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2265 u8 reserved[12]; 2266 }; 2267 2268 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2269 2270 /* Initialize OCSD (0xFE02, direct) */ 2271 struct i40e_aqc_opc_oem_ocsd_initialize { 2272 u8 type_status; 2273 u8 reserved1[3]; 2274 __le32 ocsd_memory_block_addr_high; 2275 __le32 ocsd_memory_block_addr_low; 2276 __le32 requested_update_interval; 2277 }; 2278 2279 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2280 2281 /* Initialize OCBB (0xFE03, direct) */ 2282 struct i40e_aqc_opc_oem_ocbb_initialize { 2283 u8 type_status; 2284 u8 reserved1[3]; 2285 __le32 ocbb_memory_block_addr_high; 2286 __le32 ocbb_memory_block_addr_low; 2287 u8 reserved2[4]; 2288 }; 2289 2290 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2291 2292 /* debug commands */ 2293 2294 /* get device id (0xFF00) uses the generic structure */ 2295 2296 /* set test more (0xFF01, internal) */ 2297 2298 struct i40e_acq_set_test_mode { 2299 u8 mode; 2300 #define I40E_AQ_TEST_PARTIAL 0 2301 #define I40E_AQ_TEST_FULL 1 2302 #define I40E_AQ_TEST_NVM 2 2303 u8 reserved[3]; 2304 u8 command; 2305 #define I40E_AQ_TEST_OPEN 0 2306 #define I40E_AQ_TEST_CLOSE 1 2307 #define I40E_AQ_TEST_INC 2 2308 u8 reserved2[3]; 2309 __le32 address_high; 2310 __le32 address_low; 2311 }; 2312 2313 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2314 2315 /* Debug Read Register command (0xFF03) 2316 * Debug Write Register command (0xFF04) 2317 */ 2318 struct i40e_aqc_debug_reg_read_write { 2319 __le32 reserved; 2320 __le32 address; 2321 __le32 value_high; 2322 __le32 value_low; 2323 }; 2324 2325 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2326 2327 /* Scatter/gather Reg Read (indirect 0xFF05) 2328 * Scatter/gather Reg Write (indirect 0xFF06) 2329 */ 2330 2331 /* i40e_aq_desc is used for the command */ 2332 struct i40e_aqc_debug_reg_sg_element_data { 2333 __le32 address; 2334 __le32 value; 2335 }; 2336 2337 /* Debug Modify register (direct 0xFF07) */ 2338 struct i40e_aqc_debug_modify_reg { 2339 __le32 address; 2340 __le32 value; 2341 __le32 clear_mask; 2342 __le32 set_mask; 2343 }; 2344 2345 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2346 2347 /* dump internal data (0xFF08, indirect) */ 2348 2349 #define I40E_AQ_CLUSTER_ID_AUX 0 2350 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2351 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2352 #define I40E_AQ_CLUSTER_ID_HMC 3 2353 #define I40E_AQ_CLUSTER_ID_MAC0 4 2354 #define I40E_AQ_CLUSTER_ID_MAC1 5 2355 #define I40E_AQ_CLUSTER_ID_MAC2 6 2356 #define I40E_AQ_CLUSTER_ID_MAC3 7 2357 #define I40E_AQ_CLUSTER_ID_DCB 8 2358 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2359 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2360 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2361 2362 struct i40e_aqc_debug_dump_internals { 2363 u8 cluster_id; 2364 u8 table_id; 2365 __le16 data_size; 2366 __le32 idx; 2367 __le32 address_high; 2368 __le32 address_low; 2369 }; 2370 2371 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2372 2373 struct i40e_aqc_debug_modify_internals { 2374 u8 cluster_id; 2375 u8 cluster_specific_params[7]; 2376 __le32 address_high; 2377 __le32 address_low; 2378 }; 2379 2380 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2381 2382 #endif /* _I40E_ADMINQ_CMD_H_ */ 2383