1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_ADMINQ_CMD_H_ 36 #define _I40E_ADMINQ_CMD_H_ 37 38 /* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 #define I40E_FW_API_VERSION_MAJOR 0x0001 45 #define I40E_FW_API_VERSION_MINOR 0x0004 46 47 struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69 }; 70 71 /* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76 /* command flags and offsets*/ 77 #define I40E_AQ_FLAG_DD_SHIFT 0 78 #define I40E_AQ_FLAG_CMP_SHIFT 1 79 #define I40E_AQ_FLAG_ERR_SHIFT 2 80 #define I40E_AQ_FLAG_VFE_SHIFT 3 81 #define I40E_AQ_FLAG_LB_SHIFT 9 82 #define I40E_AQ_FLAG_RD_SHIFT 10 83 #define I40E_AQ_FLAG_VFC_SHIFT 11 84 #define I40E_AQ_FLAG_BUF_SHIFT 12 85 #define I40E_AQ_FLAG_SI_SHIFT 13 86 #define I40E_AQ_FLAG_EI_SHIFT 14 87 #define I40E_AQ_FLAG_FE_SHIFT 15 88 89 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101 /* error codes */ 102 enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126 }; 127 128 /* Admin Queue command opcodes */ 129 enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* LAA */ 144 i40e_aqc_opc_mac_address_read = 0x0107, 145 i40e_aqc_opc_mac_address_write = 0x0108, 146 147 /* PXE */ 148 i40e_aqc_opc_clear_pxe_mode = 0x0110, 149 150 /* internal switch commands */ 151 i40e_aqc_opc_get_switch_config = 0x0200, 152 i40e_aqc_opc_add_statistics = 0x0201, 153 i40e_aqc_opc_remove_statistics = 0x0202, 154 i40e_aqc_opc_set_port_parameters = 0x0203, 155 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156 157 i40e_aqc_opc_add_vsi = 0x0210, 158 i40e_aqc_opc_update_vsi_parameters = 0x0211, 159 i40e_aqc_opc_get_vsi_parameters = 0x0212, 160 161 i40e_aqc_opc_add_pv = 0x0220, 162 i40e_aqc_opc_update_pv_parameters = 0x0221, 163 i40e_aqc_opc_get_pv_parameters = 0x0222, 164 165 i40e_aqc_opc_add_veb = 0x0230, 166 i40e_aqc_opc_update_veb_parameters = 0x0231, 167 i40e_aqc_opc_get_veb_parameters = 0x0232, 168 169 i40e_aqc_opc_delete_element = 0x0243, 170 171 i40e_aqc_opc_add_macvlan = 0x0250, 172 i40e_aqc_opc_remove_macvlan = 0x0251, 173 i40e_aqc_opc_add_vlan = 0x0252, 174 i40e_aqc_opc_remove_vlan = 0x0253, 175 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 176 i40e_aqc_opc_add_tag = 0x0255, 177 i40e_aqc_opc_remove_tag = 0x0256, 178 i40e_aqc_opc_add_multicast_etag = 0x0257, 179 i40e_aqc_opc_remove_multicast_etag = 0x0258, 180 i40e_aqc_opc_update_tag = 0x0259, 181 i40e_aqc_opc_add_control_packet_filter = 0x025A, 182 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 183 i40e_aqc_opc_add_cloud_filters = 0x025C, 184 i40e_aqc_opc_remove_cloud_filters = 0x025D, 185 186 i40e_aqc_opc_add_mirror_rule = 0x0260, 187 i40e_aqc_opc_delete_mirror_rule = 0x0261, 188 189 /* DCB commands */ 190 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 191 i40e_aqc_opc_dcb_updated = 0x0302, 192 193 /* TX scheduler */ 194 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 195 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 196 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 197 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 198 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 199 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 200 201 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 202 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 203 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 204 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 205 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 206 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 207 i40e_aqc_opc_query_port_ets_config = 0x0419, 208 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 209 i40e_aqc_opc_suspend_port_tx = 0x041B, 210 i40e_aqc_opc_resume_port_tx = 0x041C, 211 i40e_aqc_opc_configure_partition_bw = 0x041D, 212 213 /* hmc */ 214 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 215 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 216 217 /* phy commands*/ 218 i40e_aqc_opc_get_phy_abilities = 0x0600, 219 i40e_aqc_opc_set_phy_config = 0x0601, 220 i40e_aqc_opc_set_mac_config = 0x0603, 221 i40e_aqc_opc_set_link_restart_an = 0x0605, 222 i40e_aqc_opc_get_link_status = 0x0607, 223 i40e_aqc_opc_set_phy_int_mask = 0x0613, 224 i40e_aqc_opc_get_local_advt_reg = 0x0614, 225 i40e_aqc_opc_set_local_advt_reg = 0x0615, 226 i40e_aqc_opc_get_partner_advt = 0x0616, 227 i40e_aqc_opc_set_lb_modes = 0x0618, 228 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 229 i40e_aqc_opc_set_phy_debug = 0x0622, 230 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 231 232 /* NVM commands */ 233 i40e_aqc_opc_nvm_read = 0x0701, 234 i40e_aqc_opc_nvm_erase = 0x0702, 235 i40e_aqc_opc_nvm_update = 0x0703, 236 i40e_aqc_opc_nvm_config_read = 0x0704, 237 i40e_aqc_opc_nvm_config_write = 0x0705, 238 239 /* virtualization commands */ 240 i40e_aqc_opc_send_msg_to_pf = 0x0801, 241 i40e_aqc_opc_send_msg_to_vf = 0x0802, 242 i40e_aqc_opc_send_msg_to_peer = 0x0803, 243 244 /* alternate structure */ 245 i40e_aqc_opc_alternate_write = 0x0900, 246 i40e_aqc_opc_alternate_write_indirect = 0x0901, 247 i40e_aqc_opc_alternate_read = 0x0902, 248 i40e_aqc_opc_alternate_read_indirect = 0x0903, 249 i40e_aqc_opc_alternate_write_done = 0x0904, 250 i40e_aqc_opc_alternate_set_mode = 0x0905, 251 i40e_aqc_opc_alternate_clear_port = 0x0906, 252 253 /* LLDP commands */ 254 i40e_aqc_opc_lldp_get_mib = 0x0A00, 255 i40e_aqc_opc_lldp_update_mib = 0x0A01, 256 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 257 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 258 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 259 i40e_aqc_opc_lldp_stop = 0x0A05, 260 i40e_aqc_opc_lldp_start = 0x0A06, 261 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 262 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 263 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 264 265 /* Tunnel commands */ 266 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 267 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 268 269 /* Async Events */ 270 i40e_aqc_opc_event_lan_overflow = 0x1001, 271 272 /* OEM commands */ 273 i40e_aqc_opc_oem_parameter_change = 0xFE00, 274 i40e_aqc_opc_oem_device_status_change = 0xFE01, 275 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 276 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 277 278 /* debug commands */ 279 i40e_aqc_opc_debug_read_reg = 0xFF03, 280 i40e_aqc_opc_debug_write_reg = 0xFF04, 281 i40e_aqc_opc_debug_modify_reg = 0xFF07, 282 i40e_aqc_opc_debug_dump_internals = 0xFF08, 283 }; 284 285 /* command structures and indirect data structures */ 286 287 /* Structure naming conventions: 288 * - no suffix for direct command descriptor structures 289 * - _data for indirect sent data 290 * - _resp for indirect return data (data which is both will use _data) 291 * - _completion for direct return data 292 * - _element_ for repeated elements (may also be _data or _resp) 293 * 294 * Command structures are expected to overlay the params.raw member of the basic 295 * descriptor, and as such cannot exceed 16 bytes in length. 296 */ 297 298 /* This macro is used to generate a compilation error if a structure 299 * is not exactly the correct length. It gives a divide by zero error if the 300 * structure is not of the correct size, otherwise it creates an enum that is 301 * never used. 302 */ 303 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 304 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 305 306 /* This macro is used extensively to ensure that command structures are 16 307 * bytes in length as they have to map to the raw array of that size. 308 */ 309 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 310 311 /* internal (0x00XX) commands */ 312 313 /* Get version (direct 0x0001) */ 314 struct i40e_aqc_get_version { 315 __le32 rom_ver; 316 __le32 fw_build; 317 __le16 fw_major; 318 __le16 fw_minor; 319 __le16 api_major; 320 __le16 api_minor; 321 }; 322 323 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 324 325 /* Send driver version (indirect 0x0002) */ 326 struct i40e_aqc_driver_version { 327 u8 driver_major_ver; 328 u8 driver_minor_ver; 329 u8 driver_build_ver; 330 u8 driver_subbuild_ver; 331 u8 reserved[4]; 332 __le32 address_high; 333 __le32 address_low; 334 }; 335 336 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 337 338 /* Queue Shutdown (direct 0x0003) */ 339 struct i40e_aqc_queue_shutdown { 340 __le32 driver_unloading; 341 #define I40E_AQ_DRIVER_UNLOADING 0x1 342 u8 reserved[12]; 343 }; 344 345 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 346 347 /* Set PF context (0x0004, direct) */ 348 struct i40e_aqc_set_pf_context { 349 u8 pf_id; 350 u8 reserved[15]; 351 }; 352 353 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 354 355 /* Request resource ownership (direct 0x0008) 356 * Release resource ownership (direct 0x0009) 357 */ 358 #define I40E_AQ_RESOURCE_NVM 1 359 #define I40E_AQ_RESOURCE_SDP 2 360 #define I40E_AQ_RESOURCE_ACCESS_READ 1 361 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 362 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 363 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 364 365 struct i40e_aqc_request_resource { 366 __le16 resource_id; 367 __le16 access_type; 368 __le32 timeout; 369 __le32 resource_number; 370 u8 reserved[4]; 371 }; 372 373 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 374 375 /* Get function capabilities (indirect 0x000A) 376 * Get device capabilities (indirect 0x000B) 377 */ 378 struct i40e_aqc_list_capabilites { 379 u8 command_flags; 380 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 381 u8 pf_index; 382 u8 reserved[2]; 383 __le32 count; 384 __le32 addr_high; 385 __le32 addr_low; 386 }; 387 388 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 389 390 struct i40e_aqc_list_capabilities_element_resp { 391 __le16 id; 392 u8 major_rev; 393 u8 minor_rev; 394 __le32 number; 395 __le32 logical_id; 396 __le32 phys_id; 397 u8 reserved[16]; 398 }; 399 400 /* list of caps */ 401 402 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 403 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 404 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 405 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 406 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 407 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 408 #define I40E_AQ_CAP_ID_SRIOV 0x0012 409 #define I40E_AQ_CAP_ID_VF 0x0013 410 #define I40E_AQ_CAP_ID_VMDQ 0x0014 411 #define I40E_AQ_CAP_ID_8021QBG 0x0015 412 #define I40E_AQ_CAP_ID_8021QBR 0x0016 413 #define I40E_AQ_CAP_ID_VSI 0x0017 414 #define I40E_AQ_CAP_ID_DCB 0x0018 415 #define I40E_AQ_CAP_ID_FCOE 0x0021 416 #define I40E_AQ_CAP_ID_ISCSI 0x0022 417 #define I40E_AQ_CAP_ID_RSS 0x0040 418 #define I40E_AQ_CAP_ID_RXQ 0x0041 419 #define I40E_AQ_CAP_ID_TXQ 0x0042 420 #define I40E_AQ_CAP_ID_MSIX 0x0043 421 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 422 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 423 #define I40E_AQ_CAP_ID_1588 0x0046 424 #define I40E_AQ_CAP_ID_IWARP 0x0051 425 #define I40E_AQ_CAP_ID_LED 0x0061 426 #define I40E_AQ_CAP_ID_SDP 0x0062 427 #define I40E_AQ_CAP_ID_MDIO 0x0063 428 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 429 #define I40E_AQ_CAP_ID_CEM 0x00F2 430 431 /* Set CPPM Configuration (direct 0x0103) */ 432 struct i40e_aqc_cppm_configuration { 433 __le16 command_flags; 434 #define I40E_AQ_CPPM_EN_LTRC 0x0800 435 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 436 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 437 #define I40E_AQ_CPPM_EN_HPTC 0x4000 438 #define I40E_AQ_CPPM_EN_DMARC 0x8000 439 __le16 ttlx; 440 __le32 dmacr; 441 __le16 dmcth; 442 u8 hptc; 443 u8 reserved; 444 __le32 pfltrc; 445 }; 446 447 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 448 449 /* Set ARP Proxy command / response (indirect 0x0104) */ 450 struct i40e_aqc_arp_proxy_data { 451 __le16 command_flags; 452 #define I40E_AQ_ARP_INIT_IPV4 0x0008 453 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 454 #define I40E_AQ_ARP_ENA 0x0020 455 #define I40E_AQ_ARP_ADD_IPV4 0x0040 456 #define I40E_AQ_ARP_DEL_IPV4 0x0080 457 __le16 table_id; 458 __le32 pfpm_proxyfc; 459 __le32 ip_addr; 460 u8 mac_addr[6]; 461 u8 reserved[2]; 462 }; 463 464 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 465 466 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 467 struct i40e_aqc_ns_proxy_data { 468 __le16 table_idx_mac_addr_0; 469 __le16 table_idx_mac_addr_1; 470 __le16 table_idx_ipv6_0; 471 __le16 table_idx_ipv6_1; 472 __le16 control; 473 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 474 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 475 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 476 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 477 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 478 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 479 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 480 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 481 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 482 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 483 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 484 u8 mac_addr_0[6]; 485 u8 mac_addr_1[6]; 486 u8 local_mac_addr[6]; 487 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 488 u8 ipv6_addr_1[16]; 489 }; 490 491 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 492 493 /* Manage LAA Command (0x0106) - obsolete */ 494 struct i40e_aqc_mng_laa { 495 __le16 command_flags; 496 #define I40E_AQ_LAA_FLAG_WR 0x8000 497 u8 reserved[2]; 498 __le32 sal; 499 __le16 sah; 500 u8 reserved2[6]; 501 }; 502 503 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 504 505 /* Manage MAC Address Read Command (indirect 0x0107) */ 506 struct i40e_aqc_mac_address_read { 507 __le16 command_flags; 508 #define I40E_AQC_LAN_ADDR_VALID 0x10 509 #define I40E_AQC_SAN_ADDR_VALID 0x20 510 #define I40E_AQC_PORT_ADDR_VALID 0x40 511 #define I40E_AQC_WOL_ADDR_VALID 0x80 512 #define I40E_AQC_MC_MAG_EN_VALID 0x100 513 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 514 u8 reserved[6]; 515 __le32 addr_high; 516 __le32 addr_low; 517 }; 518 519 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 520 521 struct i40e_aqc_mac_address_read_data { 522 u8 pf_lan_mac[6]; 523 u8 pf_san_mac[6]; 524 u8 port_mac[6]; 525 u8 pf_wol_mac[6]; 526 }; 527 528 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 529 530 /* Manage MAC Address Write Command (0x0108) */ 531 struct i40e_aqc_mac_address_write { 532 __le16 command_flags; 533 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 534 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 535 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 536 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 537 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 538 539 __le16 mac_sah; 540 __le32 mac_sal; 541 u8 reserved[8]; 542 }; 543 544 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 545 546 /* PXE commands (0x011x) */ 547 548 /* Clear PXE Command and response (direct 0x0110) */ 549 struct i40e_aqc_clear_pxe { 550 u8 rx_cnt; 551 u8 reserved[15]; 552 }; 553 554 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 555 556 /* Switch configuration commands (0x02xx) */ 557 558 /* Used by many indirect commands that only pass an seid and a buffer in the 559 * command 560 */ 561 struct i40e_aqc_switch_seid { 562 __le16 seid; 563 u8 reserved[6]; 564 __le32 addr_high; 565 __le32 addr_low; 566 }; 567 568 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 569 570 /* Get Switch Configuration command (indirect 0x0200) 571 * uses i40e_aqc_switch_seid for the descriptor 572 */ 573 struct i40e_aqc_get_switch_config_header_resp { 574 __le16 num_reported; 575 __le16 num_total; 576 u8 reserved[12]; 577 }; 578 579 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 580 581 struct i40e_aqc_switch_config_element_resp { 582 u8 element_type; 583 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 584 #define I40E_AQ_SW_ELEM_TYPE_PF 2 585 #define I40E_AQ_SW_ELEM_TYPE_VF 3 586 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 587 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 588 #define I40E_AQ_SW_ELEM_TYPE_PV 16 589 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 590 #define I40E_AQ_SW_ELEM_TYPE_PA 18 591 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 592 u8 revision; 593 #define I40E_AQ_SW_ELEM_REV_1 1 594 __le16 seid; 595 __le16 uplink_seid; 596 __le16 downlink_seid; 597 u8 reserved[3]; 598 u8 connection_type; 599 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 600 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 601 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 602 __le16 scheduler_id; 603 __le16 element_info; 604 }; 605 606 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 607 608 /* Get Switch Configuration (indirect 0x0200) 609 * an array of elements are returned in the response buffer 610 * the first in the array is the header, remainder are elements 611 */ 612 struct i40e_aqc_get_switch_config_resp { 613 struct i40e_aqc_get_switch_config_header_resp header; 614 struct i40e_aqc_switch_config_element_resp element[1]; 615 }; 616 617 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 618 619 /* Add Statistics (direct 0x0201) 620 * Remove Statistics (direct 0x0202) 621 */ 622 struct i40e_aqc_add_remove_statistics { 623 __le16 seid; 624 __le16 vlan; 625 __le16 stat_index; 626 u8 reserved[10]; 627 }; 628 629 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 630 631 /* Set Port Parameters command (direct 0x0203) */ 632 struct i40e_aqc_set_port_parameters { 633 __le16 command_flags; 634 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 635 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 636 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 637 __le16 bad_frame_vsi; 638 __le16 default_seid; /* reserved for command */ 639 u8 reserved[10]; 640 }; 641 642 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 643 644 /* Get Switch Resource Allocation (indirect 0x0204) */ 645 struct i40e_aqc_get_switch_resource_alloc { 646 u8 num_entries; /* reserved for command */ 647 u8 reserved[7]; 648 __le32 addr_high; 649 __le32 addr_low; 650 }; 651 652 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 653 654 /* expect an array of these structs in the response buffer */ 655 struct i40e_aqc_switch_resource_alloc_element_resp { 656 u8 resource_type; 657 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 658 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 659 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 660 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 661 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 662 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 663 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 664 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 665 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 666 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 667 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 668 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 669 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 670 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 671 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 672 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 673 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 674 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 675 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 676 u8 reserved1; 677 __le16 guaranteed; 678 __le16 total; 679 __le16 used; 680 __le16 total_unalloced; 681 u8 reserved2[6]; 682 }; 683 684 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 685 686 /* Add VSI (indirect 0x0210) 687 * this indirect command uses struct i40e_aqc_vsi_properties_data 688 * as the indirect buffer (128 bytes) 689 * 690 * Update VSI (indirect 0x211) 691 * uses the same data structure as Add VSI 692 * 693 * Get VSI (indirect 0x0212) 694 * uses the same completion and data structure as Add VSI 695 */ 696 struct i40e_aqc_add_get_update_vsi { 697 __le16 uplink_seid; 698 u8 connection_type; 699 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 700 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 701 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 702 u8 reserved1; 703 u8 vf_id; 704 u8 reserved2; 705 __le16 vsi_flags; 706 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 707 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 708 #define I40E_AQ_VSI_TYPE_VF 0x0 709 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 710 #define I40E_AQ_VSI_TYPE_PF 0x2 711 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 712 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 713 __le32 addr_high; 714 __le32 addr_low; 715 }; 716 717 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 718 719 struct i40e_aqc_add_get_update_vsi_completion { 720 __le16 seid; 721 __le16 vsi_number; 722 __le16 vsi_used; 723 __le16 vsi_free; 724 __le32 addr_high; 725 __le32 addr_low; 726 }; 727 728 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 729 730 struct i40e_aqc_vsi_properties_data { 731 /* first 96 byte are written by SW */ 732 __le16 valid_sections; 733 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 734 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 735 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 736 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 737 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 738 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 739 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 740 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 741 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 742 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 743 /* switch section */ 744 __le16 switch_id; /* 12bit id combined with flags below */ 745 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 746 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 747 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 748 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 749 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 750 u8 sw_reserved[2]; 751 /* security section */ 752 u8 sec_flags; 753 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 754 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 755 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 756 u8 sec_reserved; 757 /* VLAN section */ 758 __le16 pvid; /* VLANS include priority bits */ 759 __le16 fcoe_pvid; 760 u8 port_vlan_flags; 761 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 762 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 763 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 764 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 765 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 766 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 767 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 768 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 769 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 770 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 771 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 772 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 773 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 774 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 775 u8 pvlan_reserved[3]; 776 /* ingress egress up sections */ 777 __le32 ingress_table; /* bitmap, 3 bits per up */ 778 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 779 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 780 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 781 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 782 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 783 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 784 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 785 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 786 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 787 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 788 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 789 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 790 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 791 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 792 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 793 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 794 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 795 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 796 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 797 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 798 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 799 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 800 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 801 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 802 __le32 egress_table; /* same defines as for ingress table */ 803 /* cascaded PV section */ 804 __le16 cas_pv_tag; 805 u8 cas_pv_flags; 806 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 807 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 808 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 809 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 810 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 811 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 812 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 813 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 814 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 815 u8 cas_pv_reserved; 816 /* queue mapping section */ 817 __le16 mapping_flags; 818 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 819 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 820 __le16 queue_mapping[16]; 821 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 822 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 823 __le16 tc_mapping[8]; 824 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 825 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 826 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 827 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 828 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 829 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 830 /* queueing option section */ 831 u8 queueing_opt_flags; 832 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 833 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 834 u8 queueing_opt_reserved[3]; 835 /* scheduler section */ 836 u8 up_enable_bits; 837 u8 sched_reserved; 838 /* outer up section */ 839 __le32 outer_up_table; /* same structure and defines as ingress table */ 840 u8 cmd_reserved[8]; 841 /* last 32 bytes are written by FW */ 842 __le16 qs_handle[8]; 843 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 844 __le16 stat_counter_idx; 845 __le16 sched_id; 846 u8 resp_reserved[12]; 847 }; 848 849 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 850 851 /* Add Port Virtualizer (direct 0x0220) 852 * also used for update PV (direct 0x0221) but only flags are used 853 * (IS_CTRL_PORT only works on add PV) 854 */ 855 struct i40e_aqc_add_update_pv { 856 __le16 command_flags; 857 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 858 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 859 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 860 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 861 __le16 uplink_seid; 862 __le16 connected_seid; 863 u8 reserved[10]; 864 }; 865 866 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 867 868 struct i40e_aqc_add_update_pv_completion { 869 /* reserved for update; for add also encodes error if rc == ENOSPC */ 870 __le16 pv_seid; 871 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 872 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 873 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 874 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 875 u8 reserved[14]; 876 }; 877 878 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 879 880 /* Get PV Params (direct 0x0222) 881 * uses i40e_aqc_switch_seid for the descriptor 882 */ 883 884 struct i40e_aqc_get_pv_params_completion { 885 __le16 seid; 886 __le16 default_stag; 887 __le16 pv_flags; /* same flags as add_pv */ 888 #define I40E_AQC_GET_PV_PV_TYPE 0x1 889 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 890 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 891 u8 reserved[8]; 892 __le16 default_port_seid; 893 }; 894 895 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 896 897 /* Add VEB (direct 0x0230) */ 898 struct i40e_aqc_add_veb { 899 __le16 uplink_seid; 900 __le16 downlink_seid; 901 __le16 veb_flags; 902 #define I40E_AQC_ADD_VEB_FLOATING 0x1 903 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 904 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 905 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 906 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 907 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 908 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 909 u8 enable_tcs; 910 u8 reserved[9]; 911 }; 912 913 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 914 915 struct i40e_aqc_add_veb_completion { 916 u8 reserved[6]; 917 __le16 switch_seid; 918 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 919 __le16 veb_seid; 920 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 921 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 922 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 923 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 924 __le16 statistic_index; 925 __le16 vebs_used; 926 __le16 vebs_free; 927 }; 928 929 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 930 931 /* Get VEB Parameters (direct 0x0232) 932 * uses i40e_aqc_switch_seid for the descriptor 933 */ 934 struct i40e_aqc_get_veb_parameters_completion { 935 __le16 seid; 936 __le16 switch_id; 937 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 938 __le16 statistic_index; 939 __le16 vebs_used; 940 __le16 vebs_free; 941 u8 reserved[4]; 942 }; 943 944 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 945 946 /* Delete Element (direct 0x0243) 947 * uses the generic i40e_aqc_switch_seid 948 */ 949 950 /* Add MAC-VLAN (indirect 0x0250) */ 951 952 /* used for the command for most vlan commands */ 953 struct i40e_aqc_macvlan { 954 __le16 num_addresses; 955 __le16 seid[3]; 956 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 957 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 958 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 959 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 960 __le32 addr_high; 961 __le32 addr_low; 962 }; 963 964 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 965 966 /* indirect data for command and response */ 967 struct i40e_aqc_add_macvlan_element_data { 968 u8 mac_addr[6]; 969 __le16 vlan_tag; 970 __le16 flags; 971 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 972 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 973 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 974 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 975 __le16 queue_number; 976 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 977 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 978 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 979 /* response section */ 980 u8 match_method; 981 #define I40E_AQC_MM_PERFECT_MATCH 0x01 982 #define I40E_AQC_MM_HASH_MATCH 0x02 983 #define I40E_AQC_MM_ERR_NO_RES 0xFF 984 u8 reserved1[3]; 985 }; 986 987 struct i40e_aqc_add_remove_macvlan_completion { 988 __le16 perfect_mac_used; 989 __le16 perfect_mac_free; 990 __le16 unicast_hash_free; 991 __le16 multicast_hash_free; 992 __le32 addr_high; 993 __le32 addr_low; 994 }; 995 996 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 997 998 /* Remove MAC-VLAN (indirect 0x0251) 999 * uses i40e_aqc_macvlan for the descriptor 1000 * data points to an array of num_addresses of elements 1001 */ 1002 1003 struct i40e_aqc_remove_macvlan_element_data { 1004 u8 mac_addr[6]; 1005 __le16 vlan_tag; 1006 u8 flags; 1007 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1008 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1009 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1010 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1011 u8 reserved[3]; 1012 /* reply section */ 1013 u8 error_code; 1014 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1015 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1016 u8 reply_reserved[3]; 1017 }; 1018 1019 /* Add VLAN (indirect 0x0252) 1020 * Remove VLAN (indirect 0x0253) 1021 * use the generic i40e_aqc_macvlan for the command 1022 */ 1023 struct i40e_aqc_add_remove_vlan_element_data { 1024 __le16 vlan_tag; 1025 u8 vlan_flags; 1026 /* flags for add VLAN */ 1027 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1028 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1029 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1030 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1031 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1032 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1033 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1034 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1035 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1036 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1037 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1038 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1039 /* flags for remove VLAN */ 1040 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1041 u8 reserved; 1042 u8 result; 1043 /* flags for add VLAN */ 1044 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1045 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1046 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1047 /* flags for remove VLAN */ 1048 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1049 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1050 u8 reserved1[3]; 1051 }; 1052 1053 struct i40e_aqc_add_remove_vlan_completion { 1054 u8 reserved[4]; 1055 __le16 vlans_used; 1056 __le16 vlans_free; 1057 __le32 addr_high; 1058 __le32 addr_low; 1059 }; 1060 1061 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1062 struct i40e_aqc_set_vsi_promiscuous_modes { 1063 __le16 promiscuous_flags; 1064 __le16 valid_flags; 1065 /* flags used for both fields above */ 1066 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1067 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1068 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1069 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1070 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1071 __le16 seid; 1072 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1073 __le16 vlan_tag; 1074 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1075 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1076 u8 reserved[8]; 1077 }; 1078 1079 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1080 1081 /* Add S/E-tag command (direct 0x0255) 1082 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1083 */ 1084 struct i40e_aqc_add_tag { 1085 __le16 flags; 1086 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1087 __le16 seid; 1088 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1089 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1090 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1091 __le16 tag; 1092 __le16 queue_number; 1093 u8 reserved[8]; 1094 }; 1095 1096 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1097 1098 struct i40e_aqc_add_remove_tag_completion { 1099 u8 reserved[12]; 1100 __le16 tags_used; 1101 __le16 tags_free; 1102 }; 1103 1104 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1105 1106 /* Remove S/E-tag command (direct 0x0256) 1107 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1108 */ 1109 struct i40e_aqc_remove_tag { 1110 __le16 seid; 1111 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1112 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1113 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1114 __le16 tag; 1115 u8 reserved[12]; 1116 }; 1117 1118 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1119 1120 /* Add multicast E-Tag (direct 0x0257) 1121 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1122 * and no external data 1123 */ 1124 struct i40e_aqc_add_remove_mcast_etag { 1125 __le16 pv_seid; 1126 __le16 etag; 1127 u8 num_unicast_etags; 1128 u8 reserved[3]; 1129 __le32 addr_high; /* address of array of 2-byte s-tags */ 1130 __le32 addr_low; 1131 }; 1132 1133 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1134 1135 struct i40e_aqc_add_remove_mcast_etag_completion { 1136 u8 reserved[4]; 1137 __le16 mcast_etags_used; 1138 __le16 mcast_etags_free; 1139 __le32 addr_high; 1140 __le32 addr_low; 1141 1142 }; 1143 1144 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1145 1146 /* Update S/E-Tag (direct 0x0259) */ 1147 struct i40e_aqc_update_tag { 1148 __le16 seid; 1149 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1150 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1151 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1152 __le16 old_tag; 1153 __le16 new_tag; 1154 u8 reserved[10]; 1155 }; 1156 1157 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1158 1159 struct i40e_aqc_update_tag_completion { 1160 u8 reserved[12]; 1161 __le16 tags_used; 1162 __le16 tags_free; 1163 }; 1164 1165 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1166 1167 /* Add Control Packet filter (direct 0x025A) 1168 * Remove Control Packet filter (direct 0x025B) 1169 * uses the i40e_aqc_add_oveb_cloud, 1170 * and the generic direct completion structure 1171 */ 1172 struct i40e_aqc_add_remove_control_packet_filter { 1173 u8 mac[6]; 1174 __le16 etype; 1175 __le16 flags; 1176 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1181 __le16 seid; 1182 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1183 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1184 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1185 __le16 queue; 1186 u8 reserved[2]; 1187 }; 1188 1189 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1190 1191 struct i40e_aqc_add_remove_control_packet_filter_completion { 1192 __le16 mac_etype_used; 1193 __le16 etype_used; 1194 __le16 mac_etype_free; 1195 __le16 etype_free; 1196 u8 reserved[8]; 1197 }; 1198 1199 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1200 1201 /* Add Cloud filters (indirect 0x025C) 1202 * Remove Cloud filters (indirect 0x025D) 1203 * uses the i40e_aqc_add_remove_cloud_filters, 1204 * and the generic indirect completion structure 1205 */ 1206 struct i40e_aqc_add_remove_cloud_filters { 1207 u8 num_filters; 1208 u8 reserved; 1209 __le16 seid; 1210 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1211 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1212 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1213 u8 reserved2[4]; 1214 __le32 addr_high; 1215 __le32 addr_low; 1216 }; 1217 1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1219 1220 struct i40e_aqc_add_remove_cloud_filters_element_data { 1221 u8 outer_mac[6]; 1222 u8 inner_mac[6]; 1223 __le16 inner_vlan; 1224 union { 1225 struct { 1226 u8 reserved[12]; 1227 u8 data[4]; 1228 } v4; 1229 struct { 1230 u8 data[16]; 1231 } v6; 1232 } ipaddr; 1233 __le16 flags; 1234 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1235 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1236 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1237 /* 0x0000 reserved */ 1238 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1239 /* 0x0002 reserved */ 1240 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1241 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1242 /* 0x0005 reserved */ 1243 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1244 /* 0x0007 reserved */ 1245 /* 0x0008 reserved */ 1246 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1247 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1248 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1249 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1250 1251 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1252 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1253 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1254 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1255 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1256 1257 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1263 1264 __le32 tenant_id; 1265 u8 reserved[4]; 1266 __le16 queue_number; 1267 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1268 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1269 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1270 u8 reserved2[14]; 1271 /* response section */ 1272 u8 allocation_result; 1273 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1274 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1275 u8 response_reserved[7]; 1276 }; 1277 1278 struct i40e_aqc_remove_cloud_filters_completion { 1279 __le16 perfect_ovlan_used; 1280 __le16 perfect_ovlan_free; 1281 __le16 vlan_used; 1282 __le16 vlan_free; 1283 __le32 addr_high; 1284 __le32 addr_low; 1285 }; 1286 1287 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1288 1289 /* Add Mirror Rule (indirect or direct 0x0260) 1290 * Delete Mirror Rule (indirect or direct 0x0261) 1291 * note: some rule types (4,5) do not use an external buffer. 1292 * take care to set the flags correctly. 1293 */ 1294 struct i40e_aqc_add_delete_mirror_rule { 1295 __le16 seid; 1296 __le16 rule_type; 1297 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1298 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1299 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1300 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1301 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1302 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1303 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1304 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1305 __le16 num_entries; 1306 __le16 destination; /* VSI for add, rule id for delete */ 1307 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1308 __le32 addr_low; 1309 }; 1310 1311 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1312 1313 struct i40e_aqc_add_delete_mirror_rule_completion { 1314 u8 reserved[2]; 1315 __le16 rule_id; /* only used on add */ 1316 __le16 mirror_rules_used; 1317 __le16 mirror_rules_free; 1318 __le32 addr_high; 1319 __le32 addr_low; 1320 }; 1321 1322 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1323 1324 /* DCB 0x03xx*/ 1325 1326 /* PFC Ignore (direct 0x0301) 1327 * the command and response use the same descriptor structure 1328 */ 1329 struct i40e_aqc_pfc_ignore { 1330 u8 tc_bitmap; 1331 u8 command_flags; /* unused on response */ 1332 #define I40E_AQC_PFC_IGNORE_SET 0x80 1333 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1334 u8 reserved[14]; 1335 }; 1336 1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1338 1339 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1340 * with no parameters 1341 */ 1342 1343 /* TX scheduler 0x04xx */ 1344 1345 /* Almost all the indirect commands use 1346 * this generic struct to pass the SEID in param0 1347 */ 1348 struct i40e_aqc_tx_sched_ind { 1349 __le16 vsi_seid; 1350 u8 reserved[6]; 1351 __le32 addr_high; 1352 __le32 addr_low; 1353 }; 1354 1355 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1356 1357 /* Several commands respond with a set of queue set handles */ 1358 struct i40e_aqc_qs_handles_resp { 1359 __le16 qs_handles[8]; 1360 }; 1361 1362 /* Configure VSI BW limits (direct 0x0400) */ 1363 struct i40e_aqc_configure_vsi_bw_limit { 1364 __le16 vsi_seid; 1365 u8 reserved[2]; 1366 __le16 credit; 1367 u8 reserved1[2]; 1368 u8 max_credit; /* 0-3, limit = 2^max */ 1369 u8 reserved2[7]; 1370 }; 1371 1372 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1373 1374 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1375 * responds with i40e_aqc_qs_handles_resp 1376 */ 1377 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1378 u8 tc_valid_bits; 1379 u8 reserved[15]; 1380 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1381 1382 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1383 __le16 tc_bw_max[2]; 1384 u8 reserved1[28]; 1385 }; 1386 1387 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1388 1389 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1390 * responds with i40e_aqc_qs_handles_resp 1391 */ 1392 struct i40e_aqc_configure_vsi_tc_bw_data { 1393 u8 tc_valid_bits; 1394 u8 reserved[3]; 1395 u8 tc_bw_credits[8]; 1396 u8 reserved1[4]; 1397 __le16 qs_handles[8]; 1398 }; 1399 1400 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1401 1402 /* Query vsi bw configuration (indirect 0x0408) */ 1403 struct i40e_aqc_query_vsi_bw_config_resp { 1404 u8 tc_valid_bits; 1405 u8 tc_suspended_bits; 1406 u8 reserved[14]; 1407 __le16 qs_handles[8]; 1408 u8 reserved1[4]; 1409 __le16 port_bw_limit; 1410 u8 reserved2[2]; 1411 u8 max_bw; /* 0-3, limit = 2^max */ 1412 u8 reserved3[23]; 1413 }; 1414 1415 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1416 1417 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1418 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1419 u8 tc_valid_bits; 1420 u8 reserved[3]; 1421 u8 share_credits[8]; 1422 __le16 credits[8]; 1423 1424 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1425 __le16 tc_bw_max[2]; 1426 }; 1427 1428 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1429 1430 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1431 struct i40e_aqc_configure_switching_comp_bw_limit { 1432 __le16 seid; 1433 u8 reserved[2]; 1434 __le16 credit; 1435 u8 reserved1[2]; 1436 u8 max_bw; /* 0-3, limit = 2^max */ 1437 u8 reserved2[7]; 1438 }; 1439 1440 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1441 1442 /* Enable Physical Port ETS (indirect 0x0413) 1443 * Modify Physical Port ETS (indirect 0x0414) 1444 * Disable Physical Port ETS (indirect 0x0415) 1445 */ 1446 struct i40e_aqc_configure_switching_comp_ets_data { 1447 u8 reserved[4]; 1448 u8 tc_valid_bits; 1449 u8 seepage; 1450 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1451 u8 tc_strict_priority_flags; 1452 u8 reserved1[17]; 1453 u8 tc_bw_share_credits[8]; 1454 u8 reserved2[96]; 1455 }; 1456 1457 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1458 1459 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1460 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1461 u8 tc_valid_bits; 1462 u8 reserved[15]; 1463 __le16 tc_bw_credit[8]; 1464 1465 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1466 __le16 tc_bw_max[2]; 1467 u8 reserved1[28]; 1468 }; 1469 1470 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1471 1472 /* Configure Switching Component Bandwidth Allocation per Tc 1473 * (indirect 0x0417) 1474 */ 1475 struct i40e_aqc_configure_switching_comp_bw_config_data { 1476 u8 tc_valid_bits; 1477 u8 reserved[2]; 1478 u8 absolute_credits; /* bool */ 1479 u8 tc_bw_share_credits[8]; 1480 u8 reserved1[20]; 1481 }; 1482 1483 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1484 1485 /* Query Switching Component Configuration (indirect 0x0418) */ 1486 struct i40e_aqc_query_switching_comp_ets_config_resp { 1487 u8 tc_valid_bits; 1488 u8 reserved[35]; 1489 __le16 port_bw_limit; 1490 u8 reserved1[2]; 1491 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1492 u8 reserved2[23]; 1493 }; 1494 1495 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1496 1497 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1498 struct i40e_aqc_query_port_ets_config_resp { 1499 u8 reserved[4]; 1500 u8 tc_valid_bits; 1501 u8 reserved1; 1502 u8 tc_strict_priority_bits; 1503 u8 reserved2; 1504 u8 tc_bw_share_credits[8]; 1505 __le16 tc_bw_limits[8]; 1506 1507 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1508 __le16 tc_bw_max[2]; 1509 u8 reserved3[32]; 1510 }; 1511 1512 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1513 1514 /* Query Switching Component Bandwidth Allocation per Traffic Type 1515 * (indirect 0x041A) 1516 */ 1517 struct i40e_aqc_query_switching_comp_bw_config_resp { 1518 u8 tc_valid_bits; 1519 u8 reserved[2]; 1520 u8 absolute_credits_enable; /* bool */ 1521 u8 tc_bw_share_credits[8]; 1522 __le16 tc_bw_limits[8]; 1523 1524 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1525 __le16 tc_bw_max[2]; 1526 }; 1527 1528 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1529 1530 /* Suspend/resume port TX traffic 1531 * (direct 0x041B and 0x041C) uses the generic SEID struct 1532 */ 1533 1534 /* Configure partition BW 1535 * (indirect 0x041D) 1536 */ 1537 struct i40e_aqc_configure_partition_bw_data { 1538 __le16 pf_valid_bits; 1539 u8 min_bw[16]; /* guaranteed bandwidth */ 1540 u8 max_bw[16]; /* bandwidth limit */ 1541 }; 1542 1543 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1544 1545 /* Get and set the active HMC resource profile and status. 1546 * (direct 0x0500) and (direct 0x0501) 1547 */ 1548 struct i40e_aq_get_set_hmc_resource_profile { 1549 u8 pm_profile; 1550 u8 pe_vf_enabled; 1551 u8 reserved[14]; 1552 }; 1553 1554 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1555 1556 enum i40e_aq_hmc_profile { 1557 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1558 I40E_HMC_PROFILE_DEFAULT = 1, 1559 I40E_HMC_PROFILE_FAVOR_VF = 2, 1560 I40E_HMC_PROFILE_EQUAL = 3, 1561 }; 1562 1563 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1564 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1565 1566 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1567 1568 /* set in param0 for get phy abilities to report qualified modules */ 1569 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1570 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1571 1572 enum i40e_aq_phy_type { 1573 I40E_PHY_TYPE_SGMII = 0x0, 1574 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1575 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1576 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1577 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1578 I40E_PHY_TYPE_XAUI = 0x5, 1579 I40E_PHY_TYPE_XFI = 0x6, 1580 I40E_PHY_TYPE_SFI = 0x7, 1581 I40E_PHY_TYPE_XLAUI = 0x8, 1582 I40E_PHY_TYPE_XLPPI = 0x9, 1583 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1584 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1585 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1586 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1587 I40E_PHY_TYPE_100BASE_TX = 0x11, 1588 I40E_PHY_TYPE_1000BASE_T = 0x12, 1589 I40E_PHY_TYPE_10GBASE_T = 0x13, 1590 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1591 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1592 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1593 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1594 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1595 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1596 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1597 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1598 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1599 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1600 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1601 I40E_PHY_TYPE_MAX 1602 }; 1603 1604 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1605 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1606 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1607 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1608 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1609 1610 enum i40e_aq_link_speed { 1611 I40E_LINK_SPEED_UNKNOWN = 0, 1612 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1613 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1614 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1615 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1616 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1617 }; 1618 1619 struct i40e_aqc_module_desc { 1620 u8 oui[3]; 1621 u8 reserved1; 1622 u8 part_number[16]; 1623 u8 revision[4]; 1624 u8 reserved2[8]; 1625 }; 1626 1627 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1628 1629 struct i40e_aq_get_phy_abilities_resp { 1630 __le32 phy_type; /* bitmap using the above enum for offsets */ 1631 u8 link_speed; /* bitmap using the above enum bit patterns */ 1632 u8 abilities; 1633 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1634 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1635 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1636 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1637 #define I40E_AQ_PHY_AN_ENABLED 0x10 1638 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1639 __le16 eee_capability; 1640 #define I40E_AQ_EEE_100BASE_TX 0x0002 1641 #define I40E_AQ_EEE_1000BASE_T 0x0004 1642 #define I40E_AQ_EEE_10GBASE_T 0x0008 1643 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1644 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1645 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1646 __le32 eeer_val; 1647 u8 d3_lpan; 1648 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1649 u8 reserved[3]; 1650 u8 phy_id[4]; 1651 u8 module_type[3]; 1652 u8 qualified_module_count; 1653 #define I40E_AQ_PHY_MAX_QMS 16 1654 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1655 }; 1656 1657 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1658 1659 /* Set PHY Config (direct 0x0601) */ 1660 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1661 __le32 phy_type; 1662 u8 link_speed; 1663 u8 abilities; 1664 /* bits 0-2 use the values from get_phy_abilities_resp */ 1665 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1666 #define I40E_AQ_PHY_ENABLE_AN 0x10 1667 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1668 __le16 eee_capability; 1669 __le32 eeer; 1670 u8 low_power_ctrl; 1671 u8 reserved[3]; 1672 }; 1673 1674 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1675 1676 /* Set MAC Config command data structure (direct 0x0603) */ 1677 struct i40e_aq_set_mac_config { 1678 __le16 max_frame_size; 1679 u8 params; 1680 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1681 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1694 u8 tx_timer_priority; /* bitmap */ 1695 __le16 tx_timer_value; 1696 __le16 fc_refresh_threshold; 1697 u8 reserved[8]; 1698 }; 1699 1700 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1701 1702 /* Restart Auto-Negotiation (direct 0x605) */ 1703 struct i40e_aqc_set_link_restart_an { 1704 u8 command; 1705 #define I40E_AQ_PHY_RESTART_AN 0x02 1706 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1707 u8 reserved[15]; 1708 }; 1709 1710 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1711 1712 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1713 struct i40e_aqc_get_link_status { 1714 __le16 command_flags; /* only field set on command */ 1715 #define I40E_AQ_LSE_MASK 0x3 1716 #define I40E_AQ_LSE_NOP 0x0 1717 #define I40E_AQ_LSE_DISABLE 0x2 1718 #define I40E_AQ_LSE_ENABLE 0x3 1719 /* only response uses this flag */ 1720 #define I40E_AQ_LSE_IS_ENABLED 0x1 1721 u8 phy_type; /* i40e_aq_phy_type */ 1722 u8 link_speed; /* i40e_aq_link_speed */ 1723 u8 link_info; 1724 #define I40E_AQ_LINK_UP 0x01 1725 #define I40E_AQ_LINK_FAULT 0x02 1726 #define I40E_AQ_LINK_FAULT_TX 0x04 1727 #define I40E_AQ_LINK_FAULT_RX 0x08 1728 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1729 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1730 #define I40E_AQ_SIGNAL_DETECT 0x80 1731 u8 an_info; 1732 #define I40E_AQ_AN_COMPLETED 0x01 1733 #define I40E_AQ_LP_AN_ABILITY 0x02 1734 #define I40E_AQ_PD_FAULT 0x04 1735 #define I40E_AQ_FEC_EN 0x08 1736 #define I40E_AQ_PHY_LOW_POWER 0x10 1737 #define I40E_AQ_LINK_PAUSE_TX 0x20 1738 #define I40E_AQ_LINK_PAUSE_RX 0x40 1739 #define I40E_AQ_QUALIFIED_MODULE 0x80 1740 u8 ext_info; 1741 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1742 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1743 #define I40E_AQ_LINK_TX_SHIFT 0x02 1744 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1745 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1746 #define I40E_AQ_LINK_TX_DRAINED 0x01 1747 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1748 #define I40E_AQ_LINK_FORCED_40G 0x10 1749 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1750 __le16 max_frame_size; 1751 u8 config; 1752 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1753 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1754 u8 reserved[5]; 1755 }; 1756 1757 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1758 1759 /* Set event mask command (direct 0x613) */ 1760 struct i40e_aqc_set_phy_int_mask { 1761 u8 reserved[8]; 1762 __le16 event_mask; 1763 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1764 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1765 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1766 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1767 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1768 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1769 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1770 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1771 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1772 u8 reserved1[6]; 1773 }; 1774 1775 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1776 1777 /* Get Local AN advt register (direct 0x0614) 1778 * Set Local AN advt register (direct 0x0615) 1779 * Get Link Partner AN advt register (direct 0x0616) 1780 */ 1781 struct i40e_aqc_an_advt_reg { 1782 __le32 local_an_reg0; 1783 __le16 local_an_reg1; 1784 u8 reserved[10]; 1785 }; 1786 1787 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1788 1789 /* Set Loopback mode (0x0618) */ 1790 struct i40e_aqc_set_lb_mode { 1791 __le16 lb_mode; 1792 #define I40E_AQ_LB_PHY_LOCAL 0x01 1793 #define I40E_AQ_LB_PHY_REMOTE 0x02 1794 #define I40E_AQ_LB_MAC_LOCAL 0x04 1795 u8 reserved[14]; 1796 }; 1797 1798 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1799 1800 /* Set PHY Debug command (0x0622) */ 1801 struct i40e_aqc_set_phy_debug { 1802 u8 command_flags; 1803 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1804 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1805 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1806 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1807 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1808 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1809 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1810 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1811 u8 reserved[15]; 1812 }; 1813 1814 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1815 1816 enum i40e_aq_phy_reg_type { 1817 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1818 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1819 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1820 }; 1821 1822 /* NVM Read command (indirect 0x0701) 1823 * NVM Erase commands (direct 0x0702) 1824 * NVM Update commands (indirect 0x0703) 1825 */ 1826 struct i40e_aqc_nvm_update { 1827 u8 command_flags; 1828 #define I40E_AQ_NVM_LAST_CMD 0x01 1829 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1830 u8 module_pointer; 1831 __le16 length; 1832 __le32 offset; 1833 __le32 addr_high; 1834 __le32 addr_low; 1835 }; 1836 1837 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1838 1839 /* NVM Config Read (indirect 0x0704) */ 1840 struct i40e_aqc_nvm_config_read { 1841 __le16 cmd_flags; 1842 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1843 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1844 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1845 __le16 element_count; 1846 __le16 element_id; /* Feature/field ID */ 1847 __le16 element_id_msw; /* MSWord of field ID */ 1848 __le32 address_high; 1849 __le32 address_low; 1850 }; 1851 1852 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1853 1854 /* NVM Config Write (indirect 0x0705) */ 1855 struct i40e_aqc_nvm_config_write { 1856 __le16 cmd_flags; 1857 __le16 element_count; 1858 u8 reserved[4]; 1859 __le32 address_high; 1860 __le32 address_low; 1861 }; 1862 1863 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1864 1865 /* Used for 0x0704 as well as for 0x0705 commands */ 1866 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1867 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1868 #define I40E_AQ_ANVM_FEATURE 0 1869 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1870 struct i40e_aqc_nvm_config_data_feature { 1871 __le16 feature_id; 1872 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1873 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1874 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1875 __le16 feature_options; 1876 __le16 feature_selection; 1877 }; 1878 1879 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1880 1881 struct i40e_aqc_nvm_config_data_immediate_field { 1882 __le32 field_id; 1883 __le32 field_value; 1884 __le16 field_options; 1885 __le16 reserved; 1886 }; 1887 1888 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1889 1890 /* Send to PF command (indirect 0x0801) id is only used by PF 1891 * Send to VF command (indirect 0x0802) id is only used by PF 1892 * Send to Peer PF command (indirect 0x0803) 1893 */ 1894 struct i40e_aqc_pf_vf_message { 1895 __le32 id; 1896 u8 reserved[4]; 1897 __le32 addr_high; 1898 __le32 addr_low; 1899 }; 1900 1901 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1902 1903 /* Alternate structure */ 1904 1905 /* Direct write (direct 0x0900) 1906 * Direct read (direct 0x0902) 1907 */ 1908 struct i40e_aqc_alternate_write { 1909 __le32 address0; 1910 __le32 data0; 1911 __le32 address1; 1912 __le32 data1; 1913 }; 1914 1915 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1916 1917 /* Indirect write (indirect 0x0901) 1918 * Indirect read (indirect 0x0903) 1919 */ 1920 1921 struct i40e_aqc_alternate_ind_write { 1922 __le32 address; 1923 __le32 length; 1924 __le32 addr_high; 1925 __le32 addr_low; 1926 }; 1927 1928 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1929 1930 /* Done alternate write (direct 0x0904) 1931 * uses i40e_aq_desc 1932 */ 1933 struct i40e_aqc_alternate_write_done { 1934 __le16 cmd_flags; 1935 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1936 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1937 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1938 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1939 u8 reserved[14]; 1940 }; 1941 1942 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1943 1944 /* Set OEM mode (direct 0x0905) */ 1945 struct i40e_aqc_alternate_set_mode { 1946 __le32 mode; 1947 #define I40E_AQ_ALTERNATE_MODE_NONE 0 1948 #define I40E_AQ_ALTERNATE_MODE_OEM 1 1949 u8 reserved[12]; 1950 }; 1951 1952 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1953 1954 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1955 1956 /* async events 0x10xx */ 1957 1958 /* Lan Queue Overflow Event (direct, 0x1001) */ 1959 struct i40e_aqc_lan_overflow { 1960 __le32 prtdcb_rupto; 1961 __le32 otx_ctl; 1962 u8 reserved[8]; 1963 }; 1964 1965 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1966 1967 /* Get LLDP MIB (indirect 0x0A00) */ 1968 struct i40e_aqc_lldp_get_mib { 1969 u8 type; 1970 u8 reserved1; 1971 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1972 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 1973 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 1974 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1975 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1976 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1977 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1978 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1979 #define I40E_AQ_LLDP_TX_SHIFT 0x4 1980 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1981 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 1982 __le16 local_len; 1983 __le16 remote_len; 1984 u8 reserved2[2]; 1985 __le32 addr_high; 1986 __le32 addr_low; 1987 }; 1988 1989 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1990 1991 /* Configure LLDP MIB Change Event (direct 0x0A01) 1992 * also used for the event (with type in the command field) 1993 */ 1994 struct i40e_aqc_lldp_update_mib { 1995 u8 command; 1996 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1997 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1998 u8 reserved[7]; 1999 __le32 addr_high; 2000 __le32 addr_low; 2001 }; 2002 2003 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2004 2005 /* Add LLDP TLV (indirect 0x0A02) 2006 * Delete LLDP TLV (indirect 0x0A04) 2007 */ 2008 struct i40e_aqc_lldp_add_tlv { 2009 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2010 u8 reserved1[1]; 2011 __le16 len; 2012 u8 reserved2[4]; 2013 __le32 addr_high; 2014 __le32 addr_low; 2015 }; 2016 2017 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2018 2019 /* Update LLDP TLV (indirect 0x0A03) */ 2020 struct i40e_aqc_lldp_update_tlv { 2021 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2022 u8 reserved; 2023 __le16 old_len; 2024 __le16 new_offset; 2025 __le16 new_len; 2026 __le32 addr_high; 2027 __le32 addr_low; 2028 }; 2029 2030 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2031 2032 /* Stop LLDP (direct 0x0A05) */ 2033 struct i40e_aqc_lldp_stop { 2034 u8 command; 2035 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2036 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2037 u8 reserved[15]; 2038 }; 2039 2040 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2041 2042 /* Start LLDP (direct 0x0A06) */ 2043 2044 struct i40e_aqc_lldp_start { 2045 u8 command; 2046 #define I40E_AQ_LLDP_AGENT_START 0x1 2047 u8 reserved[15]; 2048 }; 2049 2050 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2051 2052 /* Get CEE DCBX Oper Config (0x0A07) 2053 * uses the generic descriptor struct 2054 * returns below as indirect response 2055 */ 2056 2057 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2058 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2059 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2060 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2061 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2062 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2063 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2064 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2065 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2066 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2067 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2068 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2069 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2070 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2071 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xA 2072 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2073 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2074 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2075 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2076 u8 reserved1; 2077 u8 oper_num_tc; 2078 u8 oper_prio_tc[4]; 2079 u8 reserved2; 2080 u8 oper_tc_bw[8]; 2081 u8 oper_pfc_en; 2082 u8 reserved3; 2083 __le16 oper_app_prio; 2084 u8 reserved4; 2085 __le16 tlv_status; 2086 }; 2087 2088 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2089 2090 struct i40e_aqc_get_cee_dcb_cfg_resp { 2091 u8 oper_num_tc; 2092 u8 oper_prio_tc[4]; 2093 u8 oper_tc_bw[8]; 2094 u8 oper_pfc_en; 2095 __le16 oper_app_prio; 2096 __le32 tlv_status; 2097 u8 reserved[12]; 2098 }; 2099 2100 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2101 2102 /* Set Local LLDP MIB (indirect 0x0A08) 2103 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2104 */ 2105 struct i40e_aqc_lldp_set_local_mib { 2106 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2107 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2108 u8 type; 2109 u8 reserved0; 2110 __le16 length; 2111 u8 reserved1[4]; 2112 __le32 address_high; 2113 __le32 address_low; 2114 }; 2115 2116 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2117 2118 /* Stop/Start LLDP Agent (direct 0x0A09) 2119 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2120 */ 2121 struct i40e_aqc_lldp_stop_start_specific_agent { 2122 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2123 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2124 u8 command; 2125 u8 reserved[15]; 2126 }; 2127 2128 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2129 2130 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2131 struct i40e_aqc_add_udp_tunnel { 2132 __le16 udp_port; 2133 u8 reserved0[3]; 2134 u8 protocol_type; 2135 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2136 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2137 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2138 u8 reserved1[10]; 2139 }; 2140 2141 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2142 2143 struct i40e_aqc_add_udp_tunnel_completion { 2144 __le16 udp_port; 2145 u8 filter_entry_index; 2146 u8 multiple_pfs; 2147 #define I40E_AQC_SINGLE_PF 0x0 2148 #define I40E_AQC_MULTIPLE_PFS 0x1 2149 u8 total_filters; 2150 u8 reserved[11]; 2151 }; 2152 2153 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2154 2155 /* remove UDP Tunnel command (0x0B01) */ 2156 struct i40e_aqc_remove_udp_tunnel { 2157 u8 reserved[2]; 2158 u8 index; /* 0 to 15 */ 2159 u8 reserved2[13]; 2160 }; 2161 2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2163 2164 struct i40e_aqc_del_udp_tunnel_completion { 2165 __le16 udp_port; 2166 u8 index; /* 0 to 15 */ 2167 u8 multiple_pfs; 2168 u8 total_filters_used; 2169 u8 reserved1[11]; 2170 }; 2171 2172 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2173 2174 /* tunnel key structure 0x0B10 */ 2175 2176 struct i40e_aqc_tunnel_key_structure { 2177 u8 key1_off; 2178 u8 key2_off; 2179 u8 key1_len; /* 0 to 15 */ 2180 u8 key2_len; /* 0 to 15 */ 2181 u8 flags; 2182 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2183 /* response flags */ 2184 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2185 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2186 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2187 u8 network_key_index; 2188 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2189 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2190 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2191 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2192 u8 reserved[10]; 2193 }; 2194 2195 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2196 2197 /* OEM mode commands (direct 0xFE0x) */ 2198 struct i40e_aqc_oem_param_change { 2199 __le32 param_type; 2200 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2201 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2202 #define I40E_AQ_OEM_PARAM_MAC 2 2203 __le32 param_value1; 2204 __le16 param_value2; 2205 u8 reserved[6]; 2206 }; 2207 2208 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2209 2210 struct i40e_aqc_oem_state_change { 2211 __le32 state; 2212 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2213 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2214 u8 reserved[12]; 2215 }; 2216 2217 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2218 2219 /* Initialize OCSD (0xFE02, direct) */ 2220 struct i40e_aqc_opc_oem_ocsd_initialize { 2221 u8 type_status; 2222 u8 reserved1[3]; 2223 __le32 ocsd_memory_block_addr_high; 2224 __le32 ocsd_memory_block_addr_low; 2225 __le32 requested_update_interval; 2226 }; 2227 2228 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2229 2230 /* Initialize OCBB (0xFE03, direct) */ 2231 struct i40e_aqc_opc_oem_ocbb_initialize { 2232 u8 type_status; 2233 u8 reserved1[3]; 2234 __le32 ocbb_memory_block_addr_high; 2235 __le32 ocbb_memory_block_addr_low; 2236 u8 reserved2[4]; 2237 }; 2238 2239 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2240 2241 /* debug commands */ 2242 2243 /* get device id (0xFF00) uses the generic structure */ 2244 2245 /* set test more (0xFF01, internal) */ 2246 2247 struct i40e_acq_set_test_mode { 2248 u8 mode; 2249 #define I40E_AQ_TEST_PARTIAL 0 2250 #define I40E_AQ_TEST_FULL 1 2251 #define I40E_AQ_TEST_NVM 2 2252 u8 reserved[3]; 2253 u8 command; 2254 #define I40E_AQ_TEST_OPEN 0 2255 #define I40E_AQ_TEST_CLOSE 1 2256 #define I40E_AQ_TEST_INC 2 2257 u8 reserved2[3]; 2258 __le32 address_high; 2259 __le32 address_low; 2260 }; 2261 2262 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2263 2264 /* Debug Read Register command (0xFF03) 2265 * Debug Write Register command (0xFF04) 2266 */ 2267 struct i40e_aqc_debug_reg_read_write { 2268 __le32 reserved; 2269 __le32 address; 2270 __le32 value_high; 2271 __le32 value_low; 2272 }; 2273 2274 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2275 2276 /* Scatter/gather Reg Read (indirect 0xFF05) 2277 * Scatter/gather Reg Write (indirect 0xFF06) 2278 */ 2279 2280 /* i40e_aq_desc is used for the command */ 2281 struct i40e_aqc_debug_reg_sg_element_data { 2282 __le32 address; 2283 __le32 value; 2284 }; 2285 2286 /* Debug Modify register (direct 0xFF07) */ 2287 struct i40e_aqc_debug_modify_reg { 2288 __le32 address; 2289 __le32 value; 2290 __le32 clear_mask; 2291 __le32 set_mask; 2292 }; 2293 2294 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2295 2296 /* dump internal data (0xFF08, indirect) */ 2297 2298 #define I40E_AQ_CLUSTER_ID_AUX 0 2299 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2300 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2301 #define I40E_AQ_CLUSTER_ID_HMC 3 2302 #define I40E_AQ_CLUSTER_ID_MAC0 4 2303 #define I40E_AQ_CLUSTER_ID_MAC1 5 2304 #define I40E_AQ_CLUSTER_ID_MAC2 6 2305 #define I40E_AQ_CLUSTER_ID_MAC3 7 2306 #define I40E_AQ_CLUSTER_ID_DCB 8 2307 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2308 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2309 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2310 2311 struct i40e_aqc_debug_dump_internals { 2312 u8 cluster_id; 2313 u8 table_id; 2314 __le16 data_size; 2315 __le32 idx; 2316 __le32 address_high; 2317 __le32 address_low; 2318 }; 2319 2320 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2321 2322 struct i40e_aqc_debug_modify_internals { 2323 u8 cluster_id; 2324 u8 cluster_specific_params[7]; 2325 __le32 address_high; 2326 __le32 address_low; 2327 }; 2328 2329 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2330 2331 #endif 2332