1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_x540.h" 36 #include "ixgbe_type.h" 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 #define IXGBE_X540_MAX_TX_QUEUES 128 42 #define IXGBE_X540_MAX_RX_QUEUES 128 43 #define IXGBE_X540_RAR_ENTRIES 128 44 #define IXGBE_X540_MC_TBL_SIZE 128 45 #define IXGBE_X540_VFT_TBL_SIZE 128 46 #define IXGBE_X540_RX_PB_SIZE 384 47 48 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 49 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 50 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 54 * @hw: pointer to hardware structure 55 * 56 * Initialize the function pointers and assign the MAC type for X540. 57 * Does not touch the hardware. 58 **/ 59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 60 { 61 struct ixgbe_mac_info *mac = &hw->mac; 62 struct ixgbe_phy_info *phy = &hw->phy; 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 s32 ret_val; 65 u16 i; 66 67 DEBUGFUNC("ixgbe_init_ops_X540"); 68 69 ret_val = ixgbe_init_phy_ops_generic(hw); 70 ret_val = ixgbe_init_ops_generic(hw); 71 72 73 /* EEPROM */ 74 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 75 eeprom->ops.read = ixgbe_read_eerd_X540; 76 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 77 eeprom->ops.write = ixgbe_write_eewr_X540; 78 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 79 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 80 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 81 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 82 83 /* PHY */ 84 phy->ops.init = ixgbe_init_phy_ops_generic; 85 phy->ops.reset = NULL; 86 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 87 88 /* MAC */ 89 mac->ops.reset_hw = ixgbe_reset_hw_X540; 90 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 91 mac->ops.get_media_type = ixgbe_get_media_type_X540; 92 mac->ops.get_supported_physical_layer = 93 ixgbe_get_supported_physical_layer_X540; 94 mac->ops.read_analog_reg8 = NULL; 95 mac->ops.write_analog_reg8 = NULL; 96 mac->ops.start_hw = ixgbe_start_hw_X540; 97 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 98 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 99 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 100 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 101 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 102 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 103 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 104 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540; 105 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 106 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 107 108 /* RAR, Multicast, VLAN */ 109 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 110 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 111 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 112 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 113 mac->rar_highwater = 1; 114 mac->ops.set_vfta = ixgbe_set_vfta_generic; 115 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 116 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 117 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 118 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 119 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 120 121 /* Link */ 122 mac->ops.get_link_capabilities = 123 ixgbe_get_copper_link_capabilities_generic; 124 mac->ops.setup_link = ixgbe_setup_mac_link_X540; 125 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 126 mac->ops.check_link = ixgbe_check_mac_link_generic; 127 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 128 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 129 mac->ops.bypass_set = ixgbe_bypass_set_generic; 130 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 131 132 133 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 134 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 135 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 136 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 137 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 138 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 139 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 140 141 /* 142 * FWSM register 143 * ARC supported; valid only if manageability features are 144 * enabled. 145 */ 146 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 147 & IXGBE_FWSM_MODE_MASK); 148 149 for (i = 0; i < 64; i++) 150 hw->mbx.ops[i].init_params = ixgbe_init_mbx_params_pf; 151 152 /* LEDs */ 153 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 154 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 155 156 /* Manageability interface */ 157 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 158 159 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 160 161 return ret_val; 162 } 163 164 /** 165 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 166 * @hw: pointer to hardware structure 167 * @speed: pointer to link speed 168 * @autoneg: true when autoneg or autotry is enabled 169 * 170 * Determines the link capabilities by reading the AUTOC register. 171 **/ 172 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 173 ixgbe_link_speed *speed, 174 bool *autoneg) 175 { 176 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 177 178 return IXGBE_SUCCESS; 179 } 180 181 /** 182 * ixgbe_get_media_type_X540 - Get media type 183 * @hw: pointer to hardware structure 184 * 185 * Returns the media type (fiber, copper, backplane) 186 **/ 187 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 188 { 189 UNREFERENCED_1PARAMETER(hw); 190 return ixgbe_media_type_copper; 191 } 192 193 /** 194 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 195 * @hw: pointer to hardware structure 196 * @speed: new link speed 197 * @autoneg_wait_to_complete: true when waiting for completion is needed 198 **/ 199 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 200 ixgbe_link_speed speed, 201 bool autoneg_wait_to_complete) 202 { 203 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 204 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 205 } 206 207 /** 208 * ixgbe_reset_hw_X540 - Perform hardware reset 209 * @hw: pointer to hardware structure 210 * 211 * Resets the hardware by resetting the transmit and receive units, masks 212 * and clears all interrupts, and perform a reset. 213 **/ 214 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 215 { 216 s32 status; 217 u32 ctrl, i; 218 u32 swfw_mask = hw->phy.phy_semaphore_mask; 219 220 DEBUGFUNC("ixgbe_reset_hw_X540"); 221 222 /* Call adapter stop to disable tx/rx and clear interrupts */ 223 status = hw->mac.ops.stop_adapter(hw); 224 if (status != IXGBE_SUCCESS) 225 goto reset_hw_out; 226 227 /* flush pending Tx transactions */ 228 ixgbe_clear_tx_pending(hw); 229 230 mac_reset_top: 231 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 232 if (status != IXGBE_SUCCESS) { 233 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 234 "semaphore failed with %d", status); 235 return IXGBE_ERR_SWFW_SYNC; 236 } 237 ctrl = IXGBE_CTRL_RST; 238 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 239 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 240 IXGBE_WRITE_FLUSH(hw); 241 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 242 243 /* Poll for reset bit to self-clear indicating reset is complete */ 244 for (i = 0; i < 10; i++) { 245 usec_delay(1); 246 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 247 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 248 break; 249 } 250 251 if (ctrl & IXGBE_CTRL_RST_MASK) { 252 status = IXGBE_ERR_RESET_FAILED; 253 ERROR_REPORT1(IXGBE_ERROR_POLLING, 254 "Reset polling failed to complete.\n"); 255 } 256 msec_delay(100); 257 258 /* 259 * Double resets are required for recovery from certain error 260 * conditions. Between resets, it is necessary to stall to allow time 261 * for any pending HW events to complete. 262 */ 263 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 264 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 265 goto mac_reset_top; 266 } 267 268 /* Set the Rx packet buffer size. */ 269 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 270 271 /* Store the permanent mac address */ 272 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 273 274 /* 275 * Store MAC address from RAR0, clear receive address registers, and 276 * clear the multicast table. Also reset num_rar_entries to 128, 277 * since we modify this value when programming the SAN MAC address. 278 */ 279 hw->mac.num_rar_entries = 128; 280 hw->mac.ops.init_rx_addrs(hw); 281 282 /* Store the permanent SAN mac address */ 283 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 284 285 /* Add the SAN MAC address to the RAR only if it's a valid address */ 286 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 287 /* Save the SAN MAC RAR index */ 288 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 289 290 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 291 hw->mac.san_addr, 0, IXGBE_RAH_AV); 292 293 /* clear VMDq pool/queue selection for this RAR */ 294 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 295 IXGBE_CLEAR_VMDQ_ALL); 296 297 /* Reserve the last RAR for the SAN MAC address */ 298 hw->mac.num_rar_entries--; 299 } 300 301 /* Store the alternative WWNN/WWPN prefix */ 302 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 303 &hw->mac.wwpn_prefix); 304 305 reset_hw_out: 306 return status; 307 } 308 309 /** 310 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 311 * @hw: pointer to hardware structure 312 * 313 * Starts the hardware using the generic start_hw function 314 * and the generation start_hw function. 315 * Then performs revision-specific operations, if any. 316 **/ 317 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 318 { 319 s32 ret_val = IXGBE_SUCCESS; 320 321 DEBUGFUNC("ixgbe_start_hw_X540"); 322 323 ret_val = ixgbe_start_hw_generic(hw); 324 if (ret_val != IXGBE_SUCCESS) 325 goto out; 326 327 ixgbe_start_hw_gen2(hw); 328 329 out: 330 return ret_val; 331 } 332 333 /** 334 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 335 * @hw: pointer to hardware structure 336 * 337 * Determines physical layer capabilities of the current configuration. 338 **/ 339 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 340 { 341 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 342 u16 ext_ability = 0; 343 344 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 345 346 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 347 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 348 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 349 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 350 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 351 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 352 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 353 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 354 355 return physical_layer; 356 } 357 358 /** 359 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 360 * @hw: pointer to hardware structure 361 * 362 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 363 * ixgbe_hw struct in order to set up EEPROM access. 364 **/ 365 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 366 { 367 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 368 u32 eec; 369 u16 eeprom_size; 370 371 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 372 373 if (eeprom->type == ixgbe_eeprom_uninitialized) { 374 eeprom->semaphore_delay = 10; 375 eeprom->type = ixgbe_flash; 376 377 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 378 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 379 IXGBE_EEC_SIZE_SHIFT); 380 eeprom->word_size = 1 << (eeprom_size + 381 IXGBE_EEPROM_WORD_SIZE_SHIFT); 382 383 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 384 eeprom->type, eeprom->word_size); 385 } 386 387 return IXGBE_SUCCESS; 388 } 389 390 /** 391 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 392 * @hw: pointer to hardware structure 393 * @offset: offset of word in the EEPROM to read 394 * @data: word read from the EEPROM 395 * 396 * Reads a 16 bit word from the EEPROM using the EERD register. 397 **/ 398 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 399 { 400 s32 status = IXGBE_SUCCESS; 401 402 DEBUGFUNC("ixgbe_read_eerd_X540"); 403 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 404 IXGBE_SUCCESS) { 405 status = ixgbe_read_eerd_generic(hw, offset, data); 406 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 407 } else { 408 status = IXGBE_ERR_SWFW_SYNC; 409 } 410 411 return status; 412 } 413 414 /** 415 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 416 * @hw: pointer to hardware structure 417 * @offset: offset of word in the EEPROM to read 418 * @words: number of words 419 * @data: word(s) read from the EEPROM 420 * 421 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 422 **/ 423 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 424 u16 offset, u16 words, u16 *data) 425 { 426 s32 status = IXGBE_SUCCESS; 427 428 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 429 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 430 IXGBE_SUCCESS) { 431 status = ixgbe_read_eerd_buffer_generic(hw, offset, 432 words, data); 433 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 434 } else { 435 status = IXGBE_ERR_SWFW_SYNC; 436 } 437 438 return status; 439 } 440 441 /** 442 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 443 * @hw: pointer to hardware structure 444 * @offset: offset of word in the EEPROM to write 445 * @data: word write to the EEPROM 446 * 447 * Write a 16 bit word to the EEPROM using the EEWR register. 448 **/ 449 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 450 { 451 s32 status = IXGBE_SUCCESS; 452 453 DEBUGFUNC("ixgbe_write_eewr_X540"); 454 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 455 IXGBE_SUCCESS) { 456 status = ixgbe_write_eewr_generic(hw, offset, data); 457 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 458 } else { 459 status = IXGBE_ERR_SWFW_SYNC; 460 } 461 462 return status; 463 } 464 465 /** 466 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 467 * @hw: pointer to hardware structure 468 * @offset: offset of word in the EEPROM to write 469 * @words: number of words 470 * @data: word(s) write to the EEPROM 471 * 472 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 473 **/ 474 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 475 u16 offset, u16 words, u16 *data) 476 { 477 s32 status = IXGBE_SUCCESS; 478 479 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 480 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 481 IXGBE_SUCCESS) { 482 status = ixgbe_write_eewr_buffer_generic(hw, offset, 483 words, data); 484 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 485 } else { 486 status = IXGBE_ERR_SWFW_SYNC; 487 } 488 489 return status; 490 } 491 492 /** 493 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 494 * 495 * This function does not use synchronization for EERD and EEWR. It can 496 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 497 * 498 * @hw: pointer to hardware structure 499 * 500 * Returns a negative error code on error, or the 16-bit checksum 501 **/ 502 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 503 { 504 u16 i, j; 505 u16 checksum = 0; 506 u16 length = 0; 507 u16 pointer = 0; 508 u16 word = 0; 509 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 510 511 /* Do not use hw->eeprom.ops.read because we do not want to take 512 * the synchronization semaphores here. Instead use 513 * ixgbe_read_eerd_generic 514 */ 515 516 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 517 518 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the 519 * checksum itself 520 */ 521 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 522 if (ixgbe_read_eerd_generic(hw, i, &word)) { 523 DEBUGOUT("EEPROM read failed\n"); 524 return IXGBE_ERR_EEPROM; 525 } 526 checksum += word; 527 } 528 529 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 530 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 531 */ 532 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 533 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 534 continue; 535 536 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 537 DEBUGOUT("EEPROM read failed\n"); 538 return IXGBE_ERR_EEPROM; 539 } 540 541 /* Skip pointer section if the pointer is invalid. */ 542 if (pointer == 0xFFFF || pointer == 0 || 543 pointer >= hw->eeprom.word_size) 544 continue; 545 546 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 547 DEBUGOUT("EEPROM read failed\n"); 548 return IXGBE_ERR_EEPROM; 549 } 550 551 /* Skip pointer section if length is invalid. */ 552 if (length == 0xFFFF || length == 0 || 553 (pointer + length) >= hw->eeprom.word_size) 554 continue; 555 556 for (j = pointer + 1; j <= pointer + length; j++) { 557 if (ixgbe_read_eerd_generic(hw, j, &word)) { 558 DEBUGOUT("EEPROM read failed\n"); 559 return IXGBE_ERR_EEPROM; 560 } 561 checksum += word; 562 } 563 } 564 565 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 566 567 return (s32)checksum; 568 } 569 570 /** 571 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 572 * @hw: pointer to hardware structure 573 * @checksum_val: calculated checksum 574 * 575 * Performs checksum calculation and validates the EEPROM checksum. If the 576 * caller does not need checksum_val, the value can be NULL. 577 **/ 578 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 579 u16 *checksum_val) 580 { 581 s32 status; 582 u16 checksum; 583 u16 read_checksum = 0; 584 585 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 586 587 /* Read the first word from the EEPROM. If this times out or fails, do 588 * not continue or we could be in for a very long wait while every 589 * EEPROM read fails 590 */ 591 status = hw->eeprom.ops.read(hw, 0, &checksum); 592 if (status) { 593 DEBUGOUT("EEPROM read failed\n"); 594 return status; 595 } 596 597 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 598 return IXGBE_ERR_SWFW_SYNC; 599 600 status = hw->eeprom.ops.calc_checksum(hw); 601 if (status < 0) 602 goto out; 603 604 checksum = (u16)(status & 0xffff); 605 606 /* Do not use hw->eeprom.ops.read because we do not want to take 607 * the synchronization semaphores twice here. 608 */ 609 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 610 &read_checksum); 611 if (status) 612 goto out; 613 614 /* Verify read checksum from EEPROM is the same as 615 * calculated checksum 616 */ 617 if (read_checksum != checksum) { 618 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 619 "Invalid EEPROM checksum"); 620 status = IXGBE_ERR_EEPROM_CHECKSUM; 621 } 622 623 /* If the user cares, return the calculated checksum */ 624 if (checksum_val) 625 *checksum_val = checksum; 626 627 out: 628 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 629 630 return status; 631 } 632 633 /** 634 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 635 * @hw: pointer to hardware structure 636 * 637 * After writing EEPROM to shadow RAM using EEWR register, software calculates 638 * checksum and updates the EEPROM and instructs the hardware to update 639 * the flash. 640 **/ 641 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 642 { 643 s32 status; 644 u16 checksum; 645 646 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 647 648 /* Read the first word from the EEPROM. If this times out or fails, do 649 * not continue or we could be in for a very long wait while every 650 * EEPROM read fails 651 */ 652 status = hw->eeprom.ops.read(hw, 0, &checksum); 653 if (status) { 654 DEBUGOUT("EEPROM read failed\n"); 655 return status; 656 } 657 658 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 659 return IXGBE_ERR_SWFW_SYNC; 660 661 status = hw->eeprom.ops.calc_checksum(hw); 662 if (status < 0) 663 goto out; 664 665 checksum = (u16)(status & 0xffff); 666 667 /* Do not use hw->eeprom.ops.write because we do not want to 668 * take the synchronization semaphores twice here. 669 */ 670 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 671 if (status) 672 goto out; 673 674 status = ixgbe_update_flash_X540(hw); 675 676 out: 677 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 678 679 return status; 680 } 681 682 /** 683 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 684 * @hw: pointer to hardware structure 685 * 686 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 687 * EEPROM from shadow RAM to the flash device. 688 **/ 689 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 690 { 691 u32 flup; 692 s32 status; 693 694 DEBUGFUNC("ixgbe_update_flash_X540"); 695 696 status = ixgbe_poll_flash_update_done_X540(hw); 697 if (status == IXGBE_ERR_EEPROM) { 698 DEBUGOUT("Flash update time out\n"); 699 goto out; 700 } 701 702 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 703 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 704 705 status = ixgbe_poll_flash_update_done_X540(hw); 706 if (status == IXGBE_SUCCESS) 707 DEBUGOUT("Flash update complete\n"); 708 else 709 DEBUGOUT("Flash update time out\n"); 710 711 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 712 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 713 714 if (flup & IXGBE_EEC_SEC1VAL) { 715 flup |= IXGBE_EEC_FLUP; 716 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 717 } 718 719 status = ixgbe_poll_flash_update_done_X540(hw); 720 if (status == IXGBE_SUCCESS) 721 DEBUGOUT("Flash update complete\n"); 722 else 723 DEBUGOUT("Flash update time out\n"); 724 } 725 out: 726 return status; 727 } 728 729 /** 730 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 731 * @hw: pointer to hardware structure 732 * 733 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 734 * flash update is done. 735 **/ 736 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 737 { 738 u32 i; 739 u32 reg; 740 s32 status = IXGBE_ERR_EEPROM; 741 742 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 743 744 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 745 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 746 if (reg & IXGBE_EEC_FLUDONE) { 747 status = IXGBE_SUCCESS; 748 break; 749 } 750 msec_delay(5); 751 } 752 753 if (i == IXGBE_FLUDONE_ATTEMPTS) 754 ERROR_REPORT1(IXGBE_ERROR_POLLING, 755 "Flash update status polling timed out"); 756 757 return status; 758 } 759 760 /** 761 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 762 * @hw: pointer to hardware structure 763 * @mask: Mask to specify which semaphore to acquire 764 * 765 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 766 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 767 **/ 768 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 769 { 770 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 771 u32 fwmask = swmask << 5; 772 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 773 u32 timeout = 200; 774 u32 hwmask = 0; 775 u32 swfw_sync; 776 u32 i; 777 778 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 779 780 if (swmask & IXGBE_GSSR_EEP_SM) 781 hwmask |= IXGBE_GSSR_FLASH_SM; 782 783 /* SW only mask doesn't have FW bit pair */ 784 if (mask & IXGBE_GSSR_SW_MNG_SM) 785 swmask |= IXGBE_GSSR_SW_MNG_SM; 786 787 swmask |= swi2c_mask; 788 fwmask |= swi2c_mask << 2; 789 if (hw->mac.type >= ixgbe_mac_X550) 790 timeout = 1000; 791 792 for (i = 0; i < timeout; i++) { 793 /* SW NVM semaphore bit is used for access to all 794 * SW_FW_SYNC bits (not just NVM) 795 */ 796 if (ixgbe_get_swfw_sync_semaphore(hw)) { 797 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); 798 return IXGBE_ERR_SWFW_SYNC; 799 } 800 801 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 802 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 803 swfw_sync |= swmask; 804 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 805 swfw_sync); 806 ixgbe_release_swfw_sync_semaphore(hw); 807 return IXGBE_SUCCESS; 808 } 809 /* Firmware currently using resource (fwmask), hardware 810 * currently using resource (hwmask), or other software 811 * thread currently using resource (swmask) 812 */ 813 ixgbe_release_swfw_sync_semaphore(hw); 814 msec_delay(5); 815 } 816 817 /* If the resource is not released by the FW/HW the SW can assume that 818 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 819 * of the requested resource(s) while ignoring the corresponding FW/HW 820 * bits in the SW_FW_SYNC register. 821 */ 822 if (ixgbe_get_swfw_sync_semaphore(hw)) { 823 DEBUGOUT("Failed to get NVM semaphore and register semaphore while forcefully ignoring FW semaphore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n"); 824 return IXGBE_ERR_SWFW_SYNC; 825 } 826 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 827 if (swfw_sync & (fwmask | hwmask)) { 828 swfw_sync |= swmask; 829 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 830 ixgbe_release_swfw_sync_semaphore(hw); 831 msec_delay(5); 832 return IXGBE_SUCCESS; 833 } 834 /* If the resource is not released by other SW the SW can assume that 835 * the other SW malfunctions. In that case the SW should clear all SW 836 * flags that it does not own and then repeat the whole process once 837 * again. 838 */ 839 if (swfw_sync & swmask) { 840 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 841 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 842 IXGBE_GSSR_SW_MNG_SM; 843 844 if (swi2c_mask) 845 rmask |= IXGBE_GSSR_I2C_MASK; 846 ixgbe_release_swfw_sync_X540(hw, rmask); 847 ixgbe_release_swfw_sync_semaphore(hw); 848 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n"); 849 return IXGBE_ERR_SWFW_SYNC; 850 } 851 ixgbe_release_swfw_sync_semaphore(hw); 852 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n"); 853 854 return IXGBE_ERR_SWFW_SYNC; 855 } 856 857 /** 858 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 859 * @hw: pointer to hardware structure 860 * @mask: Mask to specify which semaphore to release 861 * 862 * Releases the SWFW semaphore through the SW_FW_SYNC register 863 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 864 **/ 865 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 866 { 867 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 868 u32 swfw_sync; 869 870 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 871 872 if (mask & IXGBE_GSSR_I2C_MASK) 873 swmask |= mask & IXGBE_GSSR_I2C_MASK; 874 ixgbe_get_swfw_sync_semaphore(hw); 875 876 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 877 swfw_sync &= ~swmask; 878 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 879 880 ixgbe_release_swfw_sync_semaphore(hw); 881 msec_delay(2); 882 } 883 884 /** 885 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 886 * @hw: pointer to hardware structure 887 * 888 * Sets the hardware semaphores so SW/FW can gain control of shared resources 889 **/ 890 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 891 { 892 s32 status = IXGBE_ERR_EEPROM; 893 u32 timeout = 2000; 894 u32 i; 895 u32 swsm; 896 897 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 898 899 /* Get SMBI software semaphore between device drivers first */ 900 for (i = 0; i < timeout; i++) { 901 /* 902 * If the SMBI bit is 0 when we read it, then the bit will be 903 * set and we have the semaphore 904 */ 905 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 906 if (!(swsm & IXGBE_SWSM_SMBI)) { 907 status = IXGBE_SUCCESS; 908 break; 909 } 910 usec_delay(50); 911 } 912 913 /* Now get the semaphore between SW/FW through the REGSMP bit */ 914 if (status == IXGBE_SUCCESS) { 915 for (i = 0; i < timeout; i++) { 916 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 917 if (!(swsm & IXGBE_SWFW_REGSMP)) 918 break; 919 920 usec_delay(50); 921 } 922 923 /* 924 * Release semaphores and return error if SW NVM semaphore 925 * was not granted because we don't have access to the EEPROM 926 */ 927 if (i >= timeout) { 928 ERROR_REPORT1(IXGBE_ERROR_POLLING, 929 "REGSMP Software NVM semaphore not granted.\n"); 930 ixgbe_release_swfw_sync_semaphore(hw); 931 status = IXGBE_ERR_EEPROM; 932 } 933 } else { 934 ERROR_REPORT1(IXGBE_ERROR_POLLING, 935 "Software semaphore SMBI between device drivers " 936 "not granted.\n"); 937 } 938 939 return status; 940 } 941 942 /** 943 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 944 * @hw: pointer to hardware structure 945 * 946 * This function clears hardware semaphore bits. 947 **/ 948 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 949 { 950 u32 swsm; 951 952 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 953 954 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 955 956 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 957 swsm &= ~IXGBE_SWFW_REGSMP; 958 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 959 960 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 961 swsm &= ~IXGBE_SWSM_SMBI; 962 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 963 964 IXGBE_WRITE_FLUSH(hw); 965 } 966 967 /** 968 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore 969 * @hw: pointer to hardware structure 970 * 971 * This function reset hardware semaphore bits for a semaphore that may 972 * have be left locked due to a catastrophic failure. 973 **/ 974 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) 975 { 976 u32 rmask; 977 978 /* First try to grab the semaphore but we don't need to bother 979 * looking to see whether we got the lock or not since we do 980 * the same thing regardless of whether we got the lock or not. 981 * We got the lock - we release it. 982 * We timeout trying to get the lock - we force its release. 983 */ 984 ixgbe_get_swfw_sync_semaphore(hw); 985 ixgbe_release_swfw_sync_semaphore(hw); 986 987 /* Acquire and release all software resources. */ 988 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 989 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 990 IXGBE_GSSR_SW_MNG_SM; 991 992 rmask |= IXGBE_GSSR_I2C_MASK; 993 ixgbe_acquire_swfw_sync_X540(hw, rmask); 994 ixgbe_release_swfw_sync_X540(hw, rmask); 995 } 996 997 /** 998 * ixgbe_blink_led_start_X540 - Blink LED based on index. 999 * @hw: pointer to hardware structure 1000 * @index: led number to blink 1001 * 1002 * Devices that implement the version 2 interface: 1003 * X540 1004 **/ 1005 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 1006 { 1007 u32 macc_reg; 1008 u32 ledctl_reg; 1009 ixgbe_link_speed speed; 1010 bool link_up; 1011 1012 DEBUGFUNC("ixgbe_blink_led_start_X540"); 1013 1014 if (index > 3) 1015 return IXGBE_ERR_PARAM; 1016 1017 /* 1018 * Link should be up in order for the blink bit in the LED control 1019 * register to work. Force link and speed in the MAC if link is down. 1020 * This will be reversed when we stop the blinking. 1021 */ 1022 hw->mac.ops.check_link(hw, &speed, &link_up, false); 1023 if (link_up == false) { 1024 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1025 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 1026 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1027 } 1028 /* Set the LED to LINK_UP + BLINK. */ 1029 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1030 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1031 ledctl_reg |= IXGBE_LED_BLINK(index); 1032 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1033 IXGBE_WRITE_FLUSH(hw); 1034 1035 return IXGBE_SUCCESS; 1036 } 1037 1038 /** 1039 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 1040 * @hw: pointer to hardware structure 1041 * @index: led number to stop blinking 1042 * 1043 * Devices that implement the version 2 interface: 1044 * X540 1045 **/ 1046 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 1047 { 1048 u32 macc_reg; 1049 u32 ledctl_reg; 1050 1051 if (index > 3) 1052 return IXGBE_ERR_PARAM; 1053 1054 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 1055 1056 /* Restore the LED to its default value. */ 1057 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1058 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1059 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1060 ledctl_reg &= ~IXGBE_LED_BLINK(index); 1061 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1062 1063 /* Unforce link and speed in the MAC. */ 1064 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1065 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1066 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1067 IXGBE_WRITE_FLUSH(hw); 1068 1069 return IXGBE_SUCCESS; 1070 } 1071