xref: /freebsd/sys/dev/ixgbe/ixgbe_phy.h (revision 409a390c3341fb4f162cd7de1fd595a323ebbfd8)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2009, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _IXGBE_PHY_H_
36 #define _IXGBE_PHY_H_
37 
38 #include "ixgbe_type.h"
39 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
40 
41 /* EEPROM byte offsets */
42 #define IXGBE_SFF_IDENTIFIER         0x0
43 #define IXGBE_SFF_IDENTIFIER_SFP     0x3
44 #define IXGBE_SFF_VENDOR_OUI_BYTE0   0x25
45 #define IXGBE_SFF_VENDOR_OUI_BYTE1   0x26
46 #define IXGBE_SFF_VENDOR_OUI_BYTE2   0x27
47 #define IXGBE_SFF_1GBE_COMP_CODES    0x6
48 #define IXGBE_SFF_10GBE_COMP_CODES   0x3
49 #define IXGBE_SFF_CABLE_TECHNOLOGY   0x8
50 
51 /* Bitmasks */
52 #define IXGBE_SFF_DA_PASSIVE_CABLE           0x4
53 #define IXGBE_SFF_1GBASESX_CAPABLE           0x1
54 #define IXGBE_SFF_1GBASELX_CAPABLE           0x2
55 #define IXGBE_SFF_10GBASESR_CAPABLE          0x10
56 #define IXGBE_SFF_10GBASELR_CAPABLE          0x20
57 #define IXGBE_I2C_EEPROM_READ_MASK           0x100
58 #define IXGBE_I2C_EEPROM_STATUS_MASK         0x3
59 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
60 #define IXGBE_I2C_EEPROM_STATUS_PASS         0x1
61 #define IXGBE_I2C_EEPROM_STATUS_FAIL         0x2
62 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS  0x3
63 
64 /* Bit-shift macros */
65 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
66 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
67 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
68 
69 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
70 #define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
71 #define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
72 #define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
73 #define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
74 
75 /* I2C SDA and SCL timing parameters for standard mode */
76 #define IXGBE_I2C_T_HD_STA  4
77 #define IXGBE_I2C_T_LOW     5
78 #define IXGBE_I2C_T_HIGH    4
79 #define IXGBE_I2C_T_SU_STA  5
80 #define IXGBE_I2C_T_HD_DATA 5
81 #define IXGBE_I2C_T_SU_DATA 1
82 #define IXGBE_I2C_T_RISE    1
83 #define IXGBE_I2C_T_FALL    1
84 #define IXGBE_I2C_T_SU_STO  4
85 #define IXGBE_I2C_T_BUF     5
86 
87 
88 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
89 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
90 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
91 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
92 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
93 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
94 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
95                                u32 device_type, u16 *phy_data);
96 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
97                                 u32 device_type, u16 phy_data);
98 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
99 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
100                                        ixgbe_link_speed speed,
101                                        bool autoneg,
102                                        bool autoneg_wait_to_complete);
103 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
104                                              ixgbe_link_speed *speed,
105                                              bool *autoneg);
106 
107 /* PHY specific */
108 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
109                              ixgbe_link_speed *speed,
110                              bool *link_up);
111 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
112 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
113                                        u16 *firmware_version);
114 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
115                                        u16 *firmware_version);
116 
117 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
118 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
119 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
120                                         u16 *list_offset,
121                                         u16 *data_offset);
122 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
123                                 u8 dev_addr, u8 *data);
124 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
125                                  u8 dev_addr, u8 data);
126 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
127                                   u8 *eeprom_data);
128 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
129                                    u8 eeprom_data);
130 #endif /* _IXGBE_PHY_H_ */
131