1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53 /** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61 { 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68 } 69 70 /** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78 { 79 s32 status; 80 81 status = ixgbe_clock_in_i2c_byte(hw, byte); 82 if (status) 83 return status; 84 /* ACK */ 85 return ixgbe_clock_out_i2c_bit(hw, FALSE); 86 } 87 88 /** 89 * ixgbe_ones_comp_byte_add - Perform one's complement addition 90 * @add1 - addend 1 91 * @add2 - addend 2 92 * 93 * Returns one's complement 8-bit sum. 94 */ 95 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 96 { 97 u16 sum = add1 + add2; 98 99 sum = (sum & 0xFF) + (sum >> 8); 100 return sum & 0xFF; 101 } 102 103 /** 104 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 105 * @hw: pointer to the hardware structure 106 * @addr: I2C bus address to read from 107 * @reg: I2C device register to read from 108 * @val: pointer to location to receive read value 109 * 110 * Returns an error code on error. 111 */ 112 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 113 u16 reg, u16 *val) 114 { 115 u32 swfw_mask = hw->phy.phy_semaphore_mask; 116 int max_retry = 10; 117 int retry = 0; 118 u8 csum_byte; 119 u8 high_bits; 120 u8 low_bits; 121 u8 reg_high; 122 u8 csum; 123 124 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 126 csum = ~csum; 127 do { 128 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 129 return IXGBE_ERR_SWFW_SYNC; 130 ixgbe_i2c_start(hw); 131 /* Device Address and write indication */ 132 if (ixgbe_out_i2c_byte_ack(hw, addr)) 133 goto fail; 134 /* Write bits 14:8 */ 135 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 136 goto fail; 137 /* Write bits 7:0 */ 138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 139 goto fail; 140 /* Write csum */ 141 if (ixgbe_out_i2c_byte_ack(hw, csum)) 142 goto fail; 143 /* Re-start condition */ 144 ixgbe_i2c_start(hw); 145 /* Device Address and read indication */ 146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 147 goto fail; 148 /* Get upper bits */ 149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 150 goto fail; 151 /* Get low bits */ 152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 153 goto fail; 154 /* Get csum */ 155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 156 goto fail; 157 /* NACK */ 158 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 159 goto fail; 160 ixgbe_i2c_stop(hw); 161 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 162 *val = (high_bits << 8) | low_bits; 163 return 0; 164 165 fail: 166 ixgbe_i2c_bus_clear(hw); 167 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 168 retry++; 169 if (retry < max_retry) 170 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 171 else 172 DEBUGOUT("I2C byte read combined error.\n"); 173 } while (retry < max_retry); 174 175 return IXGBE_ERR_I2C; 176 } 177 178 /** 179 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 180 * @hw: pointer to the hardware structure 181 * @addr: I2C bus address to write to 182 * @reg: I2C device register to write to 183 * @val: value to write 184 * 185 * Returns an error code on error. 186 */ 187 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 188 u8 addr, u16 reg, u16 val) 189 { 190 int max_retry = 1; 191 int retry = 0; 192 u8 reg_high; 193 u8 csum; 194 195 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 196 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 197 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 198 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 199 csum = ~csum; 200 do { 201 ixgbe_i2c_start(hw); 202 /* Device Address and write indication */ 203 if (ixgbe_out_i2c_byte_ack(hw, addr)) 204 goto fail; 205 /* Write bits 14:8 */ 206 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 207 goto fail; 208 /* Write bits 7:0 */ 209 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 210 goto fail; 211 /* Write data 15:8 */ 212 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 213 goto fail; 214 /* Write data 7:0 */ 215 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 216 goto fail; 217 /* Write csum */ 218 if (ixgbe_out_i2c_byte_ack(hw, csum)) 219 goto fail; 220 ixgbe_i2c_stop(hw); 221 return 0; 222 223 fail: 224 ixgbe_i2c_bus_clear(hw); 225 retry++; 226 if (retry < max_retry) 227 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 228 else 229 DEBUGOUT("I2C byte write combined error.\n"); 230 } while (retry < max_retry); 231 232 return IXGBE_ERR_I2C; 233 } 234 235 /** 236 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 237 * @hw: pointer to the hardware structure 238 * 239 * Initialize the function pointers. 240 **/ 241 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 242 { 243 struct ixgbe_phy_info *phy = &hw->phy; 244 245 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 246 247 /* PHY */ 248 phy->ops.identify = ixgbe_identify_phy_generic; 249 phy->ops.reset = ixgbe_reset_phy_generic; 250 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 251 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 252 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 253 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 254 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 255 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 256 phy->ops.check_link = NULL; 257 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 258 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 259 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 260 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 261 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 262 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 263 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 264 phy->ops.identify_sfp = ixgbe_identify_module_generic; 265 phy->sfp_type = ixgbe_sfp_type_unknown; 266 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 267 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 268 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 269 return IXGBE_SUCCESS; 270 } 271 272 /** 273 * ixgbe_identify_phy_generic - Get physical layer module 274 * @hw: pointer to hardware structure 275 * 276 * Determines the physical layer module found on the current adapter. 277 **/ 278 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 279 { 280 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 281 u32 phy_addr; 282 u16 ext_ability = 0; 283 284 DEBUGFUNC("ixgbe_identify_phy_generic"); 285 286 if (!hw->phy.phy_semaphore_mask) { 287 if (hw->bus.lan_id) 288 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 289 else 290 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 291 } 292 293 if (hw->phy.type == ixgbe_phy_unknown) { 294 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 295 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 296 hw->phy.addr = phy_addr; 297 ixgbe_get_phy_id(hw); 298 hw->phy.type = 299 ixgbe_get_phy_type_from_id(hw->phy.id); 300 301 if (hw->phy.type == ixgbe_phy_unknown) { 302 hw->phy.ops.read_reg(hw, 303 IXGBE_MDIO_PHY_EXT_ABILITY, 304 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 305 &ext_ability); 306 if (ext_ability & 307 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 308 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 309 hw->phy.type = 310 ixgbe_phy_cu_unknown; 311 else 312 hw->phy.type = 313 ixgbe_phy_generic; 314 } 315 316 status = IXGBE_SUCCESS; 317 break; 318 } 319 } 320 321 /* Certain media types do not have a phy so an address will not 322 * be found and the code will take this path. Caller has to 323 * decide if it is an error or not. 324 */ 325 if (status != IXGBE_SUCCESS) { 326 hw->phy.addr = 0; 327 } 328 } else { 329 status = IXGBE_SUCCESS; 330 } 331 332 return status; 333 } 334 335 /** 336 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 337 * @hw: pointer to the hardware structure 338 * 339 * This function checks the MMNGC.MNG_VETO bit to see if there are 340 * any constraints on link from manageability. For MAC's that don't 341 * have this bit just return faluse since the link can not be blocked 342 * via this method. 343 **/ 344 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 345 { 346 u32 mmngc; 347 348 DEBUGFUNC("ixgbe_check_reset_blocked"); 349 350 /* If we don't have this bit, it can't be blocking */ 351 if (hw->mac.type == ixgbe_mac_82598EB) 352 return FALSE; 353 354 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 355 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 356 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 357 "MNG_VETO bit detected.\n"); 358 return TRUE; 359 } 360 361 return FALSE; 362 } 363 364 /** 365 * ixgbe_validate_phy_addr - Determines phy address is valid 366 * @hw: pointer to hardware structure 367 * 368 **/ 369 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 370 { 371 u16 phy_id = 0; 372 bool valid = FALSE; 373 374 DEBUGFUNC("ixgbe_validate_phy_addr"); 375 376 hw->phy.addr = phy_addr; 377 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 378 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 379 380 if (phy_id != 0xFFFF && phy_id != 0x0) 381 valid = TRUE; 382 383 return valid; 384 } 385 386 /** 387 * ixgbe_get_phy_id - Get the phy type 388 * @hw: pointer to hardware structure 389 * 390 **/ 391 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 392 { 393 u32 status; 394 u16 phy_id_high = 0; 395 u16 phy_id_low = 0; 396 397 DEBUGFUNC("ixgbe_get_phy_id"); 398 399 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 400 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 401 &phy_id_high); 402 403 if (status == IXGBE_SUCCESS) { 404 hw->phy.id = (u32)(phy_id_high << 16); 405 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 406 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 407 &phy_id_low); 408 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 409 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 410 } 411 return status; 412 } 413 414 /** 415 * ixgbe_get_phy_type_from_id - Get the phy type 416 * @hw: pointer to hardware structure 417 * 418 **/ 419 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 420 { 421 enum ixgbe_phy_type phy_type; 422 423 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 424 425 switch (phy_id) { 426 case TN1010_PHY_ID: 427 phy_type = ixgbe_phy_tn; 428 break; 429 case X550_PHY_ID: 430 case X540_PHY_ID: 431 phy_type = ixgbe_phy_aq; 432 break; 433 case QT2022_PHY_ID: 434 phy_type = ixgbe_phy_qt; 435 break; 436 case ATH_PHY_ID: 437 phy_type = ixgbe_phy_nl; 438 break; 439 case X557_PHY_ID: 440 phy_type = ixgbe_phy_x550em_ext_t; 441 break; 442 default: 443 phy_type = ixgbe_phy_unknown; 444 break; 445 } 446 447 DEBUGOUT1("phy type found is %d\n", phy_type); 448 return phy_type; 449 } 450 451 /** 452 * ixgbe_reset_phy_generic - Performs a PHY reset 453 * @hw: pointer to hardware structure 454 **/ 455 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 456 { 457 u32 i; 458 u16 ctrl = 0; 459 s32 status = IXGBE_SUCCESS; 460 461 DEBUGFUNC("ixgbe_reset_phy_generic"); 462 463 if (hw->phy.type == ixgbe_phy_unknown) 464 status = ixgbe_identify_phy_generic(hw); 465 466 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 467 goto out; 468 469 /* Don't reset PHY if it's shut down due to overtemp. */ 470 if (!hw->phy.reset_if_overtemp && 471 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 472 goto out; 473 474 /* Blocked by MNG FW so bail */ 475 if (ixgbe_check_reset_blocked(hw)) 476 goto out; 477 478 /* 479 * Perform soft PHY reset to the PHY_XS. 480 * This will cause a soft reset to the PHY 481 */ 482 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 483 IXGBE_MDIO_PHY_XS_DEV_TYPE, 484 IXGBE_MDIO_PHY_XS_RESET); 485 486 /* 487 * Poll for reset bit to self-clear indicating reset is complete. 488 * Some PHYs could take up to 3 seconds to complete and need about 489 * 1.7 usec delay after the reset is complete. 490 */ 491 for (i = 0; i < 30; i++) { 492 msec_delay(100); 493 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 494 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 495 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 496 usec_delay(2); 497 break; 498 } 499 } 500 501 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 502 status = IXGBE_ERR_RESET_FAILED; 503 ERROR_REPORT1(IXGBE_ERROR_POLLING, 504 "PHY reset polling failed to complete.\n"); 505 } 506 507 out: 508 return status; 509 } 510 511 /** 512 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 513 * the SWFW lock 514 * @hw: pointer to hardware structure 515 * @reg_addr: 32 bit address of PHY register to read 516 * @phy_data: Pointer to read data from PHY register 517 **/ 518 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 519 u16 *phy_data) 520 { 521 u32 i, data, command; 522 523 /* Setup and write the address cycle command */ 524 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 525 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 526 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 527 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 528 529 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 530 531 /* 532 * Check every 10 usec to see if the address cycle completed. 533 * The MDI Command bit will clear when the operation is 534 * complete 535 */ 536 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 537 usec_delay(10); 538 539 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 540 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 541 break; 542 } 543 544 545 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 546 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 547 return IXGBE_ERR_PHY; 548 } 549 550 /* 551 * Address cycle complete, setup and write the read 552 * command 553 */ 554 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 555 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 556 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 557 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 558 559 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 560 561 /* 562 * Check every 10 usec to see if the address cycle 563 * completed. The MDI Command bit will clear when the 564 * operation is complete 565 */ 566 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 567 usec_delay(10); 568 569 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 570 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 571 break; 572 } 573 574 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 575 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 576 return IXGBE_ERR_PHY; 577 } 578 579 /* 580 * Read operation is complete. Get the data 581 * from MSRWD 582 */ 583 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 584 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 585 *phy_data = (u16)(data); 586 587 return IXGBE_SUCCESS; 588 } 589 590 /** 591 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 592 * using the SWFW lock - this function is needed in most cases 593 * @hw: pointer to hardware structure 594 * @reg_addr: 32 bit address of PHY register to read 595 * @phy_data: Pointer to read data from PHY register 596 **/ 597 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 598 u32 device_type, u16 *phy_data) 599 { 600 s32 status; 601 u32 gssr = hw->phy.phy_semaphore_mask; 602 603 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 604 605 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 606 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 607 phy_data); 608 hw->mac.ops.release_swfw_sync(hw, gssr); 609 } else { 610 status = IXGBE_ERR_SWFW_SYNC; 611 } 612 613 return status; 614 } 615 616 /** 617 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 618 * without SWFW lock 619 * @hw: pointer to hardware structure 620 * @reg_addr: 32 bit PHY register to write 621 * @device_type: 5 bit device type 622 * @phy_data: Data to write to the PHY register 623 **/ 624 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 625 u32 device_type, u16 phy_data) 626 { 627 u32 i, command; 628 629 /* Put the data in the MDI single read and write data register*/ 630 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 631 632 /* Setup and write the address cycle command */ 633 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 634 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 635 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 636 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 637 638 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 639 640 /* 641 * Check every 10 usec to see if the address cycle completed. 642 * The MDI Command bit will clear when the operation is 643 * complete 644 */ 645 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 646 usec_delay(10); 647 648 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 649 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 650 break; 651 } 652 653 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 654 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 655 return IXGBE_ERR_PHY; 656 } 657 658 /* 659 * Address cycle complete, setup and write the write 660 * command 661 */ 662 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 663 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 664 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 665 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 666 667 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 668 669 /* 670 * Check every 10 usec to see if the address cycle 671 * completed. The MDI Command bit will clear when the 672 * operation is complete 673 */ 674 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 675 usec_delay(10); 676 677 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 678 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 679 break; 680 } 681 682 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 683 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 684 return IXGBE_ERR_PHY; 685 } 686 687 return IXGBE_SUCCESS; 688 } 689 690 /** 691 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 692 * using SWFW lock- this function is needed in most cases 693 * @hw: pointer to hardware structure 694 * @reg_addr: 32 bit PHY register to write 695 * @device_type: 5 bit device type 696 * @phy_data: Data to write to the PHY register 697 **/ 698 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 699 u32 device_type, u16 phy_data) 700 { 701 s32 status; 702 u32 gssr = hw->phy.phy_semaphore_mask; 703 704 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 705 706 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 707 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 708 phy_data); 709 hw->mac.ops.release_swfw_sync(hw, gssr); 710 } else { 711 status = IXGBE_ERR_SWFW_SYNC; 712 } 713 714 return status; 715 } 716 717 /** 718 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 719 * @hw: pointer to hardware structure 720 * 721 * Restart auto-negotiation and PHY and waits for completion. 722 **/ 723 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 724 { 725 s32 status = IXGBE_SUCCESS; 726 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 727 bool autoneg = FALSE; 728 ixgbe_link_speed speed; 729 730 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 731 732 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 733 734 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 735 /* Set or unset auto-negotiation 10G advertisement */ 736 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 737 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 738 &autoneg_reg); 739 740 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 741 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 742 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 743 744 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 745 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 746 autoneg_reg); 747 } 748 749 if (hw->mac.type == ixgbe_mac_X550) { 750 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 751 /* Set or unset auto-negotiation 1G advertisement */ 752 hw->phy.ops.read_reg(hw, 753 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 754 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 755 &autoneg_reg); 756 757 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 758 if (hw->phy.autoneg_advertised & 759 IXGBE_LINK_SPEED_5GB_FULL) 760 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 761 762 hw->phy.ops.write_reg(hw, 763 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 764 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 765 autoneg_reg); 766 } 767 768 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 769 /* Set or unset auto-negotiation 1G advertisement */ 770 hw->phy.ops.read_reg(hw, 771 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 772 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 773 &autoneg_reg); 774 775 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 776 if (hw->phy.autoneg_advertised & 777 IXGBE_LINK_SPEED_2_5GB_FULL) 778 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 779 780 hw->phy.ops.write_reg(hw, 781 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 782 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 783 autoneg_reg); 784 } 785 } 786 787 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 788 /* Set or unset auto-negotiation 1G advertisement */ 789 hw->phy.ops.read_reg(hw, 790 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 791 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 792 &autoneg_reg); 793 794 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 795 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 796 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 797 798 hw->phy.ops.write_reg(hw, 799 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 800 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 801 autoneg_reg); 802 } 803 804 if (speed & IXGBE_LINK_SPEED_100_FULL) { 805 /* Set or unset auto-negotiation 100M advertisement */ 806 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 807 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 808 &autoneg_reg); 809 810 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 811 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 812 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 813 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 814 815 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 816 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 817 autoneg_reg); 818 } 819 820 /* Blocked by MNG FW so don't reset PHY */ 821 if (ixgbe_check_reset_blocked(hw)) 822 return status; 823 824 /* Restart PHY auto-negotiation. */ 825 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 827 828 autoneg_reg |= IXGBE_MII_RESTART; 829 830 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 831 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 832 833 return status; 834 } 835 836 /** 837 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 838 * @hw: pointer to hardware structure 839 * @speed: new link speed 840 **/ 841 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 842 ixgbe_link_speed speed, 843 bool autoneg_wait_to_complete) 844 { 845 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 846 847 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 848 849 /* 850 * Clear autoneg_advertised and set new values based on input link 851 * speed. 852 */ 853 hw->phy.autoneg_advertised = 0; 854 855 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 856 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 857 858 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 859 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 860 861 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 862 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 863 864 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 865 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 866 867 if (speed & IXGBE_LINK_SPEED_100_FULL) 868 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 869 870 /* Setup link based on the new speed settings */ 871 hw->phy.ops.setup_link(hw); 872 873 return IXGBE_SUCCESS; 874 } 875 876 /** 877 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 878 * @hw: pointer to hardware structure 879 * @speed: pointer to link speed 880 * @autoneg: boolean auto-negotiation value 881 * 882 * Determines the supported link capabilities by reading the PHY auto 883 * negotiation register. 884 **/ 885 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 886 ixgbe_link_speed *speed, 887 bool *autoneg) 888 { 889 s32 status; 890 u16 speed_ability; 891 892 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 893 894 *speed = 0; 895 *autoneg = TRUE; 896 897 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 898 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 899 &speed_ability); 900 901 if (status == IXGBE_SUCCESS) { 902 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 903 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 904 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 905 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 906 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 907 *speed |= IXGBE_LINK_SPEED_100_FULL; 908 } 909 910 /* Internal PHY does not support 100 Mbps */ 911 if (hw->mac.type == ixgbe_mac_X550EM_x) 912 *speed &= ~IXGBE_LINK_SPEED_100_FULL; 913 914 if (hw->mac.type == ixgbe_mac_X550) { 915 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 916 *speed |= IXGBE_LINK_SPEED_5GB_FULL; 917 } 918 919 return status; 920 } 921 922 /** 923 * ixgbe_check_phy_link_tnx - Determine link and speed status 924 * @hw: pointer to hardware structure 925 * 926 * Reads the VS1 register to determine if link is up and the current speed for 927 * the PHY. 928 **/ 929 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 930 bool *link_up) 931 { 932 s32 status = IXGBE_SUCCESS; 933 u32 time_out; 934 u32 max_time_out = 10; 935 u16 phy_link = 0; 936 u16 phy_speed = 0; 937 u16 phy_data = 0; 938 939 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 940 941 /* Initialize speed and link to default case */ 942 *link_up = FALSE; 943 *speed = IXGBE_LINK_SPEED_10GB_FULL; 944 945 /* 946 * Check current speed and link status of the PHY register. 947 * This is a vendor specific register and may have to 948 * be changed for other copper PHYs. 949 */ 950 for (time_out = 0; time_out < max_time_out; time_out++) { 951 usec_delay(10); 952 status = hw->phy.ops.read_reg(hw, 953 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 954 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 955 &phy_data); 956 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 957 phy_speed = phy_data & 958 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 959 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 960 *link_up = TRUE; 961 if (phy_speed == 962 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 963 *speed = IXGBE_LINK_SPEED_1GB_FULL; 964 break; 965 } 966 } 967 968 return status; 969 } 970 971 /** 972 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 973 * @hw: pointer to hardware structure 974 * 975 * Restart auto-negotiation and PHY and waits for completion. 976 **/ 977 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 978 { 979 s32 status = IXGBE_SUCCESS; 980 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 981 bool autoneg = FALSE; 982 ixgbe_link_speed speed; 983 984 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 985 986 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 987 988 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 989 /* Set or unset auto-negotiation 10G advertisement */ 990 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 991 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 992 &autoneg_reg); 993 994 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 995 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 996 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 997 998 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 999 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1000 autoneg_reg); 1001 } 1002 1003 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1004 /* Set or unset auto-negotiation 1G advertisement */ 1005 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1006 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1007 &autoneg_reg); 1008 1009 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1010 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1011 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1012 1013 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1014 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1015 autoneg_reg); 1016 } 1017 1018 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1019 /* Set or unset auto-negotiation 100M advertisement */ 1020 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1021 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1022 &autoneg_reg); 1023 1024 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1025 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1026 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1027 1028 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1029 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1030 autoneg_reg); 1031 } 1032 1033 /* Blocked by MNG FW so don't reset PHY */ 1034 if (ixgbe_check_reset_blocked(hw)) 1035 return status; 1036 1037 /* Restart PHY auto-negotiation. */ 1038 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1039 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1040 1041 autoneg_reg |= IXGBE_MII_RESTART; 1042 1043 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1044 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1045 1046 return status; 1047 } 1048 1049 /** 1050 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1051 * @hw: pointer to hardware structure 1052 * @firmware_version: pointer to the PHY Firmware Version 1053 **/ 1054 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1055 u16 *firmware_version) 1056 { 1057 s32 status; 1058 1059 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1060 1061 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1062 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1063 firmware_version); 1064 1065 return status; 1066 } 1067 1068 /** 1069 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1070 * @hw: pointer to hardware structure 1071 * @firmware_version: pointer to the PHY Firmware Version 1072 **/ 1073 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1074 u16 *firmware_version) 1075 { 1076 s32 status; 1077 1078 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1079 1080 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1081 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1082 firmware_version); 1083 1084 return status; 1085 } 1086 1087 /** 1088 * ixgbe_reset_phy_nl - Performs a PHY reset 1089 * @hw: pointer to hardware structure 1090 **/ 1091 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1092 { 1093 u16 phy_offset, control, eword, edata, block_crc; 1094 bool end_data = FALSE; 1095 u16 list_offset, data_offset; 1096 u16 phy_data = 0; 1097 s32 ret_val = IXGBE_SUCCESS; 1098 u32 i; 1099 1100 DEBUGFUNC("ixgbe_reset_phy_nl"); 1101 1102 /* Blocked by MNG FW so bail */ 1103 if (ixgbe_check_reset_blocked(hw)) 1104 goto out; 1105 1106 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1107 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1108 1109 /* reset the PHY and poll for completion */ 1110 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1111 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1112 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1113 1114 for (i = 0; i < 100; i++) { 1115 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1116 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1117 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1118 break; 1119 msec_delay(10); 1120 } 1121 1122 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1123 DEBUGOUT("PHY reset did not complete.\n"); 1124 ret_val = IXGBE_ERR_PHY; 1125 goto out; 1126 } 1127 1128 /* Get init offsets */ 1129 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1130 &data_offset); 1131 if (ret_val != IXGBE_SUCCESS) 1132 goto out; 1133 1134 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1135 data_offset++; 1136 while (!end_data) { 1137 /* 1138 * Read control word from PHY init contents offset 1139 */ 1140 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1141 if (ret_val) 1142 goto err_eeprom; 1143 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1144 IXGBE_CONTROL_SHIFT_NL; 1145 edata = eword & IXGBE_DATA_MASK_NL; 1146 switch (control) { 1147 case IXGBE_DELAY_NL: 1148 data_offset++; 1149 DEBUGOUT1("DELAY: %d MS\n", edata); 1150 msec_delay(edata); 1151 break; 1152 case IXGBE_DATA_NL: 1153 DEBUGOUT("DATA:\n"); 1154 data_offset++; 1155 ret_val = hw->eeprom.ops.read(hw, data_offset, 1156 &phy_offset); 1157 if (ret_val) 1158 goto err_eeprom; 1159 data_offset++; 1160 for (i = 0; i < edata; i++) { 1161 ret_val = hw->eeprom.ops.read(hw, data_offset, 1162 &eword); 1163 if (ret_val) 1164 goto err_eeprom; 1165 hw->phy.ops.write_reg(hw, phy_offset, 1166 IXGBE_TWINAX_DEV, eword); 1167 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1168 phy_offset); 1169 data_offset++; 1170 phy_offset++; 1171 } 1172 break; 1173 case IXGBE_CONTROL_NL: 1174 data_offset++; 1175 DEBUGOUT("CONTROL:\n"); 1176 if (edata == IXGBE_CONTROL_EOL_NL) { 1177 DEBUGOUT("EOL\n"); 1178 end_data = TRUE; 1179 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1180 DEBUGOUT("SOL\n"); 1181 } else { 1182 DEBUGOUT("Bad control value\n"); 1183 ret_val = IXGBE_ERR_PHY; 1184 goto out; 1185 } 1186 break; 1187 default: 1188 DEBUGOUT("Bad control type\n"); 1189 ret_val = IXGBE_ERR_PHY; 1190 goto out; 1191 } 1192 } 1193 1194 out: 1195 return ret_val; 1196 1197 err_eeprom: 1198 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1199 "eeprom read at offset %d failed", data_offset); 1200 return IXGBE_ERR_PHY; 1201 } 1202 1203 /** 1204 * ixgbe_identify_module_generic - Identifies module type 1205 * @hw: pointer to hardware structure 1206 * 1207 * Determines HW type and calls appropriate function. 1208 **/ 1209 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1210 { 1211 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1212 1213 DEBUGFUNC("ixgbe_identify_module_generic"); 1214 1215 switch (hw->mac.ops.get_media_type(hw)) { 1216 case ixgbe_media_type_fiber: 1217 status = ixgbe_identify_sfp_module_generic(hw); 1218 break; 1219 1220 case ixgbe_media_type_fiber_qsfp: 1221 status = ixgbe_identify_qsfp_module_generic(hw); 1222 break; 1223 1224 default: 1225 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1226 status = IXGBE_ERR_SFP_NOT_PRESENT; 1227 break; 1228 } 1229 1230 return status; 1231 } 1232 1233 /** 1234 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1235 * @hw: pointer to hardware structure 1236 * 1237 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1238 **/ 1239 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1240 { 1241 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1242 u32 vendor_oui = 0; 1243 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1244 u8 identifier = 0; 1245 u8 comp_codes_1g = 0; 1246 u8 comp_codes_10g = 0; 1247 u8 oui_bytes[3] = {0, 0, 0}; 1248 u8 cable_tech = 0; 1249 u8 cable_spec = 0; 1250 u16 enforce_sfp = 0; 1251 1252 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1253 1254 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1255 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1256 status = IXGBE_ERR_SFP_NOT_PRESENT; 1257 goto out; 1258 } 1259 1260 /* LAN ID is needed for I2C access */ 1261 hw->mac.ops.set_lan_id(hw); 1262 1263 status = hw->phy.ops.read_i2c_eeprom(hw, 1264 IXGBE_SFF_IDENTIFIER, 1265 &identifier); 1266 1267 if (status != IXGBE_SUCCESS) 1268 goto err_read_i2c_eeprom; 1269 1270 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1271 hw->phy.type = ixgbe_phy_sfp_unsupported; 1272 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1273 } else { 1274 status = hw->phy.ops.read_i2c_eeprom(hw, 1275 IXGBE_SFF_1GBE_COMP_CODES, 1276 &comp_codes_1g); 1277 1278 if (status != IXGBE_SUCCESS) 1279 goto err_read_i2c_eeprom; 1280 1281 status = hw->phy.ops.read_i2c_eeprom(hw, 1282 IXGBE_SFF_10GBE_COMP_CODES, 1283 &comp_codes_10g); 1284 1285 if (status != IXGBE_SUCCESS) 1286 goto err_read_i2c_eeprom; 1287 status = hw->phy.ops.read_i2c_eeprom(hw, 1288 IXGBE_SFF_CABLE_TECHNOLOGY, 1289 &cable_tech); 1290 1291 if (status != IXGBE_SUCCESS) 1292 goto err_read_i2c_eeprom; 1293 1294 /* ID Module 1295 * ========= 1296 * 0 SFP_DA_CU 1297 * 1 SFP_SR 1298 * 2 SFP_LR 1299 * 3 SFP_DA_CORE0 - 82599-specific 1300 * 4 SFP_DA_CORE1 - 82599-specific 1301 * 5 SFP_SR/LR_CORE0 - 82599-specific 1302 * 6 SFP_SR/LR_CORE1 - 82599-specific 1303 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1304 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1305 * 9 SFP_1g_cu_CORE0 - 82599-specific 1306 * 10 SFP_1g_cu_CORE1 - 82599-specific 1307 * 11 SFP_1g_sx_CORE0 - 82599-specific 1308 * 12 SFP_1g_sx_CORE1 - 82599-specific 1309 */ 1310 if (hw->mac.type == ixgbe_mac_82598EB) { 1311 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1312 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1313 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1314 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1315 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1316 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1317 else 1318 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1319 } else { 1320 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1321 if (hw->bus.lan_id == 0) 1322 hw->phy.sfp_type = 1323 ixgbe_sfp_type_da_cu_core0; 1324 else 1325 hw->phy.sfp_type = 1326 ixgbe_sfp_type_da_cu_core1; 1327 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1328 hw->phy.ops.read_i2c_eeprom( 1329 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1330 &cable_spec); 1331 if (cable_spec & 1332 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1333 if (hw->bus.lan_id == 0) 1334 hw->phy.sfp_type = 1335 ixgbe_sfp_type_da_act_lmt_core0; 1336 else 1337 hw->phy.sfp_type = 1338 ixgbe_sfp_type_da_act_lmt_core1; 1339 } else { 1340 hw->phy.sfp_type = 1341 ixgbe_sfp_type_unknown; 1342 } 1343 } else if (comp_codes_10g & 1344 (IXGBE_SFF_10GBASESR_CAPABLE | 1345 IXGBE_SFF_10GBASELR_CAPABLE)) { 1346 if (hw->bus.lan_id == 0) 1347 hw->phy.sfp_type = 1348 ixgbe_sfp_type_srlr_core0; 1349 else 1350 hw->phy.sfp_type = 1351 ixgbe_sfp_type_srlr_core1; 1352 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1353 if (hw->bus.lan_id == 0) 1354 hw->phy.sfp_type = 1355 ixgbe_sfp_type_1g_cu_core0; 1356 else 1357 hw->phy.sfp_type = 1358 ixgbe_sfp_type_1g_cu_core1; 1359 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1360 if (hw->bus.lan_id == 0) 1361 hw->phy.sfp_type = 1362 ixgbe_sfp_type_1g_sx_core0; 1363 else 1364 hw->phy.sfp_type = 1365 ixgbe_sfp_type_1g_sx_core1; 1366 } else { 1367 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1368 } 1369 } 1370 1371 if (hw->phy.sfp_type != stored_sfp_type) 1372 hw->phy.sfp_setup_needed = TRUE; 1373 1374 /* Determine if the SFP+ PHY is dual speed or not. */ 1375 hw->phy.multispeed_fiber = FALSE; 1376 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1377 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1378 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1379 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1380 hw->phy.multispeed_fiber = TRUE; 1381 1382 /* Determine PHY vendor */ 1383 if (hw->phy.type != ixgbe_phy_nl) { 1384 hw->phy.id = identifier; 1385 status = hw->phy.ops.read_i2c_eeprom(hw, 1386 IXGBE_SFF_VENDOR_OUI_BYTE0, 1387 &oui_bytes[0]); 1388 1389 if (status != IXGBE_SUCCESS) 1390 goto err_read_i2c_eeprom; 1391 1392 status = hw->phy.ops.read_i2c_eeprom(hw, 1393 IXGBE_SFF_VENDOR_OUI_BYTE1, 1394 &oui_bytes[1]); 1395 1396 if (status != IXGBE_SUCCESS) 1397 goto err_read_i2c_eeprom; 1398 1399 status = hw->phy.ops.read_i2c_eeprom(hw, 1400 IXGBE_SFF_VENDOR_OUI_BYTE2, 1401 &oui_bytes[2]); 1402 1403 if (status != IXGBE_SUCCESS) 1404 goto err_read_i2c_eeprom; 1405 1406 vendor_oui = 1407 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1408 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1409 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1410 1411 switch (vendor_oui) { 1412 case IXGBE_SFF_VENDOR_OUI_TYCO: 1413 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1414 hw->phy.type = 1415 ixgbe_phy_sfp_passive_tyco; 1416 break; 1417 case IXGBE_SFF_VENDOR_OUI_FTL: 1418 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1419 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1420 else 1421 hw->phy.type = ixgbe_phy_sfp_ftl; 1422 break; 1423 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1424 hw->phy.type = ixgbe_phy_sfp_avago; 1425 break; 1426 case IXGBE_SFF_VENDOR_OUI_INTEL: 1427 hw->phy.type = ixgbe_phy_sfp_intel; 1428 break; 1429 default: 1430 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1431 hw->phy.type = 1432 ixgbe_phy_sfp_passive_unknown; 1433 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1434 hw->phy.type = 1435 ixgbe_phy_sfp_active_unknown; 1436 else 1437 hw->phy.type = ixgbe_phy_sfp_unknown; 1438 break; 1439 } 1440 } 1441 1442 /* Allow any DA cable vendor */ 1443 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1444 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1445 status = IXGBE_SUCCESS; 1446 goto out; 1447 } 1448 1449 /* Verify supported 1G SFP modules */ 1450 if (comp_codes_10g == 0 && 1451 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1452 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1453 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1454 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1455 hw->phy.type = ixgbe_phy_sfp_unsupported; 1456 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1457 goto out; 1458 } 1459 1460 /* Anything else 82598-based is supported */ 1461 if (hw->mac.type == ixgbe_mac_82598EB) { 1462 status = IXGBE_SUCCESS; 1463 goto out; 1464 } 1465 1466 ixgbe_get_device_caps(hw, &enforce_sfp); 1467 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1468 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1469 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1470 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1471 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1472 /* Make sure we're a supported PHY type */ 1473 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1474 status = IXGBE_SUCCESS; 1475 } else { 1476 if (hw->allow_unsupported_sfp == TRUE) { 1477 EWARN(hw, "WARNING: Intel (R) Network " 1478 "Connections are quality tested " 1479 "using Intel (R) Ethernet Optics." 1480 " Using untested modules is not " 1481 "supported and may cause unstable" 1482 " operation or damage to the " 1483 "module or the adapter. Intel " 1484 "Corporation is not responsible " 1485 "for any harm caused by using " 1486 "untested modules.\n", status); 1487 status = IXGBE_SUCCESS; 1488 } else { 1489 DEBUGOUT("SFP+ module not supported\n"); 1490 hw->phy.type = 1491 ixgbe_phy_sfp_unsupported; 1492 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1493 } 1494 } 1495 } else { 1496 status = IXGBE_SUCCESS; 1497 } 1498 } 1499 1500 out: 1501 return status; 1502 1503 err_read_i2c_eeprom: 1504 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1505 if (hw->phy.type != ixgbe_phy_nl) { 1506 hw->phy.id = 0; 1507 hw->phy.type = ixgbe_phy_unknown; 1508 } 1509 return IXGBE_ERR_SFP_NOT_PRESENT; 1510 } 1511 1512 /** 1513 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1514 * @hw: pointer to hardware structure 1515 * 1516 * Determines physical layer capabilities of the current SFP. 1517 */ 1518 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1519 { 1520 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1521 u8 comp_codes_10g = 0; 1522 u8 comp_codes_1g = 0; 1523 1524 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1525 1526 hw->phy.ops.identify_sfp(hw); 1527 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1528 return physical_layer; 1529 1530 switch (hw->phy.type) { 1531 case ixgbe_phy_sfp_passive_tyco: 1532 case ixgbe_phy_sfp_passive_unknown: 1533 case ixgbe_phy_qsfp_passive_unknown: 1534 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1535 break; 1536 case ixgbe_phy_sfp_ftl_active: 1537 case ixgbe_phy_sfp_active_unknown: 1538 case ixgbe_phy_qsfp_active_unknown: 1539 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1540 break; 1541 case ixgbe_phy_sfp_avago: 1542 case ixgbe_phy_sfp_ftl: 1543 case ixgbe_phy_sfp_intel: 1544 case ixgbe_phy_sfp_unknown: 1545 hw->phy.ops.read_i2c_eeprom(hw, 1546 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1547 hw->phy.ops.read_i2c_eeprom(hw, 1548 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1549 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1550 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1551 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1552 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1553 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1554 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1555 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1556 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1557 break; 1558 case ixgbe_phy_qsfp_intel: 1559 case ixgbe_phy_qsfp_unknown: 1560 hw->phy.ops.read_i2c_eeprom(hw, 1561 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1562 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1563 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1564 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1565 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1566 break; 1567 default: 1568 break; 1569 } 1570 1571 return physical_layer; 1572 } 1573 1574 /** 1575 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1576 * @hw: pointer to hardware structure 1577 * 1578 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1579 **/ 1580 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1581 { 1582 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1583 u32 vendor_oui = 0; 1584 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1585 u8 identifier = 0; 1586 u8 comp_codes_1g = 0; 1587 u8 comp_codes_10g = 0; 1588 u8 oui_bytes[3] = {0, 0, 0}; 1589 u16 enforce_sfp = 0; 1590 u8 connector = 0; 1591 u8 cable_length = 0; 1592 u8 device_tech = 0; 1593 bool active_cable = FALSE; 1594 1595 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1596 1597 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1598 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1599 status = IXGBE_ERR_SFP_NOT_PRESENT; 1600 goto out; 1601 } 1602 1603 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1604 &identifier); 1605 1606 if (status != IXGBE_SUCCESS) 1607 goto err_read_i2c_eeprom; 1608 1609 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1610 hw->phy.type = ixgbe_phy_sfp_unsupported; 1611 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1612 goto out; 1613 } 1614 1615 hw->phy.id = identifier; 1616 1617 /* LAN ID is needed for sfp_type determination */ 1618 hw->mac.ops.set_lan_id(hw); 1619 1620 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1621 &comp_codes_10g); 1622 1623 if (status != IXGBE_SUCCESS) 1624 goto err_read_i2c_eeprom; 1625 1626 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1627 &comp_codes_1g); 1628 1629 if (status != IXGBE_SUCCESS) 1630 goto err_read_i2c_eeprom; 1631 1632 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1633 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1634 if (hw->bus.lan_id == 0) 1635 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1636 else 1637 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1638 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1639 IXGBE_SFF_10GBASELR_CAPABLE)) { 1640 if (hw->bus.lan_id == 0) 1641 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1642 else 1643 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1644 } else { 1645 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1646 active_cable = TRUE; 1647 1648 if (!active_cable) { 1649 /* check for active DA cables that pre-date 1650 * SFF-8436 v3.6 */ 1651 hw->phy.ops.read_i2c_eeprom(hw, 1652 IXGBE_SFF_QSFP_CONNECTOR, 1653 &connector); 1654 1655 hw->phy.ops.read_i2c_eeprom(hw, 1656 IXGBE_SFF_QSFP_CABLE_LENGTH, 1657 &cable_length); 1658 1659 hw->phy.ops.read_i2c_eeprom(hw, 1660 IXGBE_SFF_QSFP_DEVICE_TECH, 1661 &device_tech); 1662 1663 if ((connector == 1664 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1665 (cable_length > 0) && 1666 ((device_tech >> 4) == 1667 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1668 active_cable = TRUE; 1669 } 1670 1671 if (active_cable) { 1672 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1673 if (hw->bus.lan_id == 0) 1674 hw->phy.sfp_type = 1675 ixgbe_sfp_type_da_act_lmt_core0; 1676 else 1677 hw->phy.sfp_type = 1678 ixgbe_sfp_type_da_act_lmt_core1; 1679 } else { 1680 /* unsupported module type */ 1681 hw->phy.type = ixgbe_phy_sfp_unsupported; 1682 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1683 goto out; 1684 } 1685 } 1686 1687 if (hw->phy.sfp_type != stored_sfp_type) 1688 hw->phy.sfp_setup_needed = TRUE; 1689 1690 /* Determine if the QSFP+ PHY is dual speed or not. */ 1691 hw->phy.multispeed_fiber = FALSE; 1692 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1693 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1694 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1695 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1696 hw->phy.multispeed_fiber = TRUE; 1697 1698 /* Determine PHY vendor for optical modules */ 1699 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1700 IXGBE_SFF_10GBASELR_CAPABLE)) { 1701 status = hw->phy.ops.read_i2c_eeprom(hw, 1702 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1703 &oui_bytes[0]); 1704 1705 if (status != IXGBE_SUCCESS) 1706 goto err_read_i2c_eeprom; 1707 1708 status = hw->phy.ops.read_i2c_eeprom(hw, 1709 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1710 &oui_bytes[1]); 1711 1712 if (status != IXGBE_SUCCESS) 1713 goto err_read_i2c_eeprom; 1714 1715 status = hw->phy.ops.read_i2c_eeprom(hw, 1716 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1717 &oui_bytes[2]); 1718 1719 if (status != IXGBE_SUCCESS) 1720 goto err_read_i2c_eeprom; 1721 1722 vendor_oui = 1723 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1724 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1725 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1726 1727 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1728 hw->phy.type = ixgbe_phy_qsfp_intel; 1729 else 1730 hw->phy.type = ixgbe_phy_qsfp_unknown; 1731 1732 ixgbe_get_device_caps(hw, &enforce_sfp); 1733 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1734 /* Make sure we're a supported PHY type */ 1735 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1736 status = IXGBE_SUCCESS; 1737 } else { 1738 if (hw->allow_unsupported_sfp == TRUE) { 1739 EWARN(hw, "WARNING: Intel (R) Network " 1740 "Connections are quality tested " 1741 "using Intel (R) Ethernet Optics." 1742 " Using untested modules is not " 1743 "supported and may cause unstable" 1744 " operation or damage to the " 1745 "module or the adapter. Intel " 1746 "Corporation is not responsible " 1747 "for any harm caused by using " 1748 "untested modules.\n", status); 1749 status = IXGBE_SUCCESS; 1750 } else { 1751 DEBUGOUT("QSFP module not supported\n"); 1752 hw->phy.type = 1753 ixgbe_phy_sfp_unsupported; 1754 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1755 } 1756 } 1757 } else { 1758 status = IXGBE_SUCCESS; 1759 } 1760 } 1761 1762 out: 1763 return status; 1764 1765 err_read_i2c_eeprom: 1766 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1767 hw->phy.id = 0; 1768 hw->phy.type = ixgbe_phy_unknown; 1769 1770 return IXGBE_ERR_SFP_NOT_PRESENT; 1771 } 1772 1773 1774 /** 1775 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1776 * @hw: pointer to hardware structure 1777 * @list_offset: offset to the SFP ID list 1778 * @data_offset: offset to the SFP data block 1779 * 1780 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1781 * so it returns the offsets to the phy init sequence block. 1782 **/ 1783 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1784 u16 *list_offset, 1785 u16 *data_offset) 1786 { 1787 u16 sfp_id; 1788 u16 sfp_type = hw->phy.sfp_type; 1789 1790 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1791 1792 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1793 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1794 1795 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1796 return IXGBE_ERR_SFP_NOT_PRESENT; 1797 1798 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1799 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1800 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1801 1802 /* 1803 * Limiting active cables and 1G Phys must be initialized as 1804 * SR modules 1805 */ 1806 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1807 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1808 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1809 sfp_type = ixgbe_sfp_type_srlr_core0; 1810 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1811 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1812 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1813 sfp_type = ixgbe_sfp_type_srlr_core1; 1814 1815 /* Read offset to PHY init contents */ 1816 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1817 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1818 "eeprom read at offset %d failed", 1819 IXGBE_PHY_INIT_OFFSET_NL); 1820 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1821 } 1822 1823 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1824 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1825 1826 /* Shift offset to first ID word */ 1827 (*list_offset)++; 1828 1829 /* 1830 * Find the matching SFP ID in the EEPROM 1831 * and program the init sequence 1832 */ 1833 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1834 goto err_phy; 1835 1836 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1837 if (sfp_id == sfp_type) { 1838 (*list_offset)++; 1839 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1840 goto err_phy; 1841 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1842 DEBUGOUT("SFP+ module not supported\n"); 1843 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1844 } else { 1845 break; 1846 } 1847 } else { 1848 (*list_offset) += 2; 1849 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1850 goto err_phy; 1851 } 1852 } 1853 1854 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1855 DEBUGOUT("No matching SFP+ module found\n"); 1856 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1857 } 1858 1859 return IXGBE_SUCCESS; 1860 1861 err_phy: 1862 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1863 "eeprom read at offset %d failed", *list_offset); 1864 return IXGBE_ERR_PHY; 1865 } 1866 1867 /** 1868 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1869 * @hw: pointer to hardware structure 1870 * @byte_offset: EEPROM byte offset to read 1871 * @eeprom_data: value read 1872 * 1873 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1874 **/ 1875 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1876 u8 *eeprom_data) 1877 { 1878 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1879 1880 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1881 IXGBE_I2C_EEPROM_DEV_ADDR, 1882 eeprom_data); 1883 } 1884 1885 /** 1886 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1887 * @hw: pointer to hardware structure 1888 * @byte_offset: byte offset at address 0xA2 1889 * @eeprom_data: value read 1890 * 1891 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1892 **/ 1893 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1894 u8 *sff8472_data) 1895 { 1896 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1897 IXGBE_I2C_EEPROM_DEV_ADDR2, 1898 sff8472_data); 1899 } 1900 1901 /** 1902 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1903 * @hw: pointer to hardware structure 1904 * @byte_offset: EEPROM byte offset to write 1905 * @eeprom_data: value to write 1906 * 1907 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1908 **/ 1909 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1910 u8 eeprom_data) 1911 { 1912 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1913 1914 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1915 IXGBE_I2C_EEPROM_DEV_ADDR, 1916 eeprom_data); 1917 } 1918 1919 /** 1920 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1921 * @hw: pointer to hardware structure 1922 * @offset: eeprom offset to be read 1923 * @addr: I2C address to be read 1924 */ 1925 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1926 { 1927 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1928 offset == IXGBE_SFF_IDENTIFIER && 1929 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1930 return TRUE; 1931 return FALSE; 1932 } 1933 1934 /** 1935 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1936 * @hw: pointer to hardware structure 1937 * @byte_offset: byte offset to read 1938 * @data: value read 1939 * 1940 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1941 * a specified device address. 1942 **/ 1943 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1944 u8 dev_addr, u8 *data) 1945 { 1946 s32 status; 1947 u32 max_retry = 10; 1948 u32 retry = 0; 1949 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1950 bool nack = 1; 1951 *data = 0; 1952 1953 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1954 1955 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 1956 max_retry = IXGBE_SFP_DETECT_RETRIES; 1957 1958 do { 1959 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1960 return IXGBE_ERR_SWFW_SYNC; 1961 1962 ixgbe_i2c_start(hw); 1963 1964 /* Device Address and write indication */ 1965 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1966 if (status != IXGBE_SUCCESS) 1967 goto fail; 1968 1969 status = ixgbe_get_i2c_ack(hw); 1970 if (status != IXGBE_SUCCESS) 1971 goto fail; 1972 1973 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1974 if (status != IXGBE_SUCCESS) 1975 goto fail; 1976 1977 status = ixgbe_get_i2c_ack(hw); 1978 if (status != IXGBE_SUCCESS) 1979 goto fail; 1980 1981 ixgbe_i2c_start(hw); 1982 1983 /* Device Address and read indication */ 1984 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1985 if (status != IXGBE_SUCCESS) 1986 goto fail; 1987 1988 status = ixgbe_get_i2c_ack(hw); 1989 if (status != IXGBE_SUCCESS) 1990 goto fail; 1991 1992 status = ixgbe_clock_in_i2c_byte(hw, data); 1993 if (status != IXGBE_SUCCESS) 1994 goto fail; 1995 1996 status = ixgbe_clock_out_i2c_bit(hw, nack); 1997 if (status != IXGBE_SUCCESS) 1998 goto fail; 1999 2000 ixgbe_i2c_stop(hw); 2001 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2002 return IXGBE_SUCCESS; 2003 2004 fail: 2005 ixgbe_i2c_bus_clear(hw); 2006 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2007 msec_delay(100); 2008 retry++; 2009 if (retry < max_retry) 2010 DEBUGOUT("I2C byte read error - Retrying.\n"); 2011 else 2012 DEBUGOUT("I2C byte read error.\n"); 2013 2014 } while (retry < max_retry); 2015 2016 return status; 2017 } 2018 2019 /** 2020 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2021 * @hw: pointer to hardware structure 2022 * @byte_offset: byte offset to write 2023 * @data: value to write 2024 * 2025 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2026 * a specified device address. 2027 **/ 2028 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2029 u8 dev_addr, u8 data) 2030 { 2031 s32 status = IXGBE_SUCCESS; 2032 u32 max_retry = 1; 2033 u32 retry = 0; 2034 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2035 2036 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2037 2038 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 2039 status = IXGBE_ERR_SWFW_SYNC; 2040 goto write_byte_out; 2041 } 2042 2043 do { 2044 ixgbe_i2c_start(hw); 2045 2046 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2047 if (status != IXGBE_SUCCESS) 2048 goto fail; 2049 2050 status = ixgbe_get_i2c_ack(hw); 2051 if (status != IXGBE_SUCCESS) 2052 goto fail; 2053 2054 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2055 if (status != IXGBE_SUCCESS) 2056 goto fail; 2057 2058 status = ixgbe_get_i2c_ack(hw); 2059 if (status != IXGBE_SUCCESS) 2060 goto fail; 2061 2062 status = ixgbe_clock_out_i2c_byte(hw, data); 2063 if (status != IXGBE_SUCCESS) 2064 goto fail; 2065 2066 status = ixgbe_get_i2c_ack(hw); 2067 if (status != IXGBE_SUCCESS) 2068 goto fail; 2069 2070 ixgbe_i2c_stop(hw); 2071 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2072 return IXGBE_SUCCESS; 2073 2074 fail: 2075 ixgbe_i2c_bus_clear(hw); 2076 retry++; 2077 if (retry < max_retry) 2078 DEBUGOUT("I2C byte write error - Retrying.\n"); 2079 else 2080 DEBUGOUT("I2C byte write error.\n"); 2081 } while (retry < max_retry); 2082 2083 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2084 2085 write_byte_out: 2086 return status; 2087 } 2088 2089 /** 2090 * ixgbe_i2c_start - Sets I2C start condition 2091 * @hw: pointer to hardware structure 2092 * 2093 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2094 * Set bit-bang mode on X550 hardware. 2095 **/ 2096 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2097 { 2098 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2099 2100 DEBUGFUNC("ixgbe_i2c_start"); 2101 2102 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2103 2104 /* Start condition must begin with data and clock high */ 2105 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2106 ixgbe_raise_i2c_clk(hw, &i2cctl); 2107 2108 /* Setup time for start condition (4.7us) */ 2109 usec_delay(IXGBE_I2C_T_SU_STA); 2110 2111 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2112 2113 /* Hold time for start condition (4us) */ 2114 usec_delay(IXGBE_I2C_T_HD_STA); 2115 2116 ixgbe_lower_i2c_clk(hw, &i2cctl); 2117 2118 /* Minimum low period of clock is 4.7 us */ 2119 usec_delay(IXGBE_I2C_T_LOW); 2120 2121 } 2122 2123 /** 2124 * ixgbe_i2c_stop - Sets I2C stop condition 2125 * @hw: pointer to hardware structure 2126 * 2127 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2128 * Disables bit-bang mode and negates data output enable on X550 2129 * hardware. 2130 **/ 2131 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2132 { 2133 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2134 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2135 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2136 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2137 2138 DEBUGFUNC("ixgbe_i2c_stop"); 2139 2140 /* Stop condition must begin with data low and clock high */ 2141 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2142 ixgbe_raise_i2c_clk(hw, &i2cctl); 2143 2144 /* Setup time for stop condition (4us) */ 2145 usec_delay(IXGBE_I2C_T_SU_STO); 2146 2147 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2148 2149 /* bus free time between stop and start (4.7us)*/ 2150 usec_delay(IXGBE_I2C_T_BUF); 2151 2152 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2153 i2cctl &= ~bb_en_bit; 2154 i2cctl |= data_oe_bit | clk_oe_bit; 2155 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2156 IXGBE_WRITE_FLUSH(hw); 2157 } 2158 } 2159 2160 /** 2161 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2162 * @hw: pointer to hardware structure 2163 * @data: data byte to clock in 2164 * 2165 * Clocks in one byte data via I2C data/clock 2166 **/ 2167 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2168 { 2169 s32 i; 2170 bool bit = 0; 2171 2172 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2173 2174 *data = 0; 2175 for (i = 7; i >= 0; i--) { 2176 ixgbe_clock_in_i2c_bit(hw, &bit); 2177 *data |= bit << i; 2178 } 2179 2180 return IXGBE_SUCCESS; 2181 } 2182 2183 /** 2184 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2185 * @hw: pointer to hardware structure 2186 * @data: data byte clocked out 2187 * 2188 * Clocks out one byte data via I2C data/clock 2189 **/ 2190 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2191 { 2192 s32 status = IXGBE_SUCCESS; 2193 s32 i; 2194 u32 i2cctl; 2195 bool bit; 2196 2197 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2198 2199 for (i = 7; i >= 0; i--) { 2200 bit = (data >> i) & 0x1; 2201 status = ixgbe_clock_out_i2c_bit(hw, bit); 2202 2203 if (status != IXGBE_SUCCESS) 2204 break; 2205 } 2206 2207 /* Release SDA line (set high) */ 2208 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2209 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2210 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2211 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2212 IXGBE_WRITE_FLUSH(hw); 2213 2214 return status; 2215 } 2216 2217 /** 2218 * ixgbe_get_i2c_ack - Polls for I2C ACK 2219 * @hw: pointer to hardware structure 2220 * 2221 * Clocks in/out one bit via I2C data/clock 2222 **/ 2223 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2224 { 2225 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2226 s32 status = IXGBE_SUCCESS; 2227 u32 i = 0; 2228 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2229 u32 timeout = 10; 2230 bool ack = 1; 2231 2232 DEBUGFUNC("ixgbe_get_i2c_ack"); 2233 2234 if (data_oe_bit) { 2235 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2236 i2cctl |= data_oe_bit; 2237 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2238 IXGBE_WRITE_FLUSH(hw); 2239 } 2240 ixgbe_raise_i2c_clk(hw, &i2cctl); 2241 2242 /* Minimum high period of clock is 4us */ 2243 usec_delay(IXGBE_I2C_T_HIGH); 2244 2245 /* Poll for ACK. Note that ACK in I2C spec is 2246 * transition from 1 to 0 */ 2247 for (i = 0; i < timeout; i++) { 2248 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2249 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2250 2251 usec_delay(1); 2252 if (!ack) 2253 break; 2254 } 2255 2256 if (ack) { 2257 DEBUGOUT("I2C ack was not received.\n"); 2258 status = IXGBE_ERR_I2C; 2259 } 2260 2261 ixgbe_lower_i2c_clk(hw, &i2cctl); 2262 2263 /* Minimum low period of clock is 4.7 us */ 2264 usec_delay(IXGBE_I2C_T_LOW); 2265 2266 return status; 2267 } 2268 2269 /** 2270 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2271 * @hw: pointer to hardware structure 2272 * @data: read data value 2273 * 2274 * Clocks in one bit via I2C data/clock 2275 **/ 2276 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2277 { 2278 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2279 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2280 2281 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2282 2283 if (data_oe_bit) { 2284 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2285 i2cctl |= data_oe_bit; 2286 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2287 IXGBE_WRITE_FLUSH(hw); 2288 } 2289 ixgbe_raise_i2c_clk(hw, &i2cctl); 2290 2291 /* Minimum high period of clock is 4us */ 2292 usec_delay(IXGBE_I2C_T_HIGH); 2293 2294 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2295 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2296 2297 ixgbe_lower_i2c_clk(hw, &i2cctl); 2298 2299 /* Minimum low period of clock is 4.7 us */ 2300 usec_delay(IXGBE_I2C_T_LOW); 2301 2302 return IXGBE_SUCCESS; 2303 } 2304 2305 /** 2306 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2307 * @hw: pointer to hardware structure 2308 * @data: data value to write 2309 * 2310 * Clocks out one bit via I2C data/clock 2311 **/ 2312 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2313 { 2314 s32 status; 2315 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2316 2317 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2318 2319 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2320 if (status == IXGBE_SUCCESS) { 2321 ixgbe_raise_i2c_clk(hw, &i2cctl); 2322 2323 /* Minimum high period of clock is 4us */ 2324 usec_delay(IXGBE_I2C_T_HIGH); 2325 2326 ixgbe_lower_i2c_clk(hw, &i2cctl); 2327 2328 /* Minimum low period of clock is 4.7 us. 2329 * This also takes care of the data hold time. 2330 */ 2331 usec_delay(IXGBE_I2C_T_LOW); 2332 } else { 2333 status = IXGBE_ERR_I2C; 2334 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2335 "I2C data was not set to %X\n", data); 2336 } 2337 2338 return status; 2339 } 2340 2341 /** 2342 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2343 * @hw: pointer to hardware structure 2344 * @i2cctl: Current value of I2CCTL register 2345 * 2346 * Raises the I2C clock line '0'->'1' 2347 * Negates the I2C clock output enable on X550 hardware. 2348 **/ 2349 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2350 { 2351 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2352 u32 i = 0; 2353 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2354 u32 i2cctl_r = 0; 2355 2356 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2357 2358 if (clk_oe_bit) { 2359 *i2cctl |= clk_oe_bit; 2360 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2361 } 2362 2363 for (i = 0; i < timeout; i++) { 2364 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2365 2366 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2367 IXGBE_WRITE_FLUSH(hw); 2368 /* SCL rise time (1000ns) */ 2369 usec_delay(IXGBE_I2C_T_RISE); 2370 2371 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2372 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2373 break; 2374 } 2375 } 2376 2377 /** 2378 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2379 * @hw: pointer to hardware structure 2380 * @i2cctl: Current value of I2CCTL register 2381 * 2382 * Lowers the I2C clock line '1'->'0' 2383 * Asserts the I2C clock output enable on X550 hardware. 2384 **/ 2385 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2386 { 2387 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2388 2389 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2390 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2391 2392 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2393 IXGBE_WRITE_FLUSH(hw); 2394 2395 /* SCL fall time (300ns) */ 2396 usec_delay(IXGBE_I2C_T_FALL); 2397 } 2398 2399 /** 2400 * ixgbe_set_i2c_data - Sets the I2C data bit 2401 * @hw: pointer to hardware structure 2402 * @i2cctl: Current value of I2CCTL register 2403 * @data: I2C data value (0 or 1) to set 2404 * 2405 * Sets the I2C data bit 2406 * Asserts the I2C data output enable on X550 hardware. 2407 **/ 2408 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2409 { 2410 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2411 s32 status = IXGBE_SUCCESS; 2412 2413 DEBUGFUNC("ixgbe_set_i2c_data"); 2414 2415 if (data) 2416 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2417 else 2418 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2419 *i2cctl &= ~data_oe_bit; 2420 2421 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2422 IXGBE_WRITE_FLUSH(hw); 2423 2424 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2425 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2426 2427 if (!data) /* Can't verify data in this case */ 2428 return IXGBE_SUCCESS; 2429 if (data_oe_bit) { 2430 *i2cctl |= data_oe_bit; 2431 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2432 IXGBE_WRITE_FLUSH(hw); 2433 } 2434 2435 /* Verify data was set correctly */ 2436 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2437 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2438 status = IXGBE_ERR_I2C; 2439 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2440 "Error - I2C data was not set to %X.\n", 2441 data); 2442 } 2443 2444 return status; 2445 } 2446 2447 /** 2448 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2449 * @hw: pointer to hardware structure 2450 * @i2cctl: Current value of I2CCTL register 2451 * 2452 * Returns the I2C data bit value 2453 * Negates the I2C data output enable on X550 hardware. 2454 **/ 2455 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2456 { 2457 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2458 bool data; 2459 2460 DEBUGFUNC("ixgbe_get_i2c_data"); 2461 2462 if (data_oe_bit) { 2463 *i2cctl |= data_oe_bit; 2464 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2465 IXGBE_WRITE_FLUSH(hw); 2466 usec_delay(IXGBE_I2C_T_FALL); 2467 } 2468 2469 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2470 data = 1; 2471 else 2472 data = 0; 2473 2474 return data; 2475 } 2476 2477 /** 2478 * ixgbe_i2c_bus_clear - Clears the I2C bus 2479 * @hw: pointer to hardware structure 2480 * 2481 * Clears the I2C bus by sending nine clock pulses. 2482 * Used when data line is stuck low. 2483 **/ 2484 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2485 { 2486 u32 i2cctl; 2487 u32 i; 2488 2489 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2490 2491 ixgbe_i2c_start(hw); 2492 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2493 2494 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2495 2496 for (i = 0; i < 9; i++) { 2497 ixgbe_raise_i2c_clk(hw, &i2cctl); 2498 2499 /* Min high period of clock is 4us */ 2500 usec_delay(IXGBE_I2C_T_HIGH); 2501 2502 ixgbe_lower_i2c_clk(hw, &i2cctl); 2503 2504 /* Min low period of clock is 4.7us*/ 2505 usec_delay(IXGBE_I2C_T_LOW); 2506 } 2507 2508 ixgbe_i2c_start(hw); 2509 2510 /* Put the i2c bus back to default state */ 2511 ixgbe_i2c_stop(hw); 2512 } 2513 2514 /** 2515 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2516 * @hw: pointer to hardware structure 2517 * 2518 * Checks if the LASI temp alarm status was triggered due to overtemp 2519 **/ 2520 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2521 { 2522 s32 status = IXGBE_SUCCESS; 2523 u16 phy_data = 0; 2524 2525 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2526 2527 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2528 goto out; 2529 2530 /* Check that the LASI temp alarm status was triggered */ 2531 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2532 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2533 2534 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2535 goto out; 2536 2537 status = IXGBE_ERR_OVERTEMP; 2538 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2539 out: 2540 return status; 2541 } 2542 2543 /** 2544 * ixgbe_set_copper_phy_power - Control power for copper phy 2545 * @hw: pointer to hardware structure 2546 * @on: TRUE for on, FALSE for off 2547 */ 2548 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2549 { 2550 u32 status; 2551 u16 reg; 2552 2553 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2554 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2555 ®); 2556 if (status) 2557 return status; 2558 2559 if (on) { 2560 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2561 } else { 2562 if (ixgbe_check_reset_blocked(hw)) 2563 return 0; 2564 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2565 } 2566 2567 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2568 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2569 reg); 2570 return status; 2571 } 2572