1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53 /** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61 { 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68 } 69 70 /** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78 { 79 ixgbe_clock_in_i2c_byte(hw, byte); 80 /* ACK */ 81 return ixgbe_clock_out_i2c_bit(hw, false); 82 } 83 84 /** 85 * ixgbe_ones_comp_byte_add - Perform one's complement addition 86 * @add1: addend 1 87 * @add2: addend 2 88 * 89 * Returns one's complement 8-bit sum. 90 */ 91 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 92 { 93 u16 sum = add1 + add2; 94 95 sum = (sum & 0xFF) + (sum >> 8); 96 return sum & 0xFF; 97 } 98 99 /** 100 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 101 * @hw: pointer to the hardware structure 102 * @addr: I2C bus address to read from 103 * @reg: I2C device register to read from 104 * @val: pointer to location to receive read value 105 * @lock: true if to take and release semaphore 106 * 107 * Returns an error code on error. 108 */ 109 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 110 u16 *val, bool lock) 111 { 112 u32 swfw_mask = hw->phy.phy_semaphore_mask; 113 int max_retry = 3; 114 int retry = 0; 115 u8 csum_byte; 116 u8 high_bits; 117 u8 low_bits; 118 u8 reg_high; 119 u8 csum; 120 121 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 122 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 123 csum = ~csum; 124 do { 125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 126 return IXGBE_ERR_SWFW_SYNC; 127 ixgbe_i2c_start(hw); 128 /* Device Address and write indication */ 129 if (ixgbe_out_i2c_byte_ack(hw, addr)) 130 goto fail; 131 /* Write bits 14:8 */ 132 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 133 goto fail; 134 /* Write bits 7:0 */ 135 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 136 goto fail; 137 /* Write csum */ 138 if (ixgbe_out_i2c_byte_ack(hw, csum)) 139 goto fail; 140 /* Re-start condition */ 141 ixgbe_i2c_start(hw); 142 /* Device Address and read indication */ 143 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 144 goto fail; 145 /* Get upper bits */ 146 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 147 goto fail; 148 /* Get low bits */ 149 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 150 goto fail; 151 /* Get csum */ 152 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 153 /* NACK */ 154 if (ixgbe_clock_out_i2c_bit(hw, false)) 155 goto fail; 156 ixgbe_i2c_stop(hw); 157 if (lock) 158 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 159 *val = (high_bits << 8) | low_bits; 160 return 0; 161 162 fail: 163 ixgbe_i2c_bus_clear(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 if (retry < max_retry) 167 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 168 else 169 DEBUGOUT("I2C byte read combined error.\n"); 170 retry++; 171 } while (retry <= max_retry); 172 173 return IXGBE_ERR_I2C; 174 } 175 176 /** 177 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 178 * @hw: pointer to the hardware structure 179 * @addr: I2C bus address to write to 180 * @reg: I2C device register to write to 181 * @val: value to write 182 * @lock: true if to take and release semaphore 183 * 184 * Returns an error code on error. 185 */ 186 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 187 u16 val, bool lock) 188 { 189 u32 swfw_mask = hw->phy.phy_semaphore_mask; 190 int max_retry = 1; 191 int retry = 0; 192 u8 reg_high; 193 u8 csum; 194 195 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 196 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 197 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 198 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 199 csum = ~csum; 200 do { 201 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 202 return IXGBE_ERR_SWFW_SYNC; 203 ixgbe_i2c_start(hw); 204 /* Device Address and write indication */ 205 if (ixgbe_out_i2c_byte_ack(hw, addr)) 206 goto fail; 207 /* Write bits 14:8 */ 208 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 209 goto fail; 210 /* Write bits 7:0 */ 211 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 212 goto fail; 213 /* Write data 15:8 */ 214 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 215 goto fail; 216 /* Write data 7:0 */ 217 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 218 goto fail; 219 /* Write csum */ 220 if (ixgbe_out_i2c_byte_ack(hw, csum)) 221 goto fail; 222 ixgbe_i2c_stop(hw); 223 if (lock) 224 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 225 return 0; 226 227 fail: 228 ixgbe_i2c_bus_clear(hw); 229 if (lock) 230 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 231 if (retry < max_retry) 232 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 233 else 234 DEBUGOUT("I2C byte write combined error.\n"); 235 retry++; 236 } while (retry <= max_retry); 237 238 return IXGBE_ERR_I2C; 239 } 240 241 /** 242 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 243 * @hw: pointer to the hardware structure 244 * 245 * Initialize the function pointers. 246 **/ 247 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 248 { 249 struct ixgbe_phy_info *phy = &hw->phy; 250 251 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 252 253 /* PHY */ 254 phy->ops.identify = ixgbe_identify_phy_generic; 255 phy->ops.reset = ixgbe_reset_phy_generic; 256 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 257 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 260 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 261 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 262 phy->ops.check_link = NULL; 263 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 264 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 265 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 266 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 267 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 268 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 269 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 270 phy->ops.identify_sfp = ixgbe_identify_module_generic; 271 phy->sfp_type = ixgbe_sfp_type_unknown; 272 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 273 phy->ops.write_i2c_byte_unlocked = 274 ixgbe_write_i2c_byte_generic_unlocked; 275 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 276 return IXGBE_SUCCESS; 277 } 278 279 /** 280 * ixgbe_probe_phy - Probe a single address for a PHY 281 * @hw: pointer to hardware structure 282 * @phy_addr: PHY address to probe 283 * 284 * Returns true if PHY found 285 */ 286 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 287 { 288 u16 ext_ability = 0; 289 290 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 291 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 292 phy_addr); 293 return false; 294 } 295 296 if (ixgbe_get_phy_id(hw)) 297 return false; 298 299 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 300 301 if (hw->phy.type == ixgbe_phy_unknown) { 302 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 303 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 304 if (ext_ability & 305 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 306 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 307 hw->phy.type = ixgbe_phy_cu_unknown; 308 else 309 hw->phy.type = ixgbe_phy_generic; 310 } 311 312 return true; 313 } 314 315 /** 316 * ixgbe_identify_phy_generic - Get physical layer module 317 * @hw: pointer to hardware structure 318 * 319 * Determines the physical layer module found on the current adapter. 320 **/ 321 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 322 { 323 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 324 u16 phy_addr; 325 326 DEBUGFUNC("ixgbe_identify_phy_generic"); 327 328 if (!hw->phy.phy_semaphore_mask) { 329 if (hw->bus.lan_id) 330 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 331 else 332 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 333 } 334 335 if (hw->phy.type != ixgbe_phy_unknown) 336 return IXGBE_SUCCESS; 337 338 if (hw->phy.nw_mng_if_sel) { 339 phy_addr = (hw->phy.nw_mng_if_sel & 340 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 342 if (ixgbe_probe_phy(hw, phy_addr)) 343 return IXGBE_SUCCESS; 344 else 345 return IXGBE_ERR_PHY_ADDR_INVALID; 346 } 347 348 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 349 if (ixgbe_probe_phy(hw, phy_addr)) { 350 status = IXGBE_SUCCESS; 351 break; 352 } 353 } 354 355 /* Certain media types do not have a phy so an address will not 356 * be found and the code will take this path. Caller has to 357 * decide if it is an error or not. 358 */ 359 if (status != IXGBE_SUCCESS) 360 hw->phy.addr = 0; 361 362 return status; 363 } 364 365 /** 366 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 367 * @hw: pointer to the hardware structure 368 * 369 * This function checks the MMNGC.MNG_VETO bit to see if there are 370 * any constraints on link from manageability. For MAC's that don't 371 * have this bit just return faluse since the link can not be blocked 372 * via this method. 373 **/ 374 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 375 { 376 u32 mmngc; 377 378 DEBUGFUNC("ixgbe_check_reset_blocked"); 379 380 /* If we don't have this bit, it can't be blocking */ 381 if (hw->mac.type == ixgbe_mac_82598EB) 382 return false; 383 384 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 385 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 386 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 387 "MNG_VETO bit detected.\n"); 388 return true; 389 } 390 391 return false; 392 } 393 394 /** 395 * ixgbe_validate_phy_addr - Determines phy address is valid 396 * @hw: pointer to hardware structure 397 * @phy_addr: PHY address 398 * 399 **/ 400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 401 { 402 u16 phy_id = 0; 403 bool valid = false; 404 405 DEBUGFUNC("ixgbe_validate_phy_addr"); 406 407 hw->phy.addr = phy_addr; 408 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 409 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 410 411 if (phy_id != 0xFFFF && phy_id != 0x0) 412 valid = true; 413 414 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 415 416 return valid; 417 } 418 419 /** 420 * ixgbe_get_phy_id - Get the phy type 421 * @hw: pointer to hardware structure 422 * 423 **/ 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 425 { 426 u32 status; 427 u16 phy_id_high = 0; 428 u16 phy_id_low = 0; 429 430 DEBUGFUNC("ixgbe_get_phy_id"); 431 432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 433 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 434 &phy_id_high); 435 436 if (status == IXGBE_SUCCESS) { 437 hw->phy.id = (u32)phy_id_high << 16; 438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 439 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 440 &phy_id_low); 441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 443 } 444 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 445 phy_id_high, phy_id_low); 446 447 return status; 448 } 449 450 /** 451 * ixgbe_get_phy_type_from_id - Get the phy type 452 * @phy_id: PHY ID information 453 * 454 **/ 455 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 456 { 457 enum ixgbe_phy_type phy_type; 458 459 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 460 461 switch (phy_id) { 462 case TN1010_PHY_ID: 463 phy_type = ixgbe_phy_tn; 464 break; 465 case X550_PHY_ID: 466 case X550_PHY_ID2: 467 case X550_PHY_ID3: 468 case X540_PHY_ID: 469 phy_type = ixgbe_phy_aq; 470 break; 471 case QT2022_PHY_ID: 472 phy_type = ixgbe_phy_qt; 473 break; 474 case ATH_PHY_ID: 475 phy_type = ixgbe_phy_nl; 476 break; 477 case X557_PHY_ID: 478 case X557_PHY_ID2: 479 phy_type = ixgbe_phy_x550em_ext_t; 480 break; 481 case IXGBE_M88E1500_E_PHY_ID: 482 case IXGBE_M88E1543_E_PHY_ID: 483 phy_type = ixgbe_phy_ext_1g_t; 484 break; 485 default: 486 phy_type = ixgbe_phy_unknown; 487 break; 488 } 489 return phy_type; 490 } 491 492 /** 493 * ixgbe_reset_phy_generic - Performs a PHY reset 494 * @hw: pointer to hardware structure 495 **/ 496 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 497 { 498 u32 i; 499 u16 ctrl = 0; 500 s32 status = IXGBE_SUCCESS; 501 502 DEBUGFUNC("ixgbe_reset_phy_generic"); 503 504 if (hw->phy.type == ixgbe_phy_unknown) 505 status = ixgbe_identify_phy_generic(hw); 506 507 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 508 goto out; 509 510 /* Don't reset PHY if it's shut down due to overtemp. */ 511 if (!hw->phy.reset_if_overtemp && 512 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 513 goto out; 514 515 /* Blocked by MNG FW so bail */ 516 if (ixgbe_check_reset_blocked(hw)) 517 goto out; 518 519 /* 520 * Perform soft PHY reset to the PHY_XS. 521 * This will cause a soft reset to the PHY 522 */ 523 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 524 IXGBE_MDIO_PHY_XS_DEV_TYPE, 525 IXGBE_MDIO_PHY_XS_RESET); 526 527 /* 528 * Poll for reset bit to self-clear indicating reset is complete. 529 * Some PHYs could take up to 3 seconds to complete and need about 530 * 1.7 usec delay after the reset is complete. 531 */ 532 for (i = 0; i < 30; i++) { 533 msec_delay(100); 534 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 535 status = hw->phy.ops.read_reg(hw, 536 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 537 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 538 &ctrl); 539 if (status != IXGBE_SUCCESS) 540 return status; 541 542 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 543 usec_delay(2); 544 break; 545 } 546 } else { 547 status = hw->phy.ops.read_reg(hw, 548 IXGBE_MDIO_PHY_XS_CONTROL, 549 IXGBE_MDIO_PHY_XS_DEV_TYPE, 550 &ctrl); 551 if (status != IXGBE_SUCCESS) 552 return status; 553 554 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 555 usec_delay(2); 556 break; 557 } 558 } 559 } 560 561 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 562 status = IXGBE_ERR_RESET_FAILED; 563 ERROR_REPORT1(IXGBE_ERROR_POLLING, 564 "PHY reset polling failed to complete.\n"); 565 } 566 567 out: 568 return status; 569 } 570 571 /** 572 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY 573 * @hw: pointer to hardware structure 574 **/ 575 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw) 576 { 577 u16 autoneg_reg; 578 579 /* Check if PHY reset is blocked by MNG FW */ 580 if (ixgbe_check_reset_blocked(hw)) 581 return; 582 583 /* Restart PHY auto-negotiation. */ 584 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 585 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 586 autoneg_reg |= IXGBE_MII_RESTART; 587 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 589 } 590 591 /** 592 * ixgbe_read_phy_reg_mdi - Reads a value from a specified PHY register without 593 * the SWFW lock 594 * @hw: pointer to hardware structure 595 * @reg_addr: 32 bit address of PHY register to read 596 * @device_type: 5 bit device type 597 * @phy_data: Pointer to read data from PHY register 598 **/ 599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 600 u16 *phy_data) 601 { 602 u32 i, data, command; 603 604 /* Setup and write the address cycle command */ 605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 608 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 609 610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 611 612 /* 613 * Check every 10 usec to see if the address cycle completed. 614 * The MDI Command bit will clear when the operation is 615 * complete 616 */ 617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 618 usec_delay(10); 619 620 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 622 break; 623 } 624 625 626 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 627 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 628 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 629 return IXGBE_ERR_PHY; 630 } 631 632 /* 633 * Address cycle complete, setup and write the read 634 * command 635 */ 636 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 637 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 638 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 639 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 640 641 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 642 643 /* 644 * Check every 10 usec to see if the address cycle 645 * completed. The MDI Command bit will clear when the 646 * operation is complete 647 */ 648 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 649 usec_delay(10); 650 651 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 652 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 653 break; 654 } 655 656 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 657 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 658 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 659 return IXGBE_ERR_PHY; 660 } 661 662 /* 663 * Read operation is complete. Get the data 664 * from MSRWD 665 */ 666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 668 *phy_data = (u16)(data); 669 670 return IXGBE_SUCCESS; 671 } 672 673 /** 674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 675 * using the SWFW lock - this function is needed in most cases 676 * @hw: pointer to hardware structure 677 * @reg_addr: 32 bit address of PHY register to read 678 * @device_type: 5 bit device type 679 * @phy_data: Pointer to read data from PHY register 680 **/ 681 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 682 u32 device_type, u16 *phy_data) 683 { 684 s32 status; 685 u32 gssr = hw->phy.phy_semaphore_mask; 686 687 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 688 689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 690 return IXGBE_ERR_SWFW_SYNC; 691 692 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 693 694 hw->mac.ops.release_swfw_sync(hw, gssr); 695 696 return status; 697 } 698 699 /** 700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 701 * without SWFW lock 702 * @hw: pointer to hardware structure 703 * @reg_addr: 32 bit PHY register to write 704 * @device_type: 5 bit device type 705 * @phy_data: Data to write to the PHY register 706 **/ 707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 708 u32 device_type, u16 phy_data) 709 { 710 u32 i, command; 711 712 /* Put the data in the MDI single read and write data register*/ 713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 714 715 /* Setup and write the address cycle command */ 716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 720 721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 722 723 /* 724 * Check every 10 usec to see if the address cycle completed. 725 * The MDI Command bit will clear when the operation is 726 * complete 727 */ 728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 729 usec_delay(10); 730 731 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 733 break; 734 } 735 736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 738 return IXGBE_ERR_PHY; 739 } 740 741 /* 742 * Address cycle complete, setup and write the write 743 * command 744 */ 745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 749 750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 751 752 /* 753 * Check every 10 usec to see if the address cycle 754 * completed. The MDI Command bit will clear when the 755 * operation is complete 756 */ 757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 758 usec_delay(10); 759 760 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 762 break; 763 } 764 765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 767 return IXGBE_ERR_PHY; 768 } 769 770 return IXGBE_SUCCESS; 771 } 772 773 /** 774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 775 * using SWFW lock- this function is needed in most cases 776 * @hw: pointer to hardware structure 777 * @reg_addr: 32 bit PHY register to write 778 * @device_type: 5 bit device type 779 * @phy_data: Data to write to the PHY register 780 **/ 781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 782 u32 device_type, u16 phy_data) 783 { 784 s32 status; 785 u32 gssr = hw->phy.phy_semaphore_mask; 786 787 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 788 789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 790 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 791 phy_data); 792 hw->mac.ops.release_swfw_sync(hw, gssr); 793 } else { 794 status = IXGBE_ERR_SWFW_SYNC; 795 } 796 797 return status; 798 } 799 800 /** 801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 802 * @hw: pointer to hardware structure 803 * 804 * Restart auto-negotiation and PHY and waits for completion. 805 **/ 806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 807 { 808 s32 status = IXGBE_SUCCESS; 809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 810 bool autoneg = false; 811 ixgbe_link_speed speed; 812 813 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 814 815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 816 817 /* Set or unset auto-negotiation 10G advertisement */ 818 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 820 &autoneg_reg); 821 822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 824 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 826 827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 829 autoneg_reg); 830 831 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 832 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 833 &autoneg_reg); 834 835 if (hw->mac.type == ixgbe_mac_X550) { 836 /* Set or unset auto-negotiation 5G advertisement */ 837 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 839 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 840 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 841 842 /* Set or unset auto-negotiation 2.5G advertisement */ 843 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 844 if ((hw->phy.autoneg_advertised & 845 IXGBE_LINK_SPEED_2_5GB_FULL) && 846 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 847 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 848 } 849 850 /* Set or unset auto-negotiation 1G advertisement */ 851 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 853 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 854 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 855 856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 858 autoneg_reg); 859 860 /* Set or unset auto-negotiation 100M advertisement */ 861 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 863 &autoneg_reg); 864 865 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 866 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 867 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 868 (speed & IXGBE_LINK_SPEED_100_FULL)) 869 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 870 871 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 873 autoneg_reg); 874 875 ixgbe_restart_auto_neg(hw); 876 return status; 877 } 878 879 /** 880 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 881 * @hw: pointer to hardware structure 882 * @speed: new link speed 883 * @autoneg_wait_to_complete: unused 884 **/ 885 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 886 ixgbe_link_speed speed, 887 bool autoneg_wait_to_complete) 888 { 889 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 890 891 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 892 893 /* 894 * Clear autoneg_advertised and set new values based on input link 895 * speed. 896 */ 897 hw->phy.autoneg_advertised = 0; 898 899 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 901 902 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 904 905 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 907 908 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 910 911 if (speed & IXGBE_LINK_SPEED_100_FULL) 912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 913 914 if (speed & IXGBE_LINK_SPEED_10_FULL) 915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 916 917 /* Setup link based on the new speed settings */ 918 ixgbe_setup_phy_link(hw); 919 920 return IXGBE_SUCCESS; 921 } 922 923 /** 924 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 925 * @hw: pointer to hardware structure 926 * 927 * Determines the supported link capabilities by reading the PHY auto 928 * negotiation register. 929 **/ 930 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 931 { 932 s32 status; 933 u16 speed_ability; 934 935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 936 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 937 &speed_ability); 938 if (status) 939 return status; 940 941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 945 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 947 948 switch (hw->mac.type) { 949 case ixgbe_mac_X550: 950 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 951 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 952 break; 953 case ixgbe_mac_X550EM_x: 954 case ixgbe_mac_X550EM_a: 955 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 956 break; 957 default: 958 break; 959 } 960 961 return status; 962 } 963 964 /** 965 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 966 * @hw: pointer to hardware structure 967 * @speed: pointer to link speed 968 * @autoneg: boolean auto-negotiation value 969 **/ 970 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 971 ixgbe_link_speed *speed, 972 bool *autoneg) 973 { 974 s32 status = IXGBE_SUCCESS; 975 976 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 977 978 *autoneg = true; 979 if (!hw->phy.speeds_supported) 980 status = ixgbe_get_copper_speeds_supported(hw); 981 982 *speed = hw->phy.speeds_supported; 983 return status; 984 } 985 986 /** 987 * ixgbe_check_phy_link_tnx - Determine link and speed status 988 * @hw: pointer to hardware structure 989 * @speed: current link speed 990 * @link_up: true is link is up, false otherwise 991 * 992 * Reads the VS1 register to determine if link is up and the current speed for 993 * the PHY. 994 **/ 995 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 996 bool *link_up) 997 { 998 s32 status = IXGBE_SUCCESS; 999 u32 time_out; 1000 u32 max_time_out = 10; 1001 u16 phy_link = 0; 1002 u16 phy_speed = 0; 1003 u16 phy_data = 0; 1004 1005 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1006 1007 /* Initialize speed and link to default case */ 1008 *link_up = false; 1009 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1010 1011 /* 1012 * Check current speed and link status of the PHY register. 1013 * This is a vendor specific register and may have to 1014 * be changed for other copper PHYs. 1015 */ 1016 for (time_out = 0; time_out < max_time_out; time_out++) { 1017 usec_delay(10); 1018 status = hw->phy.ops.read_reg(hw, 1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1021 &phy_data); 1022 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1023 phy_speed = phy_data & 1024 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1025 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1026 *link_up = true; 1027 if (phy_speed == 1028 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1029 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1030 break; 1031 } 1032 } 1033 1034 return status; 1035 } 1036 1037 /** 1038 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1039 * @hw: pointer to hardware structure 1040 * 1041 * Restart auto-negotiation and PHY and waits for completion. 1042 **/ 1043 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1044 { 1045 s32 status = IXGBE_SUCCESS; 1046 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1047 bool autoneg = false; 1048 ixgbe_link_speed speed; 1049 1050 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1051 1052 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1053 1054 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1055 /* Set or unset auto-negotiation 10G advertisement */ 1056 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1058 &autoneg_reg); 1059 1060 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1061 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1062 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1063 1064 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1065 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1066 autoneg_reg); 1067 } 1068 1069 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1070 /* Set or unset auto-negotiation 1G advertisement */ 1071 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1073 &autoneg_reg); 1074 1075 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1076 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1077 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1078 1079 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1081 autoneg_reg); 1082 } 1083 1084 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1085 /* Set or unset auto-negotiation 100M advertisement */ 1086 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1088 &autoneg_reg); 1089 1090 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1091 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1092 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1093 1094 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1096 autoneg_reg); 1097 } 1098 1099 ixgbe_restart_auto_neg(hw); 1100 return status; 1101 } 1102 1103 /** 1104 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1105 * @hw: pointer to hardware structure 1106 * @firmware_version: pointer to the PHY Firmware Version 1107 **/ 1108 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1109 u16 *firmware_version) 1110 { 1111 s32 status; 1112 1113 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1114 1115 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1116 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1117 firmware_version); 1118 1119 return status; 1120 } 1121 1122 /** 1123 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1124 * @hw: pointer to hardware structure 1125 * @firmware_version: pointer to the PHY Firmware Version 1126 **/ 1127 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1128 u16 *firmware_version) 1129 { 1130 s32 status; 1131 1132 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1133 1134 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1135 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1136 firmware_version); 1137 1138 return status; 1139 } 1140 1141 /** 1142 * ixgbe_reset_phy_nl - Performs a PHY reset 1143 * @hw: pointer to hardware structure 1144 **/ 1145 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1146 { 1147 u16 phy_offset, control, eword, edata, block_crc; 1148 bool end_data = false; 1149 u16 list_offset, data_offset; 1150 u16 phy_data = 0; 1151 s32 ret_val = IXGBE_SUCCESS; 1152 u32 i; 1153 1154 DEBUGFUNC("ixgbe_reset_phy_nl"); 1155 1156 /* Blocked by MNG FW so bail */ 1157 if (ixgbe_check_reset_blocked(hw)) 1158 goto out; 1159 1160 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1161 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1162 1163 /* reset the PHY and poll for completion */ 1164 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1165 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1166 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1167 1168 for (i = 0; i < 100; i++) { 1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1170 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1171 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1172 break; 1173 msec_delay(10); 1174 } 1175 1176 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1177 DEBUGOUT("PHY reset did not complete.\n"); 1178 ret_val = IXGBE_ERR_PHY; 1179 goto out; 1180 } 1181 1182 /* Get init offsets */ 1183 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1184 &data_offset); 1185 if (ret_val != IXGBE_SUCCESS) 1186 goto out; 1187 1188 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1189 data_offset++; 1190 while (!end_data) { 1191 /* 1192 * Read control word from PHY init contents offset 1193 */ 1194 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1195 if (ret_val) 1196 goto err_eeprom; 1197 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1198 IXGBE_CONTROL_SHIFT_NL; 1199 edata = eword & IXGBE_DATA_MASK_NL; 1200 switch (control) { 1201 case IXGBE_DELAY_NL: 1202 data_offset++; 1203 DEBUGOUT1("DELAY: %d MS\n", edata); 1204 msec_delay(edata); 1205 break; 1206 case IXGBE_DATA_NL: 1207 DEBUGOUT("DATA:\n"); 1208 data_offset++; 1209 ret_val = hw->eeprom.ops.read(hw, data_offset, 1210 &phy_offset); 1211 if (ret_val) 1212 goto err_eeprom; 1213 data_offset++; 1214 for (i = 0; i < edata; i++) { 1215 ret_val = hw->eeprom.ops.read(hw, data_offset, 1216 &eword); 1217 if (ret_val) 1218 goto err_eeprom; 1219 hw->phy.ops.write_reg(hw, phy_offset, 1220 IXGBE_TWINAX_DEV, eword); 1221 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1222 phy_offset); 1223 data_offset++; 1224 phy_offset++; 1225 } 1226 break; 1227 case IXGBE_CONTROL_NL: 1228 data_offset++; 1229 DEBUGOUT("CONTROL:\n"); 1230 if (edata == IXGBE_CONTROL_EOL_NL) { 1231 DEBUGOUT("EOL\n"); 1232 end_data = true; 1233 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1234 DEBUGOUT("SOL\n"); 1235 } else { 1236 DEBUGOUT("Bad control value\n"); 1237 ret_val = IXGBE_ERR_PHY; 1238 goto out; 1239 } 1240 break; 1241 default: 1242 DEBUGOUT("Bad control type\n"); 1243 ret_val = IXGBE_ERR_PHY; 1244 goto out; 1245 } 1246 } 1247 1248 out: 1249 return ret_val; 1250 1251 err_eeprom: 1252 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1253 "eeprom read at offset %d failed", data_offset); 1254 return IXGBE_ERR_PHY; 1255 } 1256 1257 /** 1258 * ixgbe_identify_module_generic - Identifies module type 1259 * @hw: pointer to hardware structure 1260 * 1261 * Determines HW type and calls appropriate function. 1262 **/ 1263 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1264 { 1265 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1266 1267 DEBUGFUNC("ixgbe_identify_module_generic"); 1268 1269 switch (hw->mac.ops.get_media_type(hw)) { 1270 case ixgbe_media_type_fiber: 1271 status = ixgbe_identify_sfp_module_generic(hw); 1272 break; 1273 1274 case ixgbe_media_type_fiber_qsfp: 1275 status = ixgbe_identify_qsfp_module_generic(hw); 1276 break; 1277 1278 default: 1279 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1280 status = IXGBE_ERR_SFP_NOT_PRESENT; 1281 break; 1282 } 1283 1284 return status; 1285 } 1286 1287 /** 1288 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1289 * @hw: pointer to hardware structure 1290 * 1291 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1292 **/ 1293 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1294 { 1295 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1296 u32 vendor_oui = 0; 1297 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1298 u8 identifier = 0; 1299 u8 comp_codes_1g = 0; 1300 u8 comp_codes_10g = 0; 1301 u8 oui_bytes[3] = {0, 0, 0}; 1302 u8 cable_tech = 0; 1303 u8 cable_spec = 0; 1304 u8 bitrate_nominal = 0; 1305 u8 sm_length_100m = 0; 1306 u8 sm_length_km = 0; 1307 u8 retries; 1308 u16 enforce_sfp = 0; 1309 bool is_10g_bx = false; 1310 static bool warned_once = false; 1311 1312 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1313 1314 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1315 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1316 status = IXGBE_ERR_SFP_NOT_PRESENT; 1317 goto out; 1318 } 1319 1320 /* LAN ID is needed for I2C access */ 1321 hw->mac.ops.set_lan_id(hw); 1322 1323 /* 1324 * Some SFPs with a microcontroller ACK I2C reads before the data 1325 * backing them is initialized. Retry successfully completed reads 1326 * with invalid identifier values before declaring the module 1327 * unsupported. Failed transactions are retried by the I2C helper. 1328 */ 1329 for (retries = 0; retries < 5; retries++) { 1330 status = hw->phy.ops.read_i2c_eeprom(hw, 1331 IXGBE_SFF_IDENTIFIER, &identifier); 1332 1333 DEBUGOUT2("status %d, SFF identifier 0x%x\n", status, 1334 identifier); 1335 if (status != IXGBE_SUCCESS || 1336 identifier == IXGBE_SFF_IDENTIFIER_SFP) 1337 break; 1338 } 1339 1340 if (status != IXGBE_SUCCESS) 1341 goto err_read_i2c_eeprom; 1342 1343 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1344 hw->phy.type = ixgbe_phy_sfp_unsupported; 1345 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1346 } else { 1347 status = hw->phy.ops.read_i2c_eeprom(hw, 1348 IXGBE_SFF_1GBE_COMP_CODES, 1349 &comp_codes_1g); 1350 1351 if (status != IXGBE_SUCCESS) 1352 goto err_read_i2c_eeprom; 1353 1354 status = hw->phy.ops.read_i2c_eeprom(hw, 1355 IXGBE_SFF_10GBE_COMP_CODES, 1356 &comp_codes_10g); 1357 1358 if (status != IXGBE_SUCCESS) 1359 goto err_read_i2c_eeprom; 1360 status = hw->phy.ops.read_i2c_eeprom(hw, 1361 IXGBE_SFF_CABLE_TECHNOLOGY, 1362 &cable_tech); 1363 1364 if (status != IXGBE_SUCCESS) 1365 goto err_read_i2c_eeprom; 1366 1367 /* 1368 * SFF-8472 identifies 10G-BX by an empty 10G compliance 1369 * byte, a nominal 10.3 GBd rate, and at least 1 km of 1370 * single-mode fiber reach. Resolve that strong signature 1371 * before falling back to the permissive 1G-BX check below. 1372 */ 1373 if (hw->mac.type != ixgbe_mac_82598EB && 1374 comp_codes_10g == 0 && 1375 (comp_codes_1g & (IXGBE_SFF_1GBASET_CAPABLE | 1376 IXGBE_SFF_1GBASESX_CAPABLE | 1377 IXGBE_SFF_1GBASELX_CAPABLE)) == 0 && 1378 (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1379 IXGBE_SFF_DA_ACTIVE_CABLE)) == 0) { 1380 status = hw->phy.ops.read_i2c_eeprom(hw, 1381 IXGBE_SFF_BITRATE_NOMINAL, &bitrate_nominal); 1382 if (status != IXGBE_SUCCESS) 1383 goto err_read_i2c_eeprom; 1384 if (bitrate_nominal == IXGBE_SFF_10G_BX_BITRATE) { 1385 status = hw->phy.ops.read_i2c_eeprom(hw, 1386 IXGBE_SFF_SM_LENGTH_KM, &sm_length_km); 1387 if (status != IXGBE_SUCCESS) 1388 goto err_read_i2c_eeprom; 1389 status = hw->phy.ops.read_i2c_eeprom(hw, 1390 IXGBE_SFF_SM_LENGTH_100M, &sm_length_100m); 1391 if (status != IXGBE_SUCCESS) 1392 goto err_read_i2c_eeprom; 1393 } 1394 is_10g_bx = bitrate_nominal == IXGBE_SFF_10G_BX_BITRATE && 1395 (sm_length_km > 0 || sm_length_100m >= 10); 1396 } 1397 1398 /* ID Module 1399 * ========= 1400 * 0 SFP_DA_CU 1401 * 1 SFP_SR 1402 * 2 SFP_LR 1403 * 3 SFP_DA_CORE0 - 82599-specific 1404 * 4 SFP_DA_CORE1 - 82599-specific 1405 * 5 SFP_SR/LR_CORE0 - 82599-specific 1406 * 6 SFP_SR/LR_CORE1 - 82599-specific 1407 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1408 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1409 * 9 SFP_1g_cu_CORE0 - 82599-specific 1410 * 10 SFP_1g_cu_CORE1 - 82599-specific 1411 * 11 SFP_1g_sx_CORE0 - 82599-specific 1412 * 12 SFP_1g_sx_CORE1 - 82599-specific 1413 */ 1414 if (hw->mac.type == ixgbe_mac_82598EB) { 1415 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1416 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1417 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1418 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1419 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1420 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1421 else 1422 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1423 } else { 1424 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1425 if (hw->bus.lan_id == 0) 1426 hw->phy.sfp_type = 1427 ixgbe_sfp_type_da_cu_core0; 1428 else 1429 hw->phy.sfp_type = 1430 ixgbe_sfp_type_da_cu_core1; 1431 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1432 hw->phy.ops.read_i2c_eeprom( 1433 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1434 &cable_spec); 1435 if (cable_spec & 1436 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1437 if (hw->bus.lan_id == 0) 1438 hw->phy.sfp_type = 1439 ixgbe_sfp_type_da_act_lmt_core0; 1440 else 1441 hw->phy.sfp_type = 1442 ixgbe_sfp_type_da_act_lmt_core1; 1443 } else { 1444 hw->phy.sfp_type = 1445 ixgbe_sfp_type_unknown; 1446 } 1447 } else if (comp_codes_10g & 1448 (IXGBE_SFF_10GBASESR_CAPABLE | 1449 IXGBE_SFF_10GBASELR_CAPABLE)) { 1450 if (hw->bus.lan_id == 0) 1451 hw->phy.sfp_type = 1452 ixgbe_sfp_type_srlr_core0; 1453 else 1454 hw->phy.sfp_type = 1455 ixgbe_sfp_type_srlr_core1; 1456 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1457 if (hw->bus.lan_id == 0) 1458 hw->phy.sfp_type = 1459 ixgbe_sfp_type_1g_cu_core0; 1460 else 1461 hw->phy.sfp_type = 1462 ixgbe_sfp_type_1g_cu_core1; 1463 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1464 if (hw->bus.lan_id == 0) 1465 hw->phy.sfp_type = 1466 ixgbe_sfp_type_1g_sx_core0; 1467 else 1468 hw->phy.sfp_type = 1469 ixgbe_sfp_type_1g_sx_core1; 1470 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1471 if (hw->bus.lan_id == 0) 1472 hw->phy.sfp_type = 1473 ixgbe_sfp_type_1g_lx_core0; 1474 else 1475 hw->phy.sfp_type = 1476 ixgbe_sfp_type_1g_lx_core1; 1477 } else if (is_10g_bx) { 1478 if (hw->bus.lan_id == 0) 1479 hw->phy.sfp_type = 1480 ixgbe_sfp_type_10g_bx_core0; 1481 else 1482 hw->phy.sfp_type = 1483 ixgbe_sfp_type_10g_bx_core1; 1484 } else if (comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) { 1485 if (hw->bus.lan_id == 0) 1486 hw->phy.sfp_type = 1487 ixgbe_sfp_type_1g_bx_core0; 1488 else 1489 hw->phy.sfp_type = 1490 ixgbe_sfp_type_1g_bx_core1; 1491 } else { 1492 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1493 } 1494 } 1495 1496 if (hw->phy.sfp_type != stored_sfp_type) 1497 hw->phy.sfp_setup_needed = true; 1498 1499 /* Determine if the SFP+ PHY is dual speed or not. */ 1500 hw->phy.multispeed_fiber = false; 1501 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1502 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1503 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1504 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)) || 1505 (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) || 1506 (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)) 1507 hw->phy.multispeed_fiber = true; 1508 1509 /* Determine PHY vendor */ 1510 if (hw->phy.type != ixgbe_phy_nl) { 1511 hw->phy.id = identifier; 1512 status = hw->phy.ops.read_i2c_eeprom(hw, 1513 IXGBE_SFF_VENDOR_OUI_BYTE0, 1514 &oui_bytes[0]); 1515 1516 if (status != IXGBE_SUCCESS) 1517 goto err_read_i2c_eeprom; 1518 1519 status = hw->phy.ops.read_i2c_eeprom(hw, 1520 IXGBE_SFF_VENDOR_OUI_BYTE1, 1521 &oui_bytes[1]); 1522 1523 if (status != IXGBE_SUCCESS) 1524 goto err_read_i2c_eeprom; 1525 1526 status = hw->phy.ops.read_i2c_eeprom(hw, 1527 IXGBE_SFF_VENDOR_OUI_BYTE2, 1528 &oui_bytes[2]); 1529 1530 if (status != IXGBE_SUCCESS) 1531 goto err_read_i2c_eeprom; 1532 1533 vendor_oui = 1534 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1535 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1536 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1537 1538 switch (vendor_oui) { 1539 case IXGBE_SFF_VENDOR_OUI_TYCO: 1540 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1541 hw->phy.type = 1542 ixgbe_phy_sfp_passive_tyco; 1543 break; 1544 case IXGBE_SFF_VENDOR_OUI_FTL: 1545 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1546 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1547 else 1548 hw->phy.type = ixgbe_phy_sfp_ftl; 1549 break; 1550 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1551 hw->phy.type = ixgbe_phy_sfp_avago; 1552 break; 1553 case IXGBE_SFF_VENDOR_OUI_INTEL: 1554 hw->phy.type = ixgbe_phy_sfp_intel; 1555 break; 1556 default: 1557 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1558 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1559 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1560 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1561 else 1562 hw->phy.type = ixgbe_phy_sfp_unknown; 1563 break; 1564 } 1565 } 1566 1567 /* Allow any DA cable vendor */ 1568 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1569 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1570 status = IXGBE_SUCCESS; 1571 goto out; 1572 } 1573 1574 /* Verify supported 1G SFP modules */ 1575 if (comp_codes_10g == 0 && 1576 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1577 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1578 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1579 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1580 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1581 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1582 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || 1583 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1 || 1584 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core0 || 1585 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core1)) { 1586 hw->phy.type = ixgbe_phy_sfp_unsupported; 1587 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1588 goto out; 1589 } 1590 1591 /* Anything else 82598-based is supported */ 1592 if (hw->mac.type == ixgbe_mac_82598EB) { 1593 status = IXGBE_SUCCESS; 1594 goto out; 1595 } 1596 1597 ixgbe_get_device_caps(hw, &enforce_sfp); 1598 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1599 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1600 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1601 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1602 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1603 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1604 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1605 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || 1606 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1 || 1607 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core0 || 1608 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core1)) { 1609 /* Make sure we're a supported PHY type */ 1610 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1611 status = IXGBE_SUCCESS; 1612 } else { 1613 if (hw->allow_unsupported_sfp == true) { 1614 if (!warned_once) 1615 EWARN(hw, 1616 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1617 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1618 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1619 warned_once = true; 1620 status = IXGBE_SUCCESS; 1621 } else { 1622 DEBUGOUT 1623 ("SFP+ module not supported\n"); 1624 hw->phy.type = 1625 ixgbe_phy_sfp_unsupported; 1626 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1627 } 1628 } 1629 } else { 1630 status = IXGBE_SUCCESS; 1631 } 1632 } 1633 1634 out: 1635 return status; 1636 1637 err_read_i2c_eeprom: 1638 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1639 if (hw->phy.type != ixgbe_phy_nl) { 1640 hw->phy.id = 0; 1641 hw->phy.type = ixgbe_phy_unknown; 1642 } 1643 return IXGBE_ERR_SFP_NOT_PRESENT; 1644 } 1645 1646 /** 1647 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1648 * @hw: pointer to hardware structure 1649 * 1650 * Determines physical layer capabilities of the current SFP. 1651 */ 1652 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1653 { 1654 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1655 u8 comp_codes_10g = 0; 1656 u8 comp_codes_1g = 0; 1657 1658 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1659 1660 hw->phy.ops.identify_sfp(hw); 1661 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1662 return physical_layer; 1663 if (hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core0 || 1664 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core1) 1665 return IXGBE_PHYSICAL_LAYER_10GBASE_BX; 1666 1667 switch (hw->phy.type) { 1668 case ixgbe_phy_sfp_passive_tyco: 1669 case ixgbe_phy_sfp_passive_unknown: 1670 case ixgbe_phy_qsfp_passive_unknown: 1671 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1672 break; 1673 case ixgbe_phy_sfp_ftl_active: 1674 case ixgbe_phy_sfp_active_unknown: 1675 case ixgbe_phy_qsfp_active_unknown: 1676 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1677 break; 1678 case ixgbe_phy_sfp_avago: 1679 case ixgbe_phy_sfp_ftl: 1680 case ixgbe_phy_sfp_intel: 1681 case ixgbe_phy_sfp_unknown: 1682 hw->phy.ops.read_i2c_eeprom(hw, 1683 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1684 hw->phy.ops.read_i2c_eeprom(hw, 1685 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1686 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1687 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1688 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1689 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1690 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1691 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1692 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1693 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1694 else if (comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) 1695 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1696 break; 1697 case ixgbe_phy_qsfp_intel: 1698 case ixgbe_phy_qsfp_unknown: 1699 hw->phy.ops.read_i2c_eeprom(hw, 1700 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1701 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1702 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1703 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1704 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1705 break; 1706 default: 1707 break; 1708 } 1709 1710 return physical_layer; 1711 } 1712 1713 /** 1714 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1715 * @hw: pointer to hardware structure 1716 * 1717 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1718 **/ 1719 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1720 { 1721 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1722 u32 vendor_oui = 0; 1723 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1724 u8 identifier = 0; 1725 u8 comp_codes_1g = 0; 1726 u8 comp_codes_10g = 0; 1727 u8 oui_bytes[3] = {0, 0, 0}; 1728 u16 enforce_sfp = 0; 1729 u8 connector = 0; 1730 u8 cable_length = 0; 1731 u8 device_tech = 0; 1732 bool active_cable = false; 1733 static bool warned_once = false; 1734 1735 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1736 1737 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1738 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1739 status = IXGBE_ERR_SFP_NOT_PRESENT; 1740 goto out; 1741 } 1742 1743 /* LAN ID is needed for I2C access */ 1744 hw->mac.ops.set_lan_id(hw); 1745 1746 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1747 &identifier); 1748 1749 if (status != IXGBE_SUCCESS) 1750 goto err_read_i2c_eeprom; 1751 1752 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1753 hw->phy.type = ixgbe_phy_sfp_unsupported; 1754 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1755 goto out; 1756 } 1757 1758 hw->phy.id = identifier; 1759 1760 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1761 &comp_codes_10g); 1762 1763 if (status != IXGBE_SUCCESS) 1764 goto err_read_i2c_eeprom; 1765 1766 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1767 &comp_codes_1g); 1768 1769 if (status != IXGBE_SUCCESS) 1770 goto err_read_i2c_eeprom; 1771 1772 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1773 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1774 if (hw->bus.lan_id == 0) 1775 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1776 else 1777 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1778 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1779 IXGBE_SFF_10GBASELR_CAPABLE)) { 1780 if (hw->bus.lan_id == 0) 1781 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1782 else 1783 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1784 } else { 1785 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1786 active_cable = true; 1787 1788 if (!active_cable) { 1789 /* check for active DA cables that pre-date 1790 * SFF-8436 v3.6 */ 1791 hw->phy.ops.read_i2c_eeprom(hw, 1792 IXGBE_SFF_QSFP_CONNECTOR, 1793 &connector); 1794 1795 hw->phy.ops.read_i2c_eeprom(hw, 1796 IXGBE_SFF_QSFP_CABLE_LENGTH, 1797 &cable_length); 1798 1799 hw->phy.ops.read_i2c_eeprom(hw, 1800 IXGBE_SFF_QSFP_DEVICE_TECH, 1801 &device_tech); 1802 1803 if ((connector == 1804 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1805 (cable_length > 0) && 1806 ((device_tech >> 4) == 1807 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1808 active_cable = true; 1809 } 1810 1811 if (active_cable) { 1812 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1813 if (hw->bus.lan_id == 0) 1814 hw->phy.sfp_type = 1815 ixgbe_sfp_type_da_act_lmt_core0; 1816 else 1817 hw->phy.sfp_type = 1818 ixgbe_sfp_type_da_act_lmt_core1; 1819 } else { 1820 /* unsupported module type */ 1821 hw->phy.type = ixgbe_phy_sfp_unsupported; 1822 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1823 goto out; 1824 } 1825 } 1826 1827 if (hw->phy.sfp_type != stored_sfp_type) 1828 hw->phy.sfp_setup_needed = true; 1829 1830 /* Determine if the QSFP+ PHY is dual speed or not. */ 1831 hw->phy.multispeed_fiber = false; 1832 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1833 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1834 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1835 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1836 hw->phy.multispeed_fiber = true; 1837 1838 /* Determine PHY vendor for optical modules */ 1839 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1840 IXGBE_SFF_10GBASELR_CAPABLE)) { 1841 status = hw->phy.ops.read_i2c_eeprom(hw, 1842 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1843 &oui_bytes[0]); 1844 1845 if (status != IXGBE_SUCCESS) 1846 goto err_read_i2c_eeprom; 1847 1848 status = hw->phy.ops.read_i2c_eeprom(hw, 1849 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1850 &oui_bytes[1]); 1851 1852 if (status != IXGBE_SUCCESS) 1853 goto err_read_i2c_eeprom; 1854 1855 status = hw->phy.ops.read_i2c_eeprom(hw, 1856 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1857 &oui_bytes[2]); 1858 1859 if (status != IXGBE_SUCCESS) 1860 goto err_read_i2c_eeprom; 1861 1862 vendor_oui = 1863 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1864 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1865 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1866 1867 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1868 hw->phy.type = ixgbe_phy_qsfp_intel; 1869 else 1870 hw->phy.type = ixgbe_phy_qsfp_unknown; 1871 1872 ixgbe_get_device_caps(hw, &enforce_sfp); 1873 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1874 /* Make sure we're a supported PHY type */ 1875 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1876 status = IXGBE_SUCCESS; 1877 } else { 1878 if (hw->allow_unsupported_sfp == true) { 1879 if (!warned_once) 1880 EWARN(hw, 1881 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1882 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1883 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1884 warned_once = true; 1885 status = IXGBE_SUCCESS; 1886 } else { 1887 DEBUGOUT("QSFP module not supported\n"); 1888 hw->phy.type = 1889 ixgbe_phy_sfp_unsupported; 1890 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1891 } 1892 } 1893 } else { 1894 status = IXGBE_SUCCESS; 1895 } 1896 } 1897 1898 out: 1899 return status; 1900 1901 err_read_i2c_eeprom: 1902 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1903 hw->phy.id = 0; 1904 hw->phy.type = ixgbe_phy_unknown; 1905 1906 return IXGBE_ERR_SFP_NOT_PRESENT; 1907 } 1908 1909 /** 1910 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1911 * @hw: pointer to hardware structure 1912 * @list_offset: offset to the SFP ID list 1913 * @data_offset: offset to the SFP data block 1914 * 1915 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1916 * so it returns the offsets to the phy init sequence block. 1917 **/ 1918 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1919 u16 *list_offset, 1920 u16 *data_offset) 1921 { 1922 u16 sfp_id; 1923 u16 sfp_type = hw->phy.sfp_type; 1924 1925 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1926 1927 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1928 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1929 1930 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1931 return IXGBE_ERR_SFP_NOT_PRESENT; 1932 1933 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1934 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1935 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1936 1937 /* 1938 * Limiting active cables, 10G-BX, and 1G PHYs must be initialized as 1939 * SR modules 1940 */ 1941 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1942 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1943 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1944 sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1945 sfp_type == ixgbe_sfp_type_1g_bx_core0 || 1946 sfp_type == ixgbe_sfp_type_10g_bx_core0) 1947 sfp_type = ixgbe_sfp_type_srlr_core0; 1948 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1949 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1950 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1951 sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1952 sfp_type == ixgbe_sfp_type_1g_bx_core1 || 1953 sfp_type == ixgbe_sfp_type_10g_bx_core1) 1954 sfp_type = ixgbe_sfp_type_srlr_core1; 1955 1956 /* Read offset to PHY init contents */ 1957 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1958 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1959 "eeprom read at offset %d failed", 1960 IXGBE_PHY_INIT_OFFSET_NL); 1961 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1962 } 1963 1964 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1965 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1966 1967 /* Shift offset to first ID word */ 1968 (*list_offset)++; 1969 1970 /* 1971 * Find the matching SFP ID in the EEPROM 1972 * and program the init sequence 1973 */ 1974 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1975 goto err_phy; 1976 1977 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1978 if (sfp_id == sfp_type) { 1979 (*list_offset)++; 1980 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1981 goto err_phy; 1982 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1983 DEBUGOUT("SFP+ module not supported\n"); 1984 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1985 } else { 1986 break; 1987 } 1988 } else { 1989 (*list_offset) += 2; 1990 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1991 goto err_phy; 1992 } 1993 } 1994 1995 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1996 DEBUGOUT("No matching SFP+ module found\n"); 1997 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1998 } 1999 2000 return IXGBE_SUCCESS; 2001 2002 err_phy: 2003 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2004 "eeprom read at offset %d failed", *list_offset); 2005 return IXGBE_ERR_PHY; 2006 } 2007 2008 /** 2009 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 2010 * @hw: pointer to hardware structure 2011 * @byte_offset: EEPROM byte offset to read 2012 * @eeprom_data: value read 2013 * 2014 * Performs byte read operation to SFP module's EEPROM over I2C interface. 2015 **/ 2016 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2017 u8 *eeprom_data) 2018 { 2019 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 2020 2021 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2022 IXGBE_I2C_EEPROM_DEV_ADDR, 2023 eeprom_data); 2024 } 2025 2026 /** 2027 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2028 * @hw: pointer to hardware structure 2029 * @byte_offset: byte offset at address 0xA2 2030 * @sff8472_data: value read 2031 * 2032 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2033 **/ 2034 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2035 u8 *sff8472_data) 2036 { 2037 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2038 IXGBE_I2C_EEPROM_DEV_ADDR2, 2039 sff8472_data); 2040 } 2041 2042 /** 2043 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2044 * @hw: pointer to hardware structure 2045 * @byte_offset: EEPROM byte offset to write 2046 * @eeprom_data: value to write 2047 * 2048 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2049 **/ 2050 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2051 u8 eeprom_data) 2052 { 2053 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2054 2055 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2056 IXGBE_I2C_EEPROM_DEV_ADDR, 2057 eeprom_data); 2058 } 2059 2060 /** 2061 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 2062 * @hw: pointer to hardware structure 2063 * @offset: eeprom offset to be read 2064 * @addr: I2C address to be read 2065 */ 2066 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2067 { 2068 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2069 offset == IXGBE_SFF_IDENTIFIER && 2070 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2071 return true; 2072 return false; 2073 } 2074 2075 /** 2076 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2077 * @hw: pointer to hardware structure 2078 * @byte_offset: byte offset to read 2079 * @dev_addr: address to read from 2080 * @data: value read 2081 * @lock: true if to take and release semaphore 2082 * 2083 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2084 * a specified device address. 2085 **/ 2086 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2087 u8 dev_addr, u8 *data, bool lock) 2088 { 2089 s32 status; 2090 u32 max_retry = 10; 2091 u32 retry = 0; 2092 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2093 bool nack = 1; 2094 *data = 0; 2095 2096 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2097 2098 if (hw->mac.type >= ixgbe_mac_X550) 2099 max_retry = 3; 2100 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2101 max_retry = IXGBE_SFP_DETECT_RETRIES; 2102 2103 do { 2104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2105 return IXGBE_ERR_SWFW_SYNC; 2106 2107 ixgbe_i2c_start(hw); 2108 2109 /* Device Address and write indication */ 2110 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2111 if (status != IXGBE_SUCCESS) 2112 goto fail; 2113 2114 status = ixgbe_get_i2c_ack(hw); 2115 if (status != IXGBE_SUCCESS) 2116 goto fail; 2117 2118 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2119 if (status != IXGBE_SUCCESS) 2120 goto fail; 2121 2122 status = ixgbe_get_i2c_ack(hw); 2123 if (status != IXGBE_SUCCESS) 2124 goto fail; 2125 2126 ixgbe_i2c_start(hw); 2127 2128 /* Device Address and read indication */ 2129 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2130 if (status != IXGBE_SUCCESS) 2131 goto fail; 2132 2133 status = ixgbe_get_i2c_ack(hw); 2134 if (status != IXGBE_SUCCESS) 2135 goto fail; 2136 2137 ixgbe_clock_in_i2c_byte(hw, data); 2138 2139 status = ixgbe_clock_out_i2c_bit(hw, nack); 2140 if (status != IXGBE_SUCCESS) 2141 goto fail; 2142 2143 ixgbe_i2c_stop(hw); 2144 if (lock) 2145 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2146 return IXGBE_SUCCESS; 2147 2148 fail: 2149 ixgbe_i2c_bus_clear(hw); 2150 if (lock) { 2151 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2152 msec_delay(100); 2153 } 2154 if (retry < max_retry) 2155 DEBUGOUT("I2C byte read error - Retrying.\n"); 2156 else 2157 DEBUGOUT("I2C byte read error.\n"); 2158 retry++; 2159 } while (retry <= max_retry); 2160 2161 return status; 2162 } 2163 2164 /** 2165 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2166 * @hw: pointer to hardware structure 2167 * @byte_offset: byte offset to read 2168 * @dev_addr: address to read from 2169 * @data: value read 2170 * 2171 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2172 * a specified device address. 2173 **/ 2174 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2175 u8 dev_addr, u8 *data) 2176 { 2177 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2178 data, true); 2179 } 2180 2181 /** 2182 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2183 * @hw: pointer to hardware structure 2184 * @byte_offset: byte offset to read 2185 * @dev_addr: address to read from 2186 * @data: value read 2187 * 2188 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2189 * a specified device address. 2190 **/ 2191 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2192 u8 dev_addr, u8 *data) 2193 { 2194 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2195 data, false); 2196 } 2197 2198 /** 2199 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2200 * @hw: pointer to hardware structure 2201 * @byte_offset: byte offset to write 2202 * @dev_addr: address to write to 2203 * @data: value to write 2204 * @lock: true if to take and release semaphore 2205 * 2206 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2207 * a specified device address. 2208 **/ 2209 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2210 u8 dev_addr, u8 data, bool lock) 2211 { 2212 s32 status; 2213 u32 max_retry = 1; 2214 u32 retry = 0; 2215 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2216 2217 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2218 2219 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2220 IXGBE_SUCCESS) 2221 return IXGBE_ERR_SWFW_SYNC; 2222 2223 do { 2224 ixgbe_i2c_start(hw); 2225 2226 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2227 if (status != IXGBE_SUCCESS) 2228 goto fail; 2229 2230 status = ixgbe_get_i2c_ack(hw); 2231 if (status != IXGBE_SUCCESS) 2232 goto fail; 2233 2234 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2235 if (status != IXGBE_SUCCESS) 2236 goto fail; 2237 2238 status = ixgbe_get_i2c_ack(hw); 2239 if (status != IXGBE_SUCCESS) 2240 goto fail; 2241 2242 status = ixgbe_clock_out_i2c_byte(hw, data); 2243 if (status != IXGBE_SUCCESS) 2244 goto fail; 2245 2246 status = ixgbe_get_i2c_ack(hw); 2247 if (status != IXGBE_SUCCESS) 2248 goto fail; 2249 2250 ixgbe_i2c_stop(hw); 2251 if (lock) 2252 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2253 return IXGBE_SUCCESS; 2254 2255 fail: 2256 ixgbe_i2c_bus_clear(hw); 2257 if (retry < max_retry) 2258 DEBUGOUT("I2C byte write error - Retrying.\n"); 2259 else 2260 DEBUGOUT("I2C byte write error.\n"); 2261 retry++; 2262 } while (retry <= max_retry); 2263 2264 if (lock) 2265 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2266 2267 return status; 2268 } 2269 2270 /** 2271 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2272 * @hw: pointer to hardware structure 2273 * @byte_offset: byte offset to write 2274 * @dev_addr: address to write to 2275 * @data: value to write 2276 * 2277 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2278 * a specified device address. 2279 **/ 2280 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2281 u8 dev_addr, u8 data) 2282 { 2283 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2284 data, true); 2285 } 2286 2287 /** 2288 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2289 * @hw: pointer to hardware structure 2290 * @byte_offset: byte offset to write 2291 * @dev_addr: address to write to 2292 * @data: value to write 2293 * 2294 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2295 * a specified device address. 2296 **/ 2297 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2298 u8 dev_addr, u8 data) 2299 { 2300 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2301 data, false); 2302 } 2303 2304 /** 2305 * ixgbe_i2c_start - Sets I2C start condition 2306 * @hw: pointer to hardware structure 2307 * 2308 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2309 * Set bit-bang mode on X550 hardware. 2310 **/ 2311 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2312 { 2313 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2314 2315 DEBUGFUNC("ixgbe_i2c_start"); 2316 2317 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2318 2319 /* Start condition must begin with data and clock high */ 2320 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2321 ixgbe_raise_i2c_clk(hw, &i2cctl); 2322 2323 /* Setup time for start condition (4.7us) */ 2324 usec_delay(IXGBE_I2C_T_SU_STA); 2325 2326 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2327 2328 /* Hold time for start condition (4us) */ 2329 usec_delay(IXGBE_I2C_T_HD_STA); 2330 2331 ixgbe_lower_i2c_clk(hw, &i2cctl); 2332 2333 /* Minimum low period of clock is 4.7 us */ 2334 usec_delay(IXGBE_I2C_T_LOW); 2335 2336 } 2337 2338 /** 2339 * ixgbe_i2c_stop - Sets I2C stop condition 2340 * @hw: pointer to hardware structure 2341 * 2342 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2343 * Disables bit-bang mode and negates data output enable on X550 2344 * hardware. 2345 **/ 2346 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2347 { 2348 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2349 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2350 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2351 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2352 2353 DEBUGFUNC("ixgbe_i2c_stop"); 2354 2355 /* Stop condition must begin with data low and clock high */ 2356 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2357 ixgbe_raise_i2c_clk(hw, &i2cctl); 2358 2359 /* Setup time for stop condition (4us) */ 2360 usec_delay(IXGBE_I2C_T_SU_STO); 2361 2362 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2363 2364 /* bus free time between stop and start (4.7us)*/ 2365 usec_delay(IXGBE_I2C_T_BUF); 2366 2367 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2368 i2cctl &= ~bb_en_bit; 2369 i2cctl |= data_oe_bit | clk_oe_bit; 2370 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2371 IXGBE_WRITE_FLUSH(hw); 2372 } 2373 } 2374 2375 /** 2376 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2377 * @hw: pointer to hardware structure 2378 * @data: data byte to clock in 2379 * 2380 * Clocks in one byte data via I2C data/clock 2381 **/ 2382 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2383 { 2384 s32 i; 2385 bool bit = 0; 2386 2387 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2388 2389 *data = 0; 2390 for (i = 7; i >= 0; i--) { 2391 ixgbe_clock_in_i2c_bit(hw, &bit); 2392 *data |= bit << i; 2393 } 2394 } 2395 2396 /** 2397 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2398 * @hw: pointer to hardware structure 2399 * @data: data byte clocked out 2400 * 2401 * Clocks out one byte data via I2C data/clock 2402 **/ 2403 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2404 { 2405 s32 status = IXGBE_SUCCESS; 2406 s32 i; 2407 u32 i2cctl; 2408 bool bit; 2409 2410 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2411 2412 for (i = 7; i >= 0; i--) { 2413 bit = (data >> i) & 0x1; 2414 status = ixgbe_clock_out_i2c_bit(hw, bit); 2415 2416 if (status != IXGBE_SUCCESS) 2417 break; 2418 } 2419 2420 /* Release SDA line (set high) */ 2421 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2422 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2423 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2424 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2425 IXGBE_WRITE_FLUSH(hw); 2426 2427 return status; 2428 } 2429 2430 /** 2431 * ixgbe_get_i2c_ack - Polls for I2C ACK 2432 * @hw: pointer to hardware structure 2433 * 2434 * Clocks in/out one bit via I2C data/clock 2435 **/ 2436 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2437 { 2438 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2439 s32 status = IXGBE_SUCCESS; 2440 u32 i = 0; 2441 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2442 u32 timeout = 10; 2443 bool ack = 1; 2444 2445 DEBUGFUNC("ixgbe_get_i2c_ack"); 2446 2447 if (data_oe_bit) { 2448 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2449 i2cctl |= data_oe_bit; 2450 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2451 IXGBE_WRITE_FLUSH(hw); 2452 } 2453 ixgbe_raise_i2c_clk(hw, &i2cctl); 2454 2455 /* Minimum high period of clock is 4us */ 2456 usec_delay(IXGBE_I2C_T_HIGH); 2457 2458 /* Poll for ACK. Note that ACK in I2C spec is 2459 * transition from 1 to 0 */ 2460 for (i = 0; i < timeout; i++) { 2461 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2462 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2463 2464 usec_delay(1); 2465 if (!ack) 2466 break; 2467 } 2468 2469 if (ack) { 2470 DEBUGOUT("I2C ack was not received.\n"); 2471 status = IXGBE_ERR_I2C; 2472 } 2473 2474 ixgbe_lower_i2c_clk(hw, &i2cctl); 2475 2476 /* Minimum low period of clock is 4.7 us */ 2477 usec_delay(IXGBE_I2C_T_LOW); 2478 2479 return status; 2480 } 2481 2482 /** 2483 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2484 * @hw: pointer to hardware structure 2485 * @data: read data value 2486 * 2487 * Clocks in one bit via I2C data/clock 2488 **/ 2489 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2490 { 2491 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2492 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2493 2494 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2495 2496 if (data_oe_bit) { 2497 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2498 i2cctl |= data_oe_bit; 2499 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2500 IXGBE_WRITE_FLUSH(hw); 2501 } 2502 ixgbe_raise_i2c_clk(hw, &i2cctl); 2503 2504 /* Minimum high period of clock is 4us */ 2505 usec_delay(IXGBE_I2C_T_HIGH); 2506 2507 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2508 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2509 2510 ixgbe_lower_i2c_clk(hw, &i2cctl); 2511 2512 /* Minimum low period of clock is 4.7 us */ 2513 usec_delay(IXGBE_I2C_T_LOW); 2514 } 2515 2516 /** 2517 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2518 * @hw: pointer to hardware structure 2519 * @data: data value to write 2520 * 2521 * Clocks out one bit via I2C data/clock 2522 **/ 2523 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2524 { 2525 s32 status; 2526 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2527 2528 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2529 2530 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2531 if (status == IXGBE_SUCCESS) { 2532 ixgbe_raise_i2c_clk(hw, &i2cctl); 2533 2534 /* Minimum high period of clock is 4us */ 2535 usec_delay(IXGBE_I2C_T_HIGH); 2536 2537 ixgbe_lower_i2c_clk(hw, &i2cctl); 2538 2539 /* Minimum low period of clock is 4.7 us. 2540 * This also takes care of the data hold time. 2541 */ 2542 usec_delay(IXGBE_I2C_T_LOW); 2543 } else { 2544 status = IXGBE_ERR_I2C; 2545 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2546 "I2C data was not set to %X\n", data); 2547 } 2548 2549 return status; 2550 } 2551 2552 /** 2553 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2554 * @hw: pointer to hardware structure 2555 * @i2cctl: Current value of I2CCTL register 2556 * 2557 * Raises the I2C clock line '0'->'1' 2558 * Negates the I2C clock output enable on X550 hardware. 2559 **/ 2560 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2561 { 2562 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2563 u32 i = 0; 2564 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2565 u32 i2cctl_r = 0; 2566 2567 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2568 2569 if (clk_oe_bit) { 2570 *i2cctl |= clk_oe_bit; 2571 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2572 } 2573 2574 for (i = 0; i < timeout; i++) { 2575 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2576 2577 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2578 IXGBE_WRITE_FLUSH(hw); 2579 /* SCL rise time (1000ns) */ 2580 usec_delay(IXGBE_I2C_T_RISE); 2581 2582 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2583 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2584 break; 2585 } 2586 } 2587 2588 /** 2589 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2590 * @hw: pointer to hardware structure 2591 * @i2cctl: Current value of I2CCTL register 2592 * 2593 * Lowers the I2C clock line '1'->'0' 2594 * Asserts the I2C clock output enable on X550 hardware. 2595 **/ 2596 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2597 { 2598 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2599 2600 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2601 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2602 2603 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2604 IXGBE_WRITE_FLUSH(hw); 2605 2606 /* SCL fall time (300ns) */ 2607 usec_delay(IXGBE_I2C_T_FALL); 2608 } 2609 2610 /** 2611 * ixgbe_set_i2c_data - Sets the I2C data bit 2612 * @hw: pointer to hardware structure 2613 * @i2cctl: Current value of I2CCTL register 2614 * @data: I2C data value (0 or 1) to set 2615 * 2616 * Sets the I2C data bit 2617 * Asserts the I2C data output enable on X550 hardware. 2618 **/ 2619 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2620 { 2621 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2622 s32 status = IXGBE_SUCCESS; 2623 2624 DEBUGFUNC("ixgbe_set_i2c_data"); 2625 2626 if (data) 2627 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2628 else 2629 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2630 *i2cctl &= ~data_oe_bit; 2631 2632 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2633 IXGBE_WRITE_FLUSH(hw); 2634 2635 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2636 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2637 2638 if (!data) /* Can't verify data in this case */ 2639 return IXGBE_SUCCESS; 2640 if (data_oe_bit) { 2641 *i2cctl |= data_oe_bit; 2642 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2643 IXGBE_WRITE_FLUSH(hw); 2644 } 2645 2646 /* Verify data was set correctly */ 2647 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2648 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2649 status = IXGBE_ERR_I2C; 2650 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2651 "Error - I2C data was not set to %X.\n", 2652 data); 2653 } 2654 2655 return status; 2656 } 2657 2658 /** 2659 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2660 * @hw: pointer to hardware structure 2661 * @i2cctl: Current value of I2CCTL register 2662 * 2663 * Returns the I2C data bit value 2664 * Negates the I2C data output enable on X550 hardware. 2665 **/ 2666 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2667 { 2668 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2669 bool data; 2670 2671 DEBUGFUNC("ixgbe_get_i2c_data"); 2672 2673 if (data_oe_bit) { 2674 *i2cctl |= data_oe_bit; 2675 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2676 IXGBE_WRITE_FLUSH(hw); 2677 usec_delay(IXGBE_I2C_T_FALL); 2678 } 2679 2680 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2681 data = 1; 2682 else 2683 data = 0; 2684 2685 return data; 2686 } 2687 2688 /** 2689 * ixgbe_i2c_bus_clear - Clears the I2C bus 2690 * @hw: pointer to hardware structure 2691 * 2692 * Clears the I2C bus by sending nine clock pulses. 2693 * Used when data line is stuck low. 2694 **/ 2695 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2696 { 2697 u32 i2cctl; 2698 u32 i; 2699 2700 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2701 2702 ixgbe_i2c_start(hw); 2703 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2704 2705 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2706 2707 for (i = 0; i < 9; i++) { 2708 ixgbe_raise_i2c_clk(hw, &i2cctl); 2709 2710 /* Min high period of clock is 4us */ 2711 usec_delay(IXGBE_I2C_T_HIGH); 2712 2713 ixgbe_lower_i2c_clk(hw, &i2cctl); 2714 2715 /* Min low period of clock is 4.7us*/ 2716 usec_delay(IXGBE_I2C_T_LOW); 2717 } 2718 2719 ixgbe_i2c_start(hw); 2720 2721 /* Put the i2c bus back to default state */ 2722 ixgbe_i2c_stop(hw); 2723 } 2724 2725 /** 2726 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2727 * @hw: pointer to hardware structure 2728 * 2729 * Checks if the LASI temp alarm status was triggered due to overtemp 2730 **/ 2731 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2732 { 2733 s32 status = IXGBE_SUCCESS; 2734 u16 phy_data = 0; 2735 2736 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2737 2738 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2739 goto out; 2740 2741 /* Check that the LASI temp alarm status was triggered */ 2742 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2743 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2744 2745 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2746 goto out; 2747 2748 status = IXGBE_ERR_OVERTEMP; 2749 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2750 out: 2751 return status; 2752 } 2753 2754 /** 2755 * ixgbe_set_copper_phy_power - Control power for copper phy 2756 * @hw: pointer to hardware structure 2757 * @on: true for on, false for off 2758 */ 2759 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2760 { 2761 u32 status; 2762 u16 reg; 2763 2764 if (!on && ixgbe_mng_present(hw)) 2765 return 0; 2766 2767 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2768 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2769 ®); 2770 if (status) 2771 return status; 2772 2773 if (on) { 2774 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2775 } else { 2776 if (ixgbe_check_reset_blocked(hw)) 2777 return 0; 2778 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2779 } 2780 2781 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2782 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2783 reg); 2784 return status; 2785 } 2786