1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53 /** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61 { 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68 } 69 70 /** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78 { 79 ixgbe_clock_in_i2c_byte(hw, byte); 80 /* ACK */ 81 return ixgbe_clock_out_i2c_bit(hw, false); 82 } 83 84 /** 85 * ixgbe_ones_comp_byte_add - Perform one's complement addition 86 * @add1: addend 1 87 * @add2: addend 2 88 * 89 * Returns one's complement 8-bit sum. 90 */ 91 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 92 { 93 u16 sum = add1 + add2; 94 95 sum = (sum & 0xFF) + (sum >> 8); 96 return sum & 0xFF; 97 } 98 99 /** 100 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 101 * @hw: pointer to the hardware structure 102 * @addr: I2C bus address to read from 103 * @reg: I2C device register to read from 104 * @val: pointer to location to receive read value 105 * @lock: true if to take and release semaphore 106 * 107 * Returns an error code on error. 108 */ 109 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 110 u16 *val, bool lock) 111 { 112 u32 swfw_mask = hw->phy.phy_semaphore_mask; 113 int max_retry = 3; 114 int retry = 0; 115 u8 csum_byte; 116 u8 high_bits; 117 u8 low_bits; 118 u8 reg_high; 119 u8 csum; 120 121 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 122 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 123 csum = ~csum; 124 do { 125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 126 return IXGBE_ERR_SWFW_SYNC; 127 ixgbe_i2c_start(hw); 128 /* Device Address and write indication */ 129 if (ixgbe_out_i2c_byte_ack(hw, addr)) 130 goto fail; 131 /* Write bits 14:8 */ 132 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 133 goto fail; 134 /* Write bits 7:0 */ 135 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 136 goto fail; 137 /* Write csum */ 138 if (ixgbe_out_i2c_byte_ack(hw, csum)) 139 goto fail; 140 /* Re-start condition */ 141 ixgbe_i2c_start(hw); 142 /* Device Address and read indication */ 143 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 144 goto fail; 145 /* Get upper bits */ 146 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 147 goto fail; 148 /* Get low bits */ 149 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 150 goto fail; 151 /* Get csum */ 152 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 153 /* NACK */ 154 if (ixgbe_clock_out_i2c_bit(hw, false)) 155 goto fail; 156 ixgbe_i2c_stop(hw); 157 if (lock) 158 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 159 *val = (high_bits << 8) | low_bits; 160 return 0; 161 162 fail: 163 ixgbe_i2c_bus_clear(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 if (retry < max_retry) 167 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 168 else 169 DEBUGOUT("I2C byte read combined error.\n"); 170 retry++; 171 } while (retry <= max_retry); 172 173 return IXGBE_ERR_I2C; 174 } 175 176 /** 177 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 178 * @hw: pointer to the hardware structure 179 * @addr: I2C bus address to write to 180 * @reg: I2C device register to write to 181 * @val: value to write 182 * @lock: true if to take and release semaphore 183 * 184 * Returns an error code on error. 185 */ 186 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 187 u16 val, bool lock) 188 { 189 u32 swfw_mask = hw->phy.phy_semaphore_mask; 190 int max_retry = 1; 191 int retry = 0; 192 u8 reg_high; 193 u8 csum; 194 195 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 196 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 197 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 198 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 199 csum = ~csum; 200 do { 201 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 202 return IXGBE_ERR_SWFW_SYNC; 203 ixgbe_i2c_start(hw); 204 /* Device Address and write indication */ 205 if (ixgbe_out_i2c_byte_ack(hw, addr)) 206 goto fail; 207 /* Write bits 14:8 */ 208 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 209 goto fail; 210 /* Write bits 7:0 */ 211 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 212 goto fail; 213 /* Write data 15:8 */ 214 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 215 goto fail; 216 /* Write data 7:0 */ 217 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 218 goto fail; 219 /* Write csum */ 220 if (ixgbe_out_i2c_byte_ack(hw, csum)) 221 goto fail; 222 ixgbe_i2c_stop(hw); 223 if (lock) 224 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 225 return 0; 226 227 fail: 228 ixgbe_i2c_bus_clear(hw); 229 if (lock) 230 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 231 if (retry < max_retry) 232 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 233 else 234 DEBUGOUT("I2C byte write combined error.\n"); 235 retry++; 236 } while (retry <= max_retry); 237 238 return IXGBE_ERR_I2C; 239 } 240 241 /** 242 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 243 * @hw: pointer to the hardware structure 244 * 245 * Initialize the function pointers. 246 **/ 247 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 248 { 249 struct ixgbe_phy_info *phy = &hw->phy; 250 251 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 252 253 /* PHY */ 254 phy->ops.identify = ixgbe_identify_phy_generic; 255 phy->ops.reset = ixgbe_reset_phy_generic; 256 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 257 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 260 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 261 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 262 phy->ops.check_link = NULL; 263 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 264 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 265 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 266 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 267 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 268 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 269 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 270 phy->ops.identify_sfp = ixgbe_identify_module_generic; 271 phy->sfp_type = ixgbe_sfp_type_unknown; 272 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 273 phy->ops.write_i2c_byte_unlocked = 274 ixgbe_write_i2c_byte_generic_unlocked; 275 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 276 return IXGBE_SUCCESS; 277 } 278 279 /** 280 * ixgbe_probe_phy - Probe a single address for a PHY 281 * @hw: pointer to hardware structure 282 * @phy_addr: PHY address to probe 283 * 284 * Returns true if PHY found 285 */ 286 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 287 { 288 u16 ext_ability = 0; 289 290 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 291 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 292 phy_addr); 293 return false; 294 } 295 296 if (ixgbe_get_phy_id(hw)) 297 return false; 298 299 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 300 301 if (hw->phy.type == ixgbe_phy_unknown) { 302 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 303 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 304 if (ext_ability & 305 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 306 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 307 hw->phy.type = ixgbe_phy_cu_unknown; 308 else 309 hw->phy.type = ixgbe_phy_generic; 310 } 311 312 return true; 313 } 314 315 /** 316 * ixgbe_identify_phy_generic - Get physical layer module 317 * @hw: pointer to hardware structure 318 * 319 * Determines the physical layer module found on the current adapter. 320 **/ 321 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 322 { 323 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 324 u16 phy_addr; 325 326 DEBUGFUNC("ixgbe_identify_phy_generic"); 327 328 if (!hw->phy.phy_semaphore_mask) { 329 if (hw->bus.lan_id) 330 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 331 else 332 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 333 } 334 335 if (hw->phy.type != ixgbe_phy_unknown) 336 return IXGBE_SUCCESS; 337 338 if (hw->phy.nw_mng_if_sel) { 339 phy_addr = (hw->phy.nw_mng_if_sel & 340 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 342 if (ixgbe_probe_phy(hw, phy_addr)) 343 return IXGBE_SUCCESS; 344 else 345 return IXGBE_ERR_PHY_ADDR_INVALID; 346 } 347 348 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 349 if (ixgbe_probe_phy(hw, phy_addr)) { 350 status = IXGBE_SUCCESS; 351 break; 352 } 353 } 354 355 /* Certain media types do not have a phy so an address will not 356 * be found and the code will take this path. Caller has to 357 * decide if it is an error or not. 358 */ 359 if (status != IXGBE_SUCCESS) 360 hw->phy.addr = 0; 361 362 return status; 363 } 364 365 /** 366 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 367 * @hw: pointer to the hardware structure 368 * 369 * This function checks the MMNGC.MNG_VETO bit to see if there are 370 * any constraints on link from manageability. For MAC's that don't 371 * have this bit just return faluse since the link can not be blocked 372 * via this method. 373 **/ 374 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 375 { 376 u32 mmngc; 377 378 DEBUGFUNC("ixgbe_check_reset_blocked"); 379 380 /* If we don't have this bit, it can't be blocking */ 381 if (hw->mac.type == ixgbe_mac_82598EB) 382 return false; 383 384 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 385 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 386 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 387 "MNG_VETO bit detected.\n"); 388 return true; 389 } 390 391 return false; 392 } 393 394 /** 395 * ixgbe_validate_phy_addr - Determines phy address is valid 396 * @hw: pointer to hardware structure 397 * @phy_addr: PHY address 398 * 399 **/ 400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 401 { 402 u16 phy_id = 0; 403 bool valid = false; 404 405 DEBUGFUNC("ixgbe_validate_phy_addr"); 406 407 hw->phy.addr = phy_addr; 408 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 409 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 410 411 if (phy_id != 0xFFFF && phy_id != 0x0) 412 valid = true; 413 414 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 415 416 return valid; 417 } 418 419 /** 420 * ixgbe_get_phy_id - Get the phy type 421 * @hw: pointer to hardware structure 422 * 423 **/ 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 425 { 426 u32 status; 427 u16 phy_id_high = 0; 428 u16 phy_id_low = 0; 429 430 DEBUGFUNC("ixgbe_get_phy_id"); 431 432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 433 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 434 &phy_id_high); 435 436 if (status == IXGBE_SUCCESS) { 437 hw->phy.id = (u32)(phy_id_high << 16); 438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 439 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 440 &phy_id_low); 441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 443 } 444 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 445 phy_id_high, phy_id_low); 446 447 return status; 448 } 449 450 /** 451 * ixgbe_get_phy_type_from_id - Get the phy type 452 * @phy_id: PHY ID information 453 * 454 **/ 455 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 456 { 457 enum ixgbe_phy_type phy_type; 458 459 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 460 461 switch (phy_id) { 462 case TN1010_PHY_ID: 463 phy_type = ixgbe_phy_tn; 464 break; 465 case X550_PHY_ID: 466 case X540_PHY_ID: 467 phy_type = ixgbe_phy_aq; 468 break; 469 case QT2022_PHY_ID: 470 phy_type = ixgbe_phy_qt; 471 break; 472 case ATH_PHY_ID: 473 phy_type = ixgbe_phy_nl; 474 break; 475 case X557_PHY_ID: 476 case X557_PHY_ID2: 477 phy_type = ixgbe_phy_x550em_ext_t; 478 break; 479 case IXGBE_M88E1500_E_PHY_ID: 480 case IXGBE_M88E1543_E_PHY_ID: 481 phy_type = ixgbe_phy_ext_1g_t; 482 break; 483 default: 484 phy_type = ixgbe_phy_unknown; 485 break; 486 } 487 return phy_type; 488 } 489 490 /** 491 * ixgbe_reset_phy_generic - Performs a PHY reset 492 * @hw: pointer to hardware structure 493 **/ 494 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 495 { 496 u32 i; 497 u16 ctrl = 0; 498 s32 status = IXGBE_SUCCESS; 499 500 DEBUGFUNC("ixgbe_reset_phy_generic"); 501 502 if (hw->phy.type == ixgbe_phy_unknown) 503 status = ixgbe_identify_phy_generic(hw); 504 505 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 506 goto out; 507 508 /* Don't reset PHY if it's shut down due to overtemp. */ 509 if (!hw->phy.reset_if_overtemp && 510 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 511 goto out; 512 513 /* Blocked by MNG FW so bail */ 514 if (ixgbe_check_reset_blocked(hw)) 515 goto out; 516 517 /* 518 * Perform soft PHY reset to the PHY_XS. 519 * This will cause a soft reset to the PHY 520 */ 521 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 522 IXGBE_MDIO_PHY_XS_DEV_TYPE, 523 IXGBE_MDIO_PHY_XS_RESET); 524 525 /* 526 * Poll for reset bit to self-clear indicating reset is complete. 527 * Some PHYs could take up to 3 seconds to complete and need about 528 * 1.7 usec delay after the reset is complete. 529 */ 530 for (i = 0; i < 30; i++) { 531 msec_delay(100); 532 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 533 status = hw->phy.ops.read_reg(hw, 534 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 535 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 536 &ctrl); 537 if (status != IXGBE_SUCCESS) 538 return status; 539 540 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 541 usec_delay(2); 542 break; 543 } 544 } else { 545 status = hw->phy.ops.read_reg(hw, 546 IXGBE_MDIO_PHY_XS_CONTROL, 547 IXGBE_MDIO_PHY_XS_DEV_TYPE, 548 &ctrl); 549 if (status != IXGBE_SUCCESS) 550 return status; 551 552 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 553 usec_delay(2); 554 break; 555 } 556 } 557 } 558 559 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 560 status = IXGBE_ERR_RESET_FAILED; 561 ERROR_REPORT1(IXGBE_ERROR_POLLING, 562 "PHY reset polling failed to complete.\n"); 563 } 564 565 out: 566 return status; 567 } 568 569 /** 570 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY 571 * @hw: pointer to hardware structure 572 **/ 573 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw) 574 { 575 u16 autoneg_reg; 576 577 /* Check if PHY reset is blocked by MNG FW */ 578 if (ixgbe_check_reset_blocked(hw)) 579 return; 580 581 /* Restart PHY auto-negotiation. */ 582 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 583 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 584 autoneg_reg |= IXGBE_MII_RESTART; 585 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 586 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 587 } 588 589 /** 590 * ixgbe_read_phy_reg_mdi - Reads a value from a specified PHY register without 591 * the SWFW lock 592 * @hw: pointer to hardware structure 593 * @reg_addr: 32 bit address of PHY register to read 594 * @device_type: 5 bit device type 595 * @phy_data: Pointer to read data from PHY register 596 **/ 597 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 598 u16 *phy_data) 599 { 600 u32 i, data, command; 601 602 /* Setup and write the address cycle command */ 603 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 604 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 605 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 606 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 607 608 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 609 610 /* 611 * Check every 10 usec to see if the address cycle completed. 612 * The MDI Command bit will clear when the operation is 613 * complete 614 */ 615 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 616 usec_delay(10); 617 618 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 619 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 620 break; 621 } 622 623 624 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 625 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 626 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 627 return IXGBE_ERR_PHY; 628 } 629 630 /* 631 * Address cycle complete, setup and write the read 632 * command 633 */ 634 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 635 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 636 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 637 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 638 639 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 640 641 /* 642 * Check every 10 usec to see if the address cycle 643 * completed. The MDI Command bit will clear when the 644 * operation is complete 645 */ 646 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 647 usec_delay(10); 648 649 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 650 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 651 break; 652 } 653 654 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 655 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 656 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 657 return IXGBE_ERR_PHY; 658 } 659 660 /* 661 * Read operation is complete. Get the data 662 * from MSRWD 663 */ 664 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 665 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 666 *phy_data = (u16)(data); 667 668 return IXGBE_SUCCESS; 669 } 670 671 /** 672 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 673 * using the SWFW lock - this function is needed in most cases 674 * @hw: pointer to hardware structure 675 * @reg_addr: 32 bit address of PHY register to read 676 * @device_type: 5 bit device type 677 * @phy_data: Pointer to read data from PHY register 678 **/ 679 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 680 u32 device_type, u16 *phy_data) 681 { 682 s32 status; 683 u32 gssr = hw->phy.phy_semaphore_mask; 684 685 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 686 687 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 688 return IXGBE_ERR_SWFW_SYNC; 689 690 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 691 692 hw->mac.ops.release_swfw_sync(hw, gssr); 693 694 return status; 695 } 696 697 /** 698 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 699 * without SWFW lock 700 * @hw: pointer to hardware structure 701 * @reg_addr: 32 bit PHY register to write 702 * @device_type: 5 bit device type 703 * @phy_data: Data to write to the PHY register 704 **/ 705 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 706 u32 device_type, u16 phy_data) 707 { 708 u32 i, command; 709 710 /* Put the data in the MDI single read and write data register*/ 711 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 712 713 /* Setup and write the address cycle command */ 714 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 715 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 717 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 718 719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 720 721 /* 722 * Check every 10 usec to see if the address cycle completed. 723 * The MDI Command bit will clear when the operation is 724 * complete 725 */ 726 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 727 usec_delay(10); 728 729 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 730 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 731 break; 732 } 733 734 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 735 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 736 return IXGBE_ERR_PHY; 737 } 738 739 /* 740 * Address cycle complete, setup and write the write 741 * command 742 */ 743 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 744 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 745 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 746 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 747 748 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 749 750 /* 751 * Check every 10 usec to see if the address cycle 752 * completed. The MDI Command bit will clear when the 753 * operation is complete 754 */ 755 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 756 usec_delay(10); 757 758 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 759 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 760 break; 761 } 762 763 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 764 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 765 return IXGBE_ERR_PHY; 766 } 767 768 return IXGBE_SUCCESS; 769 } 770 771 /** 772 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 773 * using SWFW lock- this function is needed in most cases 774 * @hw: pointer to hardware structure 775 * @reg_addr: 32 bit PHY register to write 776 * @device_type: 5 bit device type 777 * @phy_data: Data to write to the PHY register 778 **/ 779 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 780 u32 device_type, u16 phy_data) 781 { 782 s32 status; 783 u32 gssr = hw->phy.phy_semaphore_mask; 784 785 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 786 787 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 788 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 789 phy_data); 790 hw->mac.ops.release_swfw_sync(hw, gssr); 791 } else { 792 status = IXGBE_ERR_SWFW_SYNC; 793 } 794 795 return status; 796 } 797 798 /** 799 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 800 * @hw: pointer to hardware structure 801 * 802 * Restart auto-negotiation and PHY and waits for completion. 803 **/ 804 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 805 { 806 s32 status = IXGBE_SUCCESS; 807 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 808 bool autoneg = false; 809 ixgbe_link_speed speed; 810 811 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 812 813 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 814 815 /* Set or unset auto-negotiation 10G advertisement */ 816 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 818 &autoneg_reg); 819 820 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 822 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 823 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 824 825 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 827 autoneg_reg); 828 829 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 831 &autoneg_reg); 832 833 if (hw->mac.type == ixgbe_mac_X550) { 834 /* Set or unset auto-negotiation 5G advertisement */ 835 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 837 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 838 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 839 840 /* Set or unset auto-negotiation 2.5G advertisement */ 841 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 842 if ((hw->phy.autoneg_advertised & 843 IXGBE_LINK_SPEED_2_5GB_FULL) && 844 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 845 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 846 } 847 848 /* Set or unset auto-negotiation 1G advertisement */ 849 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 851 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 852 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 853 854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 856 autoneg_reg); 857 858 /* Set or unset auto-negotiation 100M advertisement */ 859 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 860 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 861 &autoneg_reg); 862 863 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 864 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 865 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 866 (speed & IXGBE_LINK_SPEED_100_FULL)) 867 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 868 869 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 870 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 871 autoneg_reg); 872 873 ixgbe_restart_auto_neg(hw); 874 return status; 875 } 876 877 /** 878 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 879 * @hw: pointer to hardware structure 880 * @speed: new link speed 881 * @autoneg_wait_to_complete: unused 882 **/ 883 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 884 ixgbe_link_speed speed, 885 bool autoneg_wait_to_complete) 886 { 887 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 888 889 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 890 891 /* 892 * Clear autoneg_advertised and set new values based on input link 893 * speed. 894 */ 895 hw->phy.autoneg_advertised = 0; 896 897 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 899 900 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 902 903 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 905 906 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 908 909 if (speed & IXGBE_LINK_SPEED_100_FULL) 910 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 911 912 if (speed & IXGBE_LINK_SPEED_10_FULL) 913 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 914 915 /* Setup link based on the new speed settings */ 916 ixgbe_setup_phy_link(hw); 917 918 return IXGBE_SUCCESS; 919 } 920 921 /** 922 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 923 * @hw: pointer to hardware structure 924 * 925 * Determines the supported link capabilities by reading the PHY auto 926 * negotiation register. 927 **/ 928 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 929 { 930 s32 status; 931 u16 speed_ability; 932 933 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 934 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 935 &speed_ability); 936 if (status) 937 return status; 938 939 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 940 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 945 946 switch (hw->mac.type) { 947 case ixgbe_mac_X550: 948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 949 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 950 break; 951 case ixgbe_mac_X550EM_x: 952 case ixgbe_mac_X550EM_a: 953 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 954 break; 955 default: 956 break; 957 } 958 959 return status; 960 } 961 962 /** 963 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 964 * @hw: pointer to hardware structure 965 * @speed: pointer to link speed 966 * @autoneg: boolean auto-negotiation value 967 **/ 968 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 969 ixgbe_link_speed *speed, 970 bool *autoneg) 971 { 972 s32 status = IXGBE_SUCCESS; 973 974 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 975 976 *autoneg = true; 977 if (!hw->phy.speeds_supported) 978 status = ixgbe_get_copper_speeds_supported(hw); 979 980 *speed = hw->phy.speeds_supported; 981 return status; 982 } 983 984 /** 985 * ixgbe_check_phy_link_tnx - Determine link and speed status 986 * @hw: pointer to hardware structure 987 * @speed: current link speed 988 * @link_up: true is link is up, false otherwise 989 * 990 * Reads the VS1 register to determine if link is up and the current speed for 991 * the PHY. 992 **/ 993 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 994 bool *link_up) 995 { 996 s32 status = IXGBE_SUCCESS; 997 u32 time_out; 998 u32 max_time_out = 10; 999 u16 phy_link = 0; 1000 u16 phy_speed = 0; 1001 u16 phy_data = 0; 1002 1003 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1004 1005 /* Initialize speed and link to default case */ 1006 *link_up = false; 1007 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1008 1009 /* 1010 * Check current speed and link status of the PHY register. 1011 * This is a vendor specific register and may have to 1012 * be changed for other copper PHYs. 1013 */ 1014 for (time_out = 0; time_out < max_time_out; time_out++) { 1015 usec_delay(10); 1016 status = hw->phy.ops.read_reg(hw, 1017 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1018 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1019 &phy_data); 1020 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1021 phy_speed = phy_data & 1022 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1023 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1024 *link_up = true; 1025 if (phy_speed == 1026 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1027 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1028 break; 1029 } 1030 } 1031 1032 return status; 1033 } 1034 1035 /** 1036 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1037 * @hw: pointer to hardware structure 1038 * 1039 * Restart auto-negotiation and PHY and waits for completion. 1040 **/ 1041 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1042 { 1043 s32 status = IXGBE_SUCCESS; 1044 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1045 bool autoneg = false; 1046 ixgbe_link_speed speed; 1047 1048 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1049 1050 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1051 1052 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1053 /* Set or unset auto-negotiation 10G advertisement */ 1054 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1055 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1056 &autoneg_reg); 1057 1058 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1059 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1060 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1061 1062 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1063 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1064 autoneg_reg); 1065 } 1066 1067 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1068 /* Set or unset auto-negotiation 1G advertisement */ 1069 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1070 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1071 &autoneg_reg); 1072 1073 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1074 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1075 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1076 1077 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1078 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1079 autoneg_reg); 1080 } 1081 1082 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1083 /* Set or unset auto-negotiation 100M advertisement */ 1084 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1086 &autoneg_reg); 1087 1088 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1089 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1090 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1091 1092 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1093 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1094 autoneg_reg); 1095 } 1096 1097 ixgbe_restart_auto_neg(hw); 1098 return status; 1099 } 1100 1101 /** 1102 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1103 * @hw: pointer to hardware structure 1104 * @firmware_version: pointer to the PHY Firmware Version 1105 **/ 1106 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1107 u16 *firmware_version) 1108 { 1109 s32 status; 1110 1111 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1112 1113 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1114 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1115 firmware_version); 1116 1117 return status; 1118 } 1119 1120 /** 1121 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1122 * @hw: pointer to hardware structure 1123 * @firmware_version: pointer to the PHY Firmware Version 1124 **/ 1125 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1126 u16 *firmware_version) 1127 { 1128 s32 status; 1129 1130 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1131 1132 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1133 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1134 firmware_version); 1135 1136 return status; 1137 } 1138 1139 /** 1140 * ixgbe_reset_phy_nl - Performs a PHY reset 1141 * @hw: pointer to hardware structure 1142 **/ 1143 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1144 { 1145 u16 phy_offset, control, eword, edata, block_crc; 1146 bool end_data = false; 1147 u16 list_offset, data_offset; 1148 u16 phy_data = 0; 1149 s32 ret_val = IXGBE_SUCCESS; 1150 u32 i; 1151 1152 DEBUGFUNC("ixgbe_reset_phy_nl"); 1153 1154 /* Blocked by MNG FW so bail */ 1155 if (ixgbe_check_reset_blocked(hw)) 1156 goto out; 1157 1158 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1159 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1160 1161 /* reset the PHY and poll for completion */ 1162 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1163 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1164 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1165 1166 for (i = 0; i < 100; i++) { 1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1168 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1169 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1170 break; 1171 msec_delay(10); 1172 } 1173 1174 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1175 DEBUGOUT("PHY reset did not complete.\n"); 1176 ret_val = IXGBE_ERR_PHY; 1177 goto out; 1178 } 1179 1180 /* Get init offsets */ 1181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1182 &data_offset); 1183 if (ret_val != IXGBE_SUCCESS) 1184 goto out; 1185 1186 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1187 data_offset++; 1188 while (!end_data) { 1189 /* 1190 * Read control word from PHY init contents offset 1191 */ 1192 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1193 if (ret_val) 1194 goto err_eeprom; 1195 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1196 IXGBE_CONTROL_SHIFT_NL; 1197 edata = eword & IXGBE_DATA_MASK_NL; 1198 switch (control) { 1199 case IXGBE_DELAY_NL: 1200 data_offset++; 1201 DEBUGOUT1("DELAY: %d MS\n", edata); 1202 msec_delay(edata); 1203 break; 1204 case IXGBE_DATA_NL: 1205 DEBUGOUT("DATA:\n"); 1206 data_offset++; 1207 ret_val = hw->eeprom.ops.read(hw, data_offset, 1208 &phy_offset); 1209 if (ret_val) 1210 goto err_eeprom; 1211 data_offset++; 1212 for (i = 0; i < edata; i++) { 1213 ret_val = hw->eeprom.ops.read(hw, data_offset, 1214 &eword); 1215 if (ret_val) 1216 goto err_eeprom; 1217 hw->phy.ops.write_reg(hw, phy_offset, 1218 IXGBE_TWINAX_DEV, eword); 1219 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1220 phy_offset); 1221 data_offset++; 1222 phy_offset++; 1223 } 1224 break; 1225 case IXGBE_CONTROL_NL: 1226 data_offset++; 1227 DEBUGOUT("CONTROL:\n"); 1228 if (edata == IXGBE_CONTROL_EOL_NL) { 1229 DEBUGOUT("EOL\n"); 1230 end_data = true; 1231 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1232 DEBUGOUT("SOL\n"); 1233 } else { 1234 DEBUGOUT("Bad control value\n"); 1235 ret_val = IXGBE_ERR_PHY; 1236 goto out; 1237 } 1238 break; 1239 default: 1240 DEBUGOUT("Bad control type\n"); 1241 ret_val = IXGBE_ERR_PHY; 1242 goto out; 1243 } 1244 } 1245 1246 out: 1247 return ret_val; 1248 1249 err_eeprom: 1250 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1251 "eeprom read at offset %d failed", data_offset); 1252 return IXGBE_ERR_PHY; 1253 } 1254 1255 /** 1256 * ixgbe_identify_module_generic - Identifies module type 1257 * @hw: pointer to hardware structure 1258 * 1259 * Determines HW type and calls appropriate function. 1260 **/ 1261 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1262 { 1263 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1264 1265 DEBUGFUNC("ixgbe_identify_module_generic"); 1266 1267 switch (hw->mac.ops.get_media_type(hw)) { 1268 case ixgbe_media_type_fiber: 1269 status = ixgbe_identify_sfp_module_generic(hw); 1270 break; 1271 1272 case ixgbe_media_type_fiber_qsfp: 1273 status = ixgbe_identify_qsfp_module_generic(hw); 1274 break; 1275 1276 default: 1277 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1278 status = IXGBE_ERR_SFP_NOT_PRESENT; 1279 break; 1280 } 1281 1282 return status; 1283 } 1284 1285 /** 1286 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1287 * @hw: pointer to hardware structure 1288 * 1289 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1290 **/ 1291 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1292 { 1293 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1294 u32 vendor_oui = 0; 1295 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1296 u8 identifier = 0; 1297 u8 comp_codes_1g = 0; 1298 u8 comp_codes_10g = 0; 1299 u8 oui_bytes[3] = {0, 0, 0}; 1300 u8 cable_tech = 0; 1301 u8 cable_spec = 0; 1302 u8 retries; 1303 u16 enforce_sfp = 0; 1304 static bool warned_once = false; 1305 1306 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1307 1308 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1309 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1310 status = IXGBE_ERR_SFP_NOT_PRESENT; 1311 goto out; 1312 } 1313 1314 /* LAN ID is needed for I2C access */ 1315 hw->mac.ops.set_lan_id(hw); 1316 1317 /* 1318 * Some SFPs with a microcontroller ACK I2C reads before the data 1319 * backing them is initialized. Retry successfully completed reads 1320 * with invalid identifier values before declaring the module 1321 * unsupported. Failed transactions are retried by the I2C helper. 1322 */ 1323 for (retries = 0; retries < 5; retries++) { 1324 status = hw->phy.ops.read_i2c_eeprom(hw, 1325 IXGBE_SFF_IDENTIFIER, &identifier); 1326 1327 DEBUGOUT2("status %d, SFF identifier 0x%x\n", status, 1328 identifier); 1329 if (status != IXGBE_SUCCESS || 1330 identifier == IXGBE_SFF_IDENTIFIER_SFP) 1331 break; 1332 } 1333 1334 if (status != IXGBE_SUCCESS) 1335 goto err_read_i2c_eeprom; 1336 1337 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1338 hw->phy.type = ixgbe_phy_sfp_unsupported; 1339 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1340 } else { 1341 status = hw->phy.ops.read_i2c_eeprom(hw, 1342 IXGBE_SFF_1GBE_COMP_CODES, 1343 &comp_codes_1g); 1344 1345 if (status != IXGBE_SUCCESS) 1346 goto err_read_i2c_eeprom; 1347 1348 status = hw->phy.ops.read_i2c_eeprom(hw, 1349 IXGBE_SFF_10GBE_COMP_CODES, 1350 &comp_codes_10g); 1351 1352 if (status != IXGBE_SUCCESS) 1353 goto err_read_i2c_eeprom; 1354 status = hw->phy.ops.read_i2c_eeprom(hw, 1355 IXGBE_SFF_CABLE_TECHNOLOGY, 1356 &cable_tech); 1357 1358 if (status != IXGBE_SUCCESS) 1359 goto err_read_i2c_eeprom; 1360 1361 /* ID Module 1362 * ========= 1363 * 0 SFP_DA_CU 1364 * 1 SFP_SR 1365 * 2 SFP_LR 1366 * 3 SFP_DA_CORE0 - 82599-specific 1367 * 4 SFP_DA_CORE1 - 82599-specific 1368 * 5 SFP_SR/LR_CORE0 - 82599-specific 1369 * 6 SFP_SR/LR_CORE1 - 82599-specific 1370 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1371 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1372 * 9 SFP_1g_cu_CORE0 - 82599-specific 1373 * 10 SFP_1g_cu_CORE1 - 82599-specific 1374 * 11 SFP_1g_sx_CORE0 - 82599-specific 1375 * 12 SFP_1g_sx_CORE1 - 82599-specific 1376 */ 1377 if (hw->mac.type == ixgbe_mac_82598EB) { 1378 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1379 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1380 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1381 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1382 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1383 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1384 else 1385 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1386 } else { 1387 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1388 if (hw->bus.lan_id == 0) 1389 hw->phy.sfp_type = 1390 ixgbe_sfp_type_da_cu_core0; 1391 else 1392 hw->phy.sfp_type = 1393 ixgbe_sfp_type_da_cu_core1; 1394 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1395 hw->phy.ops.read_i2c_eeprom( 1396 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1397 &cable_spec); 1398 if (cable_spec & 1399 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1400 if (hw->bus.lan_id == 0) 1401 hw->phy.sfp_type = 1402 ixgbe_sfp_type_da_act_lmt_core0; 1403 else 1404 hw->phy.sfp_type = 1405 ixgbe_sfp_type_da_act_lmt_core1; 1406 } else { 1407 hw->phy.sfp_type = 1408 ixgbe_sfp_type_unknown; 1409 } 1410 } else if (comp_codes_10g & 1411 (IXGBE_SFF_10GBASESR_CAPABLE | 1412 IXGBE_SFF_10GBASELR_CAPABLE)) { 1413 if (hw->bus.lan_id == 0) 1414 hw->phy.sfp_type = 1415 ixgbe_sfp_type_srlr_core0; 1416 else 1417 hw->phy.sfp_type = 1418 ixgbe_sfp_type_srlr_core1; 1419 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1420 if (hw->bus.lan_id == 0) 1421 hw->phy.sfp_type = 1422 ixgbe_sfp_type_1g_cu_core0; 1423 else 1424 hw->phy.sfp_type = 1425 ixgbe_sfp_type_1g_cu_core1; 1426 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1427 if (hw->bus.lan_id == 0) 1428 hw->phy.sfp_type = 1429 ixgbe_sfp_type_1g_sx_core0; 1430 else 1431 hw->phy.sfp_type = 1432 ixgbe_sfp_type_1g_sx_core1; 1433 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1434 if (hw->bus.lan_id == 0) 1435 hw->phy.sfp_type = 1436 ixgbe_sfp_type_1g_lx_core0; 1437 else 1438 hw->phy.sfp_type = 1439 ixgbe_sfp_type_1g_lx_core1; 1440 } else if (comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) { 1441 if (hw->bus.lan_id == 0) 1442 hw->phy.sfp_type = 1443 ixgbe_sfp_type_1g_bx_core0; 1444 else 1445 hw->phy.sfp_type = 1446 ixgbe_sfp_type_1g_bx_core1; 1447 } else { 1448 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1449 } 1450 } 1451 1452 if (hw->phy.sfp_type != stored_sfp_type) 1453 hw->phy.sfp_setup_needed = true; 1454 1455 /* Determine if the SFP+ PHY is dual speed or not. */ 1456 hw->phy.multispeed_fiber = false; 1457 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1458 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1459 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1460 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)) || 1461 (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) || 1462 (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)) 1463 hw->phy.multispeed_fiber = true; 1464 1465 /* Determine PHY vendor */ 1466 if (hw->phy.type != ixgbe_phy_nl) { 1467 hw->phy.id = identifier; 1468 status = hw->phy.ops.read_i2c_eeprom(hw, 1469 IXGBE_SFF_VENDOR_OUI_BYTE0, 1470 &oui_bytes[0]); 1471 1472 if (status != IXGBE_SUCCESS) 1473 goto err_read_i2c_eeprom; 1474 1475 status = hw->phy.ops.read_i2c_eeprom(hw, 1476 IXGBE_SFF_VENDOR_OUI_BYTE1, 1477 &oui_bytes[1]); 1478 1479 if (status != IXGBE_SUCCESS) 1480 goto err_read_i2c_eeprom; 1481 1482 status = hw->phy.ops.read_i2c_eeprom(hw, 1483 IXGBE_SFF_VENDOR_OUI_BYTE2, 1484 &oui_bytes[2]); 1485 1486 if (status != IXGBE_SUCCESS) 1487 goto err_read_i2c_eeprom; 1488 1489 vendor_oui = 1490 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1491 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1492 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1493 1494 switch (vendor_oui) { 1495 case IXGBE_SFF_VENDOR_OUI_TYCO: 1496 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1497 hw->phy.type = 1498 ixgbe_phy_sfp_passive_tyco; 1499 break; 1500 case IXGBE_SFF_VENDOR_OUI_FTL: 1501 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1502 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1503 else 1504 hw->phy.type = ixgbe_phy_sfp_ftl; 1505 break; 1506 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1507 hw->phy.type = ixgbe_phy_sfp_avago; 1508 break; 1509 case IXGBE_SFF_VENDOR_OUI_INTEL: 1510 hw->phy.type = ixgbe_phy_sfp_intel; 1511 break; 1512 default: 1513 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1514 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1515 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1516 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1517 else 1518 hw->phy.type = ixgbe_phy_sfp_unknown; 1519 break; 1520 } 1521 } 1522 1523 /* Allow any DA cable vendor */ 1524 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1525 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1526 status = IXGBE_SUCCESS; 1527 goto out; 1528 } 1529 1530 /* Verify supported 1G SFP modules */ 1531 if (comp_codes_10g == 0 && 1532 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || 1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) { 1540 hw->phy.type = ixgbe_phy_sfp_unsupported; 1541 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1542 goto out; 1543 } 1544 1545 /* Anything else 82598-based is supported */ 1546 if (hw->mac.type == ixgbe_mac_82598EB) { 1547 status = IXGBE_SUCCESS; 1548 goto out; 1549 } 1550 1551 ixgbe_get_device_caps(hw, &enforce_sfp); 1552 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1553 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1554 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1555 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1556 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1557 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1558 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) { 1561 /* Make sure we're a supported PHY type */ 1562 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1563 status = IXGBE_SUCCESS; 1564 } else { 1565 if (hw->allow_unsupported_sfp == true) { 1566 if (!warned_once) 1567 EWARN(hw, 1568 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1569 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1570 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1571 warned_once = true; 1572 status = IXGBE_SUCCESS; 1573 } else { 1574 DEBUGOUT 1575 ("SFP+ module not supported\n"); 1576 hw->phy.type = 1577 ixgbe_phy_sfp_unsupported; 1578 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1579 } 1580 } 1581 } else { 1582 status = IXGBE_SUCCESS; 1583 } 1584 } 1585 1586 out: 1587 return status; 1588 1589 err_read_i2c_eeprom: 1590 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1591 if (hw->phy.type != ixgbe_phy_nl) { 1592 hw->phy.id = 0; 1593 hw->phy.type = ixgbe_phy_unknown; 1594 } 1595 return IXGBE_ERR_SFP_NOT_PRESENT; 1596 } 1597 1598 /** 1599 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1600 * @hw: pointer to hardware structure 1601 * 1602 * Determines physical layer capabilities of the current SFP. 1603 */ 1604 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1605 { 1606 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1607 u8 comp_codes_10g = 0; 1608 u8 comp_codes_1g = 0; 1609 1610 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1611 1612 hw->phy.ops.identify_sfp(hw); 1613 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1614 return physical_layer; 1615 1616 switch (hw->phy.type) { 1617 case ixgbe_phy_sfp_passive_tyco: 1618 case ixgbe_phy_sfp_passive_unknown: 1619 case ixgbe_phy_qsfp_passive_unknown: 1620 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1621 break; 1622 case ixgbe_phy_sfp_ftl_active: 1623 case ixgbe_phy_sfp_active_unknown: 1624 case ixgbe_phy_qsfp_active_unknown: 1625 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1626 break; 1627 case ixgbe_phy_sfp_avago: 1628 case ixgbe_phy_sfp_ftl: 1629 case ixgbe_phy_sfp_intel: 1630 case ixgbe_phy_sfp_unknown: 1631 hw->phy.ops.read_i2c_eeprom(hw, 1632 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1633 hw->phy.ops.read_i2c_eeprom(hw, 1634 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1635 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1636 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1637 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1638 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1639 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1640 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1641 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1642 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1643 else if (comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) 1644 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1645 break; 1646 case ixgbe_phy_qsfp_intel: 1647 case ixgbe_phy_qsfp_unknown: 1648 hw->phy.ops.read_i2c_eeprom(hw, 1649 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1650 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1651 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1652 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1653 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1654 break; 1655 default: 1656 break; 1657 } 1658 1659 return physical_layer; 1660 } 1661 1662 /** 1663 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1664 * @hw: pointer to hardware structure 1665 * 1666 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1667 **/ 1668 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1669 { 1670 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1671 u32 vendor_oui = 0; 1672 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1673 u8 identifier = 0; 1674 u8 comp_codes_1g = 0; 1675 u8 comp_codes_10g = 0; 1676 u8 oui_bytes[3] = {0, 0, 0}; 1677 u16 enforce_sfp = 0; 1678 u8 connector = 0; 1679 u8 cable_length = 0; 1680 u8 device_tech = 0; 1681 bool active_cable = false; 1682 static bool warned_once = false; 1683 1684 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1685 1686 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1687 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1688 status = IXGBE_ERR_SFP_NOT_PRESENT; 1689 goto out; 1690 } 1691 1692 /* LAN ID is needed for I2C access */ 1693 hw->mac.ops.set_lan_id(hw); 1694 1695 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1696 &identifier); 1697 1698 if (status != IXGBE_SUCCESS) 1699 goto err_read_i2c_eeprom; 1700 1701 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1702 hw->phy.type = ixgbe_phy_sfp_unsupported; 1703 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1704 goto out; 1705 } 1706 1707 hw->phy.id = identifier; 1708 1709 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1710 &comp_codes_10g); 1711 1712 if (status != IXGBE_SUCCESS) 1713 goto err_read_i2c_eeprom; 1714 1715 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1716 &comp_codes_1g); 1717 1718 if (status != IXGBE_SUCCESS) 1719 goto err_read_i2c_eeprom; 1720 1721 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1722 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1723 if (hw->bus.lan_id == 0) 1724 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1725 else 1726 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1727 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1728 IXGBE_SFF_10GBASELR_CAPABLE)) { 1729 if (hw->bus.lan_id == 0) 1730 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1731 else 1732 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1733 } else { 1734 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1735 active_cable = true; 1736 1737 if (!active_cable) { 1738 /* check for active DA cables that pre-date 1739 * SFF-8436 v3.6 */ 1740 hw->phy.ops.read_i2c_eeprom(hw, 1741 IXGBE_SFF_QSFP_CONNECTOR, 1742 &connector); 1743 1744 hw->phy.ops.read_i2c_eeprom(hw, 1745 IXGBE_SFF_QSFP_CABLE_LENGTH, 1746 &cable_length); 1747 1748 hw->phy.ops.read_i2c_eeprom(hw, 1749 IXGBE_SFF_QSFP_DEVICE_TECH, 1750 &device_tech); 1751 1752 if ((connector == 1753 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1754 (cable_length > 0) && 1755 ((device_tech >> 4) == 1756 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1757 active_cable = true; 1758 } 1759 1760 if (active_cable) { 1761 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1762 if (hw->bus.lan_id == 0) 1763 hw->phy.sfp_type = 1764 ixgbe_sfp_type_da_act_lmt_core0; 1765 else 1766 hw->phy.sfp_type = 1767 ixgbe_sfp_type_da_act_lmt_core1; 1768 } else { 1769 /* unsupported module type */ 1770 hw->phy.type = ixgbe_phy_sfp_unsupported; 1771 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1772 goto out; 1773 } 1774 } 1775 1776 if (hw->phy.sfp_type != stored_sfp_type) 1777 hw->phy.sfp_setup_needed = true; 1778 1779 /* Determine if the QSFP+ PHY is dual speed or not. */ 1780 hw->phy.multispeed_fiber = false; 1781 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1782 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1783 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1784 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1785 hw->phy.multispeed_fiber = true; 1786 1787 /* Determine PHY vendor for optical modules */ 1788 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1789 IXGBE_SFF_10GBASELR_CAPABLE)) { 1790 status = hw->phy.ops.read_i2c_eeprom(hw, 1791 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1792 &oui_bytes[0]); 1793 1794 if (status != IXGBE_SUCCESS) 1795 goto err_read_i2c_eeprom; 1796 1797 status = hw->phy.ops.read_i2c_eeprom(hw, 1798 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1799 &oui_bytes[1]); 1800 1801 if (status != IXGBE_SUCCESS) 1802 goto err_read_i2c_eeprom; 1803 1804 status = hw->phy.ops.read_i2c_eeprom(hw, 1805 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1806 &oui_bytes[2]); 1807 1808 if (status != IXGBE_SUCCESS) 1809 goto err_read_i2c_eeprom; 1810 1811 vendor_oui = 1812 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1813 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1814 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1815 1816 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1817 hw->phy.type = ixgbe_phy_qsfp_intel; 1818 else 1819 hw->phy.type = ixgbe_phy_qsfp_unknown; 1820 1821 ixgbe_get_device_caps(hw, &enforce_sfp); 1822 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1823 /* Make sure we're a supported PHY type */ 1824 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1825 status = IXGBE_SUCCESS; 1826 } else { 1827 if (hw->allow_unsupported_sfp == true) { 1828 if (!warned_once) 1829 EWARN(hw, 1830 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1831 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1832 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1833 warned_once = true; 1834 status = IXGBE_SUCCESS; 1835 } else { 1836 DEBUGOUT("QSFP module not supported\n"); 1837 hw->phy.type = 1838 ixgbe_phy_sfp_unsupported; 1839 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1840 } 1841 } 1842 } else { 1843 status = IXGBE_SUCCESS; 1844 } 1845 } 1846 1847 out: 1848 return status; 1849 1850 err_read_i2c_eeprom: 1851 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1852 hw->phy.id = 0; 1853 hw->phy.type = ixgbe_phy_unknown; 1854 1855 return IXGBE_ERR_SFP_NOT_PRESENT; 1856 } 1857 1858 /** 1859 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1860 * @hw: pointer to hardware structure 1861 * @list_offset: offset to the SFP ID list 1862 * @data_offset: offset to the SFP data block 1863 * 1864 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1865 * so it returns the offsets to the phy init sequence block. 1866 **/ 1867 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1868 u16 *list_offset, 1869 u16 *data_offset) 1870 { 1871 u16 sfp_id; 1872 u16 sfp_type = hw->phy.sfp_type; 1873 1874 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1875 1876 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1877 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1878 1879 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1880 return IXGBE_ERR_SFP_NOT_PRESENT; 1881 1882 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1883 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1884 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1885 1886 /* 1887 * Limiting active cables and 1G Phys must be initialized as 1888 * SR modules 1889 */ 1890 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1891 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1892 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1893 sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1894 sfp_type == ixgbe_sfp_type_1g_bx_core0) 1895 sfp_type = ixgbe_sfp_type_srlr_core0; 1896 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1897 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1898 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1899 sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1900 sfp_type == ixgbe_sfp_type_1g_bx_core1) 1901 sfp_type = ixgbe_sfp_type_srlr_core1; 1902 1903 /* Read offset to PHY init contents */ 1904 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1905 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1906 "eeprom read at offset %d failed", 1907 IXGBE_PHY_INIT_OFFSET_NL); 1908 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1909 } 1910 1911 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1912 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1913 1914 /* Shift offset to first ID word */ 1915 (*list_offset)++; 1916 1917 /* 1918 * Find the matching SFP ID in the EEPROM 1919 * and program the init sequence 1920 */ 1921 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1922 goto err_phy; 1923 1924 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1925 if (sfp_id == sfp_type) { 1926 (*list_offset)++; 1927 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1928 goto err_phy; 1929 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1930 DEBUGOUT("SFP+ module not supported\n"); 1931 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1932 } else { 1933 break; 1934 } 1935 } else { 1936 (*list_offset) += 2; 1937 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1938 goto err_phy; 1939 } 1940 } 1941 1942 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1943 DEBUGOUT("No matching SFP+ module found\n"); 1944 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1945 } 1946 1947 return IXGBE_SUCCESS; 1948 1949 err_phy: 1950 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1951 "eeprom read at offset %d failed", *list_offset); 1952 return IXGBE_ERR_PHY; 1953 } 1954 1955 /** 1956 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1957 * @hw: pointer to hardware structure 1958 * @byte_offset: EEPROM byte offset to read 1959 * @eeprom_data: value read 1960 * 1961 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1962 **/ 1963 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1964 u8 *eeprom_data) 1965 { 1966 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1967 1968 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1969 IXGBE_I2C_EEPROM_DEV_ADDR, 1970 eeprom_data); 1971 } 1972 1973 /** 1974 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1975 * @hw: pointer to hardware structure 1976 * @byte_offset: byte offset at address 0xA2 1977 * @sff8472_data: value read 1978 * 1979 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1980 **/ 1981 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1982 u8 *sff8472_data) 1983 { 1984 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1985 IXGBE_I2C_EEPROM_DEV_ADDR2, 1986 sff8472_data); 1987 } 1988 1989 /** 1990 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1991 * @hw: pointer to hardware structure 1992 * @byte_offset: EEPROM byte offset to write 1993 * @eeprom_data: value to write 1994 * 1995 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1996 **/ 1997 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1998 u8 eeprom_data) 1999 { 2000 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2001 2002 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2003 IXGBE_I2C_EEPROM_DEV_ADDR, 2004 eeprom_data); 2005 } 2006 2007 /** 2008 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 2009 * @hw: pointer to hardware structure 2010 * @offset: eeprom offset to be read 2011 * @addr: I2C address to be read 2012 */ 2013 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2014 { 2015 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2016 offset == IXGBE_SFF_IDENTIFIER && 2017 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2018 return true; 2019 return false; 2020 } 2021 2022 /** 2023 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2024 * @hw: pointer to hardware structure 2025 * @byte_offset: byte offset to read 2026 * @dev_addr: address to read from 2027 * @data: value read 2028 * @lock: true if to take and release semaphore 2029 * 2030 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2031 * a specified device address. 2032 **/ 2033 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2034 u8 dev_addr, u8 *data, bool lock) 2035 { 2036 s32 status; 2037 u32 max_retry = 10; 2038 u32 retry = 0; 2039 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2040 bool nack = 1; 2041 *data = 0; 2042 2043 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2044 2045 if (hw->mac.type >= ixgbe_mac_X550) 2046 max_retry = 3; 2047 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2048 max_retry = IXGBE_SFP_DETECT_RETRIES; 2049 2050 do { 2051 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2052 return IXGBE_ERR_SWFW_SYNC; 2053 2054 ixgbe_i2c_start(hw); 2055 2056 /* Device Address and write indication */ 2057 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2058 if (status != IXGBE_SUCCESS) 2059 goto fail; 2060 2061 status = ixgbe_get_i2c_ack(hw); 2062 if (status != IXGBE_SUCCESS) 2063 goto fail; 2064 2065 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2066 if (status != IXGBE_SUCCESS) 2067 goto fail; 2068 2069 status = ixgbe_get_i2c_ack(hw); 2070 if (status != IXGBE_SUCCESS) 2071 goto fail; 2072 2073 ixgbe_i2c_start(hw); 2074 2075 /* Device Address and read indication */ 2076 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2077 if (status != IXGBE_SUCCESS) 2078 goto fail; 2079 2080 status = ixgbe_get_i2c_ack(hw); 2081 if (status != IXGBE_SUCCESS) 2082 goto fail; 2083 2084 ixgbe_clock_in_i2c_byte(hw, data); 2085 2086 status = ixgbe_clock_out_i2c_bit(hw, nack); 2087 if (status != IXGBE_SUCCESS) 2088 goto fail; 2089 2090 ixgbe_i2c_stop(hw); 2091 if (lock) 2092 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2093 return IXGBE_SUCCESS; 2094 2095 fail: 2096 ixgbe_i2c_bus_clear(hw); 2097 if (lock) { 2098 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2099 msec_delay(100); 2100 } 2101 if (retry < max_retry) 2102 DEBUGOUT("I2C byte read error - Retrying.\n"); 2103 else 2104 DEBUGOUT("I2C byte read error.\n"); 2105 retry++; 2106 } while (retry <= max_retry); 2107 2108 return status; 2109 } 2110 2111 /** 2112 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2113 * @hw: pointer to hardware structure 2114 * @byte_offset: byte offset to read 2115 * @dev_addr: address to read from 2116 * @data: value read 2117 * 2118 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2119 * a specified device address. 2120 **/ 2121 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2122 u8 dev_addr, u8 *data) 2123 { 2124 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2125 data, true); 2126 } 2127 2128 /** 2129 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2130 * @hw: pointer to hardware structure 2131 * @byte_offset: byte offset to read 2132 * @dev_addr: address to read from 2133 * @data: value read 2134 * 2135 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2136 * a specified device address. 2137 **/ 2138 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2139 u8 dev_addr, u8 *data) 2140 { 2141 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2142 data, false); 2143 } 2144 2145 /** 2146 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2147 * @hw: pointer to hardware structure 2148 * @byte_offset: byte offset to write 2149 * @dev_addr: address to write to 2150 * @data: value to write 2151 * @lock: true if to take and release semaphore 2152 * 2153 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2154 * a specified device address. 2155 **/ 2156 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2157 u8 dev_addr, u8 data, bool lock) 2158 { 2159 s32 status; 2160 u32 max_retry = 1; 2161 u32 retry = 0; 2162 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2163 2164 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2165 2166 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2167 IXGBE_SUCCESS) 2168 return IXGBE_ERR_SWFW_SYNC; 2169 2170 do { 2171 ixgbe_i2c_start(hw); 2172 2173 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2174 if (status != IXGBE_SUCCESS) 2175 goto fail; 2176 2177 status = ixgbe_get_i2c_ack(hw); 2178 if (status != IXGBE_SUCCESS) 2179 goto fail; 2180 2181 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2182 if (status != IXGBE_SUCCESS) 2183 goto fail; 2184 2185 status = ixgbe_get_i2c_ack(hw); 2186 if (status != IXGBE_SUCCESS) 2187 goto fail; 2188 2189 status = ixgbe_clock_out_i2c_byte(hw, data); 2190 if (status != IXGBE_SUCCESS) 2191 goto fail; 2192 2193 status = ixgbe_get_i2c_ack(hw); 2194 if (status != IXGBE_SUCCESS) 2195 goto fail; 2196 2197 ixgbe_i2c_stop(hw); 2198 if (lock) 2199 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2200 return IXGBE_SUCCESS; 2201 2202 fail: 2203 ixgbe_i2c_bus_clear(hw); 2204 if (retry < max_retry) 2205 DEBUGOUT("I2C byte write error - Retrying.\n"); 2206 else 2207 DEBUGOUT("I2C byte write error.\n"); 2208 retry++; 2209 } while (retry <= max_retry); 2210 2211 if (lock) 2212 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2213 2214 return status; 2215 } 2216 2217 /** 2218 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2219 * @hw: pointer to hardware structure 2220 * @byte_offset: byte offset to write 2221 * @dev_addr: address to write to 2222 * @data: value to write 2223 * 2224 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2225 * a specified device address. 2226 **/ 2227 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2228 u8 dev_addr, u8 data) 2229 { 2230 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2231 data, true); 2232 } 2233 2234 /** 2235 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2236 * @hw: pointer to hardware structure 2237 * @byte_offset: byte offset to write 2238 * @dev_addr: address to write to 2239 * @data: value to write 2240 * 2241 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2242 * a specified device address. 2243 **/ 2244 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2245 u8 dev_addr, u8 data) 2246 { 2247 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2248 data, false); 2249 } 2250 2251 /** 2252 * ixgbe_i2c_start - Sets I2C start condition 2253 * @hw: pointer to hardware structure 2254 * 2255 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2256 * Set bit-bang mode on X550 hardware. 2257 **/ 2258 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2259 { 2260 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2261 2262 DEBUGFUNC("ixgbe_i2c_start"); 2263 2264 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2265 2266 /* Start condition must begin with data and clock high */ 2267 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2268 ixgbe_raise_i2c_clk(hw, &i2cctl); 2269 2270 /* Setup time for start condition (4.7us) */ 2271 usec_delay(IXGBE_I2C_T_SU_STA); 2272 2273 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2274 2275 /* Hold time for start condition (4us) */ 2276 usec_delay(IXGBE_I2C_T_HD_STA); 2277 2278 ixgbe_lower_i2c_clk(hw, &i2cctl); 2279 2280 /* Minimum low period of clock is 4.7 us */ 2281 usec_delay(IXGBE_I2C_T_LOW); 2282 2283 } 2284 2285 /** 2286 * ixgbe_i2c_stop - Sets I2C stop condition 2287 * @hw: pointer to hardware structure 2288 * 2289 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2290 * Disables bit-bang mode and negates data output enable on X550 2291 * hardware. 2292 **/ 2293 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2294 { 2295 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2296 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2297 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2298 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2299 2300 DEBUGFUNC("ixgbe_i2c_stop"); 2301 2302 /* Stop condition must begin with data low and clock high */ 2303 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2304 ixgbe_raise_i2c_clk(hw, &i2cctl); 2305 2306 /* Setup time for stop condition (4us) */ 2307 usec_delay(IXGBE_I2C_T_SU_STO); 2308 2309 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2310 2311 /* bus free time between stop and start (4.7us)*/ 2312 usec_delay(IXGBE_I2C_T_BUF); 2313 2314 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2315 i2cctl &= ~bb_en_bit; 2316 i2cctl |= data_oe_bit | clk_oe_bit; 2317 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2318 IXGBE_WRITE_FLUSH(hw); 2319 } 2320 } 2321 2322 /** 2323 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2324 * @hw: pointer to hardware structure 2325 * @data: data byte to clock in 2326 * 2327 * Clocks in one byte data via I2C data/clock 2328 **/ 2329 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2330 { 2331 s32 i; 2332 bool bit = 0; 2333 2334 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2335 2336 *data = 0; 2337 for (i = 7; i >= 0; i--) { 2338 ixgbe_clock_in_i2c_bit(hw, &bit); 2339 *data |= bit << i; 2340 } 2341 } 2342 2343 /** 2344 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2345 * @hw: pointer to hardware structure 2346 * @data: data byte clocked out 2347 * 2348 * Clocks out one byte data via I2C data/clock 2349 **/ 2350 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2351 { 2352 s32 status = IXGBE_SUCCESS; 2353 s32 i; 2354 u32 i2cctl; 2355 bool bit; 2356 2357 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2358 2359 for (i = 7; i >= 0; i--) { 2360 bit = (data >> i) & 0x1; 2361 status = ixgbe_clock_out_i2c_bit(hw, bit); 2362 2363 if (status != IXGBE_SUCCESS) 2364 break; 2365 } 2366 2367 /* Release SDA line (set high) */ 2368 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2369 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2370 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2371 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2372 IXGBE_WRITE_FLUSH(hw); 2373 2374 return status; 2375 } 2376 2377 /** 2378 * ixgbe_get_i2c_ack - Polls for I2C ACK 2379 * @hw: pointer to hardware structure 2380 * 2381 * Clocks in/out one bit via I2C data/clock 2382 **/ 2383 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2384 { 2385 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2386 s32 status = IXGBE_SUCCESS; 2387 u32 i = 0; 2388 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2389 u32 timeout = 10; 2390 bool ack = 1; 2391 2392 DEBUGFUNC("ixgbe_get_i2c_ack"); 2393 2394 if (data_oe_bit) { 2395 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2396 i2cctl |= data_oe_bit; 2397 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2398 IXGBE_WRITE_FLUSH(hw); 2399 } 2400 ixgbe_raise_i2c_clk(hw, &i2cctl); 2401 2402 /* Minimum high period of clock is 4us */ 2403 usec_delay(IXGBE_I2C_T_HIGH); 2404 2405 /* Poll for ACK. Note that ACK in I2C spec is 2406 * transition from 1 to 0 */ 2407 for (i = 0; i < timeout; i++) { 2408 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2409 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2410 2411 usec_delay(1); 2412 if (!ack) 2413 break; 2414 } 2415 2416 if (ack) { 2417 DEBUGOUT("I2C ack was not received.\n"); 2418 status = IXGBE_ERR_I2C; 2419 } 2420 2421 ixgbe_lower_i2c_clk(hw, &i2cctl); 2422 2423 /* Minimum low period of clock is 4.7 us */ 2424 usec_delay(IXGBE_I2C_T_LOW); 2425 2426 return status; 2427 } 2428 2429 /** 2430 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2431 * @hw: pointer to hardware structure 2432 * @data: read data value 2433 * 2434 * Clocks in one bit via I2C data/clock 2435 **/ 2436 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2437 { 2438 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2439 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2440 2441 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2442 2443 if (data_oe_bit) { 2444 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2445 i2cctl |= data_oe_bit; 2446 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2447 IXGBE_WRITE_FLUSH(hw); 2448 } 2449 ixgbe_raise_i2c_clk(hw, &i2cctl); 2450 2451 /* Minimum high period of clock is 4us */ 2452 usec_delay(IXGBE_I2C_T_HIGH); 2453 2454 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2455 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2456 2457 ixgbe_lower_i2c_clk(hw, &i2cctl); 2458 2459 /* Minimum low period of clock is 4.7 us */ 2460 usec_delay(IXGBE_I2C_T_LOW); 2461 } 2462 2463 /** 2464 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2465 * @hw: pointer to hardware structure 2466 * @data: data value to write 2467 * 2468 * Clocks out one bit via I2C data/clock 2469 **/ 2470 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2471 { 2472 s32 status; 2473 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2474 2475 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2476 2477 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2478 if (status == IXGBE_SUCCESS) { 2479 ixgbe_raise_i2c_clk(hw, &i2cctl); 2480 2481 /* Minimum high period of clock is 4us */ 2482 usec_delay(IXGBE_I2C_T_HIGH); 2483 2484 ixgbe_lower_i2c_clk(hw, &i2cctl); 2485 2486 /* Minimum low period of clock is 4.7 us. 2487 * This also takes care of the data hold time. 2488 */ 2489 usec_delay(IXGBE_I2C_T_LOW); 2490 } else { 2491 status = IXGBE_ERR_I2C; 2492 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2493 "I2C data was not set to %X\n", data); 2494 } 2495 2496 return status; 2497 } 2498 2499 /** 2500 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2501 * @hw: pointer to hardware structure 2502 * @i2cctl: Current value of I2CCTL register 2503 * 2504 * Raises the I2C clock line '0'->'1' 2505 * Negates the I2C clock output enable on X550 hardware. 2506 **/ 2507 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2508 { 2509 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2510 u32 i = 0; 2511 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2512 u32 i2cctl_r = 0; 2513 2514 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2515 2516 if (clk_oe_bit) { 2517 *i2cctl |= clk_oe_bit; 2518 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2519 } 2520 2521 for (i = 0; i < timeout; i++) { 2522 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2523 2524 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2525 IXGBE_WRITE_FLUSH(hw); 2526 /* SCL rise time (1000ns) */ 2527 usec_delay(IXGBE_I2C_T_RISE); 2528 2529 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2530 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2531 break; 2532 } 2533 } 2534 2535 /** 2536 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2537 * @hw: pointer to hardware structure 2538 * @i2cctl: Current value of I2CCTL register 2539 * 2540 * Lowers the I2C clock line '1'->'0' 2541 * Asserts the I2C clock output enable on X550 hardware. 2542 **/ 2543 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2544 { 2545 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2546 2547 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2548 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2549 2550 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2551 IXGBE_WRITE_FLUSH(hw); 2552 2553 /* SCL fall time (300ns) */ 2554 usec_delay(IXGBE_I2C_T_FALL); 2555 } 2556 2557 /** 2558 * ixgbe_set_i2c_data - Sets the I2C data bit 2559 * @hw: pointer to hardware structure 2560 * @i2cctl: Current value of I2CCTL register 2561 * @data: I2C data value (0 or 1) to set 2562 * 2563 * Sets the I2C data bit 2564 * Asserts the I2C data output enable on X550 hardware. 2565 **/ 2566 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2567 { 2568 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2569 s32 status = IXGBE_SUCCESS; 2570 2571 DEBUGFUNC("ixgbe_set_i2c_data"); 2572 2573 if (data) 2574 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2575 else 2576 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2577 *i2cctl &= ~data_oe_bit; 2578 2579 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2580 IXGBE_WRITE_FLUSH(hw); 2581 2582 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2583 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2584 2585 if (!data) /* Can't verify data in this case */ 2586 return IXGBE_SUCCESS; 2587 if (data_oe_bit) { 2588 *i2cctl |= data_oe_bit; 2589 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2590 IXGBE_WRITE_FLUSH(hw); 2591 } 2592 2593 /* Verify data was set correctly */ 2594 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2595 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2596 status = IXGBE_ERR_I2C; 2597 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2598 "Error - I2C data was not set to %X.\n", 2599 data); 2600 } 2601 2602 return status; 2603 } 2604 2605 /** 2606 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2607 * @hw: pointer to hardware structure 2608 * @i2cctl: Current value of I2CCTL register 2609 * 2610 * Returns the I2C data bit value 2611 * Negates the I2C data output enable on X550 hardware. 2612 **/ 2613 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2614 { 2615 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2616 bool data; 2617 2618 DEBUGFUNC("ixgbe_get_i2c_data"); 2619 2620 if (data_oe_bit) { 2621 *i2cctl |= data_oe_bit; 2622 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2623 IXGBE_WRITE_FLUSH(hw); 2624 usec_delay(IXGBE_I2C_T_FALL); 2625 } 2626 2627 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2628 data = 1; 2629 else 2630 data = 0; 2631 2632 return data; 2633 } 2634 2635 /** 2636 * ixgbe_i2c_bus_clear - Clears the I2C bus 2637 * @hw: pointer to hardware structure 2638 * 2639 * Clears the I2C bus by sending nine clock pulses. 2640 * Used when data line is stuck low. 2641 **/ 2642 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2643 { 2644 u32 i2cctl; 2645 u32 i; 2646 2647 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2648 2649 ixgbe_i2c_start(hw); 2650 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2651 2652 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2653 2654 for (i = 0; i < 9; i++) { 2655 ixgbe_raise_i2c_clk(hw, &i2cctl); 2656 2657 /* Min high period of clock is 4us */ 2658 usec_delay(IXGBE_I2C_T_HIGH); 2659 2660 ixgbe_lower_i2c_clk(hw, &i2cctl); 2661 2662 /* Min low period of clock is 4.7us*/ 2663 usec_delay(IXGBE_I2C_T_LOW); 2664 } 2665 2666 ixgbe_i2c_start(hw); 2667 2668 /* Put the i2c bus back to default state */ 2669 ixgbe_i2c_stop(hw); 2670 } 2671 2672 /** 2673 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2674 * @hw: pointer to hardware structure 2675 * 2676 * Checks if the LASI temp alarm status was triggered due to overtemp 2677 **/ 2678 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2679 { 2680 s32 status = IXGBE_SUCCESS; 2681 u16 phy_data = 0; 2682 2683 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2684 2685 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2686 goto out; 2687 2688 /* Check that the LASI temp alarm status was triggered */ 2689 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2690 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2691 2692 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2693 goto out; 2694 2695 status = IXGBE_ERR_OVERTEMP; 2696 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2697 out: 2698 return status; 2699 } 2700 2701 /** 2702 * ixgbe_set_copper_phy_power - Control power for copper phy 2703 * @hw: pointer to hardware structure 2704 * @on: true for on, false for off 2705 */ 2706 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2707 { 2708 u32 status; 2709 u16 reg; 2710 2711 if (!on && ixgbe_mng_present(hw)) 2712 return 0; 2713 2714 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2715 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2716 ®); 2717 if (status) 2718 return status; 2719 2720 if (on) { 2721 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2722 } else { 2723 if (ixgbe_check_reset_blocked(hw)) 2724 return 0; 2725 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2726 } 2727 2728 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2729 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2730 reg); 2731 return status; 2732 } 2733