1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(u32 *i2cctl); 50 51 /** 52 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 53 * @hw: pointer to the hardware structure 54 * 55 * Initialize the function pointers. 56 **/ 57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 58 { 59 struct ixgbe_phy_info *phy = &hw->phy; 60 61 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 62 63 /* PHY */ 64 phy->ops.identify = &ixgbe_identify_phy_generic; 65 phy->ops.reset = &ixgbe_reset_phy_generic; 66 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 67 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 68 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 69 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 70 phy->ops.check_link = NULL; 71 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 72 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 73 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 74 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 75 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 76 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 77 phy->ops.identify_sfp = &ixgbe_identify_module_generic; 78 phy->sfp_type = ixgbe_sfp_type_unknown; 79 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 80 return IXGBE_SUCCESS; 81 } 82 83 /** 84 * ixgbe_identify_phy_generic - Get physical layer module 85 * @hw: pointer to hardware structure 86 * 87 * Determines the physical layer module found on the current adapter. 88 **/ 89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 90 { 91 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 92 u32 phy_addr; 93 u16 ext_ability = 0; 94 95 DEBUGFUNC("ixgbe_identify_phy_generic"); 96 97 if (hw->phy.type == ixgbe_phy_unknown) { 98 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 99 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 100 hw->phy.addr = phy_addr; 101 ixgbe_get_phy_id(hw); 102 hw->phy.type = 103 ixgbe_get_phy_type_from_id(hw->phy.id); 104 105 if (hw->phy.type == ixgbe_phy_unknown) { 106 hw->phy.ops.read_reg(hw, 107 IXGBE_MDIO_PHY_EXT_ABILITY, 108 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 109 &ext_ability); 110 if (ext_ability & 111 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 112 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 113 hw->phy.type = 114 ixgbe_phy_cu_unknown; 115 else 116 hw->phy.type = 117 ixgbe_phy_generic; 118 } 119 120 status = IXGBE_SUCCESS; 121 break; 122 } 123 } 124 /* clear value if nothing found */ 125 if (status != IXGBE_SUCCESS) 126 hw->phy.addr = 0; 127 } else { 128 status = IXGBE_SUCCESS; 129 } 130 131 return status; 132 } 133 134 /** 135 * ixgbe_validate_phy_addr - Determines phy address is valid 136 * @hw: pointer to hardware structure 137 * 138 **/ 139 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 140 { 141 u16 phy_id = 0; 142 bool valid = FALSE; 143 144 DEBUGFUNC("ixgbe_validate_phy_addr"); 145 146 hw->phy.addr = phy_addr; 147 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 148 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 149 150 if (phy_id != 0xFFFF && phy_id != 0x0) 151 valid = TRUE; 152 153 return valid; 154 } 155 156 /** 157 * ixgbe_get_phy_id - Get the phy type 158 * @hw: pointer to hardware structure 159 * 160 **/ 161 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 162 { 163 u32 status; 164 u16 phy_id_high = 0; 165 u16 phy_id_low = 0; 166 167 DEBUGFUNC("ixgbe_get_phy_id"); 168 169 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 170 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 171 &phy_id_high); 172 173 if (status == IXGBE_SUCCESS) { 174 hw->phy.id = (u32)(phy_id_high << 16); 175 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 176 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 177 &phy_id_low); 178 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 179 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 180 } 181 return status; 182 } 183 184 /** 185 * ixgbe_get_phy_type_from_id - Get the phy type 186 * @hw: pointer to hardware structure 187 * 188 **/ 189 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 190 { 191 enum ixgbe_phy_type phy_type; 192 193 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 194 195 switch (phy_id) { 196 case TN1010_PHY_ID: 197 phy_type = ixgbe_phy_tn; 198 break; 199 case X540_PHY_ID: 200 phy_type = ixgbe_phy_aq; 201 break; 202 case QT2022_PHY_ID: 203 phy_type = ixgbe_phy_qt; 204 break; 205 case ATH_PHY_ID: 206 phy_type = ixgbe_phy_nl; 207 break; 208 default: 209 phy_type = ixgbe_phy_unknown; 210 break; 211 } 212 213 DEBUGOUT1("phy type found is %d\n", phy_type); 214 return phy_type; 215 } 216 217 /** 218 * ixgbe_reset_phy_generic - Performs a PHY reset 219 * @hw: pointer to hardware structure 220 **/ 221 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 222 { 223 u32 i; 224 u16 ctrl = 0; 225 s32 status = IXGBE_SUCCESS; 226 227 DEBUGFUNC("ixgbe_reset_phy_generic"); 228 229 if (hw->phy.type == ixgbe_phy_unknown) 230 status = ixgbe_identify_phy_generic(hw); 231 232 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 233 goto out; 234 235 /* Don't reset PHY if it's shut down due to overtemp. */ 236 if (!hw->phy.reset_if_overtemp && 237 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 238 goto out; 239 240 /* 241 * Perform soft PHY reset to the PHY_XS. 242 * This will cause a soft reset to the PHY 243 */ 244 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 245 IXGBE_MDIO_PHY_XS_DEV_TYPE, 246 IXGBE_MDIO_PHY_XS_RESET); 247 248 /* 249 * Poll for reset bit to self-clear indicating reset is complete. 250 * Some PHYs could take up to 3 seconds to complete and need about 251 * 1.7 usec delay after the reset is complete. 252 */ 253 for (i = 0; i < 30; i++) { 254 msec_delay(100); 255 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 256 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 257 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 258 usec_delay(2); 259 break; 260 } 261 } 262 263 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 264 status = IXGBE_ERR_RESET_FAILED; 265 DEBUGOUT("PHY reset polling failed to complete.\n"); 266 } 267 268 out: 269 return status; 270 } 271 272 /** 273 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 274 * @hw: pointer to hardware structure 275 * @reg_addr: 32 bit address of PHY register to read 276 * @phy_data: Pointer to read data from PHY register 277 **/ 278 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 279 u32 device_type, u16 *phy_data) 280 { 281 u32 command; 282 u32 i; 283 u32 data; 284 s32 status = IXGBE_SUCCESS; 285 u16 gssr; 286 287 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 288 289 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 290 gssr = IXGBE_GSSR_PHY1_SM; 291 else 292 gssr = IXGBE_GSSR_PHY0_SM; 293 294 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 295 status = IXGBE_ERR_SWFW_SYNC; 296 297 if (status == IXGBE_SUCCESS) { 298 /* Setup and write the address cycle command */ 299 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 300 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 301 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 302 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 303 304 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 305 306 /* 307 * Check every 10 usec to see if the address cycle completed. 308 * The MDI Command bit will clear when the operation is 309 * complete 310 */ 311 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 312 usec_delay(10); 313 314 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 315 316 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 317 break; 318 } 319 320 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 321 DEBUGOUT("PHY address command did not complete.\n"); 322 status = IXGBE_ERR_PHY; 323 } 324 325 if (status == IXGBE_SUCCESS) { 326 /* 327 * Address cycle complete, setup and write the read 328 * command 329 */ 330 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 331 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 332 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 333 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 334 335 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 336 337 /* 338 * Check every 10 usec to see if the address cycle 339 * completed. The MDI Command bit will clear when the 340 * operation is complete 341 */ 342 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 343 usec_delay(10); 344 345 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 346 347 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 348 break; 349 } 350 351 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 352 DEBUGOUT("PHY read command didn't complete\n"); 353 status = IXGBE_ERR_PHY; 354 } else { 355 /* 356 * Read operation is complete. Get the data 357 * from MSRWD 358 */ 359 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 360 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 361 *phy_data = (u16)(data); 362 } 363 } 364 365 hw->mac.ops.release_swfw_sync(hw, gssr); 366 } 367 368 return status; 369 } 370 371 /** 372 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 373 * @hw: pointer to hardware structure 374 * @reg_addr: 32 bit PHY register to write 375 * @device_type: 5 bit device type 376 * @phy_data: Data to write to the PHY register 377 **/ 378 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 379 u32 device_type, u16 phy_data) 380 { 381 u32 command; 382 u32 i; 383 s32 status = IXGBE_SUCCESS; 384 u16 gssr; 385 386 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 387 388 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 389 gssr = IXGBE_GSSR_PHY1_SM; 390 else 391 gssr = IXGBE_GSSR_PHY0_SM; 392 393 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 394 status = IXGBE_ERR_SWFW_SYNC; 395 396 if (status == IXGBE_SUCCESS) { 397 /* Put the data in the MDI single read and write data register*/ 398 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 399 400 /* Setup and write the address cycle command */ 401 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 402 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 403 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 404 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 405 406 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 407 408 /* 409 * Check every 10 usec to see if the address cycle completed. 410 * The MDI Command bit will clear when the operation is 411 * complete 412 */ 413 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 414 usec_delay(10); 415 416 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 417 418 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 419 break; 420 } 421 422 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 423 DEBUGOUT("PHY address cmd didn't complete\n"); 424 status = IXGBE_ERR_PHY; 425 } 426 427 if (status == IXGBE_SUCCESS) { 428 /* 429 * Address cycle complete, setup and write the write 430 * command 431 */ 432 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 433 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 434 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 435 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 436 437 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 438 439 /* 440 * Check every 10 usec to see if the address cycle 441 * completed. The MDI Command bit will clear when the 442 * operation is complete 443 */ 444 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 445 usec_delay(10); 446 447 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 448 449 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 450 break; 451 } 452 453 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 454 DEBUGOUT("PHY address cmd didn't complete\n"); 455 status = IXGBE_ERR_PHY; 456 } 457 } 458 459 hw->mac.ops.release_swfw_sync(hw, gssr); 460 } 461 462 return status; 463 } 464 465 /** 466 * ixgbe_setup_phy_link_generic - Set and restart autoneg 467 * @hw: pointer to hardware structure 468 * 469 * Restart autonegotiation and PHY and waits for completion. 470 **/ 471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 472 { 473 s32 status = IXGBE_SUCCESS; 474 u32 time_out; 475 u32 max_time_out = 10; 476 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 477 bool autoneg = FALSE; 478 ixgbe_link_speed speed; 479 480 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 481 482 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 483 484 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 485 /* Set or unset auto-negotiation 10G advertisement */ 486 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 487 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 488 &autoneg_reg); 489 490 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 491 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 492 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 493 494 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 495 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 496 autoneg_reg); 497 } 498 499 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 500 /* Set or unset auto-negotiation 1G advertisement */ 501 hw->phy.ops.read_reg(hw, 502 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 503 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 504 &autoneg_reg); 505 506 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 507 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 508 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 509 510 hw->phy.ops.write_reg(hw, 511 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 512 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 513 autoneg_reg); 514 } 515 516 if (speed & IXGBE_LINK_SPEED_100_FULL) { 517 /* Set or unset auto-negotiation 100M advertisement */ 518 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 519 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 520 &autoneg_reg); 521 522 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 523 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 524 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 525 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 526 527 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 528 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 529 autoneg_reg); 530 } 531 532 /* Restart PHY autonegotiation and wait for completion */ 533 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 534 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 535 536 autoneg_reg |= IXGBE_MII_RESTART; 537 538 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 539 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 540 541 /* Wait for autonegotiation to finish */ 542 for (time_out = 0; time_out < max_time_out; time_out++) { 543 usec_delay(10); 544 /* Restart PHY autonegotiation and wait for completion */ 545 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 546 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 547 &autoneg_reg); 548 549 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 550 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 551 break; 552 } 553 554 if (time_out == max_time_out) { 555 status = IXGBE_ERR_LINK_SETUP; 556 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 557 } 558 559 return status; 560 } 561 562 /** 563 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 564 * @hw: pointer to hardware structure 565 * @speed: new link speed 566 * @autoneg: TRUE if autonegotiation enabled 567 **/ 568 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 569 ixgbe_link_speed speed, 570 bool autoneg, 571 bool autoneg_wait_to_complete) 572 { 573 UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete); 574 575 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 576 577 /* 578 * Clear autoneg_advertised and set new values based on input link 579 * speed. 580 */ 581 hw->phy.autoneg_advertised = 0; 582 583 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 584 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 585 586 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 587 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 588 589 if (speed & IXGBE_LINK_SPEED_100_FULL) 590 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 591 592 /* Setup link based on the new speed settings */ 593 hw->phy.ops.setup_link(hw); 594 595 return IXGBE_SUCCESS; 596 } 597 598 /** 599 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 600 * @hw: pointer to hardware structure 601 * @speed: pointer to link speed 602 * @autoneg: boolean auto-negotiation value 603 * 604 * Determines the link capabilities by reading the AUTOC register. 605 **/ 606 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 607 ixgbe_link_speed *speed, 608 bool *autoneg) 609 { 610 s32 status = IXGBE_ERR_LINK_SETUP; 611 u16 speed_ability; 612 613 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 614 615 *speed = 0; 616 *autoneg = TRUE; 617 618 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 619 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 620 &speed_ability); 621 622 if (status == IXGBE_SUCCESS) { 623 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 624 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 625 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 626 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 627 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 628 *speed |= IXGBE_LINK_SPEED_100_FULL; 629 } 630 631 return status; 632 } 633 634 /** 635 * ixgbe_check_phy_link_tnx - Determine link and speed status 636 * @hw: pointer to hardware structure 637 * 638 * Reads the VS1 register to determine if link is up and the current speed for 639 * the PHY. 640 **/ 641 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 642 bool *link_up) 643 { 644 s32 status = IXGBE_SUCCESS; 645 u32 time_out; 646 u32 max_time_out = 10; 647 u16 phy_link = 0; 648 u16 phy_speed = 0; 649 u16 phy_data = 0; 650 651 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 652 653 /* Initialize speed and link to default case */ 654 *link_up = FALSE; 655 *speed = IXGBE_LINK_SPEED_10GB_FULL; 656 657 /* 658 * Check current speed and link status of the PHY register. 659 * This is a vendor specific register and may have to 660 * be changed for other copper PHYs. 661 */ 662 for (time_out = 0; time_out < max_time_out; time_out++) { 663 usec_delay(10); 664 status = hw->phy.ops.read_reg(hw, 665 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 666 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 667 &phy_data); 668 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 669 phy_speed = phy_data & 670 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 671 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 672 *link_up = TRUE; 673 if (phy_speed == 674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 675 *speed = IXGBE_LINK_SPEED_1GB_FULL; 676 break; 677 } 678 } 679 680 return status; 681 } 682 683 /** 684 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 685 * @hw: pointer to hardware structure 686 * 687 * Restart autonegotiation and PHY and waits for completion. 688 **/ 689 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 690 { 691 s32 status = IXGBE_SUCCESS; 692 u32 time_out; 693 u32 max_time_out = 10; 694 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 695 bool autoneg = FALSE; 696 ixgbe_link_speed speed; 697 698 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 699 700 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 701 702 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 703 /* Set or unset auto-negotiation 10G advertisement */ 704 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 705 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 706 &autoneg_reg); 707 708 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 709 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 710 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 711 712 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 713 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 714 autoneg_reg); 715 } 716 717 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 718 /* Set or unset auto-negotiation 1G advertisement */ 719 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 720 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 721 &autoneg_reg); 722 723 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 724 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 725 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 726 727 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 728 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 729 autoneg_reg); 730 } 731 732 if (speed & IXGBE_LINK_SPEED_100_FULL) { 733 /* Set or unset auto-negotiation 100M advertisement */ 734 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 735 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 736 &autoneg_reg); 737 738 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 739 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 740 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 741 742 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 743 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 744 autoneg_reg); 745 } 746 747 /* Restart PHY autonegotiation and wait for completion */ 748 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 749 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 750 751 autoneg_reg |= IXGBE_MII_RESTART; 752 753 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 754 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 755 756 /* Wait for autonegotiation to finish */ 757 for (time_out = 0; time_out < max_time_out; time_out++) { 758 usec_delay(10); 759 /* Restart PHY autonegotiation and wait for completion */ 760 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 761 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 762 &autoneg_reg); 763 764 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 765 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 766 break; 767 } 768 769 if (time_out == max_time_out) { 770 status = IXGBE_ERR_LINK_SETUP; 771 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 772 } 773 774 return status; 775 } 776 777 /** 778 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 779 * @hw: pointer to hardware structure 780 * @firmware_version: pointer to the PHY Firmware Version 781 **/ 782 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 783 u16 *firmware_version) 784 { 785 s32 status = IXGBE_SUCCESS; 786 787 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 788 789 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 790 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 791 firmware_version); 792 793 return status; 794 } 795 796 /** 797 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 798 * @hw: pointer to hardware structure 799 * @firmware_version: pointer to the PHY Firmware Version 800 **/ 801 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 802 u16 *firmware_version) 803 { 804 s32 status = IXGBE_SUCCESS; 805 806 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 807 808 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 809 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 810 firmware_version); 811 812 return status; 813 } 814 815 /** 816 * ixgbe_reset_phy_nl - Performs a PHY reset 817 * @hw: pointer to hardware structure 818 **/ 819 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 820 { 821 u16 phy_offset, control, eword, edata, block_crc; 822 bool end_data = FALSE; 823 u16 list_offset, data_offset; 824 u16 phy_data = 0; 825 s32 ret_val = IXGBE_SUCCESS; 826 u32 i; 827 828 DEBUGFUNC("ixgbe_reset_phy_nl"); 829 830 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 831 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 832 833 /* reset the PHY and poll for completion */ 834 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 835 IXGBE_MDIO_PHY_XS_DEV_TYPE, 836 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 837 838 for (i = 0; i < 100; i++) { 839 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 840 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 841 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 842 break; 843 msec_delay(10); 844 } 845 846 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 847 DEBUGOUT("PHY reset did not complete.\n"); 848 ret_val = IXGBE_ERR_PHY; 849 goto out; 850 } 851 852 /* Get init offsets */ 853 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 854 &data_offset); 855 if (ret_val != IXGBE_SUCCESS) 856 goto out; 857 858 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 859 data_offset++; 860 while (!end_data) { 861 /* 862 * Read control word from PHY init contents offset 863 */ 864 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 865 control = (eword & IXGBE_CONTROL_MASK_NL) >> 866 IXGBE_CONTROL_SHIFT_NL; 867 edata = eword & IXGBE_DATA_MASK_NL; 868 switch (control) { 869 case IXGBE_DELAY_NL: 870 data_offset++; 871 DEBUGOUT1("DELAY: %d MS\n", edata); 872 msec_delay(edata); 873 break; 874 case IXGBE_DATA_NL: 875 DEBUGOUT("DATA:\n"); 876 data_offset++; 877 hw->eeprom.ops.read(hw, data_offset++, 878 &phy_offset); 879 for (i = 0; i < edata; i++) { 880 hw->eeprom.ops.read(hw, data_offset, &eword); 881 hw->phy.ops.write_reg(hw, phy_offset, 882 IXGBE_TWINAX_DEV, eword); 883 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 884 phy_offset); 885 data_offset++; 886 phy_offset++; 887 } 888 break; 889 case IXGBE_CONTROL_NL: 890 data_offset++; 891 DEBUGOUT("CONTROL:\n"); 892 if (edata == IXGBE_CONTROL_EOL_NL) { 893 DEBUGOUT("EOL\n"); 894 end_data = TRUE; 895 } else if (edata == IXGBE_CONTROL_SOL_NL) { 896 DEBUGOUT("SOL\n"); 897 } else { 898 DEBUGOUT("Bad control value\n"); 899 ret_val = IXGBE_ERR_PHY; 900 goto out; 901 } 902 break; 903 default: 904 DEBUGOUT("Bad control type\n"); 905 ret_val = IXGBE_ERR_PHY; 906 goto out; 907 } 908 } 909 910 out: 911 return ret_val; 912 } 913 914 /** 915 * ixgbe_identify_module_generic - Identifies module type 916 * @hw: pointer to hardware structure 917 * 918 * Determines HW type and calls appropriate function. 919 **/ 920 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 921 { 922 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 923 924 DEBUGFUNC("ixgbe_identify_module_generic"); 925 926 switch (hw->mac.ops.get_media_type(hw)) { 927 case ixgbe_media_type_fiber: 928 status = ixgbe_identify_sfp_module_generic(hw); 929 break; 930 931 932 default: 933 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 934 status = IXGBE_ERR_SFP_NOT_PRESENT; 935 break; 936 } 937 938 return status; 939 } 940 941 /** 942 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 943 * @hw: pointer to hardware structure 944 * 945 * Searches for and identifies the SFP module and assigns appropriate PHY type. 946 **/ 947 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 948 { 949 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 950 u32 vendor_oui = 0; 951 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 952 u8 identifier = 0; 953 u8 comp_codes_1g = 0; 954 u8 comp_codes_10g = 0; 955 u8 oui_bytes[3] = {0, 0, 0}; 956 u8 cable_tech = 0; 957 u8 cable_spec = 0; 958 u16 enforce_sfp = 0; 959 960 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 961 962 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 963 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 964 status = IXGBE_ERR_SFP_NOT_PRESENT; 965 goto out; 966 } 967 968 status = hw->phy.ops.read_i2c_eeprom(hw, 969 IXGBE_SFF_IDENTIFIER, 970 &identifier); 971 972 if (status == IXGBE_ERR_SWFW_SYNC || 973 status == IXGBE_ERR_I2C || 974 status == IXGBE_ERR_SFP_NOT_PRESENT) 975 goto err_read_i2c_eeprom; 976 977 /* LAN ID is needed for sfp_type determination */ 978 hw->mac.ops.set_lan_id(hw); 979 980 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 981 hw->phy.type = ixgbe_phy_sfp_unsupported; 982 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 983 } else { 984 status = hw->phy.ops.read_i2c_eeprom(hw, 985 IXGBE_SFF_1GBE_COMP_CODES, 986 &comp_codes_1g); 987 988 if (status == IXGBE_ERR_SWFW_SYNC || 989 status == IXGBE_ERR_I2C || 990 status == IXGBE_ERR_SFP_NOT_PRESENT) 991 goto err_read_i2c_eeprom; 992 993 status = hw->phy.ops.read_i2c_eeprom(hw, 994 IXGBE_SFF_10GBE_COMP_CODES, 995 &comp_codes_10g); 996 997 if (status == IXGBE_ERR_SWFW_SYNC || 998 status == IXGBE_ERR_I2C || 999 status == IXGBE_ERR_SFP_NOT_PRESENT) 1000 goto err_read_i2c_eeprom; 1001 status = hw->phy.ops.read_i2c_eeprom(hw, 1002 IXGBE_SFF_CABLE_TECHNOLOGY, 1003 &cable_tech); 1004 1005 if (status == IXGBE_ERR_SWFW_SYNC || 1006 status == IXGBE_ERR_I2C || 1007 status == IXGBE_ERR_SFP_NOT_PRESENT) 1008 goto err_read_i2c_eeprom; 1009 1010 /* ID Module 1011 * ========= 1012 * 0 SFP_DA_CU 1013 * 1 SFP_SR 1014 * 2 SFP_LR 1015 * 3 SFP_DA_CORE0 - 82599-specific 1016 * 4 SFP_DA_CORE1 - 82599-specific 1017 * 5 SFP_SR/LR_CORE0 - 82599-specific 1018 * 6 SFP_SR/LR_CORE1 - 82599-specific 1019 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1020 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1021 * 9 SFP_1g_cu_CORE0 - 82599-specific 1022 * 10 SFP_1g_cu_CORE1 - 82599-specific 1023 * 11 SFP_1g_sx_CORE0 - 82599-specific 1024 * 12 SFP_1g_sx_CORE1 - 82599-specific 1025 */ 1026 if (hw->mac.type == ixgbe_mac_82598EB) { 1027 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1028 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1029 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1030 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1031 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1032 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1033 else 1034 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1035 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1036 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1037 if (hw->bus.lan_id == 0) 1038 hw->phy.sfp_type = 1039 ixgbe_sfp_type_da_cu_core0; 1040 else 1041 hw->phy.sfp_type = 1042 ixgbe_sfp_type_da_cu_core1; 1043 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1044 hw->phy.ops.read_i2c_eeprom( 1045 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1046 &cable_spec); 1047 if (cable_spec & 1048 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1049 if (hw->bus.lan_id == 0) 1050 hw->phy.sfp_type = 1051 ixgbe_sfp_type_da_act_lmt_core0; 1052 else 1053 hw->phy.sfp_type = 1054 ixgbe_sfp_type_da_act_lmt_core1; 1055 } else { 1056 hw->phy.sfp_type = 1057 ixgbe_sfp_type_unknown; 1058 } 1059 } else if (comp_codes_10g & 1060 (IXGBE_SFF_10GBASESR_CAPABLE | 1061 IXGBE_SFF_10GBASELR_CAPABLE)) { 1062 if (hw->bus.lan_id == 0) 1063 hw->phy.sfp_type = 1064 ixgbe_sfp_type_srlr_core0; 1065 else 1066 hw->phy.sfp_type = 1067 ixgbe_sfp_type_srlr_core1; 1068 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1069 if (hw->bus.lan_id == 0) 1070 hw->phy.sfp_type = 1071 ixgbe_sfp_type_1g_cu_core0; 1072 else 1073 hw->phy.sfp_type = 1074 ixgbe_sfp_type_1g_cu_core1; 1075 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1076 if (hw->bus.lan_id == 0) 1077 hw->phy.sfp_type = 1078 ixgbe_sfp_type_1g_sx_core0; 1079 else 1080 hw->phy.sfp_type = 1081 ixgbe_sfp_type_1g_sx_core1; 1082 } else { 1083 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1084 } 1085 } 1086 1087 if (hw->phy.sfp_type != stored_sfp_type) 1088 hw->phy.sfp_setup_needed = TRUE; 1089 1090 /* Determine if the SFP+ PHY is dual speed or not. */ 1091 hw->phy.multispeed_fiber = FALSE; 1092 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1093 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1094 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1095 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1096 hw->phy.multispeed_fiber = TRUE; 1097 1098 /* Determine PHY vendor */ 1099 if (hw->phy.type != ixgbe_phy_nl) { 1100 hw->phy.id = identifier; 1101 status = hw->phy.ops.read_i2c_eeprom(hw, 1102 IXGBE_SFF_VENDOR_OUI_BYTE0, 1103 &oui_bytes[0]); 1104 1105 if (status == IXGBE_ERR_SWFW_SYNC || 1106 status == IXGBE_ERR_I2C || 1107 status == IXGBE_ERR_SFP_NOT_PRESENT) 1108 goto err_read_i2c_eeprom; 1109 1110 status = hw->phy.ops.read_i2c_eeprom(hw, 1111 IXGBE_SFF_VENDOR_OUI_BYTE1, 1112 &oui_bytes[1]); 1113 1114 if (status == IXGBE_ERR_SWFW_SYNC || 1115 status == IXGBE_ERR_I2C || 1116 status == IXGBE_ERR_SFP_NOT_PRESENT) 1117 goto err_read_i2c_eeprom; 1118 1119 status = hw->phy.ops.read_i2c_eeprom(hw, 1120 IXGBE_SFF_VENDOR_OUI_BYTE2, 1121 &oui_bytes[2]); 1122 1123 if (status == IXGBE_ERR_SWFW_SYNC || 1124 status == IXGBE_ERR_I2C || 1125 status == IXGBE_ERR_SFP_NOT_PRESENT) 1126 goto err_read_i2c_eeprom; 1127 1128 vendor_oui = 1129 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1130 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1131 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1132 1133 switch (vendor_oui) { 1134 case IXGBE_SFF_VENDOR_OUI_TYCO: 1135 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1136 hw->phy.type = 1137 ixgbe_phy_sfp_passive_tyco; 1138 break; 1139 case IXGBE_SFF_VENDOR_OUI_FTL: 1140 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1141 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1142 else 1143 hw->phy.type = ixgbe_phy_sfp_ftl; 1144 break; 1145 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1146 hw->phy.type = ixgbe_phy_sfp_avago; 1147 break; 1148 case IXGBE_SFF_VENDOR_OUI_INTEL: 1149 hw->phy.type = ixgbe_phy_sfp_intel; 1150 break; 1151 default: 1152 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1153 hw->phy.type = 1154 ixgbe_phy_sfp_passive_unknown; 1155 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1156 hw->phy.type = 1157 ixgbe_phy_sfp_active_unknown; 1158 else 1159 hw->phy.type = ixgbe_phy_sfp_unknown; 1160 break; 1161 } 1162 } 1163 1164 /* Allow any DA cable vendor */ 1165 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1166 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1167 status = IXGBE_SUCCESS; 1168 goto out; 1169 } 1170 1171 /* Verify supported 1G SFP modules */ 1172 if (comp_codes_10g == 0 && 1173 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1174 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1175 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1176 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1177 hw->phy.type = ixgbe_phy_sfp_unsupported; 1178 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1179 goto out; 1180 } 1181 1182 /* Anything else 82598-based is supported */ 1183 if (hw->mac.type == ixgbe_mac_82598EB) { 1184 status = IXGBE_SUCCESS; 1185 goto out; 1186 } 1187 1188 ixgbe_get_device_caps(hw, &enforce_sfp); 1189 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1190 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1191 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) || 1192 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) || 1193 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) { 1194 /* Make sure we're a supported PHY type */ 1195 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1196 status = IXGBE_SUCCESS; 1197 } else { 1198 if (hw->allow_unsupported_sfp == TRUE) { 1199 EWARN(hw, "WARNING: Intel (R) Network " 1200 "Connections are quality tested " 1201 "using Intel (R) Ethernet Optics." 1202 " Using untested modules is not " 1203 "supported and may cause unstable" 1204 " operation or damage to the " 1205 "module or the adapter. Intel " 1206 "Corporation is not responsible " 1207 "for any harm caused by using " 1208 "untested modules.\n", status); 1209 status = IXGBE_SUCCESS; 1210 } else { 1211 DEBUGOUT("SFP+ module not supported\n"); 1212 hw->phy.type = 1213 ixgbe_phy_sfp_unsupported; 1214 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1215 } 1216 } 1217 } else { 1218 status = IXGBE_SUCCESS; 1219 } 1220 } 1221 1222 out: 1223 return status; 1224 1225 err_read_i2c_eeprom: 1226 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1227 if (hw->phy.type != ixgbe_phy_nl) { 1228 hw->phy.id = 0; 1229 hw->phy.type = ixgbe_phy_unknown; 1230 } 1231 return IXGBE_ERR_SFP_NOT_PRESENT; 1232 } 1233 1234 1235 1236 /** 1237 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1238 * @hw: pointer to hardware structure 1239 * @list_offset: offset to the SFP ID list 1240 * @data_offset: offset to the SFP data block 1241 * 1242 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1243 * so it returns the offsets to the phy init sequence block. 1244 **/ 1245 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1246 u16 *list_offset, 1247 u16 *data_offset) 1248 { 1249 u16 sfp_id; 1250 u16 sfp_type = hw->phy.sfp_type; 1251 1252 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1253 1254 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1255 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1256 1257 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1258 return IXGBE_ERR_SFP_NOT_PRESENT; 1259 1260 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1261 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1262 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1263 1264 /* 1265 * Limiting active cables and 1G Phys must be initialized as 1266 * SR modules 1267 */ 1268 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1269 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1270 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1271 sfp_type = ixgbe_sfp_type_srlr_core0; 1272 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1273 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1274 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1275 sfp_type = ixgbe_sfp_type_srlr_core1; 1276 1277 /* Read offset to PHY init contents */ 1278 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1279 1280 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1281 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1282 1283 /* Shift offset to first ID word */ 1284 (*list_offset)++; 1285 1286 /* 1287 * Find the matching SFP ID in the EEPROM 1288 * and program the init sequence 1289 */ 1290 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1291 1292 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1293 if (sfp_id == sfp_type) { 1294 (*list_offset)++; 1295 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1296 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1297 DEBUGOUT("SFP+ module not supported\n"); 1298 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1299 } else { 1300 break; 1301 } 1302 } else { 1303 (*list_offset) += 2; 1304 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1305 return IXGBE_ERR_PHY; 1306 } 1307 } 1308 1309 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1310 DEBUGOUT("No matching SFP+ module found\n"); 1311 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1312 } 1313 1314 return IXGBE_SUCCESS; 1315 } 1316 1317 /** 1318 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1319 * @hw: pointer to hardware structure 1320 * @byte_offset: EEPROM byte offset to read 1321 * @eeprom_data: value read 1322 * 1323 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1324 **/ 1325 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1326 u8 *eeprom_data) 1327 { 1328 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1329 1330 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1331 IXGBE_I2C_EEPROM_DEV_ADDR, 1332 eeprom_data); 1333 } 1334 1335 /** 1336 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1337 * @hw: pointer to hardware structure 1338 * @byte_offset: EEPROM byte offset to write 1339 * @eeprom_data: value to write 1340 * 1341 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1342 **/ 1343 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1344 u8 eeprom_data) 1345 { 1346 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1347 1348 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1349 IXGBE_I2C_EEPROM_DEV_ADDR, 1350 eeprom_data); 1351 } 1352 1353 /** 1354 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1355 * @hw: pointer to hardware structure 1356 * @byte_offset: byte offset to read 1357 * @data: value read 1358 * 1359 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1360 * a specified device address. 1361 **/ 1362 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1363 u8 dev_addr, u8 *data) 1364 { 1365 s32 status = IXGBE_SUCCESS; 1366 u32 max_retry = 10; 1367 u32 retry = 0; 1368 u16 swfw_mask = 0; 1369 bool nack = 1; 1370 *data = 0; 1371 1372 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1373 1374 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1375 swfw_mask = IXGBE_GSSR_PHY1_SM; 1376 else 1377 swfw_mask = IXGBE_GSSR_PHY0_SM; 1378 1379 do { 1380 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 1381 != IXGBE_SUCCESS) { 1382 status = IXGBE_ERR_SWFW_SYNC; 1383 goto read_byte_out; 1384 } 1385 1386 ixgbe_i2c_start(hw); 1387 1388 /* Device Address and write indication */ 1389 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1390 if (status != IXGBE_SUCCESS) 1391 goto fail; 1392 1393 status = ixgbe_get_i2c_ack(hw); 1394 if (status != IXGBE_SUCCESS) 1395 goto fail; 1396 1397 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1398 if (status != IXGBE_SUCCESS) 1399 goto fail; 1400 1401 status = ixgbe_get_i2c_ack(hw); 1402 if (status != IXGBE_SUCCESS) 1403 goto fail; 1404 1405 ixgbe_i2c_start(hw); 1406 1407 /* Device Address and read indication */ 1408 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1409 if (status != IXGBE_SUCCESS) 1410 goto fail; 1411 1412 status = ixgbe_get_i2c_ack(hw); 1413 if (status != IXGBE_SUCCESS) 1414 goto fail; 1415 1416 status = ixgbe_clock_in_i2c_byte(hw, data); 1417 if (status != IXGBE_SUCCESS) 1418 goto fail; 1419 1420 status = ixgbe_clock_out_i2c_bit(hw, nack); 1421 if (status != IXGBE_SUCCESS) 1422 goto fail; 1423 1424 ixgbe_i2c_stop(hw); 1425 break; 1426 1427 fail: 1428 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1429 msec_delay(100); 1430 ixgbe_i2c_bus_clear(hw); 1431 retry++; 1432 if (retry < max_retry) 1433 DEBUGOUT("I2C byte read error - Retrying.\n"); 1434 else 1435 DEBUGOUT("I2C byte read error.\n"); 1436 1437 } while (retry < max_retry); 1438 1439 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1440 1441 read_byte_out: 1442 return status; 1443 } 1444 1445 /** 1446 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1447 * @hw: pointer to hardware structure 1448 * @byte_offset: byte offset to write 1449 * @data: value to write 1450 * 1451 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1452 * a specified device address. 1453 **/ 1454 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1455 u8 dev_addr, u8 data) 1456 { 1457 s32 status = IXGBE_SUCCESS; 1458 u32 max_retry = 1; 1459 u32 retry = 0; 1460 u16 swfw_mask = 0; 1461 1462 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1463 1464 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1465 swfw_mask = IXGBE_GSSR_PHY1_SM; 1466 else 1467 swfw_mask = IXGBE_GSSR_PHY0_SM; 1468 1469 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1470 status = IXGBE_ERR_SWFW_SYNC; 1471 goto write_byte_out; 1472 } 1473 1474 do { 1475 ixgbe_i2c_start(hw); 1476 1477 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1478 if (status != IXGBE_SUCCESS) 1479 goto fail; 1480 1481 status = ixgbe_get_i2c_ack(hw); 1482 if (status != IXGBE_SUCCESS) 1483 goto fail; 1484 1485 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1486 if (status != IXGBE_SUCCESS) 1487 goto fail; 1488 1489 status = ixgbe_get_i2c_ack(hw); 1490 if (status != IXGBE_SUCCESS) 1491 goto fail; 1492 1493 status = ixgbe_clock_out_i2c_byte(hw, data); 1494 if (status != IXGBE_SUCCESS) 1495 goto fail; 1496 1497 status = ixgbe_get_i2c_ack(hw); 1498 if (status != IXGBE_SUCCESS) 1499 goto fail; 1500 1501 ixgbe_i2c_stop(hw); 1502 break; 1503 1504 fail: 1505 ixgbe_i2c_bus_clear(hw); 1506 retry++; 1507 if (retry < max_retry) 1508 DEBUGOUT("I2C byte write error - Retrying.\n"); 1509 else 1510 DEBUGOUT("I2C byte write error.\n"); 1511 } while (retry < max_retry); 1512 1513 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1514 1515 write_byte_out: 1516 return status; 1517 } 1518 1519 /** 1520 * ixgbe_i2c_start - Sets I2C start condition 1521 * @hw: pointer to hardware structure 1522 * 1523 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1524 **/ 1525 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1526 { 1527 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1528 1529 DEBUGFUNC("ixgbe_i2c_start"); 1530 1531 /* Start condition must begin with data and clock high */ 1532 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1533 ixgbe_raise_i2c_clk(hw, &i2cctl); 1534 1535 /* Setup time for start condition (4.7us) */ 1536 usec_delay(IXGBE_I2C_T_SU_STA); 1537 1538 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1539 1540 /* Hold time for start condition (4us) */ 1541 usec_delay(IXGBE_I2C_T_HD_STA); 1542 1543 ixgbe_lower_i2c_clk(hw, &i2cctl); 1544 1545 /* Minimum low period of clock is 4.7 us */ 1546 usec_delay(IXGBE_I2C_T_LOW); 1547 1548 } 1549 1550 /** 1551 * ixgbe_i2c_stop - Sets I2C stop condition 1552 * @hw: pointer to hardware structure 1553 * 1554 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1555 **/ 1556 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1557 { 1558 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1559 1560 DEBUGFUNC("ixgbe_i2c_stop"); 1561 1562 /* Stop condition must begin with data low and clock high */ 1563 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1564 ixgbe_raise_i2c_clk(hw, &i2cctl); 1565 1566 /* Setup time for stop condition (4us) */ 1567 usec_delay(IXGBE_I2C_T_SU_STO); 1568 1569 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1570 1571 /* bus free time between stop and start (4.7us)*/ 1572 usec_delay(IXGBE_I2C_T_BUF); 1573 } 1574 1575 /** 1576 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1577 * @hw: pointer to hardware structure 1578 * @data: data byte to clock in 1579 * 1580 * Clocks in one byte data via I2C data/clock 1581 **/ 1582 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1583 { 1584 s32 i; 1585 bool bit = 0; 1586 1587 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1588 1589 for (i = 7; i >= 0; i--) { 1590 ixgbe_clock_in_i2c_bit(hw, &bit); 1591 *data |= bit << i; 1592 } 1593 1594 return IXGBE_SUCCESS; 1595 } 1596 1597 /** 1598 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1599 * @hw: pointer to hardware structure 1600 * @data: data byte clocked out 1601 * 1602 * Clocks out one byte data via I2C data/clock 1603 **/ 1604 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1605 { 1606 s32 status = IXGBE_SUCCESS; 1607 s32 i; 1608 u32 i2cctl; 1609 bool bit = 0; 1610 1611 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1612 1613 for (i = 7; i >= 0; i--) { 1614 bit = (data >> i) & 0x1; 1615 status = ixgbe_clock_out_i2c_bit(hw, bit); 1616 1617 if (status != IXGBE_SUCCESS) 1618 break; 1619 } 1620 1621 /* Release SDA line (set high) */ 1622 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1623 i2cctl |= IXGBE_I2C_DATA_OUT; 1624 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1625 IXGBE_WRITE_FLUSH(hw); 1626 1627 return status; 1628 } 1629 1630 /** 1631 * ixgbe_get_i2c_ack - Polls for I2C ACK 1632 * @hw: pointer to hardware structure 1633 * 1634 * Clocks in/out one bit via I2C data/clock 1635 **/ 1636 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1637 { 1638 s32 status = IXGBE_SUCCESS; 1639 u32 i = 0; 1640 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1641 u32 timeout = 10; 1642 bool ack = 1; 1643 1644 DEBUGFUNC("ixgbe_get_i2c_ack"); 1645 1646 ixgbe_raise_i2c_clk(hw, &i2cctl); 1647 1648 1649 /* Minimum high period of clock is 4us */ 1650 usec_delay(IXGBE_I2C_T_HIGH); 1651 1652 /* Poll for ACK. Note that ACK in I2C spec is 1653 * transition from 1 to 0 */ 1654 for (i = 0; i < timeout; i++) { 1655 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1656 ack = ixgbe_get_i2c_data(&i2cctl); 1657 1658 usec_delay(1); 1659 if (ack == 0) 1660 break; 1661 } 1662 1663 if (ack == 1) { 1664 DEBUGOUT("I2C ack was not received.\n"); 1665 status = IXGBE_ERR_I2C; 1666 } 1667 1668 ixgbe_lower_i2c_clk(hw, &i2cctl); 1669 1670 /* Minimum low period of clock is 4.7 us */ 1671 usec_delay(IXGBE_I2C_T_LOW); 1672 1673 return status; 1674 } 1675 1676 /** 1677 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1678 * @hw: pointer to hardware structure 1679 * @data: read data value 1680 * 1681 * Clocks in one bit via I2C data/clock 1682 **/ 1683 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1684 { 1685 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1686 1687 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1688 1689 ixgbe_raise_i2c_clk(hw, &i2cctl); 1690 1691 /* Minimum high period of clock is 4us */ 1692 usec_delay(IXGBE_I2C_T_HIGH); 1693 1694 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1695 *data = ixgbe_get_i2c_data(&i2cctl); 1696 1697 ixgbe_lower_i2c_clk(hw, &i2cctl); 1698 1699 /* Minimum low period of clock is 4.7 us */ 1700 usec_delay(IXGBE_I2C_T_LOW); 1701 1702 return IXGBE_SUCCESS; 1703 } 1704 1705 /** 1706 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1707 * @hw: pointer to hardware structure 1708 * @data: data value to write 1709 * 1710 * Clocks out one bit via I2C data/clock 1711 **/ 1712 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1713 { 1714 s32 status; 1715 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1716 1717 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1718 1719 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1720 if (status == IXGBE_SUCCESS) { 1721 ixgbe_raise_i2c_clk(hw, &i2cctl); 1722 1723 /* Minimum high period of clock is 4us */ 1724 usec_delay(IXGBE_I2C_T_HIGH); 1725 1726 ixgbe_lower_i2c_clk(hw, &i2cctl); 1727 1728 /* Minimum low period of clock is 4.7 us. 1729 * This also takes care of the data hold time. 1730 */ 1731 usec_delay(IXGBE_I2C_T_LOW); 1732 } else { 1733 status = IXGBE_ERR_I2C; 1734 DEBUGOUT1("I2C data was not set to %X\n", data); 1735 } 1736 1737 return status; 1738 } 1739 /** 1740 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1741 * @hw: pointer to hardware structure 1742 * @i2cctl: Current value of I2CCTL register 1743 * 1744 * Raises the I2C clock line '0'->'1' 1745 **/ 1746 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1747 { 1748 u32 i = 0; 1749 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1750 u32 i2cctl_r = 0; 1751 1752 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1753 1754 for (i = 0; i < timeout; i++) { 1755 *i2cctl |= IXGBE_I2C_CLK_OUT; 1756 1757 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1758 IXGBE_WRITE_FLUSH(hw); 1759 /* SCL rise time (1000ns) */ 1760 usec_delay(IXGBE_I2C_T_RISE); 1761 1762 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1763 if (i2cctl_r & IXGBE_I2C_CLK_IN) 1764 break; 1765 } 1766 } 1767 1768 /** 1769 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1770 * @hw: pointer to hardware structure 1771 * @i2cctl: Current value of I2CCTL register 1772 * 1773 * Lowers the I2C clock line '1'->'0' 1774 **/ 1775 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1776 { 1777 1778 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1779 1780 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1781 1782 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1783 IXGBE_WRITE_FLUSH(hw); 1784 1785 /* SCL fall time (300ns) */ 1786 usec_delay(IXGBE_I2C_T_FALL); 1787 } 1788 1789 /** 1790 * ixgbe_set_i2c_data - Sets the I2C data bit 1791 * @hw: pointer to hardware structure 1792 * @i2cctl: Current value of I2CCTL register 1793 * @data: I2C data value (0 or 1) to set 1794 * 1795 * Sets the I2C data bit 1796 **/ 1797 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1798 { 1799 s32 status = IXGBE_SUCCESS; 1800 1801 DEBUGFUNC("ixgbe_set_i2c_data"); 1802 1803 if (data) 1804 *i2cctl |= IXGBE_I2C_DATA_OUT; 1805 else 1806 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1807 1808 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1809 IXGBE_WRITE_FLUSH(hw); 1810 1811 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1812 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1813 1814 /* Verify data was set correctly */ 1815 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1816 if (data != ixgbe_get_i2c_data(i2cctl)) { 1817 status = IXGBE_ERR_I2C; 1818 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1819 } 1820 1821 return status; 1822 } 1823 1824 /** 1825 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1826 * @hw: pointer to hardware structure 1827 * @i2cctl: Current value of I2CCTL register 1828 * 1829 * Returns the I2C data bit value 1830 **/ 1831 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1832 { 1833 bool data; 1834 1835 DEBUGFUNC("ixgbe_get_i2c_data"); 1836 1837 if (*i2cctl & IXGBE_I2C_DATA_IN) 1838 data = 1; 1839 else 1840 data = 0; 1841 1842 return data; 1843 } 1844 1845 /** 1846 * ixgbe_i2c_bus_clear - Clears the I2C bus 1847 * @hw: pointer to hardware structure 1848 * 1849 * Clears the I2C bus by sending nine clock pulses. 1850 * Used when data line is stuck low. 1851 **/ 1852 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1853 { 1854 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1855 u32 i; 1856 1857 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1858 1859 ixgbe_i2c_start(hw); 1860 1861 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1862 1863 for (i = 0; i < 9; i++) { 1864 ixgbe_raise_i2c_clk(hw, &i2cctl); 1865 1866 /* Min high period of clock is 4us */ 1867 usec_delay(IXGBE_I2C_T_HIGH); 1868 1869 ixgbe_lower_i2c_clk(hw, &i2cctl); 1870 1871 /* Min low period of clock is 4.7us*/ 1872 usec_delay(IXGBE_I2C_T_LOW); 1873 } 1874 1875 ixgbe_i2c_start(hw); 1876 1877 /* Put the i2c bus back to default state */ 1878 ixgbe_i2c_stop(hw); 1879 } 1880 1881 /** 1882 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1883 * @hw: pointer to hardware structure 1884 * 1885 * Checks if the LASI temp alarm status was triggered due to overtemp 1886 **/ 1887 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1888 { 1889 s32 status = IXGBE_SUCCESS; 1890 u16 phy_data = 0; 1891 1892 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1893 1894 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1895 goto out; 1896 1897 /* Check that the LASI temp alarm status was triggered */ 1898 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1899 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1900 1901 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1902 goto out; 1903 1904 status = IXGBE_ERR_OVERTEMP; 1905 out: 1906 return status; 1907 } 1908