1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 42 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 45 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 52 u8 *sff8472_data); 53 54 /** 55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 56 * @hw: pointer to the hardware structure 57 * @byte: byte to send 58 * 59 * Returns an error code on error. 60 */ 61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 62 { 63 s32 status; 64 65 status = ixgbe_clock_out_i2c_byte(hw, byte); 66 if (status) 67 return status; 68 return ixgbe_get_i2c_ack(hw); 69 } 70 71 /** 72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 73 * @hw: pointer to the hardware structure 74 * @byte: pointer to a u8 to receive the byte 75 * 76 * Returns an error code on error. 77 */ 78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 79 { 80 ixgbe_clock_in_i2c_byte(hw, byte); 81 /* ACK */ 82 return ixgbe_clock_out_i2c_bit(hw, false); 83 } 84 85 /** 86 * ixgbe_ones_comp_byte_add - Perform one's complement addition 87 * @add1: addend 1 88 * @add2: addend 2 89 * 90 * Returns one's complement 8-bit sum. 91 */ 92 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 93 { 94 u16 sum = add1 + add2; 95 96 sum = (sum & 0xFF) + (sum >> 8); 97 return sum & 0xFF; 98 } 99 100 /** 101 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 102 * @hw: pointer to the hardware structure 103 * @addr: I2C bus address to read from 104 * @reg: I2C device register to read from 105 * @val: pointer to location to receive read value 106 * @lock: true if to take and release semaphore 107 * 108 * Returns an error code on error. 109 */ 110 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 111 u16 *val, bool lock) 112 { 113 u32 swfw_mask = hw->phy.phy_semaphore_mask; 114 int max_retry = 3; 115 int retry = 0; 116 u8 csum_byte; 117 u8 high_bits; 118 u8 low_bits; 119 u8 reg_high; 120 u8 csum; 121 122 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 123 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 124 csum = ~csum; 125 do { 126 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 127 return IXGBE_ERR_SWFW_SYNC; 128 ixgbe_i2c_start(hw); 129 /* Device Address and write indication */ 130 if (ixgbe_out_i2c_byte_ack(hw, addr)) 131 goto fail; 132 /* Write bits 14:8 */ 133 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 134 goto fail; 135 /* Write bits 7:0 */ 136 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 137 goto fail; 138 /* Write csum */ 139 if (ixgbe_out_i2c_byte_ack(hw, csum)) 140 goto fail; 141 /* Re-start condition */ 142 ixgbe_i2c_start(hw); 143 /* Device Address and read indication */ 144 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 145 goto fail; 146 /* Get upper bits */ 147 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 148 goto fail; 149 /* Get low bits */ 150 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 151 goto fail; 152 /* Get csum */ 153 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 154 /* NACK */ 155 if (ixgbe_clock_out_i2c_bit(hw, false)) 156 goto fail; 157 ixgbe_i2c_stop(hw); 158 if (lock) 159 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 160 *val = (high_bits << 8) | low_bits; 161 return 0; 162 163 fail: 164 ixgbe_i2c_bus_clear(hw); 165 if (lock) 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 if (retry < max_retry) 168 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 169 else 170 DEBUGOUT("I2C byte read combined error.\n"); 171 retry++; 172 } while (retry <= max_retry); 173 174 return IXGBE_ERR_I2C; 175 } 176 177 /** 178 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 179 * @hw: pointer to the hardware structure 180 * @addr: I2C bus address to write to 181 * @reg: I2C device register to write to 182 * @val: value to write 183 * @lock: true if to take and release semaphore 184 * 185 * Returns an error code on error. 186 */ 187 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 188 u16 val, bool lock) 189 { 190 u32 swfw_mask = hw->phy.phy_semaphore_mask; 191 int max_retry = 1; 192 int retry = 0; 193 u8 reg_high; 194 u8 csum; 195 196 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 197 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 198 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 199 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 200 csum = ~csum; 201 do { 202 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 203 return IXGBE_ERR_SWFW_SYNC; 204 ixgbe_i2c_start(hw); 205 /* Device Address and write indication */ 206 if (ixgbe_out_i2c_byte_ack(hw, addr)) 207 goto fail; 208 /* Write bits 14:8 */ 209 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 210 goto fail; 211 /* Write bits 7:0 */ 212 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 213 goto fail; 214 /* Write data 15:8 */ 215 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 216 goto fail; 217 /* Write data 7:0 */ 218 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 219 goto fail; 220 /* Write csum */ 221 if (ixgbe_out_i2c_byte_ack(hw, csum)) 222 goto fail; 223 ixgbe_i2c_stop(hw); 224 if (lock) 225 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 226 return 0; 227 228 fail: 229 ixgbe_i2c_bus_clear(hw); 230 if (lock) 231 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 232 if (retry < max_retry) 233 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 234 else 235 DEBUGOUT("I2C byte write combined error.\n"); 236 retry++; 237 } while (retry <= max_retry); 238 239 return IXGBE_ERR_I2C; 240 } 241 242 /** 243 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 244 * @hw: pointer to the hardware structure 245 * 246 * Initialize the function pointers. 247 **/ 248 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 249 { 250 struct ixgbe_phy_info *phy = &hw->phy; 251 252 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 253 254 /* PHY */ 255 phy->ops.identify = ixgbe_identify_phy_generic; 256 phy->ops.reset = ixgbe_reset_phy_generic; 257 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 258 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 259 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 260 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 261 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 262 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 263 phy->ops.check_link = NULL; 264 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 265 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 266 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 267 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 268 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 269 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 270 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 271 phy->ops.identify_sfp = ixgbe_identify_module_generic; 272 phy->sfp_type = ixgbe_sfp_type_unknown; 273 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 274 phy->ops.write_i2c_byte_unlocked = 275 ixgbe_write_i2c_byte_generic_unlocked; 276 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 277 return IXGBE_SUCCESS; 278 } 279 280 /** 281 * ixgbe_probe_phy - Probe a single address for a PHY 282 * @hw: pointer to hardware structure 283 * @phy_addr: PHY address to probe 284 * 285 * Returns true if PHY found 286 */ 287 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 288 { 289 u16 ext_ability = 0; 290 291 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 292 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 293 phy_addr); 294 return false; 295 } 296 297 if (ixgbe_get_phy_id(hw)) 298 return false; 299 300 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 301 302 if (hw->phy.type == ixgbe_phy_unknown) { 303 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 304 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 305 if (ext_ability & 306 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 307 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 308 hw->phy.type = ixgbe_phy_cu_unknown; 309 else 310 hw->phy.type = ixgbe_phy_generic; 311 } 312 313 return true; 314 } 315 316 /** 317 * ixgbe_identify_phy_generic - Get physical layer module 318 * @hw: pointer to hardware structure 319 * 320 * Determines the physical layer module found on the current adapter. 321 **/ 322 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 323 { 324 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 325 u16 phy_addr; 326 327 DEBUGFUNC("ixgbe_identify_phy_generic"); 328 329 if (!hw->phy.phy_semaphore_mask) { 330 if (hw->bus.lan_id) 331 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 332 else 333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 334 } 335 336 if (hw->phy.type != ixgbe_phy_unknown) 337 return IXGBE_SUCCESS; 338 339 if (hw->phy.nw_mng_if_sel) { 340 phy_addr = (hw->phy.nw_mng_if_sel & 341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 342 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 343 if (ixgbe_probe_phy(hw, phy_addr)) 344 return IXGBE_SUCCESS; 345 else 346 return IXGBE_ERR_PHY_ADDR_INVALID; 347 } 348 349 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 350 if (ixgbe_probe_phy(hw, phy_addr)) { 351 status = IXGBE_SUCCESS; 352 break; 353 } 354 } 355 356 /* Certain media types do not have a phy so an address will not 357 * be found and the code will take this path. Caller has to 358 * decide if it is an error or not. 359 */ 360 if (status != IXGBE_SUCCESS) 361 hw->phy.addr = 0; 362 363 return status; 364 } 365 366 /** 367 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 368 * @hw: pointer to the hardware structure 369 * 370 * This function checks the MMNGC.MNG_VETO bit to see if there are 371 * any constraints on link from manageability. For MAC's that don't 372 * have this bit just return faluse since the link can not be blocked 373 * via this method. 374 **/ 375 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 376 { 377 u32 mmngc; 378 379 DEBUGFUNC("ixgbe_check_reset_blocked"); 380 381 /* If we don't have this bit, it can't be blocking */ 382 if (hw->mac.type == ixgbe_mac_82598EB) 383 return false; 384 385 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 386 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 387 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 388 "MNG_VETO bit detected.\n"); 389 return true; 390 } 391 392 return false; 393 } 394 395 /** 396 * ixgbe_validate_phy_addr - Determines phy address is valid 397 * @hw: pointer to hardware structure 398 * @phy_addr: PHY address 399 * 400 **/ 401 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 402 { 403 u16 phy_id = 0; 404 bool valid = false; 405 406 DEBUGFUNC("ixgbe_validate_phy_addr"); 407 408 hw->phy.addr = phy_addr; 409 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 410 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 411 412 if (phy_id != 0xFFFF && phy_id != 0x0) 413 valid = true; 414 415 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 416 417 return valid; 418 } 419 420 /** 421 * ixgbe_get_phy_id - Get the phy type 422 * @hw: pointer to hardware structure 423 * 424 **/ 425 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 426 { 427 u32 status; 428 u16 phy_id_high = 0; 429 u16 phy_id_low = 0; 430 431 DEBUGFUNC("ixgbe_get_phy_id"); 432 433 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 434 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 435 &phy_id_high); 436 437 if (status == IXGBE_SUCCESS) { 438 hw->phy.id = (u32)(phy_id_high << 16); 439 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 440 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 441 &phy_id_low); 442 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 443 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 444 } 445 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 446 phy_id_high, phy_id_low); 447 448 return status; 449 } 450 451 /** 452 * ixgbe_get_phy_type_from_id - Get the phy type 453 * @phy_id: PHY ID information 454 * 455 **/ 456 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 457 { 458 enum ixgbe_phy_type phy_type; 459 460 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 461 462 switch (phy_id) { 463 case TN1010_PHY_ID: 464 phy_type = ixgbe_phy_tn; 465 break; 466 case X550_PHY_ID2: 467 case X550_PHY_ID3: 468 case X540_PHY_ID: 469 phy_type = ixgbe_phy_aq; 470 break; 471 case QT2022_PHY_ID: 472 phy_type = ixgbe_phy_qt; 473 break; 474 case ATH_PHY_ID: 475 phy_type = ixgbe_phy_nl; 476 break; 477 case X557_PHY_ID: 478 case X557_PHY_ID2: 479 phy_type = ixgbe_phy_x550em_ext_t; 480 break; 481 case IXGBE_M88E1500_E_PHY_ID: 482 case IXGBE_M88E1543_E_PHY_ID: 483 phy_type = ixgbe_phy_ext_1g_t; 484 break; 485 default: 486 phy_type = ixgbe_phy_unknown; 487 break; 488 } 489 return phy_type; 490 } 491 492 /** 493 * ixgbe_reset_phy_generic - Performs a PHY reset 494 * @hw: pointer to hardware structure 495 **/ 496 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 497 { 498 u32 i; 499 u16 ctrl = 0; 500 s32 status = IXGBE_SUCCESS; 501 502 DEBUGFUNC("ixgbe_reset_phy_generic"); 503 504 if (hw->phy.type == ixgbe_phy_unknown) 505 status = ixgbe_identify_phy_generic(hw); 506 507 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 508 goto out; 509 510 /* Don't reset PHY if it's shut down due to overtemp. */ 511 if (!hw->phy.reset_if_overtemp && 512 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 513 goto out; 514 515 /* Blocked by MNG FW so bail */ 516 if (ixgbe_check_reset_blocked(hw)) 517 goto out; 518 519 /* 520 * Perform soft PHY reset to the PHY_XS. 521 * This will cause a soft reset to the PHY 522 */ 523 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 524 IXGBE_MDIO_PHY_XS_DEV_TYPE, 525 IXGBE_MDIO_PHY_XS_RESET); 526 527 /* 528 * Poll for reset bit to self-clear indicating reset is complete. 529 * Some PHYs could take up to 3 seconds to complete and need about 530 * 1.7 usec delay after the reset is complete. 531 */ 532 for (i = 0; i < 30; i++) { 533 msec_delay(100); 534 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 535 status = hw->phy.ops.read_reg(hw, 536 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 537 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 538 &ctrl); 539 if (status != IXGBE_SUCCESS) 540 return status; 541 542 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 543 usec_delay(2); 544 break; 545 } 546 } else { 547 status = hw->phy.ops.read_reg(hw, 548 IXGBE_MDIO_PHY_XS_CONTROL, 549 IXGBE_MDIO_PHY_XS_DEV_TYPE, 550 &ctrl); 551 if (status != IXGBE_SUCCESS) 552 return status; 553 554 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 555 usec_delay(2); 556 break; 557 } 558 } 559 } 560 561 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 562 status = IXGBE_ERR_RESET_FAILED; 563 ERROR_REPORT1(IXGBE_ERROR_POLLING, 564 "PHY reset polling failed to complete.\n"); 565 } 566 567 out: 568 return status; 569 } 570 571 /** 572 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY 573 * @hw: pointer to hardware structure 574 **/ 575 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw) 576 { 577 u16 autoneg_reg; 578 579 /* Check if PHY reset is blocked by MNG FW */ 580 if (ixgbe_check_reset_blocked(hw)) 581 return; 582 583 /* Restart PHY auto-negotiation. */ 584 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 585 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 586 autoneg_reg |= IXGBE_MII_RESTART; 587 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 589 } 590 591 /** 592 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 593 * the SWFW lock 594 * @hw: pointer to hardware structure 595 * @reg_addr: 32 bit address of PHY register to read 596 * @device_type: 5 bit device type 597 * @phy_data: Pointer to read data from PHY register 598 **/ 599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 600 u16 *phy_data) 601 { 602 u32 i, data, command; 603 604 /* Setup and write the address cycle command */ 605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 608 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 609 610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 611 612 /* 613 * Check every 10 usec to see if the address cycle completed. 614 * The MDI Command bit will clear when the operation is 615 * complete 616 */ 617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 618 usec_delay(10); 619 620 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 622 break; 623 } 624 625 626 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 627 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 628 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 629 return IXGBE_ERR_PHY; 630 } 631 632 /* 633 * Address cycle complete, setup and write the read 634 * command 635 */ 636 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 637 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 638 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 639 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 640 641 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 642 643 /* 644 * Check every 10 usec to see if the address cycle 645 * completed. The MDI Command bit will clear when the 646 * operation is complete 647 */ 648 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 649 usec_delay(10); 650 651 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 652 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 653 break; 654 } 655 656 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 657 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 658 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 659 return IXGBE_ERR_PHY; 660 } 661 662 /* 663 * Read operation is complete. Get the data 664 * from MSRWD 665 */ 666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 668 *phy_data = (u16)(data); 669 670 return IXGBE_SUCCESS; 671 } 672 673 /** 674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 675 * using the SWFW lock - this function is needed in most cases 676 * @hw: pointer to hardware structure 677 * @reg_addr: 32 bit address of PHY register to read 678 * @device_type: 5 bit device type 679 * @phy_data: Pointer to read data from PHY register 680 **/ 681 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 682 u32 device_type, u16 *phy_data) 683 { 684 s32 status; 685 u32 gssr = hw->phy.phy_semaphore_mask; 686 687 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 688 689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 690 return IXGBE_ERR_SWFW_SYNC; 691 692 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 693 694 hw->mac.ops.release_swfw_sync(hw, gssr); 695 696 return status; 697 } 698 699 /** 700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 701 * without SWFW lock 702 * @hw: pointer to hardware structure 703 * @reg_addr: 32 bit PHY register to write 704 * @device_type: 5 bit device type 705 * @phy_data: Data to write to the PHY register 706 **/ 707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 708 u32 device_type, u16 phy_data) 709 { 710 u32 i, command; 711 712 /* Put the data in the MDI single read and write data register*/ 713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 714 715 /* Setup and write the address cycle command */ 716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 720 721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 722 723 /* 724 * Check every 10 usec to see if the address cycle completed. 725 * The MDI Command bit will clear when the operation is 726 * complete 727 */ 728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 729 usec_delay(10); 730 731 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 733 break; 734 } 735 736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 738 return IXGBE_ERR_PHY; 739 } 740 741 /* 742 * Address cycle complete, setup and write the write 743 * command 744 */ 745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 749 750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 751 752 /* 753 * Check every 10 usec to see if the address cycle 754 * completed. The MDI Command bit will clear when the 755 * operation is complete 756 */ 757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 758 usec_delay(10); 759 760 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 762 break; 763 } 764 765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 767 return IXGBE_ERR_PHY; 768 } 769 770 return IXGBE_SUCCESS; 771 } 772 773 /** 774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 775 * using SWFW lock- this function is needed in most cases 776 * @hw: pointer to hardware structure 777 * @reg_addr: 32 bit PHY register to write 778 * @device_type: 5 bit device type 779 * @phy_data: Data to write to the PHY register 780 **/ 781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 782 u32 device_type, u16 phy_data) 783 { 784 s32 status; 785 u32 gssr = hw->phy.phy_semaphore_mask; 786 787 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 788 789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 790 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 791 phy_data); 792 hw->mac.ops.release_swfw_sync(hw, gssr); 793 } else { 794 status = IXGBE_ERR_SWFW_SYNC; 795 } 796 797 return status; 798 } 799 800 /** 801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 802 * @hw: pointer to hardware structure 803 * 804 * Restart auto-negotiation and PHY and waits for completion. 805 **/ 806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 807 { 808 s32 status = IXGBE_SUCCESS; 809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 810 bool autoneg = false; 811 ixgbe_link_speed speed; 812 813 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 814 815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 816 817 /* Set or unset auto-negotiation 10G advertisement */ 818 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 820 &autoneg_reg); 821 822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 824 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 826 827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 829 autoneg_reg); 830 831 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 832 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 833 &autoneg_reg); 834 835 if (hw->mac.type == ixgbe_mac_X550) { 836 /* Set or unset auto-negotiation 5G advertisement */ 837 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 839 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 840 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 841 842 /* Set or unset auto-negotiation 2.5G advertisement */ 843 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 844 if ((hw->phy.autoneg_advertised & 845 IXGBE_LINK_SPEED_2_5GB_FULL) && 846 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 847 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 848 } 849 850 /* Set or unset auto-negotiation 1G advertisement */ 851 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 853 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 854 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 855 856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 858 autoneg_reg); 859 860 /* Set or unset auto-negotiation 100M advertisement */ 861 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 863 &autoneg_reg); 864 865 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 866 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 867 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 868 (speed & IXGBE_LINK_SPEED_100_FULL)) 869 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 870 871 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 873 autoneg_reg); 874 875 ixgbe_restart_auto_neg(hw); 876 return status; 877 } 878 879 /** 880 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 881 * @hw: pointer to hardware structure 882 * @speed: new link speed 883 * @autoneg_wait_to_complete: unused 884 **/ 885 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 886 ixgbe_link_speed speed, 887 bool autoneg_wait_to_complete) 888 { 889 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 890 891 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 892 893 /* 894 * Clear autoneg_advertised and set new values based on input link 895 * speed. 896 */ 897 hw->phy.autoneg_advertised = 0; 898 899 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 901 902 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 904 905 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 907 908 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 910 911 if (speed & IXGBE_LINK_SPEED_100_FULL) 912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 913 914 if (speed & IXGBE_LINK_SPEED_10_FULL) 915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 916 917 /* Setup link based on the new speed settings */ 918 ixgbe_setup_phy_link(hw); 919 920 return IXGBE_SUCCESS; 921 } 922 923 /** 924 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 925 * @hw: pointer to hardware structure 926 * 927 * Determines the supported link capabilities by reading the PHY auto 928 * negotiation register. 929 **/ 930 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 931 { 932 s32 status; 933 u16 speed_ability; 934 935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 936 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 937 &speed_ability); 938 if (status) 939 return status; 940 941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 945 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 947 948 switch (hw->mac.type) { 949 case ixgbe_mac_X550: 950 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 951 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 952 break; 953 case ixgbe_mac_X550EM_x: 954 case ixgbe_mac_X550EM_a: 955 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 956 break; 957 default: 958 break; 959 } 960 961 return status; 962 } 963 964 /** 965 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 966 * @hw: pointer to hardware structure 967 * @speed: pointer to link speed 968 * @autoneg: boolean auto-negotiation value 969 **/ 970 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 971 ixgbe_link_speed *speed, 972 bool *autoneg) 973 { 974 s32 status = IXGBE_SUCCESS; 975 976 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 977 978 *autoneg = true; 979 if (!hw->phy.speeds_supported) 980 status = ixgbe_get_copper_speeds_supported(hw); 981 982 *speed = hw->phy.speeds_supported; 983 return status; 984 } 985 986 /** 987 * ixgbe_check_phy_link_tnx - Determine link and speed status 988 * @hw: pointer to hardware structure 989 * @speed: current link speed 990 * @link_up: true is link is up, false otherwise 991 * 992 * Reads the VS1 register to determine if link is up and the current speed for 993 * the PHY. 994 **/ 995 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 996 bool *link_up) 997 { 998 s32 status = IXGBE_SUCCESS; 999 u32 time_out; 1000 u32 max_time_out = 10; 1001 u16 phy_link = 0; 1002 u16 phy_speed = 0; 1003 u16 phy_data = 0; 1004 1005 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1006 1007 /* Initialize speed and link to default case */ 1008 *link_up = false; 1009 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1010 1011 /* 1012 * Check current speed and link status of the PHY register. 1013 * This is a vendor specific register and may have to 1014 * be changed for other copper PHYs. 1015 */ 1016 for (time_out = 0; time_out < max_time_out; time_out++) { 1017 usec_delay(10); 1018 status = hw->phy.ops.read_reg(hw, 1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1021 &phy_data); 1022 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1023 phy_speed = phy_data & 1024 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1025 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1026 *link_up = true; 1027 if (phy_speed == 1028 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1029 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1030 break; 1031 } 1032 } 1033 1034 return status; 1035 } 1036 1037 /** 1038 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1039 * @hw: pointer to hardware structure 1040 * 1041 * Restart auto-negotiation and PHY and waits for completion. 1042 **/ 1043 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1044 { 1045 s32 status = IXGBE_SUCCESS; 1046 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1047 bool autoneg = false; 1048 ixgbe_link_speed speed; 1049 1050 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1051 1052 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1053 1054 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1055 /* Set or unset auto-negotiation 10G advertisement */ 1056 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1058 &autoneg_reg); 1059 1060 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1061 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1062 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1063 1064 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1065 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1066 autoneg_reg); 1067 } 1068 1069 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1070 /* Set or unset auto-negotiation 1G advertisement */ 1071 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1073 &autoneg_reg); 1074 1075 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1076 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1077 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1078 1079 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1081 autoneg_reg); 1082 } 1083 1084 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1085 /* Set or unset auto-negotiation 100M advertisement */ 1086 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1088 &autoneg_reg); 1089 1090 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1091 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1092 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1093 1094 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1096 autoneg_reg); 1097 } 1098 1099 ixgbe_restart_auto_neg(hw); 1100 return status; 1101 } 1102 1103 /** 1104 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1105 * @hw: pointer to hardware structure 1106 * @firmware_version: pointer to the PHY Firmware Version 1107 **/ 1108 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1109 u16 *firmware_version) 1110 { 1111 s32 status; 1112 1113 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1114 1115 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1116 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1117 firmware_version); 1118 1119 return status; 1120 } 1121 1122 /** 1123 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1124 * @hw: pointer to hardware structure 1125 * @firmware_version: pointer to the PHY Firmware Version 1126 **/ 1127 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1128 u16 *firmware_version) 1129 { 1130 s32 status; 1131 1132 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1133 1134 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1135 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1136 firmware_version); 1137 1138 return status; 1139 } 1140 1141 /** 1142 * ixgbe_reset_phy_nl - Performs a PHY reset 1143 * @hw: pointer to hardware structure 1144 **/ 1145 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1146 { 1147 u16 phy_offset, control, eword, edata, block_crc; 1148 bool end_data = false; 1149 u16 list_offset, data_offset; 1150 u16 phy_data = 0; 1151 s32 ret_val = IXGBE_SUCCESS; 1152 u32 i; 1153 1154 DEBUGFUNC("ixgbe_reset_phy_nl"); 1155 1156 /* Blocked by MNG FW so bail */ 1157 if (ixgbe_check_reset_blocked(hw)) 1158 goto out; 1159 1160 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1161 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1162 1163 /* reset the PHY and poll for completion */ 1164 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1165 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1166 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1167 1168 for (i = 0; i < 100; i++) { 1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1170 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1171 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1172 break; 1173 msec_delay(10); 1174 } 1175 1176 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1177 DEBUGOUT("PHY reset did not complete.\n"); 1178 ret_val = IXGBE_ERR_PHY; 1179 goto out; 1180 } 1181 1182 /* Get init offsets */ 1183 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1184 &data_offset); 1185 if (ret_val != IXGBE_SUCCESS) 1186 goto out; 1187 1188 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1189 data_offset++; 1190 while (!end_data) { 1191 /* 1192 * Read control word from PHY init contents offset 1193 */ 1194 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1195 if (ret_val) 1196 goto err_eeprom; 1197 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1198 IXGBE_CONTROL_SHIFT_NL; 1199 edata = eword & IXGBE_DATA_MASK_NL; 1200 switch (control) { 1201 case IXGBE_DELAY_NL: 1202 data_offset++; 1203 DEBUGOUT1("DELAY: %d MS\n", edata); 1204 msec_delay(edata); 1205 break; 1206 case IXGBE_DATA_NL: 1207 DEBUGOUT("DATA:\n"); 1208 data_offset++; 1209 ret_val = hw->eeprom.ops.read(hw, data_offset, 1210 &phy_offset); 1211 if (ret_val) 1212 goto err_eeprom; 1213 data_offset++; 1214 for (i = 0; i < edata; i++) { 1215 ret_val = hw->eeprom.ops.read(hw, data_offset, 1216 &eword); 1217 if (ret_val) 1218 goto err_eeprom; 1219 hw->phy.ops.write_reg(hw, phy_offset, 1220 IXGBE_TWINAX_DEV, eword); 1221 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1222 phy_offset); 1223 data_offset++; 1224 phy_offset++; 1225 } 1226 break; 1227 case IXGBE_CONTROL_NL: 1228 data_offset++; 1229 DEBUGOUT("CONTROL:\n"); 1230 if (edata == IXGBE_CONTROL_EOL_NL) { 1231 DEBUGOUT("EOL\n"); 1232 end_data = true; 1233 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1234 DEBUGOUT("SOL\n"); 1235 } else { 1236 DEBUGOUT("Bad control value\n"); 1237 ret_val = IXGBE_ERR_PHY; 1238 goto out; 1239 } 1240 break; 1241 default: 1242 DEBUGOUT("Bad control type\n"); 1243 ret_val = IXGBE_ERR_PHY; 1244 goto out; 1245 } 1246 } 1247 1248 out: 1249 return ret_val; 1250 1251 err_eeprom: 1252 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1253 "eeprom read at offset %d failed", data_offset); 1254 return IXGBE_ERR_PHY; 1255 } 1256 1257 /** 1258 * ixgbe_identify_module_generic - Identifies module type 1259 * @hw: pointer to hardware structure 1260 * 1261 * Determines HW type and calls appropriate function. 1262 **/ 1263 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1264 { 1265 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1266 1267 DEBUGFUNC("ixgbe_identify_module_generic"); 1268 1269 switch (hw->mac.ops.get_media_type(hw)) { 1270 case ixgbe_media_type_fiber: 1271 status = ixgbe_identify_sfp_module_generic(hw); 1272 break; 1273 1274 case ixgbe_media_type_fiber_qsfp: 1275 status = ixgbe_identify_qsfp_module_generic(hw); 1276 break; 1277 1278 default: 1279 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1280 status = IXGBE_ERR_SFP_NOT_PRESENT; 1281 break; 1282 } 1283 1284 return status; 1285 } 1286 1287 /** 1288 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1289 * @hw: pointer to hardware structure 1290 * 1291 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1292 **/ 1293 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1294 { 1295 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1296 u32 vendor_oui = 0; 1297 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1298 u8 identifier = 0; 1299 u8 comp_codes_1g = 0; 1300 u8 comp_codes_10g = 0; 1301 u8 oui_bytes[3] = {0, 0, 0}; 1302 u8 cable_tech = 0; 1303 u8 cable_spec = 0; 1304 u16 enforce_sfp = 0; 1305 static bool warned_once = false; 1306 1307 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1308 1309 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1310 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1311 status = IXGBE_ERR_SFP_NOT_PRESENT; 1312 goto out; 1313 } 1314 1315 /* LAN ID is needed for I2C access */ 1316 hw->mac.ops.set_lan_id(hw); 1317 1318 status = hw->phy.ops.read_i2c_eeprom(hw, 1319 IXGBE_SFF_IDENTIFIER, 1320 &identifier); 1321 1322 if (status != IXGBE_SUCCESS) 1323 goto err_read_i2c_eeprom; 1324 1325 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1326 hw->phy.type = ixgbe_phy_sfp_unsupported; 1327 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1328 } else { 1329 status = hw->phy.ops.read_i2c_eeprom(hw, 1330 IXGBE_SFF_1GBE_COMP_CODES, 1331 &comp_codes_1g); 1332 1333 if (status != IXGBE_SUCCESS) 1334 goto err_read_i2c_eeprom; 1335 1336 status = hw->phy.ops.read_i2c_eeprom(hw, 1337 IXGBE_SFF_10GBE_COMP_CODES, 1338 &comp_codes_10g); 1339 1340 if (status != IXGBE_SUCCESS) 1341 goto err_read_i2c_eeprom; 1342 status = hw->phy.ops.read_i2c_eeprom(hw, 1343 IXGBE_SFF_CABLE_TECHNOLOGY, 1344 &cable_tech); 1345 1346 if (status != IXGBE_SUCCESS) 1347 goto err_read_i2c_eeprom; 1348 1349 /* ID Module 1350 * ========= 1351 * 0 SFP_DA_CU 1352 * 1 SFP_SR 1353 * 2 SFP_LR 1354 * 3 SFP_DA_CORE0 - 82599-specific 1355 * 4 SFP_DA_CORE1 - 82599-specific 1356 * 5 SFP_SR/LR_CORE0 - 82599-specific 1357 * 6 SFP_SR/LR_CORE1 - 82599-specific 1358 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1359 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1360 * 9 SFP_1g_cu_CORE0 - 82599-specific 1361 * 10 SFP_1g_cu_CORE1 - 82599-specific 1362 * 11 SFP_1g_sx_CORE0 - 82599-specific 1363 * 12 SFP_1g_sx_CORE1 - 82599-specific 1364 */ 1365 if (hw->mac.type == ixgbe_mac_82598EB) { 1366 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1367 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1368 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1369 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1370 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1371 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1372 else 1373 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1374 } else { 1375 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1376 if (hw->bus.lan_id == 0) 1377 hw->phy.sfp_type = 1378 ixgbe_sfp_type_da_cu_core0; 1379 else 1380 hw->phy.sfp_type = 1381 ixgbe_sfp_type_da_cu_core1; 1382 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1383 hw->phy.ops.read_i2c_eeprom( 1384 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1385 &cable_spec); 1386 if (cable_spec & 1387 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1388 if (hw->bus.lan_id == 0) 1389 hw->phy.sfp_type = 1390 ixgbe_sfp_type_da_act_lmt_core0; 1391 else 1392 hw->phy.sfp_type = 1393 ixgbe_sfp_type_da_act_lmt_core1; 1394 } else { 1395 hw->phy.sfp_type = 1396 ixgbe_sfp_type_unknown; 1397 } 1398 } else if (comp_codes_10g & 1399 (IXGBE_SFF_10GBASESR_CAPABLE | 1400 IXGBE_SFF_10GBASELR_CAPABLE)) { 1401 if (hw->bus.lan_id == 0) 1402 hw->phy.sfp_type = 1403 ixgbe_sfp_type_srlr_core0; 1404 else 1405 hw->phy.sfp_type = 1406 ixgbe_sfp_type_srlr_core1; 1407 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1408 if (hw->bus.lan_id == 0) 1409 hw->phy.sfp_type = 1410 ixgbe_sfp_type_1g_cu_core0; 1411 else 1412 hw->phy.sfp_type = 1413 ixgbe_sfp_type_1g_cu_core1; 1414 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1415 if (hw->bus.lan_id == 0) 1416 hw->phy.sfp_type = 1417 ixgbe_sfp_type_1g_sx_core0; 1418 else 1419 hw->phy.sfp_type = 1420 ixgbe_sfp_type_1g_sx_core1; 1421 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1422 if (hw->bus.lan_id == 0) 1423 hw->phy.sfp_type = 1424 ixgbe_sfp_type_1g_lx_core0; 1425 else 1426 hw->phy.sfp_type = 1427 ixgbe_sfp_type_1g_lx_core1; 1428 } else { 1429 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1430 } 1431 } 1432 1433 if (hw->phy.sfp_type != stored_sfp_type) 1434 hw->phy.sfp_setup_needed = true; 1435 1436 /* Determine if the SFP+ PHY is dual speed or not. */ 1437 hw->phy.multispeed_fiber = false; 1438 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1439 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1440 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1441 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1442 hw->phy.multispeed_fiber = true; 1443 1444 /* Determine PHY vendor */ 1445 if (hw->phy.type != ixgbe_phy_nl) { 1446 hw->phy.id = identifier; 1447 status = hw->phy.ops.read_i2c_eeprom(hw, 1448 IXGBE_SFF_VENDOR_OUI_BYTE0, 1449 &oui_bytes[0]); 1450 1451 if (status != IXGBE_SUCCESS) 1452 goto err_read_i2c_eeprom; 1453 1454 status = hw->phy.ops.read_i2c_eeprom(hw, 1455 IXGBE_SFF_VENDOR_OUI_BYTE1, 1456 &oui_bytes[1]); 1457 1458 if (status != IXGBE_SUCCESS) 1459 goto err_read_i2c_eeprom; 1460 1461 status = hw->phy.ops.read_i2c_eeprom(hw, 1462 IXGBE_SFF_VENDOR_OUI_BYTE2, 1463 &oui_bytes[2]); 1464 1465 if (status != IXGBE_SUCCESS) 1466 goto err_read_i2c_eeprom; 1467 1468 vendor_oui = 1469 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1470 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1471 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1472 1473 switch (vendor_oui) { 1474 case IXGBE_SFF_VENDOR_OUI_TYCO: 1475 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1476 hw->phy.type = 1477 ixgbe_phy_sfp_passive_tyco; 1478 break; 1479 case IXGBE_SFF_VENDOR_OUI_FTL: 1480 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1481 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1482 else 1483 hw->phy.type = ixgbe_phy_sfp_ftl; 1484 break; 1485 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1486 hw->phy.type = ixgbe_phy_sfp_avago; 1487 break; 1488 case IXGBE_SFF_VENDOR_OUI_INTEL: 1489 hw->phy.type = ixgbe_phy_sfp_intel; 1490 break; 1491 default: 1492 hw->phy.type = ixgbe_phy_sfp_unknown; 1493 break; 1494 } 1495 } 1496 1497 /* Allow any DA cable vendor */ 1498 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1499 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1500 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1501 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1502 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1503 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1504 status = IXGBE_SUCCESS; 1505 goto out; 1506 } 1507 1508 /* Verify supported 1G SFP modules */ 1509 if (comp_codes_10g == 0 && 1510 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1516 hw->phy.type = ixgbe_phy_sfp_unsupported; 1517 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1518 goto out; 1519 } 1520 1521 /* Anything else 82598-based is supported */ 1522 if (hw->mac.type == ixgbe_mac_82598EB) { 1523 status = IXGBE_SUCCESS; 1524 goto out; 1525 } 1526 1527 ixgbe_get_device_caps(hw, &enforce_sfp); 1528 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1529 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1535 /* Make sure we're a supported PHY type */ 1536 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1537 status = IXGBE_SUCCESS; 1538 } else { 1539 if (hw->allow_unsupported_sfp == true) { 1540 if (!warned_once) 1541 EWARN(hw, 1542 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1543 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1544 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1545 warned_once = true; 1546 status = IXGBE_SUCCESS; 1547 } else { 1548 DEBUGOUT 1549 ("SFP+ module not supported\n"); 1550 hw->phy.type = 1551 ixgbe_phy_sfp_unsupported; 1552 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1553 } 1554 } 1555 } else { 1556 status = IXGBE_SUCCESS; 1557 } 1558 } 1559 1560 out: 1561 return status; 1562 1563 err_read_i2c_eeprom: 1564 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1565 if (hw->phy.type != ixgbe_phy_nl) { 1566 hw->phy.id = 0; 1567 hw->phy.type = ixgbe_phy_unknown; 1568 } 1569 return IXGBE_ERR_SFP_NOT_PRESENT; 1570 } 1571 1572 /** 1573 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1574 * @hw: pointer to hardware structure 1575 * 1576 * Determines physical layer capabilities of the current SFP. 1577 */ 1578 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1579 { 1580 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1581 u8 comp_codes_10g = 0; 1582 u8 comp_codes_1g = 0; 1583 1584 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1585 1586 hw->phy.ops.identify_sfp(hw); 1587 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1588 return physical_layer; 1589 1590 switch (hw->phy.type) { 1591 case ixgbe_phy_sfp_passive_tyco: 1592 case ixgbe_phy_sfp_passive_unknown: 1593 case ixgbe_phy_qsfp_passive_unknown: 1594 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1595 break; 1596 case ixgbe_phy_sfp_ftl_active: 1597 case ixgbe_phy_sfp_active_unknown: 1598 case ixgbe_phy_qsfp_active_unknown: 1599 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1600 break; 1601 case ixgbe_phy_sfp_avago: 1602 case ixgbe_phy_sfp_ftl: 1603 case ixgbe_phy_sfp_intel: 1604 case ixgbe_phy_sfp_unknown: 1605 hw->phy.ops.read_i2c_eeprom(hw, 1606 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1607 hw->phy.ops.read_i2c_eeprom(hw, 1608 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1609 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1610 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1611 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1612 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1613 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1614 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1615 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1616 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1617 break; 1618 case ixgbe_phy_qsfp_intel: 1619 case ixgbe_phy_qsfp_unknown: 1620 hw->phy.ops.read_i2c_eeprom(hw, 1621 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1622 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1623 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1624 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1625 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1626 break; 1627 default: 1628 break; 1629 } 1630 1631 return physical_layer; 1632 } 1633 1634 /** 1635 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1636 * @hw: pointer to hardware structure 1637 * 1638 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1639 **/ 1640 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1641 { 1642 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1643 u32 vendor_oui = 0; 1644 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1645 u8 identifier = 0; 1646 u8 comp_codes_1g = 0; 1647 u8 comp_codes_10g = 0; 1648 u8 oui_bytes[3] = {0, 0, 0}; 1649 u16 enforce_sfp = 0; 1650 u8 connector = 0; 1651 u8 cable_length = 0; 1652 u8 device_tech = 0; 1653 bool active_cable = false; 1654 static bool warned_once = false; 1655 1656 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1657 1658 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1659 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1660 status = IXGBE_ERR_SFP_NOT_PRESENT; 1661 goto out; 1662 } 1663 1664 /* LAN ID is needed for I2C access */ 1665 hw->mac.ops.set_lan_id(hw); 1666 1667 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1668 &identifier); 1669 1670 if (status != IXGBE_SUCCESS) 1671 goto err_read_i2c_eeprom; 1672 1673 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1674 hw->phy.type = ixgbe_phy_sfp_unsupported; 1675 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1676 goto out; 1677 } 1678 1679 hw->phy.id = identifier; 1680 1681 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1682 &comp_codes_10g); 1683 1684 if (status != IXGBE_SUCCESS) 1685 goto err_read_i2c_eeprom; 1686 1687 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1688 &comp_codes_1g); 1689 1690 if (status != IXGBE_SUCCESS) 1691 goto err_read_i2c_eeprom; 1692 1693 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1694 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1695 if (hw->bus.lan_id == 0) 1696 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1697 else 1698 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1699 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1700 IXGBE_SFF_10GBASELR_CAPABLE)) { 1701 if (hw->bus.lan_id == 0) 1702 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1703 else 1704 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1705 } else { 1706 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1707 active_cable = true; 1708 1709 if (!active_cable) { 1710 /* check for active DA cables that pre-date 1711 * SFF-8436 v3.6 */ 1712 hw->phy.ops.read_i2c_eeprom(hw, 1713 IXGBE_SFF_QSFP_CONNECTOR, 1714 &connector); 1715 1716 hw->phy.ops.read_i2c_eeprom(hw, 1717 IXGBE_SFF_QSFP_CABLE_LENGTH, 1718 &cable_length); 1719 1720 hw->phy.ops.read_i2c_eeprom(hw, 1721 IXGBE_SFF_QSFP_DEVICE_TECH, 1722 &device_tech); 1723 1724 if ((connector == 1725 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1726 (cable_length > 0) && 1727 ((device_tech >> 4) == 1728 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1729 active_cable = true; 1730 } 1731 1732 if (active_cable) { 1733 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1734 if (hw->bus.lan_id == 0) 1735 hw->phy.sfp_type = 1736 ixgbe_sfp_type_da_act_lmt_core0; 1737 else 1738 hw->phy.sfp_type = 1739 ixgbe_sfp_type_da_act_lmt_core1; 1740 } else { 1741 /* unsupported module type */ 1742 hw->phy.type = ixgbe_phy_sfp_unsupported; 1743 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1744 goto out; 1745 } 1746 } 1747 1748 if (hw->phy.sfp_type != stored_sfp_type) 1749 hw->phy.sfp_setup_needed = true; 1750 1751 /* Determine if the QSFP+ PHY is dual speed or not. */ 1752 hw->phy.multispeed_fiber = false; 1753 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1754 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1755 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1756 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1757 hw->phy.multispeed_fiber = true; 1758 1759 /* Determine PHY vendor for optical modules */ 1760 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1761 IXGBE_SFF_10GBASELR_CAPABLE)) { 1762 status = hw->phy.ops.read_i2c_eeprom(hw, 1763 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1764 &oui_bytes[0]); 1765 1766 if (status != IXGBE_SUCCESS) 1767 goto err_read_i2c_eeprom; 1768 1769 status = hw->phy.ops.read_i2c_eeprom(hw, 1770 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1771 &oui_bytes[1]); 1772 1773 if (status != IXGBE_SUCCESS) 1774 goto err_read_i2c_eeprom; 1775 1776 status = hw->phy.ops.read_i2c_eeprom(hw, 1777 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1778 &oui_bytes[2]); 1779 1780 if (status != IXGBE_SUCCESS) 1781 goto err_read_i2c_eeprom; 1782 1783 vendor_oui = 1784 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1785 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1786 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1787 1788 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1789 hw->phy.type = ixgbe_phy_qsfp_intel; 1790 else 1791 hw->phy.type = ixgbe_phy_qsfp_unknown; 1792 1793 ixgbe_get_device_caps(hw, &enforce_sfp); 1794 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1795 /* Make sure we're a supported PHY type */ 1796 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1797 status = IXGBE_SUCCESS; 1798 } else { 1799 if (hw->allow_unsupported_sfp == true) { 1800 if (!warned_once) 1801 EWARN(hw, 1802 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1803 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1804 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1805 warned_once = true; 1806 status = IXGBE_SUCCESS; 1807 } else { 1808 DEBUGOUT("QSFP module not supported\n"); 1809 hw->phy.type = 1810 ixgbe_phy_sfp_unsupported; 1811 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1812 } 1813 } 1814 } else { 1815 status = IXGBE_SUCCESS; 1816 } 1817 } 1818 1819 out: 1820 return status; 1821 1822 err_read_i2c_eeprom: 1823 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1824 hw->phy.id = 0; 1825 hw->phy.type = ixgbe_phy_unknown; 1826 1827 return IXGBE_ERR_SFP_NOT_PRESENT; 1828 } 1829 1830 /** 1831 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1832 * @hw: pointer to hardware structure 1833 * @list_offset: offset to the SFP ID list 1834 * @data_offset: offset to the SFP data block 1835 * 1836 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1837 * so it returns the offsets to the phy init sequence block. 1838 **/ 1839 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1840 u16 *list_offset, 1841 u16 *data_offset) 1842 { 1843 u16 sfp_id; 1844 u16 sfp_type = hw->phy.sfp_type; 1845 1846 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1847 1848 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1849 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1850 1851 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1852 return IXGBE_ERR_SFP_NOT_PRESENT; 1853 1854 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1855 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1856 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1857 1858 /* 1859 * Limiting active cables and 1G Phys must be initialized as 1860 * SR modules 1861 */ 1862 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1863 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1864 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1865 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1866 sfp_type = ixgbe_sfp_type_srlr_core0; 1867 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1868 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1869 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1870 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1871 sfp_type = ixgbe_sfp_type_srlr_core1; 1872 1873 /* Read offset to PHY init contents */ 1874 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1875 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1876 "eeprom read at offset %d failed", 1877 IXGBE_PHY_INIT_OFFSET_NL); 1878 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1879 } 1880 1881 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1882 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1883 1884 /* Shift offset to first ID word */ 1885 (*list_offset)++; 1886 1887 /* 1888 * Find the matching SFP ID in the EEPROM 1889 * and program the init sequence 1890 */ 1891 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1892 goto err_phy; 1893 1894 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1895 if (sfp_id == sfp_type) { 1896 (*list_offset)++; 1897 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1898 goto err_phy; 1899 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1900 DEBUGOUT("SFP+ module not supported\n"); 1901 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1902 } else { 1903 break; 1904 } 1905 } else { 1906 (*list_offset) += 2; 1907 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1908 goto err_phy; 1909 } 1910 } 1911 1912 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1913 DEBUGOUT("No matching SFP+ module found\n"); 1914 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1915 } 1916 1917 return IXGBE_SUCCESS; 1918 1919 err_phy: 1920 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1921 "eeprom read at offset %d failed", *list_offset); 1922 return IXGBE_ERR_PHY; 1923 } 1924 1925 /** 1926 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1927 * @hw: pointer to hardware structure 1928 * @byte_offset: EEPROM byte offset to read 1929 * @eeprom_data: value read 1930 * 1931 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1932 **/ 1933 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1934 u8 *eeprom_data) 1935 { 1936 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1937 1938 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1939 IXGBE_I2C_EEPROM_DEV_ADDR, 1940 eeprom_data); 1941 } 1942 1943 /** 1944 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1945 * @hw: pointer to hardware structure 1946 * @byte_offset: byte offset at address 0xA2 1947 * @sff8472_data: value read 1948 * 1949 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1950 **/ 1951 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1952 u8 *sff8472_data) 1953 { 1954 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1955 IXGBE_I2C_EEPROM_DEV_ADDR2, 1956 sff8472_data); 1957 } 1958 1959 /** 1960 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1961 * @hw: pointer to hardware structure 1962 * @byte_offset: EEPROM byte offset to write 1963 * @eeprom_data: value to write 1964 * 1965 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1966 **/ 1967 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1968 u8 eeprom_data) 1969 { 1970 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1971 1972 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1973 IXGBE_I2C_EEPROM_DEV_ADDR, 1974 eeprom_data); 1975 } 1976 1977 /** 1978 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 1979 * @hw: pointer to hardware structure 1980 * @offset: eeprom offset to be read 1981 * @addr: I2C address to be read 1982 */ 1983 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1984 { 1985 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1986 offset == IXGBE_SFF_IDENTIFIER && 1987 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1988 return true; 1989 return false; 1990 } 1991 1992 /** 1993 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1994 * @hw: pointer to hardware structure 1995 * @byte_offset: byte offset to read 1996 * @dev_addr: address to read from 1997 * @data: value read 1998 * @lock: true if to take and release semaphore 1999 * 2000 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2001 * a specified device address. 2002 **/ 2003 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2004 u8 dev_addr, u8 *data, bool lock) 2005 { 2006 s32 status; 2007 u32 max_retry = 10; 2008 u32 retry = 0; 2009 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2010 bool nack = 1; 2011 *data = 0; 2012 2013 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2014 2015 if (hw->mac.type >= ixgbe_mac_X550) 2016 max_retry = 3; 2017 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2018 max_retry = IXGBE_SFP_DETECT_RETRIES; 2019 2020 do { 2021 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2022 return IXGBE_ERR_SWFW_SYNC; 2023 2024 ixgbe_i2c_start(hw); 2025 2026 /* Device Address and write indication */ 2027 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2028 if (status != IXGBE_SUCCESS) 2029 goto fail; 2030 2031 status = ixgbe_get_i2c_ack(hw); 2032 if (status != IXGBE_SUCCESS) 2033 goto fail; 2034 2035 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2036 if (status != IXGBE_SUCCESS) 2037 goto fail; 2038 2039 status = ixgbe_get_i2c_ack(hw); 2040 if (status != IXGBE_SUCCESS) 2041 goto fail; 2042 2043 ixgbe_i2c_start(hw); 2044 2045 /* Device Address and read indication */ 2046 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2047 if (status != IXGBE_SUCCESS) 2048 goto fail; 2049 2050 status = ixgbe_get_i2c_ack(hw); 2051 if (status != IXGBE_SUCCESS) 2052 goto fail; 2053 2054 ixgbe_clock_in_i2c_byte(hw, data); 2055 2056 status = ixgbe_clock_out_i2c_bit(hw, nack); 2057 if (status != IXGBE_SUCCESS) 2058 goto fail; 2059 2060 ixgbe_i2c_stop(hw); 2061 if (lock) 2062 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2063 return IXGBE_SUCCESS; 2064 2065 fail: 2066 ixgbe_i2c_bus_clear(hw); 2067 if (lock) { 2068 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2069 msec_delay(100); 2070 } 2071 if (retry < max_retry) 2072 DEBUGOUT("I2C byte read error - Retrying.\n"); 2073 else 2074 DEBUGOUT("I2C byte read error.\n"); 2075 retry++; 2076 } while (retry <= max_retry); 2077 2078 return status; 2079 } 2080 2081 /** 2082 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2083 * @hw: pointer to hardware structure 2084 * @byte_offset: byte offset to read 2085 * @dev_addr: address to read from 2086 * @data: value read 2087 * 2088 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2089 * a specified device address. 2090 **/ 2091 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2092 u8 dev_addr, u8 *data) 2093 { 2094 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2095 data, true); 2096 } 2097 2098 /** 2099 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2100 * @hw: pointer to hardware structure 2101 * @byte_offset: byte offset to read 2102 * @dev_addr: address to read from 2103 * @data: value read 2104 * 2105 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2106 * a specified device address. 2107 **/ 2108 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2109 u8 dev_addr, u8 *data) 2110 { 2111 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2112 data, false); 2113 } 2114 2115 /** 2116 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2117 * @hw: pointer to hardware structure 2118 * @byte_offset: byte offset to write 2119 * @dev_addr: address to write to 2120 * @data: value to write 2121 * @lock: true if to take and release semaphore 2122 * 2123 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2124 * a specified device address. 2125 **/ 2126 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2127 u8 dev_addr, u8 data, bool lock) 2128 { 2129 s32 status; 2130 u32 max_retry = 1; 2131 u32 retry = 0; 2132 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2133 2134 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2135 2136 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2137 IXGBE_SUCCESS) 2138 return IXGBE_ERR_SWFW_SYNC; 2139 2140 do { 2141 ixgbe_i2c_start(hw); 2142 2143 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2144 if (status != IXGBE_SUCCESS) 2145 goto fail; 2146 2147 status = ixgbe_get_i2c_ack(hw); 2148 if (status != IXGBE_SUCCESS) 2149 goto fail; 2150 2151 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2152 if (status != IXGBE_SUCCESS) 2153 goto fail; 2154 2155 status = ixgbe_get_i2c_ack(hw); 2156 if (status != IXGBE_SUCCESS) 2157 goto fail; 2158 2159 status = ixgbe_clock_out_i2c_byte(hw, data); 2160 if (status != IXGBE_SUCCESS) 2161 goto fail; 2162 2163 status = ixgbe_get_i2c_ack(hw); 2164 if (status != IXGBE_SUCCESS) 2165 goto fail; 2166 2167 ixgbe_i2c_stop(hw); 2168 if (lock) 2169 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2170 return IXGBE_SUCCESS; 2171 2172 fail: 2173 ixgbe_i2c_bus_clear(hw); 2174 if (retry < max_retry) 2175 DEBUGOUT("I2C byte write error - Retrying.\n"); 2176 else 2177 DEBUGOUT("I2C byte write error.\n"); 2178 retry++; 2179 } while (retry <= max_retry); 2180 2181 if (lock) 2182 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2183 2184 return status; 2185 } 2186 2187 /** 2188 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2189 * @hw: pointer to hardware structure 2190 * @byte_offset: byte offset to write 2191 * @dev_addr: address to write to 2192 * @data: value to write 2193 * 2194 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2195 * a specified device address. 2196 **/ 2197 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2198 u8 dev_addr, u8 data) 2199 { 2200 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2201 data, true); 2202 } 2203 2204 /** 2205 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2206 * @hw: pointer to hardware structure 2207 * @byte_offset: byte offset to write 2208 * @dev_addr: address to write to 2209 * @data: value to write 2210 * 2211 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2212 * a specified device address. 2213 **/ 2214 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2215 u8 dev_addr, u8 data) 2216 { 2217 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2218 data, false); 2219 } 2220 2221 /** 2222 * ixgbe_i2c_start - Sets I2C start condition 2223 * @hw: pointer to hardware structure 2224 * 2225 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2226 * Set bit-bang mode on X550 hardware. 2227 **/ 2228 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2229 { 2230 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2231 2232 DEBUGFUNC("ixgbe_i2c_start"); 2233 2234 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2235 2236 /* Start condition must begin with data and clock high */ 2237 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2238 ixgbe_raise_i2c_clk(hw, &i2cctl); 2239 2240 /* Setup time for start condition (4.7us) */ 2241 usec_delay(IXGBE_I2C_T_SU_STA); 2242 2243 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2244 2245 /* Hold time for start condition (4us) */ 2246 usec_delay(IXGBE_I2C_T_HD_STA); 2247 2248 ixgbe_lower_i2c_clk(hw, &i2cctl); 2249 2250 /* Minimum low period of clock is 4.7 us */ 2251 usec_delay(IXGBE_I2C_T_LOW); 2252 2253 } 2254 2255 /** 2256 * ixgbe_i2c_stop - Sets I2C stop condition 2257 * @hw: pointer to hardware structure 2258 * 2259 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2260 * Disables bit-bang mode and negates data output enable on X550 2261 * hardware. 2262 **/ 2263 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2264 { 2265 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2266 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2267 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2268 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2269 2270 DEBUGFUNC("ixgbe_i2c_stop"); 2271 2272 /* Stop condition must begin with data low and clock high */ 2273 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2274 ixgbe_raise_i2c_clk(hw, &i2cctl); 2275 2276 /* Setup time for stop condition (4us) */ 2277 usec_delay(IXGBE_I2C_T_SU_STO); 2278 2279 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2280 2281 /* bus free time between stop and start (4.7us)*/ 2282 usec_delay(IXGBE_I2C_T_BUF); 2283 2284 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2285 i2cctl &= ~bb_en_bit; 2286 i2cctl |= data_oe_bit | clk_oe_bit; 2287 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2288 IXGBE_WRITE_FLUSH(hw); 2289 } 2290 } 2291 2292 /** 2293 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2294 * @hw: pointer to hardware structure 2295 * @data: data byte to clock in 2296 * 2297 * Clocks in one byte data via I2C data/clock 2298 **/ 2299 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2300 { 2301 s32 i; 2302 bool bit = 0; 2303 2304 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2305 2306 *data = 0; 2307 for (i = 7; i >= 0; i--) { 2308 ixgbe_clock_in_i2c_bit(hw, &bit); 2309 *data |= bit << i; 2310 } 2311 } 2312 2313 /** 2314 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2315 * @hw: pointer to hardware structure 2316 * @data: data byte clocked out 2317 * 2318 * Clocks out one byte data via I2C data/clock 2319 **/ 2320 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2321 { 2322 s32 status = IXGBE_SUCCESS; 2323 s32 i; 2324 u32 i2cctl; 2325 bool bit; 2326 2327 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2328 2329 for (i = 7; i >= 0; i--) { 2330 bit = (data >> i) & 0x1; 2331 status = ixgbe_clock_out_i2c_bit(hw, bit); 2332 2333 if (status != IXGBE_SUCCESS) 2334 break; 2335 } 2336 2337 /* Release SDA line (set high) */ 2338 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2339 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2340 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2341 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2342 IXGBE_WRITE_FLUSH(hw); 2343 2344 return status; 2345 } 2346 2347 /** 2348 * ixgbe_get_i2c_ack - Polls for I2C ACK 2349 * @hw: pointer to hardware structure 2350 * 2351 * Clocks in/out one bit via I2C data/clock 2352 **/ 2353 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2354 { 2355 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2356 s32 status = IXGBE_SUCCESS; 2357 u32 i = 0; 2358 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2359 u32 timeout = 10; 2360 bool ack = 1; 2361 2362 DEBUGFUNC("ixgbe_get_i2c_ack"); 2363 2364 if (data_oe_bit) { 2365 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2366 i2cctl |= data_oe_bit; 2367 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2368 IXGBE_WRITE_FLUSH(hw); 2369 } 2370 ixgbe_raise_i2c_clk(hw, &i2cctl); 2371 2372 /* Minimum high period of clock is 4us */ 2373 usec_delay(IXGBE_I2C_T_HIGH); 2374 2375 /* Poll for ACK. Note that ACK in I2C spec is 2376 * transition from 1 to 0 */ 2377 for (i = 0; i < timeout; i++) { 2378 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2379 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2380 2381 usec_delay(1); 2382 if (!ack) 2383 break; 2384 } 2385 2386 if (ack) { 2387 DEBUGOUT("I2C ack was not received.\n"); 2388 status = IXGBE_ERR_I2C; 2389 } 2390 2391 ixgbe_lower_i2c_clk(hw, &i2cctl); 2392 2393 /* Minimum low period of clock is 4.7 us */ 2394 usec_delay(IXGBE_I2C_T_LOW); 2395 2396 return status; 2397 } 2398 2399 /** 2400 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2401 * @hw: pointer to hardware structure 2402 * @data: read data value 2403 * 2404 * Clocks in one bit via I2C data/clock 2405 **/ 2406 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2407 { 2408 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2409 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2410 2411 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2412 2413 if (data_oe_bit) { 2414 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2415 i2cctl |= data_oe_bit; 2416 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2417 IXGBE_WRITE_FLUSH(hw); 2418 } 2419 ixgbe_raise_i2c_clk(hw, &i2cctl); 2420 2421 /* Minimum high period of clock is 4us */ 2422 usec_delay(IXGBE_I2C_T_HIGH); 2423 2424 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2425 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2426 2427 ixgbe_lower_i2c_clk(hw, &i2cctl); 2428 2429 /* Minimum low period of clock is 4.7 us */ 2430 usec_delay(IXGBE_I2C_T_LOW); 2431 } 2432 2433 /** 2434 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2435 * @hw: pointer to hardware structure 2436 * @data: data value to write 2437 * 2438 * Clocks out one bit via I2C data/clock 2439 **/ 2440 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2441 { 2442 s32 status; 2443 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2444 2445 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2446 2447 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2448 if (status == IXGBE_SUCCESS) { 2449 ixgbe_raise_i2c_clk(hw, &i2cctl); 2450 2451 /* Minimum high period of clock is 4us */ 2452 usec_delay(IXGBE_I2C_T_HIGH); 2453 2454 ixgbe_lower_i2c_clk(hw, &i2cctl); 2455 2456 /* Minimum low period of clock is 4.7 us. 2457 * This also takes care of the data hold time. 2458 */ 2459 usec_delay(IXGBE_I2C_T_LOW); 2460 } else { 2461 status = IXGBE_ERR_I2C; 2462 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2463 "I2C data was not set to %X\n", data); 2464 } 2465 2466 return status; 2467 } 2468 2469 /** 2470 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2471 * @hw: pointer to hardware structure 2472 * @i2cctl: Current value of I2CCTL register 2473 * 2474 * Raises the I2C clock line '0'->'1' 2475 * Negates the I2C clock output enable on X550 hardware. 2476 **/ 2477 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2478 { 2479 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2480 u32 i = 0; 2481 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2482 u32 i2cctl_r = 0; 2483 2484 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2485 2486 if (clk_oe_bit) { 2487 *i2cctl |= clk_oe_bit; 2488 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2489 } 2490 2491 for (i = 0; i < timeout; i++) { 2492 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2493 2494 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2495 IXGBE_WRITE_FLUSH(hw); 2496 /* SCL rise time (1000ns) */ 2497 usec_delay(IXGBE_I2C_T_RISE); 2498 2499 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2500 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2501 break; 2502 } 2503 } 2504 2505 /** 2506 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2507 * @hw: pointer to hardware structure 2508 * @i2cctl: Current value of I2CCTL register 2509 * 2510 * Lowers the I2C clock line '1'->'0' 2511 * Asserts the I2C clock output enable on X550 hardware. 2512 **/ 2513 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2514 { 2515 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2516 2517 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2518 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2519 2520 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2521 IXGBE_WRITE_FLUSH(hw); 2522 2523 /* SCL fall time (300ns) */ 2524 usec_delay(IXGBE_I2C_T_FALL); 2525 } 2526 2527 /** 2528 * ixgbe_set_i2c_data - Sets the I2C data bit 2529 * @hw: pointer to hardware structure 2530 * @i2cctl: Current value of I2CCTL register 2531 * @data: I2C data value (0 or 1) to set 2532 * 2533 * Sets the I2C data bit 2534 * Asserts the I2C data output enable on X550 hardware. 2535 **/ 2536 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2537 { 2538 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2539 s32 status = IXGBE_SUCCESS; 2540 2541 DEBUGFUNC("ixgbe_set_i2c_data"); 2542 2543 if (data) 2544 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2545 else 2546 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2547 *i2cctl &= ~data_oe_bit; 2548 2549 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2550 IXGBE_WRITE_FLUSH(hw); 2551 2552 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2553 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2554 2555 if (!data) /* Can't verify data in this case */ 2556 return IXGBE_SUCCESS; 2557 if (data_oe_bit) { 2558 *i2cctl |= data_oe_bit; 2559 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2560 IXGBE_WRITE_FLUSH(hw); 2561 } 2562 2563 /* Verify data was set correctly */ 2564 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2565 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2566 status = IXGBE_ERR_I2C; 2567 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2568 "Error - I2C data was not set to %X.\n", 2569 data); 2570 } 2571 2572 return status; 2573 } 2574 2575 /** 2576 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2577 * @hw: pointer to hardware structure 2578 * @i2cctl: Current value of I2CCTL register 2579 * 2580 * Returns the I2C data bit value 2581 * Negates the I2C data output enable on X550 hardware. 2582 **/ 2583 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2584 { 2585 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2586 bool data; 2587 2588 DEBUGFUNC("ixgbe_get_i2c_data"); 2589 2590 if (data_oe_bit) { 2591 *i2cctl |= data_oe_bit; 2592 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2593 IXGBE_WRITE_FLUSH(hw); 2594 usec_delay(IXGBE_I2C_T_FALL); 2595 } 2596 2597 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2598 data = 1; 2599 else 2600 data = 0; 2601 2602 return data; 2603 } 2604 2605 /** 2606 * ixgbe_i2c_bus_clear - Clears the I2C bus 2607 * @hw: pointer to hardware structure 2608 * 2609 * Clears the I2C bus by sending nine clock pulses. 2610 * Used when data line is stuck low. 2611 **/ 2612 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2613 { 2614 u32 i2cctl; 2615 u32 i; 2616 2617 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2618 2619 ixgbe_i2c_start(hw); 2620 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2621 2622 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2623 2624 for (i = 0; i < 9; i++) { 2625 ixgbe_raise_i2c_clk(hw, &i2cctl); 2626 2627 /* Min high period of clock is 4us */ 2628 usec_delay(IXGBE_I2C_T_HIGH); 2629 2630 ixgbe_lower_i2c_clk(hw, &i2cctl); 2631 2632 /* Min low period of clock is 4.7us*/ 2633 usec_delay(IXGBE_I2C_T_LOW); 2634 } 2635 2636 ixgbe_i2c_start(hw); 2637 2638 /* Put the i2c bus back to default state */ 2639 ixgbe_i2c_stop(hw); 2640 } 2641 2642 /** 2643 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2644 * @hw: pointer to hardware structure 2645 * 2646 * Checks if the LASI temp alarm status was triggered due to overtemp 2647 **/ 2648 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2649 { 2650 s32 status = IXGBE_SUCCESS; 2651 u16 phy_data = 0; 2652 2653 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2654 2655 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2656 goto out; 2657 2658 /* Check that the LASI temp alarm status was triggered */ 2659 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2660 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2661 2662 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2663 goto out; 2664 2665 status = IXGBE_ERR_OVERTEMP; 2666 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2667 out: 2668 return status; 2669 } 2670 2671 /** 2672 * ixgbe_set_copper_phy_power - Control power for copper phy 2673 * @hw: pointer to hardware structure 2674 * @on: true for on, false for off 2675 */ 2676 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2677 { 2678 u32 status; 2679 u16 reg; 2680 2681 if (!on && ixgbe_mng_present(hw)) 2682 return 0; 2683 2684 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2685 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2686 ®); 2687 if (status) 2688 return status; 2689 2690 if (on) { 2691 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2692 } else { 2693 if (ixgbe_check_reset_blocked(hw)) 2694 return 0; 2695 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2696 } 2697 2698 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2699 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2700 reg); 2701 return status; 2702 } 2703