1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(u32 *i2cctl); 50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 54 * @hw: pointer to the hardware structure 55 * 56 * Initialize the function pointers. 57 **/ 58 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 /* PHY */ 63 phy->ops.identify = &ixgbe_identify_phy_generic; 64 phy->ops.reset = &ixgbe_reset_phy_generic; 65 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 66 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 67 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 68 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 69 phy->ops.check_link = NULL; 70 phy->ops.get_firmware_version = NULL; 71 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 72 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 73 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 74 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 75 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 76 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 77 phy->sfp_type = ixgbe_sfp_type_unknown; 78 79 return IXGBE_SUCCESS; 80 } 81 82 /** 83 * ixgbe_identify_phy_generic - Get physical layer module 84 * @hw: pointer to hardware structure 85 * 86 * Determines the physical layer module found on the current adapter. 87 **/ 88 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 89 { 90 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 91 u32 phy_addr; 92 u16 ext_ability = 0; 93 94 if (hw->phy.type == ixgbe_phy_unknown) { 95 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 96 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 97 hw->phy.addr = phy_addr; 98 ixgbe_get_phy_id(hw); 99 hw->phy.type = 100 ixgbe_get_phy_type_from_id(hw->phy.id); 101 102 if (hw->phy.type == ixgbe_phy_unknown) { 103 hw->phy.ops.read_reg(hw, 104 IXGBE_MDIO_PHY_EXT_ABILITY, 105 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 106 &ext_ability); 107 if (ext_ability & 108 IXGBE_MDIO_PHY_10GBASET_ABILITY || 109 ext_ability & 110 IXGBE_MDIO_PHY_1000BASET_ABILITY) 111 hw->phy.type = 112 ixgbe_phy_cu_unknown; 113 else 114 hw->phy.type = 115 ixgbe_phy_generic; 116 } 117 118 status = IXGBE_SUCCESS; 119 break; 120 } 121 } 122 if (status != IXGBE_SUCCESS) 123 hw->phy.addr = 0; 124 } else { 125 status = IXGBE_SUCCESS; 126 } 127 128 return status; 129 } 130 131 /** 132 * ixgbe_validate_phy_addr - Determines phy address is valid 133 * @hw: pointer to hardware structure 134 * 135 **/ 136 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 137 { 138 u16 phy_id = 0; 139 bool valid = FALSE; 140 141 hw->phy.addr = phy_addr; 142 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 143 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 144 145 if (phy_id != 0xFFFF && phy_id != 0x0) 146 valid = TRUE; 147 148 return valid; 149 } 150 151 /** 152 * ixgbe_get_phy_id - Get the phy type 153 * @hw: pointer to hardware structure 154 * 155 **/ 156 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 157 { 158 u32 status; 159 u16 phy_id_high = 0; 160 u16 phy_id_low = 0; 161 162 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 163 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 164 &phy_id_high); 165 166 if (status == IXGBE_SUCCESS) { 167 hw->phy.id = (u32)(phy_id_high << 16); 168 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 169 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 170 &phy_id_low); 171 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 172 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 173 } 174 return status; 175 } 176 177 /** 178 * ixgbe_get_phy_type_from_id - Get the phy type 179 * @hw: pointer to hardware structure 180 * 181 **/ 182 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 183 { 184 enum ixgbe_phy_type phy_type; 185 186 switch (phy_id) { 187 case TN1010_PHY_ID: 188 phy_type = ixgbe_phy_tn; 189 break; 190 case AQ1002_PHY_ID: 191 phy_type = ixgbe_phy_aq; 192 break; 193 case QT2022_PHY_ID: 194 phy_type = ixgbe_phy_qt; 195 break; 196 case ATH_PHY_ID: 197 phy_type = ixgbe_phy_nl; 198 break; 199 default: 200 phy_type = ixgbe_phy_unknown; 201 break; 202 } 203 204 DEBUGOUT1("phy type found is %d\n", phy_type); 205 return phy_type; 206 } 207 208 /** 209 * ixgbe_reset_phy_generic - Performs a PHY reset 210 * @hw: pointer to hardware structure 211 **/ 212 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 213 { 214 u32 i; 215 u16 ctrl = 0; 216 s32 status = IXGBE_SUCCESS; 217 218 if (hw->phy.type == ixgbe_phy_unknown) 219 status = ixgbe_identify_phy_generic(hw); 220 221 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 222 goto out; 223 224 /* 225 * Perform soft PHY reset to the PHY_XS. 226 * This will cause a soft reset to the PHY 227 */ 228 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 229 IXGBE_MDIO_PHY_XS_DEV_TYPE, 230 IXGBE_MDIO_PHY_XS_RESET); 231 232 /* Poll for reset bit to self-clear indicating reset is complete */ 233 for (i = 0; i < 500; i++) { 234 msec_delay(1); 235 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 236 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 237 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) 238 break; 239 } 240 241 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 242 status = IXGBE_ERR_RESET_FAILED; 243 DEBUGOUT("PHY reset polling failed to complete.\n"); 244 } 245 246 out: 247 return status; 248 } 249 250 /** 251 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 252 * @hw: pointer to hardware structure 253 * @reg_addr: 32 bit address of PHY register to read 254 * @phy_data: Pointer to read data from PHY register 255 **/ 256 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 257 u32 device_type, u16 *phy_data) 258 { 259 u32 command; 260 u32 i; 261 u32 data; 262 s32 status = IXGBE_SUCCESS; 263 u16 gssr; 264 265 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 266 gssr = IXGBE_GSSR_PHY1_SM; 267 else 268 gssr = IXGBE_GSSR_PHY0_SM; 269 270 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 271 status = IXGBE_ERR_SWFW_SYNC; 272 273 if (status == IXGBE_SUCCESS) { 274 /* Setup and write the address cycle command */ 275 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 276 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 277 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 278 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 279 280 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 281 282 /* 283 * Check every 10 usec to see if the address cycle completed. 284 * The MDI Command bit will clear when the operation is 285 * complete 286 */ 287 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 288 usec_delay(10); 289 290 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 291 292 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 293 break; 294 } 295 296 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 297 DEBUGOUT("PHY address command did not complete.\n"); 298 status = IXGBE_ERR_PHY; 299 } 300 301 if (status == IXGBE_SUCCESS) { 302 /* 303 * Address cycle complete, setup and write the read 304 * command 305 */ 306 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 307 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 308 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 309 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 310 311 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 312 313 /* 314 * Check every 10 usec to see if the address cycle 315 * completed. The MDI Command bit will clear when the 316 * operation is complete 317 */ 318 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 319 usec_delay(10); 320 321 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 322 323 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 324 break; 325 } 326 327 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 328 DEBUGOUT("PHY read command didn't complete\n"); 329 status = IXGBE_ERR_PHY; 330 } else { 331 /* 332 * Read operation is complete. Get the data 333 * from MSRWD 334 */ 335 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 336 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 337 *phy_data = (u16)(data); 338 } 339 } 340 341 ixgbe_release_swfw_sync(hw, gssr); 342 } 343 344 return status; 345 } 346 347 /** 348 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 349 * @hw: pointer to hardware structure 350 * @reg_addr: 32 bit PHY register to write 351 * @device_type: 5 bit device type 352 * @phy_data: Data to write to the PHY register 353 **/ 354 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 355 u32 device_type, u16 phy_data) 356 { 357 u32 command; 358 u32 i; 359 s32 status = IXGBE_SUCCESS; 360 u16 gssr; 361 362 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 363 gssr = IXGBE_GSSR_PHY1_SM; 364 else 365 gssr = IXGBE_GSSR_PHY0_SM; 366 367 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 368 status = IXGBE_ERR_SWFW_SYNC; 369 370 if (status == IXGBE_SUCCESS) { 371 /* Put the data in the MDI single read and write data register*/ 372 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 373 374 /* Setup and write the address cycle command */ 375 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 376 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 377 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 378 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 379 380 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 381 382 /* 383 * Check every 10 usec to see if the address cycle completed. 384 * The MDI Command bit will clear when the operation is 385 * complete 386 */ 387 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 388 usec_delay(10); 389 390 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 391 392 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 393 break; 394 } 395 396 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 397 DEBUGOUT("PHY address cmd didn't complete\n"); 398 status = IXGBE_ERR_PHY; 399 } 400 401 if (status == IXGBE_SUCCESS) { 402 /* 403 * Address cycle complete, setup and write the write 404 * command 405 */ 406 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 407 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 408 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 409 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 410 411 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 412 413 /* 414 * Check every 10 usec to see if the address cycle 415 * completed. The MDI Command bit will clear when the 416 * operation is complete 417 */ 418 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 419 usec_delay(10); 420 421 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 422 423 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 424 break; 425 } 426 427 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 428 DEBUGOUT("PHY address cmd didn't complete\n"); 429 status = IXGBE_ERR_PHY; 430 } 431 } 432 433 ixgbe_release_swfw_sync(hw, gssr); 434 } 435 436 return status; 437 } 438 439 /** 440 * ixgbe_setup_phy_link_generic - Set and restart autoneg 441 * @hw: pointer to hardware structure 442 * 443 * Restart autonegotiation and PHY and waits for completion. 444 **/ 445 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 446 { 447 s32 status = IXGBE_NOT_IMPLEMENTED; 448 u32 time_out; 449 u32 max_time_out = 10; 450 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 451 452 /* 453 * Set advertisement settings in PHY based on autoneg_advertised 454 * settings. If autoneg_advertised = 0, then advertise default values 455 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 456 * for a 1G. 457 */ 458 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 459 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 460 461 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) 462 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ 463 else 464 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ 465 466 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 467 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 468 469 /* Restart PHY autonegotiation and wait for completion */ 470 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 471 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 472 473 autoneg_reg |= IXGBE_MII_RESTART; 474 475 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 476 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 477 478 /* Wait for autonegotiation to finish */ 479 for (time_out = 0; time_out < max_time_out; time_out++) { 480 usec_delay(10); 481 /* Restart PHY autonegotiation and wait for completion */ 482 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 483 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 484 &autoneg_reg); 485 486 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 487 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 488 status = IXGBE_SUCCESS; 489 break; 490 } 491 } 492 493 if (time_out == max_time_out) 494 status = IXGBE_ERR_LINK_SETUP; 495 496 return status; 497 } 498 499 /** 500 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 501 * @hw: pointer to hardware structure 502 * @speed: new link speed 503 * @autoneg: TRUE if autonegotiation enabled 504 **/ 505 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 506 ixgbe_link_speed speed, 507 bool autoneg, 508 bool autoneg_wait_to_complete) 509 { 510 UNREFERENCED_PARAMETER(autoneg); 511 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 512 513 /* 514 * Clear autoneg_advertised and set new values based on input link 515 * speed. 516 */ 517 hw->phy.autoneg_advertised = 0; 518 519 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 520 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 521 522 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 523 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 524 525 if (speed & IXGBE_LINK_SPEED_100_FULL) 526 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 527 528 /* Setup link based on the new speed settings */ 529 hw->phy.ops.setup_link(hw); 530 531 return IXGBE_SUCCESS; 532 } 533 534 /** 535 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 536 * @hw: pointer to hardware structure 537 * @speed: pointer to link speed 538 * @autoneg: boolean auto-negotiation value 539 * 540 * Determines the link capabilities by reading the AUTOC register. 541 **/ 542 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 543 ixgbe_link_speed *speed, 544 bool *autoneg) 545 { 546 s32 status = IXGBE_ERR_LINK_SETUP; 547 u16 speed_ability; 548 549 *speed = 0; 550 *autoneg = TRUE; 551 552 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 553 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 554 &speed_ability); 555 556 if (status == IXGBE_SUCCESS) { 557 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 558 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 559 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 560 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 561 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 562 *speed |= IXGBE_LINK_SPEED_100_FULL; 563 } 564 565 return status; 566 } 567 568 /** 569 * ixgbe_check_phy_link_tnx - Determine link and speed status 570 * @hw: pointer to hardware structure 571 * 572 * Reads the VS1 register to determine if link is up and the current speed for 573 * the PHY. 574 **/ 575 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 576 bool *link_up) 577 { 578 s32 status = IXGBE_SUCCESS; 579 u32 time_out; 580 u32 max_time_out = 10; 581 u16 phy_link = 0; 582 u16 phy_speed = 0; 583 u16 phy_data = 0; 584 585 /* Initialize speed and link to default case */ 586 *link_up = FALSE; 587 *speed = IXGBE_LINK_SPEED_10GB_FULL; 588 589 /* 590 * Check current speed and link status of the PHY register. 591 * This is a vendor specific register and may have to 592 * be changed for other copper PHYs. 593 */ 594 for (time_out = 0; time_out < max_time_out; time_out++) { 595 usec_delay(10); 596 status = hw->phy.ops.read_reg(hw, 597 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 598 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 599 &phy_data); 600 phy_link = phy_data & 601 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 602 phy_speed = phy_data & 603 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 604 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 605 *link_up = TRUE; 606 if (phy_speed == 607 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 608 *speed = IXGBE_LINK_SPEED_1GB_FULL; 609 break; 610 } 611 } 612 613 return status; 614 } 615 616 /** 617 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 618 * @hw: pointer to hardware structure 619 * @firmware_version: pointer to the PHY Firmware Version 620 **/ 621 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 622 u16 *firmware_version) 623 { 624 s32 status = IXGBE_SUCCESS; 625 626 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 627 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 628 firmware_version); 629 630 return status; 631 } 632 633 634 /** 635 * ixgbe_get_phy_firmware_version_aq - Gets the PHY Firmware Version 636 * @hw: pointer to hardware structure 637 * @firmware_version: pointer to the PHY Firmware Version 638 **/ 639 s32 ixgbe_get_phy_firmware_version_aq(struct ixgbe_hw *hw, 640 u16 *firmware_version) 641 { 642 s32 status = IXGBE_SUCCESS; 643 644 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 645 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 646 firmware_version); 647 648 return status; 649 } 650 651 /** 652 * ixgbe_reset_phy_nl - Performs a PHY reset 653 * @hw: pointer to hardware structure 654 **/ 655 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 656 { 657 u16 phy_offset, control, eword, edata, block_crc; 658 bool end_data = FALSE; 659 u16 list_offset, data_offset; 660 u16 phy_data = 0; 661 s32 ret_val = IXGBE_SUCCESS; 662 u32 i; 663 664 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 665 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 666 667 /* reset the PHY and poll for completion */ 668 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 669 IXGBE_MDIO_PHY_XS_DEV_TYPE, 670 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 671 672 for (i = 0; i < 100; i++) { 673 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 674 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 675 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 676 break; 677 msec_delay(10); 678 } 679 680 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 681 DEBUGOUT("PHY reset did not complete.\n"); 682 ret_val = IXGBE_ERR_PHY; 683 goto out; 684 } 685 686 /* Get init offsets */ 687 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 688 &data_offset); 689 if (ret_val != IXGBE_SUCCESS) 690 goto out; 691 692 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 693 data_offset++; 694 while (!end_data) { 695 /* 696 * Read control word from PHY init contents offset 697 */ 698 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 699 control = (eword & IXGBE_CONTROL_MASK_NL) >> 700 IXGBE_CONTROL_SHIFT_NL; 701 edata = eword & IXGBE_DATA_MASK_NL; 702 switch (control) { 703 case IXGBE_DELAY_NL: 704 data_offset++; 705 DEBUGOUT1("DELAY: %d MS\n", edata); 706 msec_delay(edata); 707 break; 708 case IXGBE_DATA_NL: 709 DEBUGOUT("DATA: \n"); 710 data_offset++; 711 hw->eeprom.ops.read(hw, data_offset++, 712 &phy_offset); 713 for (i = 0; i < edata; i++) { 714 hw->eeprom.ops.read(hw, data_offset, &eword); 715 hw->phy.ops.write_reg(hw, phy_offset, 716 IXGBE_TWINAX_DEV, eword); 717 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 718 phy_offset); 719 data_offset++; 720 phy_offset++; 721 } 722 break; 723 case IXGBE_CONTROL_NL: 724 data_offset++; 725 DEBUGOUT("CONTROL: \n"); 726 if (edata == IXGBE_CONTROL_EOL_NL) { 727 DEBUGOUT("EOL\n"); 728 end_data = TRUE; 729 } else if (edata == IXGBE_CONTROL_SOL_NL) { 730 DEBUGOUT("SOL\n"); 731 } else { 732 DEBUGOUT("Bad control value\n"); 733 ret_val = IXGBE_ERR_PHY; 734 goto out; 735 } 736 break; 737 default: 738 DEBUGOUT("Bad control type\n"); 739 ret_val = IXGBE_ERR_PHY; 740 goto out; 741 } 742 } 743 744 out: 745 return ret_val; 746 } 747 748 /** 749 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 750 * @hw: pointer to hardware structure 751 * 752 * Searches for and identifies the SFP module and assigns appropriate PHY type. 753 **/ 754 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 755 { 756 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 757 u32 vendor_oui = 0; 758 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 759 u8 identifier = 0; 760 u8 comp_codes_1g = 0; 761 u8 comp_codes_10g = 0; 762 u8 oui_bytes[3] = {0, 0, 0}; 763 u8 transmission_media = 0; 764 u16 enforce_sfp = 0; 765 766 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 767 &identifier); 768 769 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 770 status = IXGBE_ERR_SFP_NOT_PRESENT; 771 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 772 if (hw->phy.type != ixgbe_phy_nl) { 773 hw->phy.id = 0; 774 hw->phy.type = ixgbe_phy_unknown; 775 } 776 goto out; 777 } 778 779 /* LAN ID is needed for sfp_type determination */ 780 hw->mac.ops.set_lan_id(hw); 781 782 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { 783 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 784 &comp_codes_1g); 785 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 786 &comp_codes_10g); 787 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA, 788 &transmission_media); 789 790 /* ID Module 791 * ========= 792 * 0 SFP_DA_CU 793 * 1 SFP_SR 794 * 2 SFP_LR 795 * 3 SFP_DA_CORE0 - 82599-specific 796 * 4 SFP_DA_CORE1 - 82599-specific 797 * 5 SFP_SR/LR_CORE0 - 82599-specific 798 * 6 SFP_SR/LR_CORE1 - 82599-specific 799 */ 800 if (hw->mac.type == ixgbe_mac_82598EB) { 801 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) 802 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 803 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 804 hw->phy.sfp_type = ixgbe_sfp_type_sr; 805 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 806 hw->phy.sfp_type = ixgbe_sfp_type_lr; 807 else 808 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 809 } else if (hw->mac.type == ixgbe_mac_82599EB) { 810 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) 811 if (hw->bus.lan_id == 0) 812 hw->phy.sfp_type = 813 ixgbe_sfp_type_da_cu_core0; 814 else 815 hw->phy.sfp_type = 816 ixgbe_sfp_type_da_cu_core1; 817 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 818 if (hw->bus.lan_id == 0) 819 hw->phy.sfp_type = 820 ixgbe_sfp_type_srlr_core0; 821 else 822 hw->phy.sfp_type = 823 ixgbe_sfp_type_srlr_core1; 824 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 825 if (hw->bus.lan_id == 0) 826 hw->phy.sfp_type = 827 ixgbe_sfp_type_srlr_core0; 828 else 829 hw->phy.sfp_type = 830 ixgbe_sfp_type_srlr_core1; 831 else 832 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 833 } 834 835 if (hw->phy.sfp_type != stored_sfp_type) 836 hw->phy.sfp_setup_needed = TRUE; 837 838 /* Determine if the SFP+ PHY is dual speed or not. */ 839 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 840 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 841 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 842 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 843 hw->phy.multispeed_fiber = TRUE; 844 /* Determine PHY vendor */ 845 if (hw->phy.type != ixgbe_phy_nl) { 846 hw->phy.id = identifier; 847 hw->phy.ops.read_i2c_eeprom(hw, 848 IXGBE_SFF_VENDOR_OUI_BYTE0, 849 &oui_bytes[0]); 850 hw->phy.ops.read_i2c_eeprom(hw, 851 IXGBE_SFF_VENDOR_OUI_BYTE1, 852 &oui_bytes[1]); 853 hw->phy.ops.read_i2c_eeprom(hw, 854 IXGBE_SFF_VENDOR_OUI_BYTE2, 855 &oui_bytes[2]); 856 857 vendor_oui = 858 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 859 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 860 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 861 862 switch (vendor_oui) { 863 case IXGBE_SFF_VENDOR_OUI_TYCO: 864 if (transmission_media & 865 IXGBE_SFF_TWIN_AX_CAPABLE) 866 hw->phy.type = ixgbe_phy_tw_tyco; 867 break; 868 case IXGBE_SFF_VENDOR_OUI_FTL: 869 hw->phy.type = ixgbe_phy_sfp_ftl; 870 break; 871 case IXGBE_SFF_VENDOR_OUI_AVAGO: 872 hw->phy.type = ixgbe_phy_sfp_avago; 873 break; 874 case IXGBE_SFF_VENDOR_OUI_INTEL: 875 hw->phy.type = ixgbe_phy_sfp_intel; 876 break; 877 default: 878 if (transmission_media & 879 IXGBE_SFF_TWIN_AX_CAPABLE) 880 hw->phy.type = ixgbe_phy_tw_unknown; 881 else 882 hw->phy.type = ixgbe_phy_sfp_unknown; 883 break; 884 } 885 } 886 887 if (comp_codes_10g == 0) { 888 hw->phy.type = ixgbe_phy_sfp_unsupported; 889 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 890 goto out; 891 } 892 if (hw->mac.type == ixgbe_mac_82598EB || 893 (hw->phy.sfp_type != ixgbe_sfp_type_sr && 894 hw->phy.sfp_type != ixgbe_sfp_type_lr && 895 hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 && 896 hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) { 897 status = IXGBE_SUCCESS; 898 goto out; 899 } 900 901 ixgbe_get_device_caps(hw, &enforce_sfp); 902 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 903 /* Make sure we're a supported PHY type */ 904 if (hw->phy.type == ixgbe_phy_sfp_intel) { 905 status = IXGBE_SUCCESS; 906 } else { 907 DEBUGOUT("SFP+ module not supported\n"); 908 hw->phy.type = ixgbe_phy_sfp_unsupported; 909 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 910 } 911 } else { 912 status = IXGBE_SUCCESS; 913 } 914 } 915 916 out: 917 return status; 918 } 919 920 /** 921 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 922 * @hw: pointer to hardware structure 923 * @list_offset: offset to the SFP ID list 924 * @data_offset: offset to the SFP data block 925 * 926 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 927 * so it returns the offsets to the phy init sequence block. 928 **/ 929 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 930 u16 *list_offset, 931 u16 *data_offset) 932 { 933 u16 sfp_id; 934 935 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 936 return IXGBE_ERR_SFP_NOT_SUPPORTED; 937 938 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 939 return IXGBE_ERR_SFP_NOT_PRESENT; 940 941 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 942 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 943 return IXGBE_ERR_SFP_NOT_SUPPORTED; 944 945 /* Read offset to PHY init contents */ 946 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 947 948 if ((!*list_offset) || (*list_offset == 0xFFFF)) 949 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 950 951 /* Shift offset to first ID word */ 952 (*list_offset)++; 953 954 /* 955 * Find the matching SFP ID in the EEPROM 956 * and program the init sequence 957 */ 958 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 959 960 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 961 if (sfp_id == hw->phy.sfp_type) { 962 (*list_offset)++; 963 hw->eeprom.ops.read(hw, *list_offset, data_offset); 964 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 965 DEBUGOUT("SFP+ module not supported\n"); 966 return IXGBE_ERR_SFP_NOT_SUPPORTED; 967 } else { 968 break; 969 } 970 } else { 971 (*list_offset) += 2; 972 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 973 return IXGBE_ERR_PHY; 974 } 975 } 976 977 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 978 DEBUGOUT("No matching SFP+ module found\n"); 979 return IXGBE_ERR_SFP_NOT_SUPPORTED; 980 } 981 982 return IXGBE_SUCCESS; 983 } 984 985 /** 986 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 987 * @hw: pointer to hardware structure 988 * @byte_offset: EEPROM byte offset to read 989 * @eeprom_data: value read 990 * 991 * Performs byte read operation to SFP module's EEPROM over I2C interface. 992 **/ 993 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 994 u8 *eeprom_data) 995 { 996 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 997 998 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 999 IXGBE_I2C_EEPROM_DEV_ADDR, 1000 eeprom_data); 1001 } 1002 1003 /** 1004 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1005 * @hw: pointer to hardware structure 1006 * @byte_offset: EEPROM byte offset to write 1007 * @eeprom_data: value to write 1008 * 1009 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1010 **/ 1011 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1012 u8 eeprom_data) 1013 { 1014 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1015 1016 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1017 IXGBE_I2C_EEPROM_DEV_ADDR, 1018 eeprom_data); 1019 } 1020 1021 /** 1022 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1023 * @hw: pointer to hardware structure 1024 * @byte_offset: byte offset to read 1025 * @data: value read 1026 * 1027 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1028 * a specified deivce address. 1029 **/ 1030 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1031 u8 dev_addr, u8 *data) 1032 { 1033 s32 status = IXGBE_SUCCESS; 1034 u32 max_retry = 1; 1035 u32 retry = 0; 1036 u16 swfw_mask = 0; 1037 bool nack = 1; 1038 1039 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1040 1041 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1042 swfw_mask = IXGBE_GSSR_PHY1_SM; 1043 else 1044 swfw_mask = IXGBE_GSSR_PHY0_SM; 1045 1046 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1047 status = IXGBE_ERR_SWFW_SYNC; 1048 goto read_byte_out; 1049 } 1050 1051 do { 1052 ixgbe_i2c_start(hw); 1053 1054 /* Device Address and write indication */ 1055 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1056 if (status != IXGBE_SUCCESS) 1057 goto fail; 1058 1059 status = ixgbe_get_i2c_ack(hw); 1060 if (status != IXGBE_SUCCESS) 1061 goto fail; 1062 1063 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1064 if (status != IXGBE_SUCCESS) 1065 goto fail; 1066 1067 status = ixgbe_get_i2c_ack(hw); 1068 if (status != IXGBE_SUCCESS) 1069 goto fail; 1070 1071 ixgbe_i2c_start(hw); 1072 1073 /* Device Address and read indication */ 1074 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1075 if (status != IXGBE_SUCCESS) 1076 goto fail; 1077 1078 status = ixgbe_get_i2c_ack(hw); 1079 if (status != IXGBE_SUCCESS) 1080 goto fail; 1081 1082 status = ixgbe_clock_in_i2c_byte(hw, data); 1083 if (status != IXGBE_SUCCESS) 1084 goto fail; 1085 1086 status = ixgbe_clock_out_i2c_bit(hw, nack); 1087 if (status != IXGBE_SUCCESS) 1088 goto fail; 1089 1090 ixgbe_i2c_stop(hw); 1091 break; 1092 1093 fail: 1094 ixgbe_i2c_bus_clear(hw); 1095 retry++; 1096 if (retry < max_retry) 1097 DEBUGOUT("I2C byte read error - Retrying.\n"); 1098 else 1099 DEBUGOUT("I2C byte read error.\n"); 1100 1101 } while (retry < max_retry); 1102 1103 ixgbe_release_swfw_sync(hw, swfw_mask); 1104 1105 read_byte_out: 1106 return status; 1107 } 1108 1109 /** 1110 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1111 * @hw: pointer to hardware structure 1112 * @byte_offset: byte offset to write 1113 * @data: value to write 1114 * 1115 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1116 * a specified device address. 1117 **/ 1118 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1119 u8 dev_addr, u8 data) 1120 { 1121 s32 status = IXGBE_SUCCESS; 1122 u32 max_retry = 1; 1123 u32 retry = 0; 1124 u16 swfw_mask = 0; 1125 1126 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1127 1128 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1129 swfw_mask = IXGBE_GSSR_PHY1_SM; 1130 else 1131 swfw_mask = IXGBE_GSSR_PHY0_SM; 1132 1133 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1134 status = IXGBE_ERR_SWFW_SYNC; 1135 goto write_byte_out; 1136 } 1137 1138 do { 1139 ixgbe_i2c_start(hw); 1140 1141 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1142 if (status != IXGBE_SUCCESS) 1143 goto fail; 1144 1145 status = ixgbe_get_i2c_ack(hw); 1146 if (status != IXGBE_SUCCESS) 1147 goto fail; 1148 1149 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1150 if (status != IXGBE_SUCCESS) 1151 goto fail; 1152 1153 status = ixgbe_get_i2c_ack(hw); 1154 if (status != IXGBE_SUCCESS) 1155 goto fail; 1156 1157 status = ixgbe_clock_out_i2c_byte(hw, data); 1158 if (status != IXGBE_SUCCESS) 1159 goto fail; 1160 1161 status = ixgbe_get_i2c_ack(hw); 1162 if (status != IXGBE_SUCCESS) 1163 goto fail; 1164 1165 ixgbe_i2c_stop(hw); 1166 break; 1167 1168 fail: 1169 ixgbe_i2c_bus_clear(hw); 1170 retry++; 1171 if (retry < max_retry) 1172 DEBUGOUT("I2C byte write error - Retrying.\n"); 1173 else 1174 DEBUGOUT("I2C byte write error.\n"); 1175 } while (retry < max_retry); 1176 1177 ixgbe_release_swfw_sync(hw, swfw_mask); 1178 1179 write_byte_out: 1180 return status; 1181 } 1182 1183 /** 1184 * ixgbe_i2c_start - Sets I2C start condition 1185 * @hw: pointer to hardware structure 1186 * 1187 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1188 **/ 1189 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1190 { 1191 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1192 1193 DEBUGFUNC("ixgbe_i2c_start"); 1194 1195 /* Start condition must begin with data and clock high */ 1196 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1197 ixgbe_raise_i2c_clk(hw, &i2cctl); 1198 1199 /* Setup time for start condition (4.7us) */ 1200 usec_delay(IXGBE_I2C_T_SU_STA); 1201 1202 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1203 1204 /* Hold time for start condition (4us) */ 1205 usec_delay(IXGBE_I2C_T_HD_STA); 1206 1207 ixgbe_lower_i2c_clk(hw, &i2cctl); 1208 1209 /* Minimum low period of clock is 4.7 us */ 1210 usec_delay(IXGBE_I2C_T_LOW); 1211 1212 } 1213 1214 /** 1215 * ixgbe_i2c_stop - Sets I2C stop condition 1216 * @hw: pointer to hardware structure 1217 * 1218 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1219 **/ 1220 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1221 { 1222 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1223 1224 DEBUGFUNC("ixgbe_i2c_stop"); 1225 1226 /* Stop condition must begin with data low and clock high */ 1227 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1228 ixgbe_raise_i2c_clk(hw, &i2cctl); 1229 1230 /* Setup time for stop condition (4us) */ 1231 usec_delay(IXGBE_I2C_T_SU_STO); 1232 1233 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1234 1235 /* bus free time between stop and start (4.7us)*/ 1236 usec_delay(IXGBE_I2C_T_BUF); 1237 } 1238 1239 /** 1240 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1241 * @hw: pointer to hardware structure 1242 * @data: data byte to clock in 1243 * 1244 * Clocks in one byte data via I2C data/clock 1245 **/ 1246 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1247 { 1248 s32 status = IXGBE_SUCCESS; 1249 s32 i; 1250 bool bit = 0; 1251 1252 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1253 1254 for (i = 7; i >= 0; i--) { 1255 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1256 *data |= bit<<i; 1257 1258 if (status != IXGBE_SUCCESS) 1259 break; 1260 } 1261 1262 return status; 1263 } 1264 1265 /** 1266 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1267 * @hw: pointer to hardware structure 1268 * @data: data byte clocked out 1269 * 1270 * Clocks out one byte data via I2C data/clock 1271 **/ 1272 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1273 { 1274 s32 status = IXGBE_SUCCESS; 1275 s32 i; 1276 u32 i2cctl; 1277 bool bit = 0; 1278 1279 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1280 1281 for (i = 7; i >= 0; i--) { 1282 bit = (data >> i) & 0x1; 1283 status = ixgbe_clock_out_i2c_bit(hw, bit); 1284 1285 if (status != IXGBE_SUCCESS) 1286 break; 1287 } 1288 1289 /* Release SDA line (set high) */ 1290 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1291 i2cctl |= IXGBE_I2C_DATA_OUT; 1292 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1293 1294 return status; 1295 } 1296 1297 /** 1298 * ixgbe_get_i2c_ack - Polls for I2C ACK 1299 * @hw: pointer to hardware structure 1300 * 1301 * Clocks in/out one bit via I2C data/clock 1302 **/ 1303 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1304 { 1305 s32 status; 1306 u32 i = 0; 1307 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1308 u32 timeout = 10; 1309 bool ack = 1; 1310 1311 DEBUGFUNC("ixgbe_get_i2c_ack"); 1312 1313 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1314 1315 if (status != IXGBE_SUCCESS) 1316 goto out; 1317 1318 /* Minimum high period of clock is 4us */ 1319 usec_delay(IXGBE_I2C_T_HIGH); 1320 1321 /* Poll for ACK. Note that ACK in I2C spec is 1322 * transition from 1 to 0 */ 1323 for (i = 0; i < timeout; i++) { 1324 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1325 ack = ixgbe_get_i2c_data(&i2cctl); 1326 1327 usec_delay(1); 1328 if (ack == 0) 1329 break; 1330 } 1331 1332 if (ack == 1) { 1333 DEBUGOUT("I2C ack was not received.\n"); 1334 status = IXGBE_ERR_I2C; 1335 } 1336 1337 ixgbe_lower_i2c_clk(hw, &i2cctl); 1338 1339 /* Minimum low period of clock is 4.7 us */ 1340 usec_delay(IXGBE_I2C_T_LOW); 1341 1342 out: 1343 return status; 1344 } 1345 1346 /** 1347 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1348 * @hw: pointer to hardware structure 1349 * @data: read data value 1350 * 1351 * Clocks in one bit via I2C data/clock 1352 **/ 1353 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1354 { 1355 s32 status; 1356 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1357 1358 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1359 1360 /* Minimum high period of clock is 4us */ 1361 usec_delay(IXGBE_I2C_T_HIGH); 1362 1363 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1364 *data = ixgbe_get_i2c_data(&i2cctl); 1365 1366 ixgbe_lower_i2c_clk(hw, &i2cctl); 1367 1368 /* Minimum low period of clock is 4.7 us */ 1369 usec_delay(IXGBE_I2C_T_LOW); 1370 1371 return status; 1372 } 1373 1374 /** 1375 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1376 * @hw: pointer to hardware structure 1377 * @data: data value to write 1378 * 1379 * Clocks out one bit via I2C data/clock 1380 **/ 1381 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1382 { 1383 s32 status; 1384 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1385 1386 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1387 if (status == IXGBE_SUCCESS) { 1388 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1389 1390 /* Minimum high period of clock is 4us */ 1391 usec_delay(IXGBE_I2C_T_HIGH); 1392 1393 ixgbe_lower_i2c_clk(hw, &i2cctl); 1394 1395 /* Minimum low period of clock is 4.7 us. 1396 * This also takes care of the data hold time. 1397 */ 1398 usec_delay(IXGBE_I2C_T_LOW); 1399 } else { 1400 status = IXGBE_ERR_I2C; 1401 DEBUGOUT1("I2C data was not set to %X\n", data); 1402 } 1403 1404 return status; 1405 } 1406 /** 1407 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1408 * @hw: pointer to hardware structure 1409 * @i2cctl: Current value of I2CCTL register 1410 * 1411 * Raises the I2C clock line '0'->'1' 1412 **/ 1413 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1414 { 1415 s32 status = IXGBE_SUCCESS; 1416 1417 *i2cctl |= IXGBE_I2C_CLK_OUT; 1418 1419 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1420 1421 /* SCL rise time (1000ns) */ 1422 usec_delay(IXGBE_I2C_T_RISE); 1423 1424 return status; 1425 } 1426 1427 /** 1428 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1429 * @hw: pointer to hardware structure 1430 * @i2cctl: Current value of I2CCTL register 1431 * 1432 * Lowers the I2C clock line '1'->'0' 1433 **/ 1434 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1435 { 1436 1437 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1438 1439 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1440 1441 /* SCL fall time (300ns) */ 1442 usec_delay(IXGBE_I2C_T_FALL); 1443 } 1444 1445 /** 1446 * ixgbe_set_i2c_data - Sets the I2C data bit 1447 * @hw: pointer to hardware structure 1448 * @i2cctl: Current value of I2CCTL register 1449 * @data: I2C data value (0 or 1) to set 1450 * 1451 * Sets the I2C data bit 1452 **/ 1453 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1454 { 1455 s32 status = IXGBE_SUCCESS; 1456 1457 if (data) 1458 *i2cctl |= IXGBE_I2C_DATA_OUT; 1459 else 1460 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1461 1462 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1463 1464 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1465 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1466 1467 /* Verify data was set correctly */ 1468 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1469 if (data != ixgbe_get_i2c_data(i2cctl)) { 1470 status = IXGBE_ERR_I2C; 1471 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1472 } 1473 1474 return status; 1475 } 1476 1477 /** 1478 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1479 * @hw: pointer to hardware structure 1480 * @i2cctl: Current value of I2CCTL register 1481 * 1482 * Returns the I2C data bit value 1483 **/ 1484 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1485 { 1486 bool data; 1487 1488 if (*i2cctl & IXGBE_I2C_DATA_IN) 1489 data = 1; 1490 else 1491 data = 0; 1492 1493 return data; 1494 } 1495 1496 /** 1497 * ixgbe_i2c_bus_clear - Clears the I2C bus 1498 * @hw: pointer to hardware structure 1499 * 1500 * Clears the I2C bus by sending nine clock pulses. 1501 * Used when data line is stuck low. 1502 **/ 1503 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1504 { 1505 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1506 u32 i; 1507 1508 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1509 1510 ixgbe_i2c_start(hw); 1511 1512 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1513 1514 for (i = 0; i < 9; i++) { 1515 ixgbe_raise_i2c_clk(hw, &i2cctl); 1516 1517 /* Min high period of clock is 4us */ 1518 usec_delay(IXGBE_I2C_T_HIGH); 1519 1520 ixgbe_lower_i2c_clk(hw, &i2cctl); 1521 1522 /* Min low period of clock is 4.7us*/ 1523 usec_delay(IXGBE_I2C_T_LOW); 1524 } 1525 1526 ixgbe_i2c_start(hw); 1527 1528 /* Put the i2c bus back to default state */ 1529 ixgbe_i2c_stop(hw); 1530 } 1531