1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53 /** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61 { 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68 } 69 70 /** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78 { 79 ixgbe_clock_in_i2c_byte(hw, byte); 80 /* ACK */ 81 return ixgbe_clock_out_i2c_bit(hw, false); 82 } 83 84 /** 85 * ixgbe_ones_comp_byte_add - Perform one's complement addition 86 * @add1: addend 1 87 * @add2: addend 2 88 * 89 * Returns one's complement 8-bit sum. 90 */ 91 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 92 { 93 u16 sum = add1 + add2; 94 95 sum = (sum & 0xFF) + (sum >> 8); 96 return sum & 0xFF; 97 } 98 99 /** 100 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 101 * @hw: pointer to the hardware structure 102 * @addr: I2C bus address to read from 103 * @reg: I2C device register to read from 104 * @val: pointer to location to receive read value 105 * @lock: true if to take and release semaphore 106 * 107 * Returns an error code on error. 108 */ 109 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 110 u16 *val, bool lock) 111 { 112 u32 swfw_mask = hw->phy.phy_semaphore_mask; 113 int max_retry = 3; 114 int retry = 0; 115 u8 csum_byte; 116 u8 high_bits; 117 u8 low_bits; 118 u8 reg_high; 119 u8 csum; 120 121 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 122 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 123 csum = ~csum; 124 do { 125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 126 return IXGBE_ERR_SWFW_SYNC; 127 ixgbe_i2c_start(hw); 128 /* Device Address and write indication */ 129 if (ixgbe_out_i2c_byte_ack(hw, addr)) 130 goto fail; 131 /* Write bits 14:8 */ 132 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 133 goto fail; 134 /* Write bits 7:0 */ 135 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 136 goto fail; 137 /* Write csum */ 138 if (ixgbe_out_i2c_byte_ack(hw, csum)) 139 goto fail; 140 /* Re-start condition */ 141 ixgbe_i2c_start(hw); 142 /* Device Address and read indication */ 143 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 144 goto fail; 145 /* Get upper bits */ 146 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 147 goto fail; 148 /* Get low bits */ 149 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 150 goto fail; 151 /* Get csum */ 152 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 153 /* NACK */ 154 if (ixgbe_clock_out_i2c_bit(hw, false)) 155 goto fail; 156 ixgbe_i2c_stop(hw); 157 if (lock) 158 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 159 *val = (high_bits << 8) | low_bits; 160 return 0; 161 162 fail: 163 ixgbe_i2c_bus_clear(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 if (retry < max_retry) 167 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 168 else 169 DEBUGOUT("I2C byte read combined error.\n"); 170 retry++; 171 } while (retry <= max_retry); 172 173 return IXGBE_ERR_I2C; 174 } 175 176 /** 177 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 178 * @hw: pointer to the hardware structure 179 * @addr: I2C bus address to write to 180 * @reg: I2C device register to write to 181 * @val: value to write 182 * @lock: true if to take and release semaphore 183 * 184 * Returns an error code on error. 185 */ 186 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 187 u16 val, bool lock) 188 { 189 u32 swfw_mask = hw->phy.phy_semaphore_mask; 190 int max_retry = 1; 191 int retry = 0; 192 u8 reg_high; 193 u8 csum; 194 195 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 196 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 197 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 198 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 199 csum = ~csum; 200 do { 201 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 202 return IXGBE_ERR_SWFW_SYNC; 203 ixgbe_i2c_start(hw); 204 /* Device Address and write indication */ 205 if (ixgbe_out_i2c_byte_ack(hw, addr)) 206 goto fail; 207 /* Write bits 14:8 */ 208 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 209 goto fail; 210 /* Write bits 7:0 */ 211 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 212 goto fail; 213 /* Write data 15:8 */ 214 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 215 goto fail; 216 /* Write data 7:0 */ 217 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 218 goto fail; 219 /* Write csum */ 220 if (ixgbe_out_i2c_byte_ack(hw, csum)) 221 goto fail; 222 ixgbe_i2c_stop(hw); 223 if (lock) 224 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 225 return 0; 226 227 fail: 228 ixgbe_i2c_bus_clear(hw); 229 if (lock) 230 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 231 if (retry < max_retry) 232 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 233 else 234 DEBUGOUT("I2C byte write combined error.\n"); 235 retry++; 236 } while (retry <= max_retry); 237 238 return IXGBE_ERR_I2C; 239 } 240 241 /** 242 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 243 * @hw: pointer to the hardware structure 244 * 245 * Initialize the function pointers. 246 **/ 247 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 248 { 249 struct ixgbe_phy_info *phy = &hw->phy; 250 251 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 252 253 /* PHY */ 254 phy->ops.identify = ixgbe_identify_phy_generic; 255 phy->ops.reset = ixgbe_reset_phy_generic; 256 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 257 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 260 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 261 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 262 phy->ops.check_link = NULL; 263 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 264 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 265 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 266 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 267 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 268 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 269 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 270 phy->ops.identify_sfp = ixgbe_identify_module_generic; 271 phy->sfp_type = ixgbe_sfp_type_unknown; 272 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 273 phy->ops.write_i2c_byte_unlocked = 274 ixgbe_write_i2c_byte_generic_unlocked; 275 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 276 return IXGBE_SUCCESS; 277 } 278 279 /** 280 * ixgbe_probe_phy - Probe a single address for a PHY 281 * @hw: pointer to hardware structure 282 * @phy_addr: PHY address to probe 283 * 284 * Returns true if PHY found 285 */ 286 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 287 { 288 u16 ext_ability = 0; 289 290 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 291 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 292 phy_addr); 293 return false; 294 } 295 296 if (ixgbe_get_phy_id(hw)) 297 return false; 298 299 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 300 301 if (hw->phy.type == ixgbe_phy_unknown) { 302 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 303 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 304 if (ext_ability & 305 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 306 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 307 hw->phy.type = ixgbe_phy_cu_unknown; 308 else 309 hw->phy.type = ixgbe_phy_generic; 310 } 311 312 return true; 313 } 314 315 /** 316 * ixgbe_identify_phy_generic - Get physical layer module 317 * @hw: pointer to hardware structure 318 * 319 * Determines the physical layer module found on the current adapter. 320 **/ 321 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 322 { 323 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 324 u16 phy_addr; 325 326 DEBUGFUNC("ixgbe_identify_phy_generic"); 327 328 if (!hw->phy.phy_semaphore_mask) { 329 if (hw->bus.lan_id) 330 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 331 else 332 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 333 } 334 335 if (hw->phy.type != ixgbe_phy_unknown) 336 return IXGBE_SUCCESS; 337 338 if (hw->phy.nw_mng_if_sel) { 339 phy_addr = (hw->phy.nw_mng_if_sel & 340 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 342 if (ixgbe_probe_phy(hw, phy_addr)) 343 return IXGBE_SUCCESS; 344 else 345 return IXGBE_ERR_PHY_ADDR_INVALID; 346 } 347 348 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 349 if (ixgbe_probe_phy(hw, phy_addr)) { 350 status = IXGBE_SUCCESS; 351 break; 352 } 353 } 354 355 /* Certain media types do not have a phy so an address will not 356 * be found and the code will take this path. Caller has to 357 * decide if it is an error or not. 358 */ 359 if (status != IXGBE_SUCCESS) 360 hw->phy.addr = 0; 361 362 return status; 363 } 364 365 /** 366 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 367 * @hw: pointer to the hardware structure 368 * 369 * This function checks the MMNGC.MNG_VETO bit to see if there are 370 * any constraints on link from manageability. For MAC's that don't 371 * have this bit just return faluse since the link can not be blocked 372 * via this method. 373 **/ 374 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 375 { 376 u32 mmngc; 377 378 DEBUGFUNC("ixgbe_check_reset_blocked"); 379 380 /* If we don't have this bit, it can't be blocking */ 381 if (hw->mac.type == ixgbe_mac_82598EB) 382 return false; 383 384 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 385 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 386 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 387 "MNG_VETO bit detected.\n"); 388 return true; 389 } 390 391 return false; 392 } 393 394 /** 395 * ixgbe_validate_phy_addr - Determines phy address is valid 396 * @hw: pointer to hardware structure 397 * @phy_addr: PHY address 398 * 399 **/ 400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 401 { 402 u16 phy_id = 0; 403 bool valid = false; 404 405 DEBUGFUNC("ixgbe_validate_phy_addr"); 406 407 hw->phy.addr = phy_addr; 408 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 409 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 410 411 if (phy_id != 0xFFFF && phy_id != 0x0) 412 valid = true; 413 414 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 415 416 return valid; 417 } 418 419 /** 420 * ixgbe_get_phy_id - Get the phy type 421 * @hw: pointer to hardware structure 422 * 423 **/ 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 425 { 426 u32 status; 427 u16 phy_id_high = 0; 428 u16 phy_id_low = 0; 429 430 DEBUGFUNC("ixgbe_get_phy_id"); 431 432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 433 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 434 &phy_id_high); 435 436 if (status == IXGBE_SUCCESS) { 437 hw->phy.id = (u32)(phy_id_high << 16); 438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 439 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 440 &phy_id_low); 441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 443 } 444 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 445 phy_id_high, phy_id_low); 446 447 return status; 448 } 449 450 /** 451 * ixgbe_get_phy_type_from_id - Get the phy type 452 * @phy_id: PHY ID information 453 * 454 **/ 455 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 456 { 457 enum ixgbe_phy_type phy_type; 458 459 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 460 461 switch (phy_id) { 462 case TN1010_PHY_ID: 463 phy_type = ixgbe_phy_tn; 464 break; 465 case X550_PHY_ID: 466 case X540_PHY_ID: 467 phy_type = ixgbe_phy_aq; 468 break; 469 case QT2022_PHY_ID: 470 phy_type = ixgbe_phy_qt; 471 break; 472 case ATH_PHY_ID: 473 phy_type = ixgbe_phy_nl; 474 break; 475 case X557_PHY_ID: 476 case X557_PHY_ID2: 477 phy_type = ixgbe_phy_x550em_ext_t; 478 break; 479 case IXGBE_M88E1500_E_PHY_ID: 480 case IXGBE_M88E1543_E_PHY_ID: 481 phy_type = ixgbe_phy_ext_1g_t; 482 break; 483 default: 484 phy_type = ixgbe_phy_unknown; 485 break; 486 } 487 return phy_type; 488 } 489 490 /** 491 * ixgbe_reset_phy_generic - Performs a PHY reset 492 * @hw: pointer to hardware structure 493 **/ 494 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 495 { 496 u32 i; 497 u16 ctrl = 0; 498 s32 status = IXGBE_SUCCESS; 499 500 DEBUGFUNC("ixgbe_reset_phy_generic"); 501 502 if (hw->phy.type == ixgbe_phy_unknown) 503 status = ixgbe_identify_phy_generic(hw); 504 505 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 506 goto out; 507 508 /* Don't reset PHY if it's shut down due to overtemp. */ 509 if (!hw->phy.reset_if_overtemp && 510 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 511 goto out; 512 513 /* Blocked by MNG FW so bail */ 514 if (ixgbe_check_reset_blocked(hw)) 515 goto out; 516 517 /* 518 * Perform soft PHY reset to the PHY_XS. 519 * This will cause a soft reset to the PHY 520 */ 521 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 522 IXGBE_MDIO_PHY_XS_DEV_TYPE, 523 IXGBE_MDIO_PHY_XS_RESET); 524 525 /* 526 * Poll for reset bit to self-clear indicating reset is complete. 527 * Some PHYs could take up to 3 seconds to complete and need about 528 * 1.7 usec delay after the reset is complete. 529 */ 530 for (i = 0; i < 30; i++) { 531 msec_delay(100); 532 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 533 status = hw->phy.ops.read_reg(hw, 534 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 535 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 536 &ctrl); 537 if (status != IXGBE_SUCCESS) 538 return status; 539 540 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 541 usec_delay(2); 542 break; 543 } 544 } else { 545 status = hw->phy.ops.read_reg(hw, 546 IXGBE_MDIO_PHY_XS_CONTROL, 547 IXGBE_MDIO_PHY_XS_DEV_TYPE, 548 &ctrl); 549 if (status != IXGBE_SUCCESS) 550 return status; 551 552 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 553 usec_delay(2); 554 break; 555 } 556 } 557 } 558 559 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 560 status = IXGBE_ERR_RESET_FAILED; 561 ERROR_REPORT1(IXGBE_ERROR_POLLING, 562 "PHY reset polling failed to complete.\n"); 563 } 564 565 out: 566 return status; 567 } 568 569 /** 570 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY 571 * @hw: pointer to hardware structure 572 **/ 573 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw) 574 { 575 u16 autoneg_reg; 576 577 /* Check if PHY reset is blocked by MNG FW */ 578 if (ixgbe_check_reset_blocked(hw)) 579 return; 580 581 /* Restart PHY auto-negotiation. */ 582 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 583 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 584 autoneg_reg |= IXGBE_MII_RESTART; 585 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 586 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 587 } 588 589 /** 590 * ixgbe_read_phy_reg_mdi - Reads a value from a specified PHY register without 591 * the SWFW lock 592 * @hw: pointer to hardware structure 593 * @reg_addr: 32 bit address of PHY register to read 594 * @device_type: 5 bit device type 595 * @phy_data: Pointer to read data from PHY register 596 **/ 597 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 598 u16 *phy_data) 599 { 600 u32 i, data, command; 601 602 /* Setup and write the address cycle command */ 603 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 604 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 605 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 606 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 607 608 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 609 610 /* 611 * Check every 10 usec to see if the address cycle completed. 612 * The MDI Command bit will clear when the operation is 613 * complete 614 */ 615 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 616 usec_delay(10); 617 618 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 619 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 620 break; 621 } 622 623 624 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 625 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 626 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 627 return IXGBE_ERR_PHY; 628 } 629 630 /* 631 * Address cycle complete, setup and write the read 632 * command 633 */ 634 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 635 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 636 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 637 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 638 639 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 640 641 /* 642 * Check every 10 usec to see if the address cycle 643 * completed. The MDI Command bit will clear when the 644 * operation is complete 645 */ 646 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 647 usec_delay(10); 648 649 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 650 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 651 break; 652 } 653 654 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 655 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 656 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 657 return IXGBE_ERR_PHY; 658 } 659 660 /* 661 * Read operation is complete. Get the data 662 * from MSRWD 663 */ 664 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 665 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 666 *phy_data = (u16)(data); 667 668 return IXGBE_SUCCESS; 669 } 670 671 /** 672 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 673 * using the SWFW lock - this function is needed in most cases 674 * @hw: pointer to hardware structure 675 * @reg_addr: 32 bit address of PHY register to read 676 * @device_type: 5 bit device type 677 * @phy_data: Pointer to read data from PHY register 678 **/ 679 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 680 u32 device_type, u16 *phy_data) 681 { 682 s32 status; 683 u32 gssr = hw->phy.phy_semaphore_mask; 684 685 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 686 687 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 688 return IXGBE_ERR_SWFW_SYNC; 689 690 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 691 692 hw->mac.ops.release_swfw_sync(hw, gssr); 693 694 return status; 695 } 696 697 /** 698 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 699 * without SWFW lock 700 * @hw: pointer to hardware structure 701 * @reg_addr: 32 bit PHY register to write 702 * @device_type: 5 bit device type 703 * @phy_data: Data to write to the PHY register 704 **/ 705 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 706 u32 device_type, u16 phy_data) 707 { 708 u32 i, command; 709 710 /* Put the data in the MDI single read and write data register*/ 711 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 712 713 /* Setup and write the address cycle command */ 714 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 715 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 717 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 718 719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 720 721 /* 722 * Check every 10 usec to see if the address cycle completed. 723 * The MDI Command bit will clear when the operation is 724 * complete 725 */ 726 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 727 usec_delay(10); 728 729 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 730 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 731 break; 732 } 733 734 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 735 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 736 return IXGBE_ERR_PHY; 737 } 738 739 /* 740 * Address cycle complete, setup and write the write 741 * command 742 */ 743 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 744 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 745 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 746 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 747 748 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 749 750 /* 751 * Check every 10 usec to see if the address cycle 752 * completed. The MDI Command bit will clear when the 753 * operation is complete 754 */ 755 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 756 usec_delay(10); 757 758 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 759 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 760 break; 761 } 762 763 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 764 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 765 return IXGBE_ERR_PHY; 766 } 767 768 return IXGBE_SUCCESS; 769 } 770 771 /** 772 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 773 * using SWFW lock- this function is needed in most cases 774 * @hw: pointer to hardware structure 775 * @reg_addr: 32 bit PHY register to write 776 * @device_type: 5 bit device type 777 * @phy_data: Data to write to the PHY register 778 **/ 779 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 780 u32 device_type, u16 phy_data) 781 { 782 s32 status; 783 u32 gssr = hw->phy.phy_semaphore_mask; 784 785 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 786 787 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 788 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 789 phy_data); 790 hw->mac.ops.release_swfw_sync(hw, gssr); 791 } else { 792 status = IXGBE_ERR_SWFW_SYNC; 793 } 794 795 return status; 796 } 797 798 /** 799 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 800 * @hw: pointer to hardware structure 801 * 802 * Restart auto-negotiation and PHY and waits for completion. 803 **/ 804 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 805 { 806 s32 status = IXGBE_SUCCESS; 807 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 808 bool autoneg = false; 809 ixgbe_link_speed speed; 810 811 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 812 813 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 814 815 /* Set or unset auto-negotiation 10G advertisement */ 816 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 818 &autoneg_reg); 819 820 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 822 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 823 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 824 825 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 827 autoneg_reg); 828 829 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 831 &autoneg_reg); 832 833 if (hw->mac.type == ixgbe_mac_X550) { 834 /* Set or unset auto-negotiation 5G advertisement */ 835 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 837 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 838 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 839 840 /* Set or unset auto-negotiation 2.5G advertisement */ 841 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 842 if ((hw->phy.autoneg_advertised & 843 IXGBE_LINK_SPEED_2_5GB_FULL) && 844 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 845 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 846 } 847 848 /* Set or unset auto-negotiation 1G advertisement */ 849 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 851 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 852 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 853 854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 856 autoneg_reg); 857 858 /* Set or unset auto-negotiation 100M advertisement */ 859 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 860 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 861 &autoneg_reg); 862 863 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 864 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 865 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 866 (speed & IXGBE_LINK_SPEED_100_FULL)) 867 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 868 869 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 870 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 871 autoneg_reg); 872 873 ixgbe_restart_auto_neg(hw); 874 return status; 875 } 876 877 /** 878 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 879 * @hw: pointer to hardware structure 880 * @speed: new link speed 881 * @autoneg_wait_to_complete: unused 882 **/ 883 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 884 ixgbe_link_speed speed, 885 bool autoneg_wait_to_complete) 886 { 887 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 888 889 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 890 891 /* 892 * Clear autoneg_advertised and set new values based on input link 893 * speed. 894 */ 895 hw->phy.autoneg_advertised = 0; 896 897 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 899 900 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 902 903 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 905 906 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 908 909 if (speed & IXGBE_LINK_SPEED_100_FULL) 910 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 911 912 if (speed & IXGBE_LINK_SPEED_10_FULL) 913 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 914 915 /* Setup link based on the new speed settings */ 916 ixgbe_setup_phy_link(hw); 917 918 return IXGBE_SUCCESS; 919 } 920 921 /** 922 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 923 * @hw: pointer to hardware structure 924 * 925 * Determines the supported link capabilities by reading the PHY auto 926 * negotiation register. 927 **/ 928 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 929 { 930 s32 status; 931 u16 speed_ability; 932 933 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 934 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 935 &speed_ability); 936 if (status) 937 return status; 938 939 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 940 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 945 946 switch (hw->mac.type) { 947 case ixgbe_mac_X550: 948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 949 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 950 break; 951 case ixgbe_mac_X550EM_x: 952 case ixgbe_mac_X550EM_a: 953 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 954 break; 955 default: 956 break; 957 } 958 959 return status; 960 } 961 962 /** 963 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 964 * @hw: pointer to hardware structure 965 * @speed: pointer to link speed 966 * @autoneg: boolean auto-negotiation value 967 **/ 968 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 969 ixgbe_link_speed *speed, 970 bool *autoneg) 971 { 972 s32 status = IXGBE_SUCCESS; 973 974 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 975 976 *autoneg = true; 977 if (!hw->phy.speeds_supported) 978 status = ixgbe_get_copper_speeds_supported(hw); 979 980 *speed = hw->phy.speeds_supported; 981 return status; 982 } 983 984 /** 985 * ixgbe_check_phy_link_tnx - Determine link and speed status 986 * @hw: pointer to hardware structure 987 * @speed: current link speed 988 * @link_up: true is link is up, false otherwise 989 * 990 * Reads the VS1 register to determine if link is up and the current speed for 991 * the PHY. 992 **/ 993 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 994 bool *link_up) 995 { 996 s32 status = IXGBE_SUCCESS; 997 u32 time_out; 998 u32 max_time_out = 10; 999 u16 phy_link = 0; 1000 u16 phy_speed = 0; 1001 u16 phy_data = 0; 1002 1003 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1004 1005 /* Initialize speed and link to default case */ 1006 *link_up = false; 1007 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1008 1009 /* 1010 * Check current speed and link status of the PHY register. 1011 * This is a vendor specific register and may have to 1012 * be changed for other copper PHYs. 1013 */ 1014 for (time_out = 0; time_out < max_time_out; time_out++) { 1015 usec_delay(10); 1016 status = hw->phy.ops.read_reg(hw, 1017 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1018 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1019 &phy_data); 1020 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1021 phy_speed = phy_data & 1022 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1023 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1024 *link_up = true; 1025 if (phy_speed == 1026 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1027 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1028 break; 1029 } 1030 } 1031 1032 return status; 1033 } 1034 1035 /** 1036 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1037 * @hw: pointer to hardware structure 1038 * 1039 * Restart auto-negotiation and PHY and waits for completion. 1040 **/ 1041 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1042 { 1043 s32 status = IXGBE_SUCCESS; 1044 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1045 bool autoneg = false; 1046 ixgbe_link_speed speed; 1047 1048 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1049 1050 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1051 1052 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1053 /* Set or unset auto-negotiation 10G advertisement */ 1054 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1055 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1056 &autoneg_reg); 1057 1058 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1059 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1060 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1061 1062 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1063 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1064 autoneg_reg); 1065 } 1066 1067 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1068 /* Set or unset auto-negotiation 1G advertisement */ 1069 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1070 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1071 &autoneg_reg); 1072 1073 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1074 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1075 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1076 1077 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1078 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1079 autoneg_reg); 1080 } 1081 1082 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1083 /* Set or unset auto-negotiation 100M advertisement */ 1084 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1086 &autoneg_reg); 1087 1088 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1089 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1090 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1091 1092 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1093 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1094 autoneg_reg); 1095 } 1096 1097 ixgbe_restart_auto_neg(hw); 1098 return status; 1099 } 1100 1101 /** 1102 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1103 * @hw: pointer to hardware structure 1104 * @firmware_version: pointer to the PHY Firmware Version 1105 **/ 1106 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1107 u16 *firmware_version) 1108 { 1109 s32 status; 1110 1111 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1112 1113 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1114 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1115 firmware_version); 1116 1117 return status; 1118 } 1119 1120 /** 1121 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1122 * @hw: pointer to hardware structure 1123 * @firmware_version: pointer to the PHY Firmware Version 1124 **/ 1125 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1126 u16 *firmware_version) 1127 { 1128 s32 status; 1129 1130 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1131 1132 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1133 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1134 firmware_version); 1135 1136 return status; 1137 } 1138 1139 /** 1140 * ixgbe_reset_phy_nl - Performs a PHY reset 1141 * @hw: pointer to hardware structure 1142 **/ 1143 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1144 { 1145 u16 phy_offset, control, eword, edata, block_crc; 1146 bool end_data = false; 1147 u16 list_offset, data_offset; 1148 u16 phy_data = 0; 1149 s32 ret_val = IXGBE_SUCCESS; 1150 u32 i; 1151 1152 DEBUGFUNC("ixgbe_reset_phy_nl"); 1153 1154 /* Blocked by MNG FW so bail */ 1155 if (ixgbe_check_reset_blocked(hw)) 1156 goto out; 1157 1158 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1159 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1160 1161 /* reset the PHY and poll for completion */ 1162 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1163 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1164 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1165 1166 for (i = 0; i < 100; i++) { 1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1168 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1169 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1170 break; 1171 msec_delay(10); 1172 } 1173 1174 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1175 DEBUGOUT("PHY reset did not complete.\n"); 1176 ret_val = IXGBE_ERR_PHY; 1177 goto out; 1178 } 1179 1180 /* Get init offsets */ 1181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1182 &data_offset); 1183 if (ret_val != IXGBE_SUCCESS) 1184 goto out; 1185 1186 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1187 data_offset++; 1188 while (!end_data) { 1189 /* 1190 * Read control word from PHY init contents offset 1191 */ 1192 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1193 if (ret_val) 1194 goto err_eeprom; 1195 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1196 IXGBE_CONTROL_SHIFT_NL; 1197 edata = eword & IXGBE_DATA_MASK_NL; 1198 switch (control) { 1199 case IXGBE_DELAY_NL: 1200 data_offset++; 1201 DEBUGOUT1("DELAY: %d MS\n", edata); 1202 msec_delay(edata); 1203 break; 1204 case IXGBE_DATA_NL: 1205 DEBUGOUT("DATA:\n"); 1206 data_offset++; 1207 ret_val = hw->eeprom.ops.read(hw, data_offset, 1208 &phy_offset); 1209 if (ret_val) 1210 goto err_eeprom; 1211 data_offset++; 1212 for (i = 0; i < edata; i++) { 1213 ret_val = hw->eeprom.ops.read(hw, data_offset, 1214 &eword); 1215 if (ret_val) 1216 goto err_eeprom; 1217 hw->phy.ops.write_reg(hw, phy_offset, 1218 IXGBE_TWINAX_DEV, eword); 1219 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1220 phy_offset); 1221 data_offset++; 1222 phy_offset++; 1223 } 1224 break; 1225 case IXGBE_CONTROL_NL: 1226 data_offset++; 1227 DEBUGOUT("CONTROL:\n"); 1228 if (edata == IXGBE_CONTROL_EOL_NL) { 1229 DEBUGOUT("EOL\n"); 1230 end_data = true; 1231 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1232 DEBUGOUT("SOL\n"); 1233 } else { 1234 DEBUGOUT("Bad control value\n"); 1235 ret_val = IXGBE_ERR_PHY; 1236 goto out; 1237 } 1238 break; 1239 default: 1240 DEBUGOUT("Bad control type\n"); 1241 ret_val = IXGBE_ERR_PHY; 1242 goto out; 1243 } 1244 } 1245 1246 out: 1247 return ret_val; 1248 1249 err_eeprom: 1250 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1251 "eeprom read at offset %d failed", data_offset); 1252 return IXGBE_ERR_PHY; 1253 } 1254 1255 /** 1256 * ixgbe_identify_module_generic - Identifies module type 1257 * @hw: pointer to hardware structure 1258 * 1259 * Determines HW type and calls appropriate function. 1260 **/ 1261 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1262 { 1263 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1264 1265 DEBUGFUNC("ixgbe_identify_module_generic"); 1266 1267 switch (hw->mac.ops.get_media_type(hw)) { 1268 case ixgbe_media_type_fiber: 1269 status = ixgbe_identify_sfp_module_generic(hw); 1270 break; 1271 1272 case ixgbe_media_type_fiber_qsfp: 1273 status = ixgbe_identify_qsfp_module_generic(hw); 1274 break; 1275 1276 default: 1277 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1278 status = IXGBE_ERR_SFP_NOT_PRESENT; 1279 break; 1280 } 1281 1282 return status; 1283 } 1284 1285 /** 1286 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1287 * @hw: pointer to hardware structure 1288 * 1289 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1290 **/ 1291 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1292 { 1293 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1294 u32 vendor_oui = 0; 1295 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1296 u8 identifier = 0; 1297 u8 comp_codes_1g = 0; 1298 u8 comp_codes_10g = 0; 1299 u8 oui_bytes[3] = {0, 0, 0}; 1300 u8 cable_tech = 0; 1301 u8 cable_spec = 0; 1302 u16 enforce_sfp = 0; 1303 static bool warned_once = false; 1304 1305 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1306 1307 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1308 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1309 status = IXGBE_ERR_SFP_NOT_PRESENT; 1310 goto out; 1311 } 1312 1313 /* LAN ID is needed for I2C access */ 1314 hw->mac.ops.set_lan_id(hw); 1315 1316 status = hw->phy.ops.read_i2c_eeprom(hw, 1317 IXGBE_SFF_IDENTIFIER, 1318 &identifier); 1319 1320 if (status != IXGBE_SUCCESS) 1321 goto err_read_i2c_eeprom; 1322 1323 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1324 hw->phy.type = ixgbe_phy_sfp_unsupported; 1325 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1326 } else { 1327 status = hw->phy.ops.read_i2c_eeprom(hw, 1328 IXGBE_SFF_1GBE_COMP_CODES, 1329 &comp_codes_1g); 1330 1331 if (status != IXGBE_SUCCESS) 1332 goto err_read_i2c_eeprom; 1333 1334 status = hw->phy.ops.read_i2c_eeprom(hw, 1335 IXGBE_SFF_10GBE_COMP_CODES, 1336 &comp_codes_10g); 1337 1338 if (status != IXGBE_SUCCESS) 1339 goto err_read_i2c_eeprom; 1340 status = hw->phy.ops.read_i2c_eeprom(hw, 1341 IXGBE_SFF_CABLE_TECHNOLOGY, 1342 &cable_tech); 1343 1344 if (status != IXGBE_SUCCESS) 1345 goto err_read_i2c_eeprom; 1346 1347 /* ID Module 1348 * ========= 1349 * 0 SFP_DA_CU 1350 * 1 SFP_SR 1351 * 2 SFP_LR 1352 * 3 SFP_DA_CORE0 - 82599-specific 1353 * 4 SFP_DA_CORE1 - 82599-specific 1354 * 5 SFP_SR/LR_CORE0 - 82599-specific 1355 * 6 SFP_SR/LR_CORE1 - 82599-specific 1356 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1357 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1358 * 9 SFP_1g_cu_CORE0 - 82599-specific 1359 * 10 SFP_1g_cu_CORE1 - 82599-specific 1360 * 11 SFP_1g_sx_CORE0 - 82599-specific 1361 * 12 SFP_1g_sx_CORE1 - 82599-specific 1362 */ 1363 if (hw->mac.type == ixgbe_mac_82598EB) { 1364 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1365 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1366 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1367 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1368 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1369 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1370 else 1371 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1372 } else { 1373 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1374 if (hw->bus.lan_id == 0) 1375 hw->phy.sfp_type = 1376 ixgbe_sfp_type_da_cu_core0; 1377 else 1378 hw->phy.sfp_type = 1379 ixgbe_sfp_type_da_cu_core1; 1380 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1381 hw->phy.ops.read_i2c_eeprom( 1382 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1383 &cable_spec); 1384 if (cable_spec & 1385 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1386 if (hw->bus.lan_id == 0) 1387 hw->phy.sfp_type = 1388 ixgbe_sfp_type_da_act_lmt_core0; 1389 else 1390 hw->phy.sfp_type = 1391 ixgbe_sfp_type_da_act_lmt_core1; 1392 } else { 1393 hw->phy.sfp_type = 1394 ixgbe_sfp_type_unknown; 1395 } 1396 } else if (comp_codes_10g & 1397 (IXGBE_SFF_10GBASESR_CAPABLE | 1398 IXGBE_SFF_10GBASELR_CAPABLE)) { 1399 if (hw->bus.lan_id == 0) 1400 hw->phy.sfp_type = 1401 ixgbe_sfp_type_srlr_core0; 1402 else 1403 hw->phy.sfp_type = 1404 ixgbe_sfp_type_srlr_core1; 1405 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1406 if (hw->bus.lan_id == 0) 1407 hw->phy.sfp_type = 1408 ixgbe_sfp_type_1g_cu_core0; 1409 else 1410 hw->phy.sfp_type = 1411 ixgbe_sfp_type_1g_cu_core1; 1412 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1413 if (hw->bus.lan_id == 0) 1414 hw->phy.sfp_type = 1415 ixgbe_sfp_type_1g_sx_core0; 1416 else 1417 hw->phy.sfp_type = 1418 ixgbe_sfp_type_1g_sx_core1; 1419 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1420 if (hw->bus.lan_id == 0) 1421 hw->phy.sfp_type = 1422 ixgbe_sfp_type_1g_lx_core0; 1423 else 1424 hw->phy.sfp_type = 1425 ixgbe_sfp_type_1g_lx_core1; 1426 } else { 1427 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1428 } 1429 } 1430 1431 if (hw->phy.sfp_type != stored_sfp_type) 1432 hw->phy.sfp_setup_needed = true; 1433 1434 /* Determine if the SFP+ PHY is dual speed or not. */ 1435 hw->phy.multispeed_fiber = false; 1436 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1437 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1438 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1439 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)) || 1440 (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) || 1441 (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)) 1442 hw->phy.multispeed_fiber = true; 1443 1444 /* Determine PHY vendor */ 1445 if (hw->phy.type != ixgbe_phy_nl) { 1446 hw->phy.id = identifier; 1447 status = hw->phy.ops.read_i2c_eeprom(hw, 1448 IXGBE_SFF_VENDOR_OUI_BYTE0, 1449 &oui_bytes[0]); 1450 1451 if (status != IXGBE_SUCCESS) 1452 goto err_read_i2c_eeprom; 1453 1454 status = hw->phy.ops.read_i2c_eeprom(hw, 1455 IXGBE_SFF_VENDOR_OUI_BYTE1, 1456 &oui_bytes[1]); 1457 1458 if (status != IXGBE_SUCCESS) 1459 goto err_read_i2c_eeprom; 1460 1461 status = hw->phy.ops.read_i2c_eeprom(hw, 1462 IXGBE_SFF_VENDOR_OUI_BYTE2, 1463 &oui_bytes[2]); 1464 1465 if (status != IXGBE_SUCCESS) 1466 goto err_read_i2c_eeprom; 1467 1468 vendor_oui = 1469 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1470 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1471 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1472 1473 switch (vendor_oui) { 1474 case IXGBE_SFF_VENDOR_OUI_TYCO: 1475 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1476 hw->phy.type = 1477 ixgbe_phy_sfp_passive_tyco; 1478 break; 1479 case IXGBE_SFF_VENDOR_OUI_FTL: 1480 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1481 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1482 else 1483 hw->phy.type = ixgbe_phy_sfp_ftl; 1484 break; 1485 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1486 hw->phy.type = ixgbe_phy_sfp_avago; 1487 break; 1488 case IXGBE_SFF_VENDOR_OUI_INTEL: 1489 hw->phy.type = ixgbe_phy_sfp_intel; 1490 break; 1491 default: 1492 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1493 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1494 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1495 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1496 else 1497 hw->phy.type = ixgbe_phy_sfp_unknown; 1498 break; 1499 } 1500 } 1501 1502 /* Allow any DA cable vendor */ 1503 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1504 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1505 status = IXGBE_SUCCESS; 1506 goto out; 1507 } 1508 1509 /* Verify supported 1G SFP modules */ 1510 if (comp_codes_10g == 0 && 1511 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1517 hw->phy.type = ixgbe_phy_sfp_unsupported; 1518 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1519 goto out; 1520 } 1521 1522 /* Anything else 82598-based is supported */ 1523 if (hw->mac.type == ixgbe_mac_82598EB) { 1524 status = IXGBE_SUCCESS; 1525 goto out; 1526 } 1527 1528 ixgbe_get_device_caps(hw, &enforce_sfp); 1529 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1530 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1536 /* Make sure we're a supported PHY type */ 1537 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1538 status = IXGBE_SUCCESS; 1539 } else { 1540 if (hw->allow_unsupported_sfp == true) { 1541 if (!warned_once) 1542 EWARN(hw, 1543 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1544 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1545 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1546 warned_once = true; 1547 status = IXGBE_SUCCESS; 1548 } else { 1549 DEBUGOUT 1550 ("SFP+ module not supported\n"); 1551 hw->phy.type = 1552 ixgbe_phy_sfp_unsupported; 1553 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1554 } 1555 } 1556 } else { 1557 status = IXGBE_SUCCESS; 1558 } 1559 } 1560 1561 out: 1562 return status; 1563 1564 err_read_i2c_eeprom: 1565 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1566 if (hw->phy.type != ixgbe_phy_nl) { 1567 hw->phy.id = 0; 1568 hw->phy.type = ixgbe_phy_unknown; 1569 } 1570 return IXGBE_ERR_SFP_NOT_PRESENT; 1571 } 1572 1573 /** 1574 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1575 * @hw: pointer to hardware structure 1576 * 1577 * Determines physical layer capabilities of the current SFP. 1578 */ 1579 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1580 { 1581 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1582 u8 comp_codes_10g = 0; 1583 u8 comp_codes_1g = 0; 1584 1585 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1586 1587 hw->phy.ops.identify_sfp(hw); 1588 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1589 return physical_layer; 1590 1591 switch (hw->phy.type) { 1592 case ixgbe_phy_sfp_passive_tyco: 1593 case ixgbe_phy_sfp_passive_unknown: 1594 case ixgbe_phy_qsfp_passive_unknown: 1595 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1596 break; 1597 case ixgbe_phy_sfp_ftl_active: 1598 case ixgbe_phy_sfp_active_unknown: 1599 case ixgbe_phy_qsfp_active_unknown: 1600 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1601 break; 1602 case ixgbe_phy_sfp_avago: 1603 case ixgbe_phy_sfp_ftl: 1604 case ixgbe_phy_sfp_intel: 1605 case ixgbe_phy_sfp_unknown: 1606 hw->phy.ops.read_i2c_eeprom(hw, 1607 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1608 hw->phy.ops.read_i2c_eeprom(hw, 1609 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1610 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1611 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1612 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1613 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1614 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1615 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1616 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1617 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1618 break; 1619 case ixgbe_phy_qsfp_intel: 1620 case ixgbe_phy_qsfp_unknown: 1621 hw->phy.ops.read_i2c_eeprom(hw, 1622 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1623 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1624 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1625 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1626 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1627 break; 1628 default: 1629 break; 1630 } 1631 1632 return physical_layer; 1633 } 1634 1635 /** 1636 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1637 * @hw: pointer to hardware structure 1638 * 1639 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1640 **/ 1641 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1642 { 1643 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1644 u32 vendor_oui = 0; 1645 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1646 u8 identifier = 0; 1647 u8 comp_codes_1g = 0; 1648 u8 comp_codes_10g = 0; 1649 u8 oui_bytes[3] = {0, 0, 0}; 1650 u16 enforce_sfp = 0; 1651 u8 connector = 0; 1652 u8 cable_length = 0; 1653 u8 device_tech = 0; 1654 bool active_cable = false; 1655 static bool warned_once = false; 1656 1657 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1658 1659 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1660 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1661 status = IXGBE_ERR_SFP_NOT_PRESENT; 1662 goto out; 1663 } 1664 1665 /* LAN ID is needed for I2C access */ 1666 hw->mac.ops.set_lan_id(hw); 1667 1668 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1669 &identifier); 1670 1671 if (status != IXGBE_SUCCESS) 1672 goto err_read_i2c_eeprom; 1673 1674 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1675 hw->phy.type = ixgbe_phy_sfp_unsupported; 1676 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1677 goto out; 1678 } 1679 1680 hw->phy.id = identifier; 1681 1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1683 &comp_codes_10g); 1684 1685 if (status != IXGBE_SUCCESS) 1686 goto err_read_i2c_eeprom; 1687 1688 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1689 &comp_codes_1g); 1690 1691 if (status != IXGBE_SUCCESS) 1692 goto err_read_i2c_eeprom; 1693 1694 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1695 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1696 if (hw->bus.lan_id == 0) 1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1698 else 1699 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1700 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1701 IXGBE_SFF_10GBASELR_CAPABLE)) { 1702 if (hw->bus.lan_id == 0) 1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1704 else 1705 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1706 } else { 1707 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1708 active_cable = true; 1709 1710 if (!active_cable) { 1711 /* check for active DA cables that pre-date 1712 * SFF-8436 v3.6 */ 1713 hw->phy.ops.read_i2c_eeprom(hw, 1714 IXGBE_SFF_QSFP_CONNECTOR, 1715 &connector); 1716 1717 hw->phy.ops.read_i2c_eeprom(hw, 1718 IXGBE_SFF_QSFP_CABLE_LENGTH, 1719 &cable_length); 1720 1721 hw->phy.ops.read_i2c_eeprom(hw, 1722 IXGBE_SFF_QSFP_DEVICE_TECH, 1723 &device_tech); 1724 1725 if ((connector == 1726 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1727 (cable_length > 0) && 1728 ((device_tech >> 4) == 1729 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1730 active_cable = true; 1731 } 1732 1733 if (active_cable) { 1734 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1735 if (hw->bus.lan_id == 0) 1736 hw->phy.sfp_type = 1737 ixgbe_sfp_type_da_act_lmt_core0; 1738 else 1739 hw->phy.sfp_type = 1740 ixgbe_sfp_type_da_act_lmt_core1; 1741 } else { 1742 /* unsupported module type */ 1743 hw->phy.type = ixgbe_phy_sfp_unsupported; 1744 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1745 goto out; 1746 } 1747 } 1748 1749 if (hw->phy.sfp_type != stored_sfp_type) 1750 hw->phy.sfp_setup_needed = true; 1751 1752 /* Determine if the QSFP+ PHY is dual speed or not. */ 1753 hw->phy.multispeed_fiber = false; 1754 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1755 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1756 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1757 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1758 hw->phy.multispeed_fiber = true; 1759 1760 /* Determine PHY vendor for optical modules */ 1761 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1762 IXGBE_SFF_10GBASELR_CAPABLE)) { 1763 status = hw->phy.ops.read_i2c_eeprom(hw, 1764 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1765 &oui_bytes[0]); 1766 1767 if (status != IXGBE_SUCCESS) 1768 goto err_read_i2c_eeprom; 1769 1770 status = hw->phy.ops.read_i2c_eeprom(hw, 1771 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1772 &oui_bytes[1]); 1773 1774 if (status != IXGBE_SUCCESS) 1775 goto err_read_i2c_eeprom; 1776 1777 status = hw->phy.ops.read_i2c_eeprom(hw, 1778 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1779 &oui_bytes[2]); 1780 1781 if (status != IXGBE_SUCCESS) 1782 goto err_read_i2c_eeprom; 1783 1784 vendor_oui = 1785 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1786 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1787 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1788 1789 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1790 hw->phy.type = ixgbe_phy_qsfp_intel; 1791 else 1792 hw->phy.type = ixgbe_phy_qsfp_unknown; 1793 1794 ixgbe_get_device_caps(hw, &enforce_sfp); 1795 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1796 /* Make sure we're a supported PHY type */ 1797 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1798 status = IXGBE_SUCCESS; 1799 } else { 1800 if (hw->allow_unsupported_sfp == true) { 1801 if (!warned_once) 1802 EWARN(hw, 1803 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1804 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1805 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1806 warned_once = true; 1807 status = IXGBE_SUCCESS; 1808 } else { 1809 DEBUGOUT("QSFP module not supported\n"); 1810 hw->phy.type = 1811 ixgbe_phy_sfp_unsupported; 1812 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1813 } 1814 } 1815 } else { 1816 status = IXGBE_SUCCESS; 1817 } 1818 } 1819 1820 out: 1821 return status; 1822 1823 err_read_i2c_eeprom: 1824 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1825 hw->phy.id = 0; 1826 hw->phy.type = ixgbe_phy_unknown; 1827 1828 return IXGBE_ERR_SFP_NOT_PRESENT; 1829 } 1830 1831 /** 1832 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1833 * @hw: pointer to hardware structure 1834 * @list_offset: offset to the SFP ID list 1835 * @data_offset: offset to the SFP data block 1836 * 1837 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1838 * so it returns the offsets to the phy init sequence block. 1839 **/ 1840 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1841 u16 *list_offset, 1842 u16 *data_offset) 1843 { 1844 u16 sfp_id; 1845 u16 sfp_type = hw->phy.sfp_type; 1846 1847 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1848 1849 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1850 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1851 1852 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1853 return IXGBE_ERR_SFP_NOT_PRESENT; 1854 1855 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1856 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1857 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1858 1859 /* 1860 * Limiting active cables and 1G Phys must be initialized as 1861 * SR modules 1862 */ 1863 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1864 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1865 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1866 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1867 sfp_type = ixgbe_sfp_type_srlr_core0; 1868 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1869 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1870 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1871 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1872 sfp_type = ixgbe_sfp_type_srlr_core1; 1873 1874 /* Read offset to PHY init contents */ 1875 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1876 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1877 "eeprom read at offset %d failed", 1878 IXGBE_PHY_INIT_OFFSET_NL); 1879 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1880 } 1881 1882 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1883 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1884 1885 /* Shift offset to first ID word */ 1886 (*list_offset)++; 1887 1888 /* 1889 * Find the matching SFP ID in the EEPROM 1890 * and program the init sequence 1891 */ 1892 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1893 goto err_phy; 1894 1895 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1896 if (sfp_id == sfp_type) { 1897 (*list_offset)++; 1898 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1899 goto err_phy; 1900 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1901 DEBUGOUT("SFP+ module not supported\n"); 1902 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1903 } else { 1904 break; 1905 } 1906 } else { 1907 (*list_offset) += 2; 1908 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1909 goto err_phy; 1910 } 1911 } 1912 1913 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1914 DEBUGOUT("No matching SFP+ module found\n"); 1915 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1916 } 1917 1918 return IXGBE_SUCCESS; 1919 1920 err_phy: 1921 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1922 "eeprom read at offset %d failed", *list_offset); 1923 return IXGBE_ERR_PHY; 1924 } 1925 1926 /** 1927 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1928 * @hw: pointer to hardware structure 1929 * @byte_offset: EEPROM byte offset to read 1930 * @eeprom_data: value read 1931 * 1932 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1933 **/ 1934 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1935 u8 *eeprom_data) 1936 { 1937 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1938 1939 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1940 IXGBE_I2C_EEPROM_DEV_ADDR, 1941 eeprom_data); 1942 } 1943 1944 /** 1945 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1946 * @hw: pointer to hardware structure 1947 * @byte_offset: byte offset at address 0xA2 1948 * @sff8472_data: value read 1949 * 1950 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1951 **/ 1952 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1953 u8 *sff8472_data) 1954 { 1955 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1956 IXGBE_I2C_EEPROM_DEV_ADDR2, 1957 sff8472_data); 1958 } 1959 1960 /** 1961 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1962 * @hw: pointer to hardware structure 1963 * @byte_offset: EEPROM byte offset to write 1964 * @eeprom_data: value to write 1965 * 1966 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1967 **/ 1968 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1969 u8 eeprom_data) 1970 { 1971 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1972 1973 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1974 IXGBE_I2C_EEPROM_DEV_ADDR, 1975 eeprom_data); 1976 } 1977 1978 /** 1979 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 1980 * @hw: pointer to hardware structure 1981 * @offset: eeprom offset to be read 1982 * @addr: I2C address to be read 1983 */ 1984 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1985 { 1986 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1987 offset == IXGBE_SFF_IDENTIFIER && 1988 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1989 return true; 1990 return false; 1991 } 1992 1993 /** 1994 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1995 * @hw: pointer to hardware structure 1996 * @byte_offset: byte offset to read 1997 * @dev_addr: address to read from 1998 * @data: value read 1999 * @lock: true if to take and release semaphore 2000 * 2001 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2002 * a specified device address. 2003 **/ 2004 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2005 u8 dev_addr, u8 *data, bool lock) 2006 { 2007 s32 status; 2008 u32 max_retry = 10; 2009 u32 retry = 0; 2010 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2011 bool nack = 1; 2012 *data = 0; 2013 2014 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2015 2016 if (hw->mac.type >= ixgbe_mac_X550) 2017 max_retry = 3; 2018 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2019 max_retry = IXGBE_SFP_DETECT_RETRIES; 2020 2021 do { 2022 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2023 return IXGBE_ERR_SWFW_SYNC; 2024 2025 ixgbe_i2c_start(hw); 2026 2027 /* Device Address and write indication */ 2028 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2029 if (status != IXGBE_SUCCESS) 2030 goto fail; 2031 2032 status = ixgbe_get_i2c_ack(hw); 2033 if (status != IXGBE_SUCCESS) 2034 goto fail; 2035 2036 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2037 if (status != IXGBE_SUCCESS) 2038 goto fail; 2039 2040 status = ixgbe_get_i2c_ack(hw); 2041 if (status != IXGBE_SUCCESS) 2042 goto fail; 2043 2044 ixgbe_i2c_start(hw); 2045 2046 /* Device Address and read indication */ 2047 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2048 if (status != IXGBE_SUCCESS) 2049 goto fail; 2050 2051 status = ixgbe_get_i2c_ack(hw); 2052 if (status != IXGBE_SUCCESS) 2053 goto fail; 2054 2055 ixgbe_clock_in_i2c_byte(hw, data); 2056 2057 status = ixgbe_clock_out_i2c_bit(hw, nack); 2058 if (status != IXGBE_SUCCESS) 2059 goto fail; 2060 2061 ixgbe_i2c_stop(hw); 2062 if (lock) 2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2064 return IXGBE_SUCCESS; 2065 2066 fail: 2067 ixgbe_i2c_bus_clear(hw); 2068 if (lock) { 2069 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2070 msec_delay(100); 2071 } 2072 if (retry < max_retry) 2073 DEBUGOUT("I2C byte read error - Retrying.\n"); 2074 else 2075 DEBUGOUT("I2C byte read error.\n"); 2076 retry++; 2077 } while (retry <= max_retry); 2078 2079 return status; 2080 } 2081 2082 /** 2083 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2084 * @hw: pointer to hardware structure 2085 * @byte_offset: byte offset to read 2086 * @dev_addr: address to read from 2087 * @data: value read 2088 * 2089 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2090 * a specified device address. 2091 **/ 2092 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2093 u8 dev_addr, u8 *data) 2094 { 2095 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2096 data, true); 2097 } 2098 2099 /** 2100 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2101 * @hw: pointer to hardware structure 2102 * @byte_offset: byte offset to read 2103 * @dev_addr: address to read from 2104 * @data: value read 2105 * 2106 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2107 * a specified device address. 2108 **/ 2109 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2110 u8 dev_addr, u8 *data) 2111 { 2112 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2113 data, false); 2114 } 2115 2116 /** 2117 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2118 * @hw: pointer to hardware structure 2119 * @byte_offset: byte offset to write 2120 * @dev_addr: address to write to 2121 * @data: value to write 2122 * @lock: true if to take and release semaphore 2123 * 2124 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2125 * a specified device address. 2126 **/ 2127 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2128 u8 dev_addr, u8 data, bool lock) 2129 { 2130 s32 status; 2131 u32 max_retry = 1; 2132 u32 retry = 0; 2133 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2134 2135 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2136 2137 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2138 IXGBE_SUCCESS) 2139 return IXGBE_ERR_SWFW_SYNC; 2140 2141 do { 2142 ixgbe_i2c_start(hw); 2143 2144 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2145 if (status != IXGBE_SUCCESS) 2146 goto fail; 2147 2148 status = ixgbe_get_i2c_ack(hw); 2149 if (status != IXGBE_SUCCESS) 2150 goto fail; 2151 2152 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2153 if (status != IXGBE_SUCCESS) 2154 goto fail; 2155 2156 status = ixgbe_get_i2c_ack(hw); 2157 if (status != IXGBE_SUCCESS) 2158 goto fail; 2159 2160 status = ixgbe_clock_out_i2c_byte(hw, data); 2161 if (status != IXGBE_SUCCESS) 2162 goto fail; 2163 2164 status = ixgbe_get_i2c_ack(hw); 2165 if (status != IXGBE_SUCCESS) 2166 goto fail; 2167 2168 ixgbe_i2c_stop(hw); 2169 if (lock) 2170 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2171 return IXGBE_SUCCESS; 2172 2173 fail: 2174 ixgbe_i2c_bus_clear(hw); 2175 if (retry < max_retry) 2176 DEBUGOUT("I2C byte write error - Retrying.\n"); 2177 else 2178 DEBUGOUT("I2C byte write error.\n"); 2179 retry++; 2180 } while (retry <= max_retry); 2181 2182 if (lock) 2183 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2184 2185 return status; 2186 } 2187 2188 /** 2189 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2190 * @hw: pointer to hardware structure 2191 * @byte_offset: byte offset to write 2192 * @dev_addr: address to write to 2193 * @data: value to write 2194 * 2195 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2196 * a specified device address. 2197 **/ 2198 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2199 u8 dev_addr, u8 data) 2200 { 2201 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2202 data, true); 2203 } 2204 2205 /** 2206 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2207 * @hw: pointer to hardware structure 2208 * @byte_offset: byte offset to write 2209 * @dev_addr: address to write to 2210 * @data: value to write 2211 * 2212 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2213 * a specified device address. 2214 **/ 2215 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2216 u8 dev_addr, u8 data) 2217 { 2218 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2219 data, false); 2220 } 2221 2222 /** 2223 * ixgbe_i2c_start - Sets I2C start condition 2224 * @hw: pointer to hardware structure 2225 * 2226 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2227 * Set bit-bang mode on X550 hardware. 2228 **/ 2229 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2230 { 2231 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2232 2233 DEBUGFUNC("ixgbe_i2c_start"); 2234 2235 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2236 2237 /* Start condition must begin with data and clock high */ 2238 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2239 ixgbe_raise_i2c_clk(hw, &i2cctl); 2240 2241 /* Setup time for start condition (4.7us) */ 2242 usec_delay(IXGBE_I2C_T_SU_STA); 2243 2244 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2245 2246 /* Hold time for start condition (4us) */ 2247 usec_delay(IXGBE_I2C_T_HD_STA); 2248 2249 ixgbe_lower_i2c_clk(hw, &i2cctl); 2250 2251 /* Minimum low period of clock is 4.7 us */ 2252 usec_delay(IXGBE_I2C_T_LOW); 2253 2254 } 2255 2256 /** 2257 * ixgbe_i2c_stop - Sets I2C stop condition 2258 * @hw: pointer to hardware structure 2259 * 2260 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2261 * Disables bit-bang mode and negates data output enable on X550 2262 * hardware. 2263 **/ 2264 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2265 { 2266 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2267 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2268 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2269 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2270 2271 DEBUGFUNC("ixgbe_i2c_stop"); 2272 2273 /* Stop condition must begin with data low and clock high */ 2274 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2275 ixgbe_raise_i2c_clk(hw, &i2cctl); 2276 2277 /* Setup time for stop condition (4us) */ 2278 usec_delay(IXGBE_I2C_T_SU_STO); 2279 2280 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2281 2282 /* bus free time between stop and start (4.7us)*/ 2283 usec_delay(IXGBE_I2C_T_BUF); 2284 2285 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2286 i2cctl &= ~bb_en_bit; 2287 i2cctl |= data_oe_bit | clk_oe_bit; 2288 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2289 IXGBE_WRITE_FLUSH(hw); 2290 } 2291 } 2292 2293 /** 2294 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2295 * @hw: pointer to hardware structure 2296 * @data: data byte to clock in 2297 * 2298 * Clocks in one byte data via I2C data/clock 2299 **/ 2300 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2301 { 2302 s32 i; 2303 bool bit = 0; 2304 2305 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2306 2307 *data = 0; 2308 for (i = 7; i >= 0; i--) { 2309 ixgbe_clock_in_i2c_bit(hw, &bit); 2310 *data |= bit << i; 2311 } 2312 } 2313 2314 /** 2315 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2316 * @hw: pointer to hardware structure 2317 * @data: data byte clocked out 2318 * 2319 * Clocks out one byte data via I2C data/clock 2320 **/ 2321 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2322 { 2323 s32 status = IXGBE_SUCCESS; 2324 s32 i; 2325 u32 i2cctl; 2326 bool bit; 2327 2328 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2329 2330 for (i = 7; i >= 0; i--) { 2331 bit = (data >> i) & 0x1; 2332 status = ixgbe_clock_out_i2c_bit(hw, bit); 2333 2334 if (status != IXGBE_SUCCESS) 2335 break; 2336 } 2337 2338 /* Release SDA line (set high) */ 2339 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2340 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2341 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2342 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2343 IXGBE_WRITE_FLUSH(hw); 2344 2345 return status; 2346 } 2347 2348 /** 2349 * ixgbe_get_i2c_ack - Polls for I2C ACK 2350 * @hw: pointer to hardware structure 2351 * 2352 * Clocks in/out one bit via I2C data/clock 2353 **/ 2354 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2355 { 2356 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2357 s32 status = IXGBE_SUCCESS; 2358 u32 i = 0; 2359 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2360 u32 timeout = 10; 2361 bool ack = 1; 2362 2363 DEBUGFUNC("ixgbe_get_i2c_ack"); 2364 2365 if (data_oe_bit) { 2366 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2367 i2cctl |= data_oe_bit; 2368 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2369 IXGBE_WRITE_FLUSH(hw); 2370 } 2371 ixgbe_raise_i2c_clk(hw, &i2cctl); 2372 2373 /* Minimum high period of clock is 4us */ 2374 usec_delay(IXGBE_I2C_T_HIGH); 2375 2376 /* Poll for ACK. Note that ACK in I2C spec is 2377 * transition from 1 to 0 */ 2378 for (i = 0; i < timeout; i++) { 2379 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2380 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2381 2382 usec_delay(1); 2383 if (!ack) 2384 break; 2385 } 2386 2387 if (ack) { 2388 DEBUGOUT("I2C ack was not received.\n"); 2389 status = IXGBE_ERR_I2C; 2390 } 2391 2392 ixgbe_lower_i2c_clk(hw, &i2cctl); 2393 2394 /* Minimum low period of clock is 4.7 us */ 2395 usec_delay(IXGBE_I2C_T_LOW); 2396 2397 return status; 2398 } 2399 2400 /** 2401 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2402 * @hw: pointer to hardware structure 2403 * @data: read data value 2404 * 2405 * Clocks in one bit via I2C data/clock 2406 **/ 2407 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2408 { 2409 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2410 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2411 2412 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2413 2414 if (data_oe_bit) { 2415 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2416 i2cctl |= data_oe_bit; 2417 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2418 IXGBE_WRITE_FLUSH(hw); 2419 } 2420 ixgbe_raise_i2c_clk(hw, &i2cctl); 2421 2422 /* Minimum high period of clock is 4us */ 2423 usec_delay(IXGBE_I2C_T_HIGH); 2424 2425 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2426 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2427 2428 ixgbe_lower_i2c_clk(hw, &i2cctl); 2429 2430 /* Minimum low period of clock is 4.7 us */ 2431 usec_delay(IXGBE_I2C_T_LOW); 2432 } 2433 2434 /** 2435 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2436 * @hw: pointer to hardware structure 2437 * @data: data value to write 2438 * 2439 * Clocks out one bit via I2C data/clock 2440 **/ 2441 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2442 { 2443 s32 status; 2444 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2445 2446 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2447 2448 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2449 if (status == IXGBE_SUCCESS) { 2450 ixgbe_raise_i2c_clk(hw, &i2cctl); 2451 2452 /* Minimum high period of clock is 4us */ 2453 usec_delay(IXGBE_I2C_T_HIGH); 2454 2455 ixgbe_lower_i2c_clk(hw, &i2cctl); 2456 2457 /* Minimum low period of clock is 4.7 us. 2458 * This also takes care of the data hold time. 2459 */ 2460 usec_delay(IXGBE_I2C_T_LOW); 2461 } else { 2462 status = IXGBE_ERR_I2C; 2463 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2464 "I2C data was not set to %X\n", data); 2465 } 2466 2467 return status; 2468 } 2469 2470 /** 2471 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2472 * @hw: pointer to hardware structure 2473 * @i2cctl: Current value of I2CCTL register 2474 * 2475 * Raises the I2C clock line '0'->'1' 2476 * Negates the I2C clock output enable on X550 hardware. 2477 **/ 2478 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2479 { 2480 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2481 u32 i = 0; 2482 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2483 u32 i2cctl_r = 0; 2484 2485 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2486 2487 if (clk_oe_bit) { 2488 *i2cctl |= clk_oe_bit; 2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2490 } 2491 2492 for (i = 0; i < timeout; i++) { 2493 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2494 2495 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2496 IXGBE_WRITE_FLUSH(hw); 2497 /* SCL rise time (1000ns) */ 2498 usec_delay(IXGBE_I2C_T_RISE); 2499 2500 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2501 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2502 break; 2503 } 2504 } 2505 2506 /** 2507 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2508 * @hw: pointer to hardware structure 2509 * @i2cctl: Current value of I2CCTL register 2510 * 2511 * Lowers the I2C clock line '1'->'0' 2512 * Asserts the I2C clock output enable on X550 hardware. 2513 **/ 2514 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2515 { 2516 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2517 2518 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2519 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2520 2521 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2522 IXGBE_WRITE_FLUSH(hw); 2523 2524 /* SCL fall time (300ns) */ 2525 usec_delay(IXGBE_I2C_T_FALL); 2526 } 2527 2528 /** 2529 * ixgbe_set_i2c_data - Sets the I2C data bit 2530 * @hw: pointer to hardware structure 2531 * @i2cctl: Current value of I2CCTL register 2532 * @data: I2C data value (0 or 1) to set 2533 * 2534 * Sets the I2C data bit 2535 * Asserts the I2C data output enable on X550 hardware. 2536 **/ 2537 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2538 { 2539 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2540 s32 status = IXGBE_SUCCESS; 2541 2542 DEBUGFUNC("ixgbe_set_i2c_data"); 2543 2544 if (data) 2545 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2546 else 2547 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2548 *i2cctl &= ~data_oe_bit; 2549 2550 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2551 IXGBE_WRITE_FLUSH(hw); 2552 2553 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2554 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2555 2556 if (!data) /* Can't verify data in this case */ 2557 return IXGBE_SUCCESS; 2558 if (data_oe_bit) { 2559 *i2cctl |= data_oe_bit; 2560 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2561 IXGBE_WRITE_FLUSH(hw); 2562 } 2563 2564 /* Verify data was set correctly */ 2565 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2566 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2567 status = IXGBE_ERR_I2C; 2568 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2569 "Error - I2C data was not set to %X.\n", 2570 data); 2571 } 2572 2573 return status; 2574 } 2575 2576 /** 2577 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2578 * @hw: pointer to hardware structure 2579 * @i2cctl: Current value of I2CCTL register 2580 * 2581 * Returns the I2C data bit value 2582 * Negates the I2C data output enable on X550 hardware. 2583 **/ 2584 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2585 { 2586 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2587 bool data; 2588 2589 DEBUGFUNC("ixgbe_get_i2c_data"); 2590 2591 if (data_oe_bit) { 2592 *i2cctl |= data_oe_bit; 2593 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2594 IXGBE_WRITE_FLUSH(hw); 2595 usec_delay(IXGBE_I2C_T_FALL); 2596 } 2597 2598 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2599 data = 1; 2600 else 2601 data = 0; 2602 2603 return data; 2604 } 2605 2606 /** 2607 * ixgbe_i2c_bus_clear - Clears the I2C bus 2608 * @hw: pointer to hardware structure 2609 * 2610 * Clears the I2C bus by sending nine clock pulses. 2611 * Used when data line is stuck low. 2612 **/ 2613 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2614 { 2615 u32 i2cctl; 2616 u32 i; 2617 2618 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2619 2620 ixgbe_i2c_start(hw); 2621 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2622 2623 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2624 2625 for (i = 0; i < 9; i++) { 2626 ixgbe_raise_i2c_clk(hw, &i2cctl); 2627 2628 /* Min high period of clock is 4us */ 2629 usec_delay(IXGBE_I2C_T_HIGH); 2630 2631 ixgbe_lower_i2c_clk(hw, &i2cctl); 2632 2633 /* Min low period of clock is 4.7us*/ 2634 usec_delay(IXGBE_I2C_T_LOW); 2635 } 2636 2637 ixgbe_i2c_start(hw); 2638 2639 /* Put the i2c bus back to default state */ 2640 ixgbe_i2c_stop(hw); 2641 } 2642 2643 /** 2644 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2645 * @hw: pointer to hardware structure 2646 * 2647 * Checks if the LASI temp alarm status was triggered due to overtemp 2648 **/ 2649 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2650 { 2651 s32 status = IXGBE_SUCCESS; 2652 u16 phy_data = 0; 2653 2654 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2655 2656 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2657 goto out; 2658 2659 /* Check that the LASI temp alarm status was triggered */ 2660 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2661 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2662 2663 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2664 goto out; 2665 2666 status = IXGBE_ERR_OVERTEMP; 2667 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2668 out: 2669 return status; 2670 } 2671 2672 /** 2673 * ixgbe_set_copper_phy_power - Control power for copper phy 2674 * @hw: pointer to hardware structure 2675 * @on: true for on, false for off 2676 */ 2677 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2678 { 2679 u32 status; 2680 u16 reg; 2681 2682 if (!on && ixgbe_mng_present(hw)) 2683 return 0; 2684 2685 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2686 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2687 ®); 2688 if (status) 2689 return status; 2690 2691 if (on) { 2692 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2693 } else { 2694 if (ixgbe_check_reset_blocked(hw)) 2695 return 0; 2696 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2697 } 2698 2699 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2700 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2701 reg); 2702 return status; 2703 } 2704