1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(u32 *i2cctl); 50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 54 * @hw: pointer to the hardware structure 55 * 56 * Initialize the function pointers. 57 **/ 58 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 63 64 /* PHY */ 65 phy->ops.identify = &ixgbe_identify_phy_generic; 66 phy->ops.reset = &ixgbe_reset_phy_generic; 67 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 68 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 69 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 70 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 71 phy->ops.check_link = NULL; 72 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 73 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 74 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 75 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 76 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 77 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 78 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 79 phy->sfp_type = ixgbe_sfp_type_unknown; 80 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 81 phy->ops.set_low_power_state = &ixgbe_tn_set_low_power_state; 82 return IXGBE_SUCCESS; 83 } 84 85 /** 86 * ixgbe_identify_phy_generic - Get physical layer module 87 * @hw: pointer to hardware structure 88 * 89 * Determines the physical layer module found on the current adapter. 90 **/ 91 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 92 { 93 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 94 u32 phy_addr; 95 u16 ext_ability = 0; 96 97 DEBUGFUNC("ixgbe_identify_phy_generic"); 98 99 if (hw->phy.type == ixgbe_phy_unknown) { 100 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 101 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 102 hw->phy.addr = phy_addr; 103 ixgbe_get_phy_id(hw); 104 hw->phy.type = 105 ixgbe_get_phy_type_from_id(hw->phy.id); 106 107 if (hw->phy.type == ixgbe_phy_unknown) { 108 hw->phy.ops.read_reg(hw, 109 IXGBE_MDIO_PHY_EXT_ABILITY, 110 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 111 &ext_ability); 112 if (ext_ability & 113 IXGBE_MDIO_PHY_10GBASET_ABILITY || 114 ext_ability & 115 IXGBE_MDIO_PHY_1000BASET_ABILITY) 116 hw->phy.type = 117 ixgbe_phy_cu_unknown; 118 else 119 hw->phy.type = 120 ixgbe_phy_generic; 121 } 122 123 status = IXGBE_SUCCESS; 124 break; 125 } 126 } 127 if (status != IXGBE_SUCCESS) 128 hw->phy.addr = 0; 129 } else { 130 status = IXGBE_SUCCESS; 131 } 132 133 return status; 134 } 135 136 /** 137 * ixgbe_validate_phy_addr - Determines phy address is valid 138 * @hw: pointer to hardware structure 139 * 140 **/ 141 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 142 { 143 u16 phy_id = 0; 144 bool valid = FALSE; 145 146 DEBUGFUNC("ixgbe_validate_phy_addr"); 147 148 hw->phy.addr = phy_addr; 149 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 150 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 151 152 if (phy_id != 0xFFFF && phy_id != 0x0) 153 valid = TRUE; 154 155 return valid; 156 } 157 158 /** 159 * ixgbe_get_phy_id - Get the phy type 160 * @hw: pointer to hardware structure 161 * 162 **/ 163 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 164 { 165 u32 status; 166 u16 phy_id_high = 0; 167 u16 phy_id_low = 0; 168 169 DEBUGFUNC("ixgbe_get_phy_id"); 170 171 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 172 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 173 &phy_id_high); 174 175 if (status == IXGBE_SUCCESS) { 176 hw->phy.id = (u32)(phy_id_high << 16); 177 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 178 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 179 &phy_id_low); 180 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 181 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 182 } 183 return status; 184 } 185 186 /** 187 * ixgbe_get_phy_type_from_id - Get the phy type 188 * @hw: pointer to hardware structure 189 * 190 **/ 191 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 192 { 193 enum ixgbe_phy_type phy_type; 194 195 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 196 197 switch (phy_id) { 198 case TN1010_PHY_ID: 199 phy_type = ixgbe_phy_tn; 200 break; 201 case AQ1002_PHY_ID: 202 phy_type = ixgbe_phy_aq; 203 break; 204 case QT2022_PHY_ID: 205 phy_type = ixgbe_phy_qt; 206 break; 207 case ATH_PHY_ID: 208 phy_type = ixgbe_phy_nl; 209 break; 210 default: 211 phy_type = ixgbe_phy_unknown; 212 break; 213 } 214 215 DEBUGOUT1("phy type found is %d\n", phy_type); 216 return phy_type; 217 } 218 219 /** 220 * ixgbe_reset_phy_generic - Performs a PHY reset 221 * @hw: pointer to hardware structure 222 **/ 223 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 224 { 225 u32 i; 226 u16 ctrl = 0; 227 s32 status = IXGBE_SUCCESS; 228 229 DEBUGFUNC("ixgbe_reset_phy_generic"); 230 231 if (hw->phy.type == ixgbe_phy_unknown) 232 status = ixgbe_identify_phy_generic(hw); 233 234 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 235 goto out; 236 237 /* 238 * Perform soft PHY reset to the PHY_XS. 239 * This will cause a soft reset to the PHY 240 */ 241 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 242 IXGBE_MDIO_PHY_XS_DEV_TYPE, 243 IXGBE_MDIO_PHY_XS_RESET); 244 245 /* 246 * Poll for reset bit to self-clear indicating reset is complete. 247 * Some PHYs could take up to 3 seconds to complete and need about 248 * 1.7 usec delay after the reset is complete. 249 */ 250 for (i = 0; i < 30; i++) { 251 msec_delay(100); 252 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 253 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 254 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 255 usec_delay(2); 256 break; 257 } 258 } 259 260 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 261 status = IXGBE_ERR_RESET_FAILED; 262 DEBUGOUT("PHY reset polling failed to complete.\n"); 263 } 264 265 out: 266 return status; 267 } 268 269 /** 270 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 271 * @hw: pointer to hardware structure 272 * @reg_addr: 32 bit address of PHY register to read 273 * @phy_data: Pointer to read data from PHY register 274 **/ 275 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 276 u32 device_type, u16 *phy_data) 277 { 278 u32 command; 279 u32 i; 280 u32 data; 281 s32 status = IXGBE_SUCCESS; 282 u16 gssr; 283 284 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 285 286 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 287 gssr = IXGBE_GSSR_PHY1_SM; 288 else 289 gssr = IXGBE_GSSR_PHY0_SM; 290 291 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 292 status = IXGBE_ERR_SWFW_SYNC; 293 294 if (status == IXGBE_SUCCESS) { 295 /* Setup and write the address cycle command */ 296 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 297 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 298 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 299 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 300 301 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 302 303 /* 304 * Check every 10 usec to see if the address cycle completed. 305 * The MDI Command bit will clear when the operation is 306 * complete 307 */ 308 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 309 usec_delay(10); 310 311 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 312 313 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 314 break; 315 } 316 317 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 318 DEBUGOUT("PHY address command did not complete.\n"); 319 status = IXGBE_ERR_PHY; 320 } 321 322 if (status == IXGBE_SUCCESS) { 323 /* 324 * Address cycle complete, setup and write the read 325 * command 326 */ 327 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 328 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 329 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 330 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 331 332 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 333 334 /* 335 * Check every 10 usec to see if the address cycle 336 * completed. The MDI Command bit will clear when the 337 * operation is complete 338 */ 339 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 340 usec_delay(10); 341 342 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 343 344 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 345 break; 346 } 347 348 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 349 DEBUGOUT("PHY read command didn't complete\n"); 350 status = IXGBE_ERR_PHY; 351 } else { 352 /* 353 * Read operation is complete. Get the data 354 * from MSRWD 355 */ 356 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 357 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 358 *phy_data = (u16)(data); 359 } 360 } 361 362 ixgbe_release_swfw_sync(hw, gssr); 363 } 364 365 return status; 366 } 367 368 /** 369 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 370 * @hw: pointer to hardware structure 371 * @reg_addr: 32 bit PHY register to write 372 * @device_type: 5 bit device type 373 * @phy_data: Data to write to the PHY register 374 **/ 375 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 376 u32 device_type, u16 phy_data) 377 { 378 u32 command; 379 u32 i; 380 s32 status = IXGBE_SUCCESS; 381 u16 gssr; 382 383 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 384 385 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 386 gssr = IXGBE_GSSR_PHY1_SM; 387 else 388 gssr = IXGBE_GSSR_PHY0_SM; 389 390 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 391 status = IXGBE_ERR_SWFW_SYNC; 392 393 if (status == IXGBE_SUCCESS) { 394 /* Put the data in the MDI single read and write data register*/ 395 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 396 397 /* Setup and write the address cycle command */ 398 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 399 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 400 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 401 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 402 403 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 404 405 /* 406 * Check every 10 usec to see if the address cycle completed. 407 * The MDI Command bit will clear when the operation is 408 * complete 409 */ 410 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 411 usec_delay(10); 412 413 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 414 415 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 416 break; 417 } 418 419 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 420 DEBUGOUT("PHY address cmd didn't complete\n"); 421 status = IXGBE_ERR_PHY; 422 } 423 424 if (status == IXGBE_SUCCESS) { 425 /* 426 * Address cycle complete, setup and write the write 427 * command 428 */ 429 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 430 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 431 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 432 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 433 434 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 435 436 /* 437 * Check every 10 usec to see if the address cycle 438 * completed. The MDI Command bit will clear when the 439 * operation is complete 440 */ 441 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 442 usec_delay(10); 443 444 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 445 446 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 447 break; 448 } 449 450 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 451 DEBUGOUT("PHY address cmd didn't complete\n"); 452 status = IXGBE_ERR_PHY; 453 } 454 } 455 456 ixgbe_release_swfw_sync(hw, gssr); 457 } 458 459 return status; 460 } 461 462 /** 463 * ixgbe_setup_phy_link_generic - Set and restart autoneg 464 * @hw: pointer to hardware structure 465 * 466 * Restart autonegotiation and PHY and waits for completion. 467 **/ 468 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 469 { 470 s32 status = IXGBE_SUCCESS; 471 u32 time_out; 472 u32 max_time_out = 10; 473 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 474 bool autoneg = FALSE; 475 ixgbe_link_speed speed; 476 477 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 478 479 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 480 481 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 482 /* Set or unset auto-negotiation 10G advertisement */ 483 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 484 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 485 &autoneg_reg); 486 487 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 488 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 489 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 490 491 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 492 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 493 autoneg_reg); 494 } 495 496 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 497 /* Set or unset auto-negotiation 1G advertisement */ 498 hw->phy.ops.read_reg(hw, 499 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 500 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 501 &autoneg_reg); 502 503 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 504 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 505 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 506 507 hw->phy.ops.write_reg(hw, 508 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 509 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 510 autoneg_reg); 511 } 512 513 if (speed & IXGBE_LINK_SPEED_100_FULL) { 514 /* Set or unset auto-negotiation 100M advertisement */ 515 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 516 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 517 &autoneg_reg); 518 519 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 520 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 521 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 522 523 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 524 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 525 autoneg_reg); 526 } 527 528 /* Restart PHY autonegotiation and wait for completion */ 529 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 530 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 531 532 autoneg_reg |= IXGBE_MII_RESTART; 533 534 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 536 537 /* Wait for autonegotiation to finish */ 538 for (time_out = 0; time_out < max_time_out; time_out++) { 539 usec_delay(10); 540 /* Restart PHY autonegotiation and wait for completion */ 541 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 542 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 543 &autoneg_reg); 544 545 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 546 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 547 break; 548 } 549 } 550 551 if (time_out == max_time_out) { 552 status = IXGBE_ERR_LINK_SETUP; 553 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 554 } 555 556 return status; 557 } 558 559 /** 560 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 561 * @hw: pointer to hardware structure 562 * @speed: new link speed 563 * @autoneg: TRUE if autonegotiation enabled 564 **/ 565 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 566 ixgbe_link_speed speed, 567 bool autoneg, 568 bool autoneg_wait_to_complete) 569 { 570 UNREFERENCED_PARAMETER(autoneg); 571 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 572 573 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 574 575 /* 576 * Clear autoneg_advertised and set new values based on input link 577 * speed. 578 */ 579 hw->phy.autoneg_advertised = 0; 580 581 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 582 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 583 584 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 585 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 586 587 if (speed & IXGBE_LINK_SPEED_100_FULL) 588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 589 590 /* Setup link based on the new speed settings */ 591 hw->phy.ops.setup_link(hw); 592 593 return IXGBE_SUCCESS; 594 } 595 596 /** 597 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 598 * @hw: pointer to hardware structure 599 * @speed: pointer to link speed 600 * @autoneg: boolean auto-negotiation value 601 * 602 * Determines the link capabilities by reading the AUTOC register. 603 **/ 604 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 605 ixgbe_link_speed *speed, 606 bool *autoneg) 607 { 608 s32 status = IXGBE_ERR_LINK_SETUP; 609 u16 speed_ability; 610 611 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 612 613 *speed = 0; 614 *autoneg = TRUE; 615 616 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 617 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 618 &speed_ability); 619 620 if (status == IXGBE_SUCCESS) { 621 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 622 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 623 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 624 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 625 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 626 *speed |= IXGBE_LINK_SPEED_100_FULL; 627 } 628 629 return status; 630 } 631 632 /** 633 * ixgbe_check_phy_link_tnx - Determine link and speed status 634 * @hw: pointer to hardware structure 635 * 636 * Reads the VS1 register to determine if link is up and the current speed for 637 * the PHY. 638 **/ 639 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 640 bool *link_up) 641 { 642 s32 status = IXGBE_SUCCESS; 643 u32 time_out; 644 u32 max_time_out = 10; 645 u16 phy_link = 0; 646 u16 phy_speed = 0; 647 u16 phy_data = 0; 648 649 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 650 651 /* Initialize speed and link to default case */ 652 *link_up = FALSE; 653 *speed = IXGBE_LINK_SPEED_10GB_FULL; 654 655 /* 656 * Check current speed and link status of the PHY register. 657 * This is a vendor specific register and may have to 658 * be changed for other copper PHYs. 659 */ 660 for (time_out = 0; time_out < max_time_out; time_out++) { 661 usec_delay(10); 662 status = hw->phy.ops.read_reg(hw, 663 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 664 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 665 &phy_data); 666 phy_link = phy_data & 667 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 668 phy_speed = phy_data & 669 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 670 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 671 *link_up = TRUE; 672 if (phy_speed == 673 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 674 *speed = IXGBE_LINK_SPEED_1GB_FULL; 675 break; 676 } 677 } 678 679 return status; 680 } 681 682 /** 683 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 684 * @hw: pointer to hardware structure 685 * 686 * Restart autonegotiation and PHY and waits for completion. 687 **/ 688 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 689 { 690 s32 status = IXGBE_SUCCESS; 691 u32 time_out; 692 u32 max_time_out = 10; 693 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 694 bool autoneg = FALSE; 695 ixgbe_link_speed speed; 696 697 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 698 699 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 700 701 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 702 /* Set or unset auto-negotiation 10G advertisement */ 703 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 704 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 705 &autoneg_reg); 706 707 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 708 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 709 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 710 711 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 712 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 713 autoneg_reg); 714 } 715 716 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 717 /* Set or unset auto-negotiation 1G advertisement */ 718 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 719 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 720 &autoneg_reg); 721 722 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 723 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 724 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 725 726 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 727 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 728 autoneg_reg); 729 } 730 731 if (speed & IXGBE_LINK_SPEED_100_FULL) { 732 /* Set or unset auto-negotiation 100M advertisement */ 733 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 734 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 735 &autoneg_reg); 736 737 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 738 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 739 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 740 741 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 742 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 743 autoneg_reg); 744 } 745 746 /* Restart PHY autonegotiation and wait for completion */ 747 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 748 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 749 750 autoneg_reg |= IXGBE_MII_RESTART; 751 752 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 753 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 754 755 /* Wait for autonegotiation to finish */ 756 for (time_out = 0; time_out < max_time_out; time_out++) { 757 usec_delay(10); 758 /* Restart PHY autonegotiation and wait for completion */ 759 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 760 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 761 &autoneg_reg); 762 763 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 764 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 765 break; 766 } 767 } 768 769 if (time_out == max_time_out) { 770 status = IXGBE_ERR_LINK_SETUP; 771 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 772 } 773 774 return status; 775 } 776 777 778 /** 779 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 780 * @hw: pointer to hardware structure 781 * @firmware_version: pointer to the PHY Firmware Version 782 **/ 783 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 784 u16 *firmware_version) 785 { 786 s32 status = IXGBE_SUCCESS; 787 788 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 789 790 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 791 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 792 firmware_version); 793 794 return status; 795 } 796 797 798 /** 799 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 800 * @hw: pointer to hardware structure 801 * @firmware_version: pointer to the PHY Firmware Version 802 **/ 803 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 804 u16 *firmware_version) 805 { 806 s32 status = IXGBE_SUCCESS; 807 808 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 809 810 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 811 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 812 firmware_version); 813 814 return status; 815 } 816 817 /** 818 * ixgbe_reset_phy_nl - Performs a PHY reset 819 * @hw: pointer to hardware structure 820 **/ 821 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 822 { 823 u16 phy_offset, control, eword, edata, block_crc; 824 bool end_data = FALSE; 825 u16 list_offset, data_offset; 826 u16 phy_data = 0; 827 s32 ret_val = IXGBE_SUCCESS; 828 u32 i; 829 830 DEBUGFUNC("ixgbe_reset_phy_nl"); 831 832 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 833 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 834 835 /* reset the PHY and poll for completion */ 836 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 837 IXGBE_MDIO_PHY_XS_DEV_TYPE, 838 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 839 840 for (i = 0; i < 100; i++) { 841 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 842 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 843 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 844 break; 845 msec_delay(10); 846 } 847 848 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 849 DEBUGOUT("PHY reset did not complete.\n"); 850 ret_val = IXGBE_ERR_PHY; 851 goto out; 852 } 853 854 /* Get init offsets */ 855 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 856 &data_offset); 857 if (ret_val != IXGBE_SUCCESS) 858 goto out; 859 860 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 861 data_offset++; 862 while (!end_data) { 863 /* 864 * Read control word from PHY init contents offset 865 */ 866 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 867 control = (eword & IXGBE_CONTROL_MASK_NL) >> 868 IXGBE_CONTROL_SHIFT_NL; 869 edata = eword & IXGBE_DATA_MASK_NL; 870 switch (control) { 871 case IXGBE_DELAY_NL: 872 data_offset++; 873 DEBUGOUT1("DELAY: %d MS\n", edata); 874 msec_delay(edata); 875 break; 876 case IXGBE_DATA_NL: 877 DEBUGOUT("DATA: \n"); 878 data_offset++; 879 hw->eeprom.ops.read(hw, data_offset++, 880 &phy_offset); 881 for (i = 0; i < edata; i++) { 882 hw->eeprom.ops.read(hw, data_offset, &eword); 883 hw->phy.ops.write_reg(hw, phy_offset, 884 IXGBE_TWINAX_DEV, eword); 885 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 886 phy_offset); 887 data_offset++; 888 phy_offset++; 889 } 890 break; 891 case IXGBE_CONTROL_NL: 892 data_offset++; 893 DEBUGOUT("CONTROL: \n"); 894 if (edata == IXGBE_CONTROL_EOL_NL) { 895 DEBUGOUT("EOL\n"); 896 end_data = TRUE; 897 } else if (edata == IXGBE_CONTROL_SOL_NL) { 898 DEBUGOUT("SOL\n"); 899 } else { 900 DEBUGOUT("Bad control value\n"); 901 ret_val = IXGBE_ERR_PHY; 902 goto out; 903 } 904 break; 905 default: 906 DEBUGOUT("Bad control type\n"); 907 ret_val = IXGBE_ERR_PHY; 908 goto out; 909 } 910 } 911 912 out: 913 return ret_val; 914 } 915 916 /** 917 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 918 * @hw: pointer to hardware structure 919 * 920 * Searches for and identifies the SFP module and assigns appropriate PHY type. 921 **/ 922 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 923 { 924 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 925 u32 vendor_oui = 0; 926 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 927 u8 identifier = 0; 928 u8 comp_codes_1g = 0; 929 u8 comp_codes_10g = 0; 930 u8 oui_bytes[3] = {0, 0, 0}; 931 u8 cable_tech = 0; 932 u8 cable_spec = 0; 933 u16 enforce_sfp = 0; 934 935 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 936 937 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 938 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 939 status = IXGBE_ERR_SFP_NOT_PRESENT; 940 goto out; 941 } 942 943 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 944 &identifier); 945 946 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 947 status = IXGBE_ERR_SFP_NOT_PRESENT; 948 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 949 if (hw->phy.type != ixgbe_phy_nl) { 950 hw->phy.id = 0; 951 hw->phy.type = ixgbe_phy_unknown; 952 } 953 goto out; 954 } 955 956 /* LAN ID is needed for sfp_type determination */ 957 hw->mac.ops.set_lan_id(hw); 958 959 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 960 hw->phy.type = ixgbe_phy_sfp_unsupported; 961 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 962 } else { 963 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 964 &comp_codes_1g); 965 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 966 &comp_codes_10g); 967 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, 968 &cable_tech); 969 970 /* ID Module 971 * ========= 972 * 0 SFP_DA_CU 973 * 1 SFP_SR 974 * 2 SFP_LR 975 * 3 SFP_DA_CORE0 - 82599-specific 976 * 4 SFP_DA_CORE1 - 82599-specific 977 * 5 SFP_SR/LR_CORE0 - 82599-specific 978 * 6 SFP_SR/LR_CORE1 - 82599-specific 979 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 980 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 981 */ 982 if (hw->mac.type == ixgbe_mac_82598EB) { 983 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 984 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 985 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 986 hw->phy.sfp_type = ixgbe_sfp_type_sr; 987 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 988 hw->phy.sfp_type = ixgbe_sfp_type_lr; 989 else 990 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 991 } else if (hw->mac.type == ixgbe_mac_82599EB) { 992 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 993 if (hw->bus.lan_id == 0) 994 hw->phy.sfp_type = 995 ixgbe_sfp_type_da_cu_core0; 996 else 997 hw->phy.sfp_type = 998 ixgbe_sfp_type_da_cu_core1; 999 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1000 hw->phy.ops.read_i2c_eeprom( 1001 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1002 &cable_spec); 1003 if (cable_spec & 1004 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1005 if (hw->bus.lan_id == 0) 1006 hw->phy.sfp_type = 1007 ixgbe_sfp_type_da_act_lmt_core0; 1008 else 1009 hw->phy.sfp_type = 1010 ixgbe_sfp_type_da_act_lmt_core1; 1011 } else 1012 hw->phy.sfp_type = 1013 ixgbe_sfp_type_unknown; 1014 } else if (comp_codes_10g & 1015 (IXGBE_SFF_10GBASESR_CAPABLE | 1016 IXGBE_SFF_10GBASELR_CAPABLE)) { 1017 if (hw->bus.lan_id == 0) 1018 hw->phy.sfp_type = 1019 ixgbe_sfp_type_srlr_core0; 1020 else 1021 hw->phy.sfp_type = 1022 ixgbe_sfp_type_srlr_core1; 1023 } else { 1024 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1025 } 1026 } 1027 1028 if (hw->phy.sfp_type != stored_sfp_type) 1029 hw->phy.sfp_setup_needed = TRUE; 1030 1031 /* Determine if the SFP+ PHY is dual speed or not. */ 1032 hw->phy.multispeed_fiber = FALSE; 1033 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1034 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1035 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1036 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1037 hw->phy.multispeed_fiber = TRUE; 1038 1039 /* Determine PHY vendor */ 1040 if (hw->phy.type != ixgbe_phy_nl) { 1041 hw->phy.id = identifier; 1042 hw->phy.ops.read_i2c_eeprom(hw, 1043 IXGBE_SFF_VENDOR_OUI_BYTE0, 1044 &oui_bytes[0]); 1045 hw->phy.ops.read_i2c_eeprom(hw, 1046 IXGBE_SFF_VENDOR_OUI_BYTE1, 1047 &oui_bytes[1]); 1048 hw->phy.ops.read_i2c_eeprom(hw, 1049 IXGBE_SFF_VENDOR_OUI_BYTE2, 1050 &oui_bytes[2]); 1051 1052 vendor_oui = 1053 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1054 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1055 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1056 1057 switch (vendor_oui) { 1058 case IXGBE_SFF_VENDOR_OUI_TYCO: 1059 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1060 hw->phy.type = 1061 ixgbe_phy_sfp_passive_tyco; 1062 break; 1063 case IXGBE_SFF_VENDOR_OUI_FTL: 1064 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1065 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1066 else 1067 hw->phy.type = ixgbe_phy_sfp_ftl; 1068 break; 1069 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1070 hw->phy.type = ixgbe_phy_sfp_avago; 1071 break; 1072 case IXGBE_SFF_VENDOR_OUI_INTEL: 1073 hw->phy.type = ixgbe_phy_sfp_intel; 1074 break; 1075 default: 1076 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1077 hw->phy.type = 1078 ixgbe_phy_sfp_passive_unknown; 1079 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1080 hw->phy.type = 1081 ixgbe_phy_sfp_active_unknown; 1082 else 1083 hw->phy.type = ixgbe_phy_sfp_unknown; 1084 break; 1085 } 1086 } 1087 1088 /* Allow any DA cable vendor */ 1089 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1090 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1091 status = IXGBE_SUCCESS; 1092 goto out; 1093 } 1094 1095 /* 1G SFP modules are not supported */ 1096 if (comp_codes_10g == 0) { 1097 hw->phy.type = ixgbe_phy_sfp_unsupported; 1098 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1099 goto out; 1100 } 1101 1102 /* Anything else 82598-based is supported */ 1103 if (hw->mac.type == ixgbe_mac_82598EB) { 1104 status = IXGBE_SUCCESS; 1105 goto out; 1106 } 1107 1108 ixgbe_get_device_caps(hw, &enforce_sfp); 1109 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1110 /* Make sure we're a supported PHY type */ 1111 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1112 status = IXGBE_SUCCESS; 1113 } else { 1114 DEBUGOUT("SFP+ module not supported\n"); 1115 hw->phy.type = ixgbe_phy_sfp_unsupported; 1116 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1117 } 1118 } else { 1119 status = IXGBE_SUCCESS; 1120 } 1121 } 1122 1123 out: 1124 return status; 1125 } 1126 1127 /** 1128 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1129 * @hw: pointer to hardware structure 1130 * @list_offset: offset to the SFP ID list 1131 * @data_offset: offset to the SFP data block 1132 * 1133 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1134 * so it returns the offsets to the phy init sequence block. 1135 **/ 1136 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1137 u16 *list_offset, 1138 u16 *data_offset) 1139 { 1140 u16 sfp_id; 1141 u16 sfp_type = hw->phy.sfp_type; 1142 1143 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1144 1145 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1146 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1147 1148 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1149 return IXGBE_ERR_SFP_NOT_PRESENT; 1150 1151 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1152 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1153 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1154 1155 /* Limiting active cables must be initialized as SR modules */ 1156 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0) 1157 sfp_type = ixgbe_sfp_type_srlr_core0; 1158 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1) 1159 sfp_type = ixgbe_sfp_type_srlr_core1; 1160 1161 /* Read offset to PHY init contents */ 1162 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1163 1164 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1165 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1166 1167 /* Shift offset to first ID word */ 1168 (*list_offset)++; 1169 1170 /* 1171 * Find the matching SFP ID in the EEPROM 1172 * and program the init sequence 1173 */ 1174 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1175 1176 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1177 if (sfp_id == sfp_type) { 1178 (*list_offset)++; 1179 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1180 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1181 DEBUGOUT("SFP+ module not supported\n"); 1182 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1183 } else { 1184 break; 1185 } 1186 } else { 1187 (*list_offset) += 2; 1188 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1189 return IXGBE_ERR_PHY; 1190 } 1191 } 1192 1193 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1194 DEBUGOUT("No matching SFP+ module found\n"); 1195 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1196 } 1197 1198 return IXGBE_SUCCESS; 1199 } 1200 1201 /** 1202 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1203 * @hw: pointer to hardware structure 1204 * @byte_offset: EEPROM byte offset to read 1205 * @eeprom_data: value read 1206 * 1207 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1208 **/ 1209 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1210 u8 *eeprom_data) 1211 { 1212 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1213 1214 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1215 IXGBE_I2C_EEPROM_DEV_ADDR, 1216 eeprom_data); 1217 } 1218 1219 /** 1220 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1221 * @hw: pointer to hardware structure 1222 * @byte_offset: EEPROM byte offset to write 1223 * @eeprom_data: value to write 1224 * 1225 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1226 **/ 1227 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1228 u8 eeprom_data) 1229 { 1230 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1231 1232 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1233 IXGBE_I2C_EEPROM_DEV_ADDR, 1234 eeprom_data); 1235 } 1236 1237 /** 1238 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1239 * @hw: pointer to hardware structure 1240 * @byte_offset: byte offset to read 1241 * @data: value read 1242 * 1243 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1244 * a specified deivce address. 1245 **/ 1246 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1247 u8 dev_addr, u8 *data) 1248 { 1249 s32 status = IXGBE_SUCCESS; 1250 u32 max_retry = 10; 1251 u32 retry = 0; 1252 u16 swfw_mask = 0; 1253 bool nack = 1; 1254 1255 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1256 1257 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1258 swfw_mask = IXGBE_GSSR_PHY1_SM; 1259 else 1260 swfw_mask = IXGBE_GSSR_PHY0_SM; 1261 1262 1263 do { 1264 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1265 status = IXGBE_ERR_SWFW_SYNC; 1266 goto read_byte_out; 1267 } 1268 1269 ixgbe_i2c_start(hw); 1270 1271 /* Device Address and write indication */ 1272 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1273 if (status != IXGBE_SUCCESS) 1274 goto fail; 1275 1276 status = ixgbe_get_i2c_ack(hw); 1277 if (status != IXGBE_SUCCESS) 1278 goto fail; 1279 1280 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1281 if (status != IXGBE_SUCCESS) 1282 goto fail; 1283 1284 status = ixgbe_get_i2c_ack(hw); 1285 if (status != IXGBE_SUCCESS) 1286 goto fail; 1287 1288 ixgbe_i2c_start(hw); 1289 1290 /* Device Address and read indication */ 1291 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1292 if (status != IXGBE_SUCCESS) 1293 goto fail; 1294 1295 status = ixgbe_get_i2c_ack(hw); 1296 if (status != IXGBE_SUCCESS) 1297 goto fail; 1298 1299 status = ixgbe_clock_in_i2c_byte(hw, data); 1300 if (status != IXGBE_SUCCESS) 1301 goto fail; 1302 1303 status = ixgbe_clock_out_i2c_bit(hw, nack); 1304 if (status != IXGBE_SUCCESS) 1305 goto fail; 1306 1307 ixgbe_i2c_stop(hw); 1308 break; 1309 1310 fail: 1311 ixgbe_release_swfw_sync(hw, swfw_mask); 1312 msec_delay(100); 1313 ixgbe_i2c_bus_clear(hw); 1314 retry++; 1315 if (retry < max_retry) 1316 DEBUGOUT("I2C byte read error - Retrying.\n"); 1317 else 1318 DEBUGOUT("I2C byte read error.\n"); 1319 1320 } while (retry < max_retry); 1321 1322 ixgbe_release_swfw_sync(hw, swfw_mask); 1323 1324 read_byte_out: 1325 return status; 1326 } 1327 1328 /** 1329 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1330 * @hw: pointer to hardware structure 1331 * @byte_offset: byte offset to write 1332 * @data: value to write 1333 * 1334 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1335 * a specified device address. 1336 **/ 1337 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1338 u8 dev_addr, u8 data) 1339 { 1340 s32 status = IXGBE_SUCCESS; 1341 u32 max_retry = 1; 1342 u32 retry = 0; 1343 u16 swfw_mask = 0; 1344 1345 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1346 1347 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1348 swfw_mask = IXGBE_GSSR_PHY1_SM; 1349 else 1350 swfw_mask = IXGBE_GSSR_PHY0_SM; 1351 1352 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1353 status = IXGBE_ERR_SWFW_SYNC; 1354 goto write_byte_out; 1355 } 1356 1357 do { 1358 ixgbe_i2c_start(hw); 1359 1360 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1361 if (status != IXGBE_SUCCESS) 1362 goto fail; 1363 1364 status = ixgbe_get_i2c_ack(hw); 1365 if (status != IXGBE_SUCCESS) 1366 goto fail; 1367 1368 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1369 if (status != IXGBE_SUCCESS) 1370 goto fail; 1371 1372 status = ixgbe_get_i2c_ack(hw); 1373 if (status != IXGBE_SUCCESS) 1374 goto fail; 1375 1376 status = ixgbe_clock_out_i2c_byte(hw, data); 1377 if (status != IXGBE_SUCCESS) 1378 goto fail; 1379 1380 status = ixgbe_get_i2c_ack(hw); 1381 if (status != IXGBE_SUCCESS) 1382 goto fail; 1383 1384 ixgbe_i2c_stop(hw); 1385 break; 1386 1387 fail: 1388 ixgbe_i2c_bus_clear(hw); 1389 retry++; 1390 if (retry < max_retry) 1391 DEBUGOUT("I2C byte write error - Retrying.\n"); 1392 else 1393 DEBUGOUT("I2C byte write error.\n"); 1394 } while (retry < max_retry); 1395 1396 ixgbe_release_swfw_sync(hw, swfw_mask); 1397 1398 write_byte_out: 1399 return status; 1400 } 1401 1402 /** 1403 * ixgbe_i2c_start - Sets I2C start condition 1404 * @hw: pointer to hardware structure 1405 * 1406 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1407 **/ 1408 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1409 { 1410 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1411 1412 DEBUGFUNC("ixgbe_i2c_start"); 1413 1414 /* Start condition must begin with data and clock high */ 1415 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1416 ixgbe_raise_i2c_clk(hw, &i2cctl); 1417 1418 /* Setup time for start condition (4.7us) */ 1419 usec_delay(IXGBE_I2C_T_SU_STA); 1420 1421 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1422 1423 /* Hold time for start condition (4us) */ 1424 usec_delay(IXGBE_I2C_T_HD_STA); 1425 1426 ixgbe_lower_i2c_clk(hw, &i2cctl); 1427 1428 /* Minimum low period of clock is 4.7 us */ 1429 usec_delay(IXGBE_I2C_T_LOW); 1430 1431 } 1432 1433 /** 1434 * ixgbe_i2c_stop - Sets I2C stop condition 1435 * @hw: pointer to hardware structure 1436 * 1437 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1438 **/ 1439 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1440 { 1441 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1442 1443 DEBUGFUNC("ixgbe_i2c_stop"); 1444 1445 /* Stop condition must begin with data low and clock high */ 1446 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1447 ixgbe_raise_i2c_clk(hw, &i2cctl); 1448 1449 /* Setup time for stop condition (4us) */ 1450 usec_delay(IXGBE_I2C_T_SU_STO); 1451 1452 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1453 1454 /* bus free time between stop and start (4.7us)*/ 1455 usec_delay(IXGBE_I2C_T_BUF); 1456 } 1457 1458 /** 1459 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1460 * @hw: pointer to hardware structure 1461 * @data: data byte to clock in 1462 * 1463 * Clocks in one byte data via I2C data/clock 1464 **/ 1465 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1466 { 1467 s32 status = IXGBE_SUCCESS; 1468 s32 i; 1469 bool bit = 0; 1470 1471 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1472 1473 for (i = 7; i >= 0; i--) { 1474 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1475 *data |= bit<<i; 1476 1477 if (status != IXGBE_SUCCESS) 1478 break; 1479 } 1480 1481 return status; 1482 } 1483 1484 /** 1485 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1486 * @hw: pointer to hardware structure 1487 * @data: data byte clocked out 1488 * 1489 * Clocks out one byte data via I2C data/clock 1490 **/ 1491 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1492 { 1493 s32 status = IXGBE_SUCCESS; 1494 s32 i; 1495 u32 i2cctl; 1496 bool bit = 0; 1497 1498 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1499 1500 for (i = 7; i >= 0; i--) { 1501 bit = (data >> i) & 0x1; 1502 status = ixgbe_clock_out_i2c_bit(hw, bit); 1503 1504 if (status != IXGBE_SUCCESS) 1505 break; 1506 } 1507 1508 /* Release SDA line (set high) */ 1509 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1510 i2cctl |= IXGBE_I2C_DATA_OUT; 1511 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1512 1513 return status; 1514 } 1515 1516 /** 1517 * ixgbe_get_i2c_ack - Polls for I2C ACK 1518 * @hw: pointer to hardware structure 1519 * 1520 * Clocks in/out one bit via I2C data/clock 1521 **/ 1522 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1523 { 1524 s32 status; 1525 u32 i = 0; 1526 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1527 u32 timeout = 10; 1528 bool ack = 1; 1529 1530 DEBUGFUNC("ixgbe_get_i2c_ack"); 1531 1532 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1533 1534 if (status != IXGBE_SUCCESS) 1535 goto out; 1536 1537 /* Minimum high period of clock is 4us */ 1538 usec_delay(IXGBE_I2C_T_HIGH); 1539 1540 /* Poll for ACK. Note that ACK in I2C spec is 1541 * transition from 1 to 0 */ 1542 for (i = 0; i < timeout; i++) { 1543 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1544 ack = ixgbe_get_i2c_data(&i2cctl); 1545 1546 usec_delay(1); 1547 if (ack == 0) 1548 break; 1549 } 1550 1551 if (ack == 1) { 1552 DEBUGOUT("I2C ack was not received.\n"); 1553 status = IXGBE_ERR_I2C; 1554 } 1555 1556 ixgbe_lower_i2c_clk(hw, &i2cctl); 1557 1558 /* Minimum low period of clock is 4.7 us */ 1559 usec_delay(IXGBE_I2C_T_LOW); 1560 1561 out: 1562 return status; 1563 } 1564 1565 /** 1566 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1567 * @hw: pointer to hardware structure 1568 * @data: read data value 1569 * 1570 * Clocks in one bit via I2C data/clock 1571 **/ 1572 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1573 { 1574 s32 status; 1575 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1576 1577 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1578 1579 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1580 1581 /* Minimum high period of clock is 4us */ 1582 usec_delay(IXGBE_I2C_T_HIGH); 1583 1584 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1585 *data = ixgbe_get_i2c_data(&i2cctl); 1586 1587 ixgbe_lower_i2c_clk(hw, &i2cctl); 1588 1589 /* Minimum low period of clock is 4.7 us */ 1590 usec_delay(IXGBE_I2C_T_LOW); 1591 1592 return status; 1593 } 1594 1595 /** 1596 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1597 * @hw: pointer to hardware structure 1598 * @data: data value to write 1599 * 1600 * Clocks out one bit via I2C data/clock 1601 **/ 1602 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1603 { 1604 s32 status; 1605 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1606 1607 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1608 1609 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1610 if (status == IXGBE_SUCCESS) { 1611 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1612 1613 /* Minimum high period of clock is 4us */ 1614 usec_delay(IXGBE_I2C_T_HIGH); 1615 1616 ixgbe_lower_i2c_clk(hw, &i2cctl); 1617 1618 /* Minimum low period of clock is 4.7 us. 1619 * This also takes care of the data hold time. 1620 */ 1621 usec_delay(IXGBE_I2C_T_LOW); 1622 } else { 1623 status = IXGBE_ERR_I2C; 1624 DEBUGOUT1("I2C data was not set to %X\n", data); 1625 } 1626 1627 return status; 1628 } 1629 /** 1630 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1631 * @hw: pointer to hardware structure 1632 * @i2cctl: Current value of I2CCTL register 1633 * 1634 * Raises the I2C clock line '0'->'1' 1635 **/ 1636 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1637 { 1638 s32 status = IXGBE_SUCCESS; 1639 1640 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1641 1642 *i2cctl |= IXGBE_I2C_CLK_OUT; 1643 1644 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1645 1646 /* SCL rise time (1000ns) */ 1647 usec_delay(IXGBE_I2C_T_RISE); 1648 1649 return status; 1650 } 1651 1652 /** 1653 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1654 * @hw: pointer to hardware structure 1655 * @i2cctl: Current value of I2CCTL register 1656 * 1657 * Lowers the I2C clock line '1'->'0' 1658 **/ 1659 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1660 { 1661 1662 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1663 1664 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1665 1666 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1667 1668 /* SCL fall time (300ns) */ 1669 usec_delay(IXGBE_I2C_T_FALL); 1670 } 1671 1672 /** 1673 * ixgbe_set_i2c_data - Sets the I2C data bit 1674 * @hw: pointer to hardware structure 1675 * @i2cctl: Current value of I2CCTL register 1676 * @data: I2C data value (0 or 1) to set 1677 * 1678 * Sets the I2C data bit 1679 **/ 1680 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1681 { 1682 s32 status = IXGBE_SUCCESS; 1683 1684 DEBUGFUNC("ixgbe_set_i2c_data"); 1685 1686 if (data) 1687 *i2cctl |= IXGBE_I2C_DATA_OUT; 1688 else 1689 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1690 1691 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1692 1693 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1694 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1695 1696 /* Verify data was set correctly */ 1697 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1698 if (data != ixgbe_get_i2c_data(i2cctl)) { 1699 status = IXGBE_ERR_I2C; 1700 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1701 } 1702 1703 return status; 1704 } 1705 1706 /** 1707 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1708 * @hw: pointer to hardware structure 1709 * @i2cctl: Current value of I2CCTL register 1710 * 1711 * Returns the I2C data bit value 1712 **/ 1713 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1714 { 1715 bool data; 1716 1717 DEBUGFUNC("ixgbe_get_i2c_data"); 1718 1719 if (*i2cctl & IXGBE_I2C_DATA_IN) 1720 data = 1; 1721 else 1722 data = 0; 1723 1724 return data; 1725 } 1726 1727 /** 1728 * ixgbe_i2c_bus_clear - Clears the I2C bus 1729 * @hw: pointer to hardware structure 1730 * 1731 * Clears the I2C bus by sending nine clock pulses. 1732 * Used when data line is stuck low. 1733 **/ 1734 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1735 { 1736 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1737 u32 i; 1738 1739 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1740 1741 ixgbe_i2c_start(hw); 1742 1743 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1744 1745 for (i = 0; i < 9; i++) { 1746 ixgbe_raise_i2c_clk(hw, &i2cctl); 1747 1748 /* Min high period of clock is 4us */ 1749 usec_delay(IXGBE_I2C_T_HIGH); 1750 1751 ixgbe_lower_i2c_clk(hw, &i2cctl); 1752 1753 /* Min low period of clock is 4.7us*/ 1754 usec_delay(IXGBE_I2C_T_LOW); 1755 } 1756 1757 ixgbe_i2c_start(hw); 1758 1759 /* Put the i2c bus back to default state */ 1760 ixgbe_i2c_stop(hw); 1761 } 1762 1763 /** 1764 * ixgbe_check_overtemp - Checks if an overtemp occured. 1765 * @hw: pointer to hardware structure 1766 * 1767 * Checks if the LASI temp alarm status was triggered due to overtemp 1768 **/ 1769 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1770 { 1771 s32 status = IXGBE_SUCCESS; 1772 u16 phy_data = 0; 1773 1774 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1775 1776 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1777 goto out; 1778 1779 /* Check that the LASI temp alarm status was triggered */ 1780 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1781 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1782 1783 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1784 goto out; 1785 1786 status = IXGBE_ERR_OVERTEMP; 1787 out: 1788 return status; 1789 } 1790 1791 1792 /** 1793 * ixgbe_set_tn_low_power_state - Sets the teranetics phy into low power state 1794 * @hw: pointer to hardware structure 1795 * 1796 * Sets the phy into low power mode when LASI temp alarm status is triggered 1797 **/ 1798 s32 ixgbe_tn_set_low_power_state(struct ixgbe_hw *hw) 1799 { 1800 s32 status = IXGBE_SUCCESS; 1801 u16 phy_data = 0; 1802 1803 DEBUGFUNC("ixgbe_set_tn_low_power_state"); 1804 1805 /* Set the phy into low power mode */ 1806 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_CONTROL_ADDR, 1807 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1808 phy_data |= IXGBE_MDIO_PHY_LOW_POWER_MODE; 1809 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_PMD_CONTROL_ADDR, 1810 IXGBE_MDIO_PMA_PMD_DEV_TYPE, phy_data); 1811 1812 return status; 1813 } 1814 1815