1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 /** 40 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 41 * @hw: pointer to the hardware structure 42 * 43 * Initialize the function pointers. 44 **/ 45 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 46 { 47 struct ixgbe_phy_info *phy = &hw->phy; 48 49 /* PHY */ 50 phy->ops.identify = &ixgbe_identify_phy_generic; 51 phy->ops.reset = &ixgbe_reset_phy_generic; 52 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 53 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 54 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 55 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 56 phy->ops.check_link = NULL; 57 phy->ops.get_firmware_version = NULL; 58 59 return IXGBE_SUCCESS; 60 } 61 62 /** 63 * ixgbe_identify_phy_generic - Get physical layer module 64 * @hw: pointer to hardware structure 65 * 66 * Determines the physical layer module found on the current adapter. 67 **/ 68 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 69 { 70 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 71 u32 phy_addr; 72 73 if (hw->phy.type == ixgbe_phy_unknown) { 74 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 75 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 76 hw->phy.addr = phy_addr; 77 ixgbe_get_phy_id(hw); 78 hw->phy.type = 79 ixgbe_get_phy_type_from_id(hw->phy.id); 80 status = IXGBE_SUCCESS; 81 break; 82 } 83 } 84 } else { 85 status = IXGBE_SUCCESS; 86 } 87 88 return status; 89 } 90 91 /** 92 * ixgbe_validate_phy_addr - Determines phy address is valid 93 * @hw: pointer to hardware structure 94 * 95 **/ 96 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 97 { 98 u16 phy_id = 0; 99 bool valid = FALSE; 100 101 hw->phy.addr = phy_addr; 102 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 103 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 104 105 if (phy_id != 0xFFFF && phy_id != 0x0) 106 valid = TRUE; 107 108 return valid; 109 } 110 111 /** 112 * ixgbe_get_phy_id - Get the phy type 113 * @hw: pointer to hardware structure 114 * 115 **/ 116 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 117 { 118 u32 status; 119 u16 phy_id_high = 0; 120 u16 phy_id_low = 0; 121 122 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 123 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 124 &phy_id_high); 125 126 if (status == IXGBE_SUCCESS) { 127 hw->phy.id = (u32)(phy_id_high << 16); 128 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 129 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 130 &phy_id_low); 131 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 132 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 133 } 134 135 return status; 136 } 137 138 /** 139 * ixgbe_get_phy_type_from_id - Get the phy type 140 * @hw: pointer to hardware structure 141 * 142 **/ 143 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 144 { 145 enum ixgbe_phy_type phy_type; 146 147 switch (phy_id) { 148 case TN1010_PHY_ID: 149 phy_type = ixgbe_phy_tn; 150 break; 151 case QT2022_PHY_ID: 152 phy_type = ixgbe_phy_qt; 153 break; 154 case ATH_PHY_ID: 155 phy_type = ixgbe_phy_nl; 156 break; 157 default: 158 phy_type = ixgbe_phy_unknown; 159 break; 160 } 161 162 DEBUGOUT1("phy type found is %d\n", phy_type); 163 return phy_type; 164 } 165 166 /** 167 * ixgbe_reset_phy_generic - Performs a PHY reset 168 * @hw: pointer to hardware structure 169 **/ 170 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 171 { 172 /* 173 * Perform soft PHY reset to the PHY_XS. 174 * This will cause a soft reset to the PHY 175 */ 176 return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 177 IXGBE_MDIO_PHY_XS_DEV_TYPE, 178 IXGBE_MDIO_PHY_XS_RESET); 179 } 180 181 /** 182 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 183 * @hw: pointer to hardware structure 184 * @reg_addr: 32 bit address of PHY register to read 185 * @phy_data: Pointer to read data from PHY register 186 **/ 187 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 188 u32 device_type, u16 *phy_data) 189 { 190 u32 command; 191 u32 i; 192 u32 data; 193 s32 status = IXGBE_SUCCESS; 194 u16 gssr; 195 196 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 197 gssr = IXGBE_GSSR_PHY1_SM; 198 else 199 gssr = IXGBE_GSSR_PHY0_SM; 200 201 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 202 status = IXGBE_ERR_SWFW_SYNC; 203 204 if (status == IXGBE_SUCCESS) { 205 /* Setup and write the address cycle command */ 206 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 207 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 208 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 209 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 210 211 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 212 213 /* 214 * Check every 10 usec to see if the address cycle completed. 215 * The MDI Command bit will clear when the operation is 216 * complete 217 */ 218 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 219 usec_delay(10); 220 221 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 222 223 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) { 224 break; 225 } 226 } 227 228 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 229 DEBUGOUT("PHY address command did not complete.\n"); 230 status = IXGBE_ERR_PHY; 231 } 232 233 if (status == IXGBE_SUCCESS) { 234 /* 235 * Address cycle complete, setup and write the read 236 * command 237 */ 238 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 239 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 240 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 241 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 242 243 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 244 245 /* 246 * Check every 10 usec to see if the address cycle 247 * completed. The MDI Command bit will clear when the 248 * operation is complete 249 */ 250 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 251 usec_delay(10); 252 253 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 254 255 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 256 break; 257 } 258 259 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 260 DEBUGOUT("PHY read command didn't complete\n"); 261 status = IXGBE_ERR_PHY; 262 } else { 263 /* 264 * Read operation is complete. Get the data 265 * from MSRWD 266 */ 267 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 268 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 269 *phy_data = (u16)(data); 270 } 271 } 272 273 ixgbe_release_swfw_sync(hw, gssr); 274 } 275 276 return status; 277 } 278 279 /** 280 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 281 * @hw: pointer to hardware structure 282 * @reg_addr: 32 bit PHY register to write 283 * @device_type: 5 bit device type 284 * @phy_data: Data to write to the PHY register 285 **/ 286 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 287 u32 device_type, u16 phy_data) 288 { 289 u32 command; 290 u32 i; 291 s32 status = IXGBE_SUCCESS; 292 u16 gssr; 293 294 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 295 gssr = IXGBE_GSSR_PHY1_SM; 296 else 297 gssr = IXGBE_GSSR_PHY0_SM; 298 299 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 300 status = IXGBE_ERR_SWFW_SYNC; 301 302 if (status == IXGBE_SUCCESS) { 303 /* Put the data in the MDI single read and write data register*/ 304 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 305 306 /* Setup and write the address cycle command */ 307 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 308 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 309 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 310 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 311 312 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 313 314 /* 315 * Check every 10 usec to see if the address cycle completed. 316 * The MDI Command bit will clear when the operation is 317 * complete 318 */ 319 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 320 usec_delay(10); 321 322 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 323 324 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 325 break; 326 } 327 328 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 329 DEBUGOUT("PHY address cmd didn't complete\n"); 330 status = IXGBE_ERR_PHY; 331 } 332 333 if (status == IXGBE_SUCCESS) { 334 /* 335 * Address cycle complete, setup and write the write 336 * command 337 */ 338 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 339 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 340 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 341 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 342 343 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 344 345 /* 346 * Check every 10 usec to see if the address cycle 347 * completed. The MDI Command bit will clear when the 348 * operation is complete 349 */ 350 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 351 usec_delay(10); 352 353 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 354 355 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 356 break; 357 } 358 359 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 360 DEBUGOUT("PHY address cmd didn't complete\n"); 361 status = IXGBE_ERR_PHY; 362 } 363 } 364 365 ixgbe_release_swfw_sync(hw, gssr); 366 } 367 368 return status; 369 } 370 371 /** 372 * ixgbe_setup_phy_link_generic - Set and restart autoneg 373 * @hw: pointer to hardware structure 374 * 375 * Restart autonegotiation and PHY and waits for completion. 376 **/ 377 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 378 { 379 s32 status = IXGBE_NOT_IMPLEMENTED; 380 u32 time_out; 381 u32 max_time_out = 10; 382 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 383 384 /* 385 * Set advertisement settings in PHY based on autoneg_advertised 386 * settings. If autoneg_advertised = 0, then advertise default values 387 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 388 * for a 1G. 389 */ 390 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 391 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 392 393 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) 394 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */ 395 else 396 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */ 397 398 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG, 399 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 400 401 /* Restart PHY autonegotiation and wait for completion */ 402 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 403 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 404 405 autoneg_reg |= IXGBE_MII_RESTART; 406 407 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 408 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 409 410 /* Wait for autonegotiation to finish */ 411 for (time_out = 0; time_out < max_time_out; time_out++) { 412 usec_delay(10); 413 /* Restart PHY autonegotiation and wait for completion */ 414 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 415 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 416 &autoneg_reg); 417 418 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 419 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 420 status = IXGBE_SUCCESS; 421 break; 422 } 423 } 424 425 if (time_out == max_time_out) 426 status = IXGBE_ERR_LINK_SETUP; 427 428 return status; 429 } 430 431 /** 432 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 433 * @hw: pointer to hardware structure 434 * @speed: new link speed 435 * @autoneg: TRUE if autonegotiation enabled 436 **/ 437 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 438 ixgbe_link_speed speed, 439 bool autoneg, 440 bool autoneg_wait_to_complete) 441 { 442 UNREFERENCED_PARAMETER(autoneg); 443 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 444 445 /* 446 * Clear autoneg_advertised and set new values based on input link 447 * speed. 448 */ 449 hw->phy.autoneg_advertised = 0; 450 451 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 452 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 453 } 454 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 455 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 456 } 457 458 /* Setup link based on the new speed settings */ 459 hw->phy.ops.setup_link(hw); 460 461 return IXGBE_SUCCESS; 462 } 463 464 /** 465 * ixgbe_check_phy_link_tnx - Determine link and speed status 466 * @hw: pointer to hardware structure 467 * 468 * Reads the VS1 register to determine if link is up and the current speed for 469 * the PHY. 470 **/ 471 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 472 bool *link_up) 473 { 474 s32 status = IXGBE_SUCCESS; 475 u32 time_out; 476 u32 max_time_out = 10; 477 u16 phy_link = 0; 478 u16 phy_speed = 0; 479 u16 phy_data = 0; 480 481 /* Initialize speed and link to default case */ 482 *link_up = FALSE; 483 *speed = IXGBE_LINK_SPEED_10GB_FULL; 484 485 /* 486 * Check current speed and link status of the PHY register. 487 * This is a vendor specific register and may have to 488 * be changed for other copper PHYs. 489 */ 490 for (time_out = 0; time_out < max_time_out; time_out++) { 491 usec_delay(10); 492 status = hw->phy.ops.read_reg(hw, 493 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 494 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 495 &phy_data); 496 phy_link = phy_data & 497 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 498 phy_speed = phy_data & 499 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 500 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 501 *link_up = TRUE; 502 if (phy_speed == 503 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 504 *speed = IXGBE_LINK_SPEED_1GB_FULL; 505 break; 506 } 507 } 508 509 return status; 510 } 511 512 /** 513 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 514 * @hw: pointer to hardware structure 515 * @firmware_version: pointer to the PHY Firmware Version 516 **/ 517 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 518 u16 *firmware_version) 519 { 520 s32 status = IXGBE_SUCCESS; 521 522 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 523 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 524 firmware_version); 525 526 return status; 527 } 528 529 /** 530 * ixgbe_reset_phy_nl - Performs a PHY reset 531 * @hw: pointer to hardware structure 532 **/ 533 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 534 { 535 u16 phy_offset, control, eword, edata, list_crc, block_crc, id, sfp_id; 536 bool end_data = FALSE; 537 u16 list_offset, data_offset; 538 u16 phy_data = 0; 539 s32 ret_val = IXGBE_SUCCESS; 540 u32 i; 541 542 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 543 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 544 545 /* reset the PHY and poll for completion */ 546 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 547 IXGBE_MDIO_PHY_XS_DEV_TYPE, 548 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 549 550 for (i = 0; i < 100; i++) { 551 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 552 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 553 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0 ) 554 break; 555 msec_delay(10); 556 } 557 558 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 559 DEBUGOUT("PHY reset did not complete.\n"); 560 ret_val = IXGBE_ERR_PHY; 561 goto out; 562 } 563 564 /* read offset to PHY init contents */ 565 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, &list_offset); 566 567 if ((!list_offset) || (list_offset == 0xFFFF)) { 568 ret_val = IXGBE_ERR_PHY; 569 goto out; 570 } 571 572 /* Acquire the CRC */ 573 hw->eeprom.ops.read(hw, list_offset, &list_crc); 574 575 /* Shift offset to first ID word */ 576 list_offset++; 577 578 /* determine the sfp sequence based on device ID */ 579 switch (hw->device_id) { 580 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 581 sfp_id = 0; 582 break; 583 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 584 sfp_id = 1; 585 break; 586 default: 587 ret_val = IXGBE_ERR_PHY; 588 goto out; 589 } 590 591 /* 592 * Find the matching sfp ID in the EEPROM 593 * and program the init sequence 594 */ 595 hw->eeprom.ops.read(hw, list_offset, &id); 596 597 while (!((id == IXGBE_CONTROL_EOL_NL) || (end_data == TRUE))) { 598 if (id == sfp_id) { 599 list_offset++; 600 hw->eeprom.ops.read(hw, list_offset, &data_offset); 601 if ((!data_offset) || (data_offset == 0xFFFF)) 602 break; 603 ret_val = hw->eeprom.ops.read(hw, data_offset, 604 &block_crc); 605 data_offset++; 606 while (!end_data) { 607 /* 608 * Read control word from PHY init contents 609 * offset 610 */ 611 ret_val = hw->eeprom.ops.read(hw, data_offset, 612 &eword); 613 control = (eword & IXGBE_CONTROL_MASK_NL) >> 614 IXGBE_CONTROL_SHIFT_NL; 615 edata = eword & IXGBE_DATA_MASK_NL; 616 switch (control) { 617 case IXGBE_DELAY_NL: 618 data_offset++; 619 DEBUGOUT1("DELAY: %d MS\n", edata); 620 msec_delay(edata); 621 break; 622 case IXGBE_DATA_NL: 623 DEBUGOUT("DATA: \n"); 624 data_offset++; 625 hw->eeprom.ops.read(hw, data_offset++, 626 &phy_offset); 627 for (i = 0; i < edata; i++) { 628 hw->eeprom.ops.read(hw, 629 data_offset, 630 &eword); 631 hw->phy.ops.write_reg(hw, 632 phy_offset, 633 IXGBE_TWINAX_DEV, 634 eword); 635 DEBUGOUT2("Wrote %4.4x to %4.4x\n", 636 eword, phy_offset); 637 data_offset++; 638 phy_offset++; 639 } 640 break; 641 case IXGBE_CONTROL_NL: 642 data_offset++; 643 DEBUGOUT("CONTROL: \n"); 644 if (edata == IXGBE_CONTROL_EOL_NL) { 645 DEBUGOUT("EOL\n"); 646 end_data = TRUE; 647 } else if (edata == IXGBE_CONTROL_SOL_NL) { 648 DEBUGOUT("SOL\n"); 649 } else { 650 DEBUGOUT("Bad control value\n"); 651 ret_val = IXGBE_ERR_PHY; 652 goto out; 653 } 654 break; 655 default: 656 DEBUGOUT("Bad control type\n"); 657 ret_val = IXGBE_ERR_PHY; 658 goto out; 659 } 660 } 661 } else { 662 list_offset += 2; 663 ret_val = hw->eeprom.ops.read(hw, list_offset, &id); 664 if (ret_val) 665 goto out; 666 } 667 } 668 669 out: 670 return ret_val; 671 } 672