1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53 /** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61 { 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68 } 69 70 /** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78 { 79 s32 status; 80 81 status = ixgbe_clock_in_i2c_byte(hw, byte); 82 if (status) 83 return status; 84 /* ACK */ 85 return ixgbe_clock_out_i2c_bit(hw, FALSE); 86 } 87 88 /** 89 * ixgbe_ones_comp_byte_add - Perform one's complement addition 90 * @add1 - addend 1 91 * @add2 - addend 2 92 * 93 * Returns one's complement 8-bit sum. 94 */ 95 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 96 { 97 u16 sum = add1 + add2; 98 99 sum = (sum & 0xFF) + (sum >> 8); 100 return sum & 0xFF; 101 } 102 103 /** 104 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 105 * @hw: pointer to the hardware structure 106 * @addr: I2C bus address to read from 107 * @reg: I2C device register to read from 108 * @val: pointer to location to receive read value 109 * @lock: TRUE if to take and release semaphore 110 * 111 * Returns an error code on error. 112 */ 113 static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 114 u16 reg, u16 *val, bool lock) 115 { 116 u32 swfw_mask = hw->phy.phy_semaphore_mask; 117 int max_retry = 10; 118 int retry = 0; 119 u8 csum_byte; 120 u8 high_bits; 121 u8 low_bits; 122 u8 reg_high; 123 u8 csum; 124 125 if (hw->mac.type >= ixgbe_mac_X550) 126 max_retry = 3; 127 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 128 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 129 csum = ~csum; 130 do { 131 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 132 return IXGBE_ERR_SWFW_SYNC; 133 ixgbe_i2c_start(hw); 134 /* Device Address and write indication */ 135 if (ixgbe_out_i2c_byte_ack(hw, addr)) 136 goto fail; 137 /* Write bits 14:8 */ 138 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 139 goto fail; 140 /* Write bits 7:0 */ 141 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 142 goto fail; 143 /* Write csum */ 144 if (ixgbe_out_i2c_byte_ack(hw, csum)) 145 goto fail; 146 /* Re-start condition */ 147 ixgbe_i2c_start(hw); 148 /* Device Address and read indication */ 149 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 150 goto fail; 151 /* Get upper bits */ 152 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 153 goto fail; 154 /* Get low bits */ 155 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 156 goto fail; 157 /* Get csum */ 158 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 159 goto fail; 160 /* NACK */ 161 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 162 goto fail; 163 ixgbe_i2c_stop(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 *val = (high_bits << 8) | low_bits; 167 return 0; 168 169 fail: 170 ixgbe_i2c_bus_clear(hw); 171 if (lock) 172 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 173 retry++; 174 if (retry < max_retry) 175 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 176 else 177 DEBUGOUT("I2C byte read combined error.\n"); 178 } while (retry < max_retry); 179 180 return IXGBE_ERR_I2C; 181 } 182 183 /** 184 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 185 * @hw: pointer to the hardware structure 186 * @addr: I2C bus address to read from 187 * @reg: I2C device register to read from 188 * @val: pointer to location to receive read value 189 * 190 * Returns an error code on error. 191 **/ 192 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 193 u16 reg, u16 *val) 194 { 195 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 196 } 197 198 /** 199 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 200 * @hw: pointer to the hardware structure 201 * @addr: I2C bus address to read from 202 * @reg: I2C device register to read from 203 * @val: pointer to location to receive read value 204 * 205 * Returns an error code on error. 206 **/ 207 static s32 208 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 209 u16 reg, u16 *val) 210 { 211 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 212 } 213 214 /** 215 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 216 * @hw: pointer to the hardware structure 217 * @addr: I2C bus address to write to 218 * @reg: I2C device register to write to 219 * @val: value to write 220 * @lock: TRUE if to take and release semaphore 221 * 222 * Returns an error code on error. 223 */ 224 static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 225 u16 reg, u16 val, bool lock) 226 { 227 u32 swfw_mask = hw->phy.phy_semaphore_mask; 228 int max_retry = 1; 229 int retry = 0; 230 u8 reg_high; 231 u8 csum; 232 233 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 234 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 235 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 236 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 237 csum = ~csum; 238 do { 239 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 240 return IXGBE_ERR_SWFW_SYNC; 241 ixgbe_i2c_start(hw); 242 /* Device Address and write indication */ 243 if (ixgbe_out_i2c_byte_ack(hw, addr)) 244 goto fail; 245 /* Write bits 14:8 */ 246 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 247 goto fail; 248 /* Write bits 7:0 */ 249 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 250 goto fail; 251 /* Write data 15:8 */ 252 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 253 goto fail; 254 /* Write data 7:0 */ 255 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 256 goto fail; 257 /* Write csum */ 258 if (ixgbe_out_i2c_byte_ack(hw, csum)) 259 goto fail; 260 ixgbe_i2c_stop(hw); 261 if (lock) 262 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 263 return 0; 264 265 fail: 266 ixgbe_i2c_bus_clear(hw); 267 if (lock) 268 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 269 retry++; 270 if (retry < max_retry) 271 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 272 else 273 DEBUGOUT("I2C byte write combined error.\n"); 274 } while (retry < max_retry); 275 276 return IXGBE_ERR_I2C; 277 } 278 279 /** 280 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 281 * @hw: pointer to the hardware structure 282 * @addr: I2C bus address to write to 283 * @reg: I2C device register to write to 284 * @val: value to write 285 * 286 * Returns an error code on error. 287 **/ 288 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 289 u8 addr, u16 reg, u16 val) 290 { 291 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 292 } 293 294 /** 295 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 296 * @hw: pointer to the hardware structure 297 * @addr: I2C bus address to write to 298 * @reg: I2C device register to write to 299 * @val: value to write 300 * 301 * Returns an error code on error. 302 **/ 303 static s32 304 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 305 u8 addr, u16 reg, u16 val) 306 { 307 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 308 } 309 310 /** 311 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 312 * @hw: pointer to the hardware structure 313 * 314 * Initialize the function pointers. 315 **/ 316 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 317 { 318 struct ixgbe_phy_info *phy = &hw->phy; 319 320 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 321 322 /* PHY */ 323 phy->ops.identify = ixgbe_identify_phy_generic; 324 phy->ops.reset = ixgbe_reset_phy_generic; 325 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 326 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 327 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 328 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 329 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 330 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 331 phy->ops.check_link = NULL; 332 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 333 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 334 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 335 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 336 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 337 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 338 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 339 phy->ops.identify_sfp = ixgbe_identify_module_generic; 340 phy->sfp_type = ixgbe_sfp_type_unknown; 341 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 342 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 343 phy->ops.read_i2c_combined_unlocked = 344 ixgbe_read_i2c_combined_generic_unlocked; 345 phy->ops.write_i2c_combined_unlocked = 346 ixgbe_write_i2c_combined_generic_unlocked; 347 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 348 phy->ops.write_i2c_byte_unlocked = 349 ixgbe_write_i2c_byte_generic_unlocked; 350 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 351 return IXGBE_SUCCESS; 352 } 353 354 /** 355 * ixgbe_identify_phy_generic - Get physical layer module 356 * @hw: pointer to hardware structure 357 * 358 * Determines the physical layer module found on the current adapter. 359 **/ 360 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 361 { 362 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 363 u32 phy_addr; 364 u16 ext_ability = 0; 365 366 DEBUGFUNC("ixgbe_identify_phy_generic"); 367 368 if (!hw->phy.phy_semaphore_mask) { 369 if (hw->bus.lan_id) 370 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 371 else 372 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 373 } 374 375 if (hw->phy.type == ixgbe_phy_unknown) { 376 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 377 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 378 hw->phy.addr = phy_addr; 379 ixgbe_get_phy_id(hw); 380 hw->phy.type = 381 ixgbe_get_phy_type_from_id(hw->phy.id); 382 383 if (hw->phy.type == ixgbe_phy_unknown) { 384 hw->phy.ops.read_reg(hw, 385 IXGBE_MDIO_PHY_EXT_ABILITY, 386 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 387 &ext_ability); 388 if (ext_ability & 389 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 390 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 391 hw->phy.type = 392 ixgbe_phy_cu_unknown; 393 else 394 hw->phy.type = 395 ixgbe_phy_generic; 396 } 397 398 status = IXGBE_SUCCESS; 399 break; 400 } 401 } 402 403 /* Certain media types do not have a phy so an address will not 404 * be found and the code will take this path. Caller has to 405 * decide if it is an error or not. 406 */ 407 if (status != IXGBE_SUCCESS) { 408 hw->phy.addr = 0; 409 } 410 } else { 411 status = IXGBE_SUCCESS; 412 } 413 414 return status; 415 } 416 417 /** 418 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 419 * @hw: pointer to the hardware structure 420 * 421 * This function checks the MMNGC.MNG_VETO bit to see if there are 422 * any constraints on link from manageability. For MAC's that don't 423 * have this bit just return faluse since the link can not be blocked 424 * via this method. 425 **/ 426 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 427 { 428 u32 mmngc; 429 430 DEBUGFUNC("ixgbe_check_reset_blocked"); 431 432 /* If we don't have this bit, it can't be blocking */ 433 if (hw->mac.type == ixgbe_mac_82598EB) 434 return FALSE; 435 436 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 437 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 438 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 439 "MNG_VETO bit detected.\n"); 440 return TRUE; 441 } 442 443 return FALSE; 444 } 445 446 /** 447 * ixgbe_validate_phy_addr - Determines phy address is valid 448 * @hw: pointer to hardware structure 449 * 450 **/ 451 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 452 { 453 u16 phy_id = 0; 454 bool valid = FALSE; 455 456 DEBUGFUNC("ixgbe_validate_phy_addr"); 457 458 hw->phy.addr = phy_addr; 459 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 460 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 461 462 if (phy_id != 0xFFFF && phy_id != 0x0) 463 valid = TRUE; 464 465 return valid; 466 } 467 468 /** 469 * ixgbe_get_phy_id - Get the phy type 470 * @hw: pointer to hardware structure 471 * 472 **/ 473 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 474 { 475 u32 status; 476 u16 phy_id_high = 0; 477 u16 phy_id_low = 0; 478 479 DEBUGFUNC("ixgbe_get_phy_id"); 480 481 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 482 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 483 &phy_id_high); 484 485 if (status == IXGBE_SUCCESS) { 486 hw->phy.id = (u32)(phy_id_high << 16); 487 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 488 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 489 &phy_id_low); 490 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 491 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 492 } 493 return status; 494 } 495 496 /** 497 * ixgbe_get_phy_type_from_id - Get the phy type 498 * @hw: pointer to hardware structure 499 * 500 **/ 501 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 502 { 503 enum ixgbe_phy_type phy_type; 504 505 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 506 507 switch (phy_id) { 508 case TN1010_PHY_ID: 509 phy_type = ixgbe_phy_tn; 510 break; 511 case X550_PHY_ID1: 512 case X550_PHY_ID2: 513 case X550_PHY_ID3: 514 case X540_PHY_ID: 515 phy_type = ixgbe_phy_aq; 516 break; 517 case QT2022_PHY_ID: 518 phy_type = ixgbe_phy_qt; 519 break; 520 case ATH_PHY_ID: 521 phy_type = ixgbe_phy_nl; 522 break; 523 case X557_PHY_ID: 524 phy_type = ixgbe_phy_x550em_ext_t; 525 break; 526 default: 527 phy_type = ixgbe_phy_unknown; 528 break; 529 } 530 531 DEBUGOUT1("phy type found is %d\n", phy_type); 532 return phy_type; 533 } 534 535 /** 536 * ixgbe_reset_phy_generic - Performs a PHY reset 537 * @hw: pointer to hardware structure 538 **/ 539 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 540 { 541 u32 i; 542 u16 ctrl = 0; 543 s32 status = IXGBE_SUCCESS; 544 545 DEBUGFUNC("ixgbe_reset_phy_generic"); 546 547 if (hw->phy.type == ixgbe_phy_unknown) 548 status = ixgbe_identify_phy_generic(hw); 549 550 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 551 goto out; 552 553 /* Don't reset PHY if it's shut down due to overtemp. */ 554 if (!hw->phy.reset_if_overtemp && 555 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 556 goto out; 557 558 /* Blocked by MNG FW so bail */ 559 if (ixgbe_check_reset_blocked(hw)) 560 goto out; 561 562 /* 563 * Perform soft PHY reset to the PHY_XS. 564 * This will cause a soft reset to the PHY 565 */ 566 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 567 IXGBE_MDIO_PHY_XS_DEV_TYPE, 568 IXGBE_MDIO_PHY_XS_RESET); 569 570 /* 571 * Poll for reset bit to self-clear indicating reset is complete. 572 * Some PHYs could take up to 3 seconds to complete and need about 573 * 1.7 usec delay after the reset is complete. 574 */ 575 for (i = 0; i < 30; i++) { 576 msec_delay(100); 577 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 578 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 579 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 580 usec_delay(2); 581 break; 582 } 583 } 584 585 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 586 status = IXGBE_ERR_RESET_FAILED; 587 ERROR_REPORT1(IXGBE_ERROR_POLLING, 588 "PHY reset polling failed to complete.\n"); 589 } 590 591 out: 592 return status; 593 } 594 595 /** 596 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 597 * the SWFW lock 598 * @hw: pointer to hardware structure 599 * @reg_addr: 32 bit address of PHY register to read 600 * @phy_data: Pointer to read data from PHY register 601 **/ 602 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 603 u16 *phy_data) 604 { 605 u32 i, data, command; 606 607 /* Setup and write the address cycle command */ 608 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 609 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 610 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 611 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 612 613 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 614 615 /* 616 * Check every 10 usec to see if the address cycle completed. 617 * The MDI Command bit will clear when the operation is 618 * complete 619 */ 620 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 621 usec_delay(10); 622 623 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 624 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 625 break; 626 } 627 628 629 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 630 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 631 return IXGBE_ERR_PHY; 632 } 633 634 /* 635 * Address cycle complete, setup and write the read 636 * command 637 */ 638 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 639 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 640 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 641 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 642 643 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 644 645 /* 646 * Check every 10 usec to see if the address cycle 647 * completed. The MDI Command bit will clear when the 648 * operation is complete 649 */ 650 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 651 usec_delay(10); 652 653 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 654 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 655 break; 656 } 657 658 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 659 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 660 return IXGBE_ERR_PHY; 661 } 662 663 /* 664 * Read operation is complete. Get the data 665 * from MSRWD 666 */ 667 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 668 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 669 *phy_data = (u16)(data); 670 671 return IXGBE_SUCCESS; 672 } 673 674 /** 675 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 676 * using the SWFW lock - this function is needed in most cases 677 * @hw: pointer to hardware structure 678 * @reg_addr: 32 bit address of PHY register to read 679 * @phy_data: Pointer to read data from PHY register 680 **/ 681 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 682 u32 device_type, u16 *phy_data) 683 { 684 s32 status; 685 u32 gssr = hw->phy.phy_semaphore_mask; 686 687 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 688 689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 690 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 691 phy_data); 692 hw->mac.ops.release_swfw_sync(hw, gssr); 693 } else { 694 status = IXGBE_ERR_SWFW_SYNC; 695 } 696 697 return status; 698 } 699 700 /** 701 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 702 * without SWFW lock 703 * @hw: pointer to hardware structure 704 * @reg_addr: 32 bit PHY register to write 705 * @device_type: 5 bit device type 706 * @phy_data: Data to write to the PHY register 707 **/ 708 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 709 u32 device_type, u16 phy_data) 710 { 711 u32 i, command; 712 713 /* Put the data in the MDI single read and write data register*/ 714 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 715 716 /* Setup and write the address cycle command */ 717 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 718 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 719 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 720 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 721 722 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 723 724 /* 725 * Check every 10 usec to see if the address cycle completed. 726 * The MDI Command bit will clear when the operation is 727 * complete 728 */ 729 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 730 usec_delay(10); 731 732 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 733 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 734 break; 735 } 736 737 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 738 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 739 return IXGBE_ERR_PHY; 740 } 741 742 /* 743 * Address cycle complete, setup and write the write 744 * command 745 */ 746 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 747 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 748 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 749 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 750 751 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 752 753 /* 754 * Check every 10 usec to see if the address cycle 755 * completed. The MDI Command bit will clear when the 756 * operation is complete 757 */ 758 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 759 usec_delay(10); 760 761 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 762 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 763 break; 764 } 765 766 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 767 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 768 return IXGBE_ERR_PHY; 769 } 770 771 return IXGBE_SUCCESS; 772 } 773 774 /** 775 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 776 * using SWFW lock- this function is needed in most cases 777 * @hw: pointer to hardware structure 778 * @reg_addr: 32 bit PHY register to write 779 * @device_type: 5 bit device type 780 * @phy_data: Data to write to the PHY register 781 **/ 782 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 783 u32 device_type, u16 phy_data) 784 { 785 s32 status; 786 u32 gssr = hw->phy.phy_semaphore_mask; 787 788 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 789 790 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 791 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 792 phy_data); 793 hw->mac.ops.release_swfw_sync(hw, gssr); 794 } else { 795 status = IXGBE_ERR_SWFW_SYNC; 796 } 797 798 return status; 799 } 800 801 /** 802 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 803 * @hw: pointer to hardware structure 804 * 805 * Restart auto-negotiation and PHY and waits for completion. 806 **/ 807 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 808 { 809 s32 status = IXGBE_SUCCESS; 810 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 811 bool autoneg = FALSE; 812 ixgbe_link_speed speed; 813 814 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 815 816 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 817 818 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 819 /* Set or unset auto-negotiation 10G advertisement */ 820 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 821 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 822 &autoneg_reg); 823 824 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 825 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 826 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 827 828 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 829 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 830 autoneg_reg); 831 } 832 833 if (hw->mac.type == ixgbe_mac_X550) { 834 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 835 /* Set or unset auto-negotiation 5G advertisement */ 836 hw->phy.ops.read_reg(hw, 837 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 838 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 839 &autoneg_reg); 840 841 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 842 if (hw->phy.autoneg_advertised & 843 IXGBE_LINK_SPEED_5GB_FULL) 844 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 845 846 hw->phy.ops.write_reg(hw, 847 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 848 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 849 autoneg_reg); 850 } 851 852 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 853 /* Set or unset auto-negotiation 2.5G advertisement */ 854 hw->phy.ops.read_reg(hw, 855 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 856 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 857 &autoneg_reg); 858 859 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 860 if (hw->phy.autoneg_advertised & 861 IXGBE_LINK_SPEED_2_5GB_FULL) 862 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 863 864 hw->phy.ops.write_reg(hw, 865 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 866 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 867 autoneg_reg); 868 } 869 } 870 871 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 872 /* Set or unset auto-negotiation 1G advertisement */ 873 hw->phy.ops.read_reg(hw, 874 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 875 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 876 &autoneg_reg); 877 878 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 879 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 880 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 881 882 hw->phy.ops.write_reg(hw, 883 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 884 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 885 autoneg_reg); 886 } 887 888 if (speed & IXGBE_LINK_SPEED_100_FULL) { 889 /* Set or unset auto-negotiation 100M advertisement */ 890 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 892 &autoneg_reg); 893 894 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 895 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 896 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 897 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 898 899 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 900 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 901 autoneg_reg); 902 } 903 904 /* Blocked by MNG FW so don't reset PHY */ 905 if (ixgbe_check_reset_blocked(hw)) 906 return status; 907 908 /* Restart PHY auto-negotiation. */ 909 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 910 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 911 912 autoneg_reg |= IXGBE_MII_RESTART; 913 914 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 915 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 916 917 return status; 918 } 919 920 /** 921 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 922 * @hw: pointer to hardware structure 923 * @speed: new link speed 924 **/ 925 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 926 ixgbe_link_speed speed, 927 bool autoneg_wait_to_complete) 928 { 929 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 930 931 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 932 933 /* 934 * Clear autoneg_advertised and set new values based on input link 935 * speed. 936 */ 937 hw->phy.autoneg_advertised = 0; 938 939 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 940 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 941 942 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 943 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 944 945 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 946 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 947 948 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 949 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 950 951 if (speed & IXGBE_LINK_SPEED_100_FULL) 952 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 953 954 /* Setup link based on the new speed settings */ 955 ixgbe_setup_phy_link(hw); 956 957 return IXGBE_SUCCESS; 958 } 959 960 /** 961 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 962 * @hw: pointer to hardware structure 963 * 964 * Determines the supported link capabilities by reading the PHY auto 965 * negotiation register. 966 **/ 967 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 968 { 969 s32 status; 970 u16 speed_ability; 971 972 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 973 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 974 &speed_ability); 975 if (status) 976 return status; 977 978 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 979 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 980 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 981 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 982 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 983 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 984 985 switch (hw->mac.type) { 986 case ixgbe_mac_X550: 987 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 988 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 989 break; 990 case ixgbe_mac_X550EM_x: 991 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 992 break; 993 default: 994 break; 995 } 996 997 return status; 998 } 999 1000 /** 1001 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 1002 * @hw: pointer to hardware structure 1003 * @speed: pointer to link speed 1004 * @autoneg: boolean auto-negotiation value 1005 **/ 1006 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 1007 ixgbe_link_speed *speed, 1008 bool *autoneg) 1009 { 1010 s32 status = IXGBE_SUCCESS; 1011 1012 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 1013 1014 *autoneg = TRUE; 1015 if (!hw->phy.speeds_supported) 1016 status = ixgbe_get_copper_speeds_supported(hw); 1017 1018 *speed = hw->phy.speeds_supported; 1019 return status; 1020 } 1021 1022 /** 1023 * ixgbe_check_phy_link_tnx - Determine link and speed status 1024 * @hw: pointer to hardware structure 1025 * 1026 * Reads the VS1 register to determine if link is up and the current speed for 1027 * the PHY. 1028 **/ 1029 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1030 bool *link_up) 1031 { 1032 s32 status = IXGBE_SUCCESS; 1033 u32 time_out; 1034 u32 max_time_out = 10; 1035 u16 phy_link = 0; 1036 u16 phy_speed = 0; 1037 u16 phy_data = 0; 1038 1039 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1040 1041 /* Initialize speed and link to default case */ 1042 *link_up = FALSE; 1043 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1044 1045 /* 1046 * Check current speed and link status of the PHY register. 1047 * This is a vendor specific register and may have to 1048 * be changed for other copper PHYs. 1049 */ 1050 for (time_out = 0; time_out < max_time_out; time_out++) { 1051 usec_delay(10); 1052 status = hw->phy.ops.read_reg(hw, 1053 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1054 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1055 &phy_data); 1056 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1057 phy_speed = phy_data & 1058 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1059 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1060 *link_up = TRUE; 1061 if (phy_speed == 1062 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1063 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1064 break; 1065 } 1066 } 1067 1068 return status; 1069 } 1070 1071 /** 1072 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1073 * @hw: pointer to hardware structure 1074 * 1075 * Restart auto-negotiation and PHY and waits for completion. 1076 **/ 1077 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1078 { 1079 s32 status = IXGBE_SUCCESS; 1080 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1081 bool autoneg = FALSE; 1082 ixgbe_link_speed speed; 1083 1084 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1085 1086 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1087 1088 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1089 /* Set or unset auto-negotiation 10G advertisement */ 1090 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1091 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1092 &autoneg_reg); 1093 1094 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1095 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1096 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1097 1098 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1100 autoneg_reg); 1101 } 1102 1103 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1104 /* Set or unset auto-negotiation 1G advertisement */ 1105 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1106 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1107 &autoneg_reg); 1108 1109 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1110 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1111 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1112 1113 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1114 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1115 autoneg_reg); 1116 } 1117 1118 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1119 /* Set or unset auto-negotiation 100M advertisement */ 1120 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1121 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1122 &autoneg_reg); 1123 1124 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1125 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1126 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1127 1128 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1129 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1130 autoneg_reg); 1131 } 1132 1133 /* Blocked by MNG FW so don't reset PHY */ 1134 if (ixgbe_check_reset_blocked(hw)) 1135 return status; 1136 1137 /* Restart PHY auto-negotiation. */ 1138 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1139 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1140 1141 autoneg_reg |= IXGBE_MII_RESTART; 1142 1143 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1144 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1145 1146 return status; 1147 } 1148 1149 /** 1150 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1151 * @hw: pointer to hardware structure 1152 * @firmware_version: pointer to the PHY Firmware Version 1153 **/ 1154 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1155 u16 *firmware_version) 1156 { 1157 s32 status; 1158 1159 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1160 1161 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1163 firmware_version); 1164 1165 return status; 1166 } 1167 1168 /** 1169 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1170 * @hw: pointer to hardware structure 1171 * @firmware_version: pointer to the PHY Firmware Version 1172 **/ 1173 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1174 u16 *firmware_version) 1175 { 1176 s32 status; 1177 1178 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1179 1180 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1181 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1182 firmware_version); 1183 1184 return status; 1185 } 1186 1187 /** 1188 * ixgbe_reset_phy_nl - Performs a PHY reset 1189 * @hw: pointer to hardware structure 1190 **/ 1191 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1192 { 1193 u16 phy_offset, control, eword, edata, block_crc; 1194 bool end_data = FALSE; 1195 u16 list_offset, data_offset; 1196 u16 phy_data = 0; 1197 s32 ret_val = IXGBE_SUCCESS; 1198 u32 i; 1199 1200 DEBUGFUNC("ixgbe_reset_phy_nl"); 1201 1202 /* Blocked by MNG FW so bail */ 1203 if (ixgbe_check_reset_blocked(hw)) 1204 goto out; 1205 1206 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1207 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1208 1209 /* reset the PHY and poll for completion */ 1210 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1211 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1212 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1213 1214 for (i = 0; i < 100; i++) { 1215 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1216 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1217 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1218 break; 1219 msec_delay(10); 1220 } 1221 1222 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1223 DEBUGOUT("PHY reset did not complete.\n"); 1224 ret_val = IXGBE_ERR_PHY; 1225 goto out; 1226 } 1227 1228 /* Get init offsets */ 1229 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1230 &data_offset); 1231 if (ret_val != IXGBE_SUCCESS) 1232 goto out; 1233 1234 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1235 data_offset++; 1236 while (!end_data) { 1237 /* 1238 * Read control word from PHY init contents offset 1239 */ 1240 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1241 if (ret_val) 1242 goto err_eeprom; 1243 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1244 IXGBE_CONTROL_SHIFT_NL; 1245 edata = eword & IXGBE_DATA_MASK_NL; 1246 switch (control) { 1247 case IXGBE_DELAY_NL: 1248 data_offset++; 1249 DEBUGOUT1("DELAY: %d MS\n", edata); 1250 msec_delay(edata); 1251 break; 1252 case IXGBE_DATA_NL: 1253 DEBUGOUT("DATA:\n"); 1254 data_offset++; 1255 ret_val = hw->eeprom.ops.read(hw, data_offset, 1256 &phy_offset); 1257 if (ret_val) 1258 goto err_eeprom; 1259 data_offset++; 1260 for (i = 0; i < edata; i++) { 1261 ret_val = hw->eeprom.ops.read(hw, data_offset, 1262 &eword); 1263 if (ret_val) 1264 goto err_eeprom; 1265 hw->phy.ops.write_reg(hw, phy_offset, 1266 IXGBE_TWINAX_DEV, eword); 1267 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1268 phy_offset); 1269 data_offset++; 1270 phy_offset++; 1271 } 1272 break; 1273 case IXGBE_CONTROL_NL: 1274 data_offset++; 1275 DEBUGOUT("CONTROL:\n"); 1276 if (edata == IXGBE_CONTROL_EOL_NL) { 1277 DEBUGOUT("EOL\n"); 1278 end_data = TRUE; 1279 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1280 DEBUGOUT("SOL\n"); 1281 } else { 1282 DEBUGOUT("Bad control value\n"); 1283 ret_val = IXGBE_ERR_PHY; 1284 goto out; 1285 } 1286 break; 1287 default: 1288 DEBUGOUT("Bad control type\n"); 1289 ret_val = IXGBE_ERR_PHY; 1290 goto out; 1291 } 1292 } 1293 1294 out: 1295 return ret_val; 1296 1297 err_eeprom: 1298 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1299 "eeprom read at offset %d failed", data_offset); 1300 return IXGBE_ERR_PHY; 1301 } 1302 1303 /** 1304 * ixgbe_identify_module_generic - Identifies module type 1305 * @hw: pointer to hardware structure 1306 * 1307 * Determines HW type and calls appropriate function. 1308 **/ 1309 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1310 { 1311 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1312 1313 DEBUGFUNC("ixgbe_identify_module_generic"); 1314 1315 switch (hw->mac.ops.get_media_type(hw)) { 1316 case ixgbe_media_type_fiber: 1317 status = ixgbe_identify_sfp_module_generic(hw); 1318 break; 1319 1320 case ixgbe_media_type_fiber_qsfp: 1321 status = ixgbe_identify_qsfp_module_generic(hw); 1322 break; 1323 1324 default: 1325 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1326 status = IXGBE_ERR_SFP_NOT_PRESENT; 1327 break; 1328 } 1329 1330 return status; 1331 } 1332 1333 /** 1334 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1335 * @hw: pointer to hardware structure 1336 * 1337 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1338 **/ 1339 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1340 { 1341 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1342 u32 vendor_oui = 0; 1343 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1344 u8 identifier = 0; 1345 u8 comp_codes_1g = 0; 1346 u8 comp_codes_10g = 0; 1347 u8 oui_bytes[3] = {0, 0, 0}; 1348 u8 cable_tech = 0; 1349 u8 cable_spec = 0; 1350 u16 enforce_sfp = 0; 1351 1352 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1353 1354 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1355 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1356 status = IXGBE_ERR_SFP_NOT_PRESENT; 1357 goto out; 1358 } 1359 1360 /* LAN ID is needed for I2C access */ 1361 hw->mac.ops.set_lan_id(hw); 1362 1363 status = hw->phy.ops.read_i2c_eeprom(hw, 1364 IXGBE_SFF_IDENTIFIER, 1365 &identifier); 1366 1367 if (status != IXGBE_SUCCESS) 1368 goto err_read_i2c_eeprom; 1369 1370 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1371 hw->phy.type = ixgbe_phy_sfp_unsupported; 1372 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1373 } else { 1374 status = hw->phy.ops.read_i2c_eeprom(hw, 1375 IXGBE_SFF_1GBE_COMP_CODES, 1376 &comp_codes_1g); 1377 1378 if (status != IXGBE_SUCCESS) 1379 goto err_read_i2c_eeprom; 1380 1381 status = hw->phy.ops.read_i2c_eeprom(hw, 1382 IXGBE_SFF_10GBE_COMP_CODES, 1383 &comp_codes_10g); 1384 1385 if (status != IXGBE_SUCCESS) 1386 goto err_read_i2c_eeprom; 1387 status = hw->phy.ops.read_i2c_eeprom(hw, 1388 IXGBE_SFF_CABLE_TECHNOLOGY, 1389 &cable_tech); 1390 1391 if (status != IXGBE_SUCCESS) 1392 goto err_read_i2c_eeprom; 1393 1394 /* ID Module 1395 * ========= 1396 * 0 SFP_DA_CU 1397 * 1 SFP_SR 1398 * 2 SFP_LR 1399 * 3 SFP_DA_CORE0 - 82599-specific 1400 * 4 SFP_DA_CORE1 - 82599-specific 1401 * 5 SFP_SR/LR_CORE0 - 82599-specific 1402 * 6 SFP_SR/LR_CORE1 - 82599-specific 1403 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1404 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1405 * 9 SFP_1g_cu_CORE0 - 82599-specific 1406 * 10 SFP_1g_cu_CORE1 - 82599-specific 1407 * 11 SFP_1g_sx_CORE0 - 82599-specific 1408 * 12 SFP_1g_sx_CORE1 - 82599-specific 1409 */ 1410 if (hw->mac.type == ixgbe_mac_82598EB) { 1411 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1412 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1413 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1414 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1415 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1416 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1417 else 1418 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1419 } else { 1420 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1421 if (hw->bus.lan_id == 0) 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_da_cu_core0; 1424 else 1425 hw->phy.sfp_type = 1426 ixgbe_sfp_type_da_cu_core1; 1427 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1428 hw->phy.ops.read_i2c_eeprom( 1429 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1430 &cable_spec); 1431 if (cable_spec & 1432 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1433 if (hw->bus.lan_id == 0) 1434 hw->phy.sfp_type = 1435 ixgbe_sfp_type_da_act_lmt_core0; 1436 else 1437 hw->phy.sfp_type = 1438 ixgbe_sfp_type_da_act_lmt_core1; 1439 } else { 1440 hw->phy.sfp_type = 1441 ixgbe_sfp_type_unknown; 1442 } 1443 } else if (comp_codes_10g & 1444 (IXGBE_SFF_10GBASESR_CAPABLE | 1445 IXGBE_SFF_10GBASELR_CAPABLE)) { 1446 if (hw->bus.lan_id == 0) 1447 hw->phy.sfp_type = 1448 ixgbe_sfp_type_srlr_core0; 1449 else 1450 hw->phy.sfp_type = 1451 ixgbe_sfp_type_srlr_core1; 1452 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1453 if (hw->bus.lan_id == 0) 1454 hw->phy.sfp_type = 1455 ixgbe_sfp_type_1g_cu_core0; 1456 else 1457 hw->phy.sfp_type = 1458 ixgbe_sfp_type_1g_cu_core1; 1459 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1460 if (hw->bus.lan_id == 0) 1461 hw->phy.sfp_type = 1462 ixgbe_sfp_type_1g_sx_core0; 1463 else 1464 hw->phy.sfp_type = 1465 ixgbe_sfp_type_1g_sx_core1; 1466 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1467 if (hw->bus.lan_id == 0) 1468 hw->phy.sfp_type = 1469 ixgbe_sfp_type_1g_lx_core0; 1470 else 1471 hw->phy.sfp_type = 1472 ixgbe_sfp_type_1g_lx_core1; 1473 } else { 1474 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1475 } 1476 } 1477 1478 if (hw->phy.sfp_type != stored_sfp_type) 1479 hw->phy.sfp_setup_needed = TRUE; 1480 1481 /* Determine if the SFP+ PHY is dual speed or not. */ 1482 hw->phy.multispeed_fiber = FALSE; 1483 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1484 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1485 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1486 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1487 hw->phy.multispeed_fiber = TRUE; 1488 1489 /* Determine PHY vendor */ 1490 if (hw->phy.type != ixgbe_phy_nl) { 1491 hw->phy.id = identifier; 1492 status = hw->phy.ops.read_i2c_eeprom(hw, 1493 IXGBE_SFF_VENDOR_OUI_BYTE0, 1494 &oui_bytes[0]); 1495 1496 if (status != IXGBE_SUCCESS) 1497 goto err_read_i2c_eeprom; 1498 1499 status = hw->phy.ops.read_i2c_eeprom(hw, 1500 IXGBE_SFF_VENDOR_OUI_BYTE1, 1501 &oui_bytes[1]); 1502 1503 if (status != IXGBE_SUCCESS) 1504 goto err_read_i2c_eeprom; 1505 1506 status = hw->phy.ops.read_i2c_eeprom(hw, 1507 IXGBE_SFF_VENDOR_OUI_BYTE2, 1508 &oui_bytes[2]); 1509 1510 if (status != IXGBE_SUCCESS) 1511 goto err_read_i2c_eeprom; 1512 1513 vendor_oui = 1514 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1515 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1516 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1517 1518 switch (vendor_oui) { 1519 case IXGBE_SFF_VENDOR_OUI_TYCO: 1520 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1521 hw->phy.type = 1522 ixgbe_phy_sfp_passive_tyco; 1523 break; 1524 case IXGBE_SFF_VENDOR_OUI_FTL: 1525 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1526 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1527 else 1528 hw->phy.type = ixgbe_phy_sfp_ftl; 1529 break; 1530 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1531 hw->phy.type = ixgbe_phy_sfp_avago; 1532 break; 1533 case IXGBE_SFF_VENDOR_OUI_INTEL: 1534 hw->phy.type = ixgbe_phy_sfp_intel; 1535 break; 1536 default: 1537 hw->phy.type = ixgbe_phy_sfp_unknown; 1538 break; 1539 } 1540 } 1541 1542 /* Allow any DA cable vendor */ 1543 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1544 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1545 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1546 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1547 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1548 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1549 status = IXGBE_SUCCESS; 1550 goto out; 1551 } 1552 1553 /* Verify supported 1G SFP modules */ 1554 if (comp_codes_10g == 0 && 1555 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1556 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1557 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1558 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1561 hw->phy.type = ixgbe_phy_sfp_unsupported; 1562 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1563 goto out; 1564 } 1565 1566 /* Anything else 82598-based is supported */ 1567 if (hw->mac.type == ixgbe_mac_82598EB) { 1568 status = IXGBE_SUCCESS; 1569 goto out; 1570 } 1571 1572 ixgbe_get_device_caps(hw, &enforce_sfp); 1573 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1574 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1575 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1576 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1577 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1578 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1579 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1580 /* Make sure we're a supported PHY type */ 1581 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1582 status = IXGBE_SUCCESS; 1583 } else { 1584 if (hw->allow_unsupported_sfp == TRUE) { 1585 EWARN(hw, "WARNING: Intel (R) Network " 1586 "Connections are quality tested " 1587 "using Intel (R) Ethernet Optics." 1588 " Using untested modules is not " 1589 "supported and may cause unstable" 1590 " operation or damage to the " 1591 "module or the adapter. Intel " 1592 "Corporation is not responsible " 1593 "for any harm caused by using " 1594 "untested modules.\n", status); 1595 status = IXGBE_SUCCESS; 1596 } else { 1597 DEBUGOUT("SFP+ module not supported\n"); 1598 hw->phy.type = 1599 ixgbe_phy_sfp_unsupported; 1600 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1601 } 1602 } 1603 } else { 1604 status = IXGBE_SUCCESS; 1605 } 1606 } 1607 1608 out: 1609 return status; 1610 1611 err_read_i2c_eeprom: 1612 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1613 if (hw->phy.type != ixgbe_phy_nl) { 1614 hw->phy.id = 0; 1615 hw->phy.type = ixgbe_phy_unknown; 1616 } 1617 return IXGBE_ERR_SFP_NOT_PRESENT; 1618 } 1619 1620 /** 1621 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1622 * @hw: pointer to hardware structure 1623 * 1624 * Determines physical layer capabilities of the current SFP. 1625 */ 1626 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1627 { 1628 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1629 u8 comp_codes_10g = 0; 1630 u8 comp_codes_1g = 0; 1631 1632 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1633 1634 hw->phy.ops.identify_sfp(hw); 1635 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1636 return physical_layer; 1637 1638 switch (hw->phy.type) { 1639 case ixgbe_phy_sfp_passive_tyco: 1640 case ixgbe_phy_sfp_passive_unknown: 1641 case ixgbe_phy_qsfp_passive_unknown: 1642 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1643 break; 1644 case ixgbe_phy_sfp_ftl_active: 1645 case ixgbe_phy_sfp_active_unknown: 1646 case ixgbe_phy_qsfp_active_unknown: 1647 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1648 break; 1649 case ixgbe_phy_sfp_avago: 1650 case ixgbe_phy_sfp_ftl: 1651 case ixgbe_phy_sfp_intel: 1652 case ixgbe_phy_sfp_unknown: 1653 hw->phy.ops.read_i2c_eeprom(hw, 1654 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1655 hw->phy.ops.read_i2c_eeprom(hw, 1656 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1657 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1658 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1659 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1660 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1661 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1662 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1663 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1664 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1665 break; 1666 case ixgbe_phy_qsfp_intel: 1667 case ixgbe_phy_qsfp_unknown: 1668 hw->phy.ops.read_i2c_eeprom(hw, 1669 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1670 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1671 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1672 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1673 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1674 break; 1675 default: 1676 break; 1677 } 1678 1679 return physical_layer; 1680 } 1681 1682 /** 1683 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1684 * @hw: pointer to hardware structure 1685 * 1686 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1687 **/ 1688 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1689 { 1690 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1691 u32 vendor_oui = 0; 1692 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1693 u8 identifier = 0; 1694 u8 comp_codes_1g = 0; 1695 u8 comp_codes_10g = 0; 1696 u8 oui_bytes[3] = {0, 0, 0}; 1697 u16 enforce_sfp = 0; 1698 u8 connector = 0; 1699 u8 cable_length = 0; 1700 u8 device_tech = 0; 1701 bool active_cable = FALSE; 1702 1703 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1704 1705 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1706 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1707 status = IXGBE_ERR_SFP_NOT_PRESENT; 1708 goto out; 1709 } 1710 1711 /* LAN ID is needed for I2C access */ 1712 hw->mac.ops.set_lan_id(hw); 1713 1714 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1715 &identifier); 1716 1717 if (status != IXGBE_SUCCESS) 1718 goto err_read_i2c_eeprom; 1719 1720 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1721 hw->phy.type = ixgbe_phy_sfp_unsupported; 1722 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1723 goto out; 1724 } 1725 1726 hw->phy.id = identifier; 1727 1728 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1729 &comp_codes_10g); 1730 1731 if (status != IXGBE_SUCCESS) 1732 goto err_read_i2c_eeprom; 1733 1734 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1735 &comp_codes_1g); 1736 1737 if (status != IXGBE_SUCCESS) 1738 goto err_read_i2c_eeprom; 1739 1740 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1741 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1742 if (hw->bus.lan_id == 0) 1743 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1744 else 1745 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1746 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1747 IXGBE_SFF_10GBASELR_CAPABLE)) { 1748 if (hw->bus.lan_id == 0) 1749 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1750 else 1751 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1752 } else { 1753 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1754 active_cable = TRUE; 1755 1756 if (!active_cable) { 1757 /* check for active DA cables that pre-date 1758 * SFF-8436 v3.6 */ 1759 hw->phy.ops.read_i2c_eeprom(hw, 1760 IXGBE_SFF_QSFP_CONNECTOR, 1761 &connector); 1762 1763 hw->phy.ops.read_i2c_eeprom(hw, 1764 IXGBE_SFF_QSFP_CABLE_LENGTH, 1765 &cable_length); 1766 1767 hw->phy.ops.read_i2c_eeprom(hw, 1768 IXGBE_SFF_QSFP_DEVICE_TECH, 1769 &device_tech); 1770 1771 if ((connector == 1772 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1773 (cable_length > 0) && 1774 ((device_tech >> 4) == 1775 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1776 active_cable = TRUE; 1777 } 1778 1779 if (active_cable) { 1780 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1781 if (hw->bus.lan_id == 0) 1782 hw->phy.sfp_type = 1783 ixgbe_sfp_type_da_act_lmt_core0; 1784 else 1785 hw->phy.sfp_type = 1786 ixgbe_sfp_type_da_act_lmt_core1; 1787 } else { 1788 /* unsupported module type */ 1789 hw->phy.type = ixgbe_phy_sfp_unsupported; 1790 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1791 goto out; 1792 } 1793 } 1794 1795 if (hw->phy.sfp_type != stored_sfp_type) 1796 hw->phy.sfp_setup_needed = TRUE; 1797 1798 /* Determine if the QSFP+ PHY is dual speed or not. */ 1799 hw->phy.multispeed_fiber = FALSE; 1800 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1801 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1802 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1803 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1804 hw->phy.multispeed_fiber = TRUE; 1805 1806 /* Determine PHY vendor for optical modules */ 1807 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1808 IXGBE_SFF_10GBASELR_CAPABLE)) { 1809 status = hw->phy.ops.read_i2c_eeprom(hw, 1810 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1811 &oui_bytes[0]); 1812 1813 if (status != IXGBE_SUCCESS) 1814 goto err_read_i2c_eeprom; 1815 1816 status = hw->phy.ops.read_i2c_eeprom(hw, 1817 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1818 &oui_bytes[1]); 1819 1820 if (status != IXGBE_SUCCESS) 1821 goto err_read_i2c_eeprom; 1822 1823 status = hw->phy.ops.read_i2c_eeprom(hw, 1824 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1825 &oui_bytes[2]); 1826 1827 if (status != IXGBE_SUCCESS) 1828 goto err_read_i2c_eeprom; 1829 1830 vendor_oui = 1831 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1832 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1833 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1834 1835 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1836 hw->phy.type = ixgbe_phy_qsfp_intel; 1837 else 1838 hw->phy.type = ixgbe_phy_qsfp_unknown; 1839 1840 ixgbe_get_device_caps(hw, &enforce_sfp); 1841 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1842 /* Make sure we're a supported PHY type */ 1843 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1844 status = IXGBE_SUCCESS; 1845 } else { 1846 if (hw->allow_unsupported_sfp == TRUE) { 1847 EWARN(hw, "WARNING: Intel (R) Network " 1848 "Connections are quality tested " 1849 "using Intel (R) Ethernet Optics." 1850 " Using untested modules is not " 1851 "supported and may cause unstable" 1852 " operation or damage to the " 1853 "module or the adapter. Intel " 1854 "Corporation is not responsible " 1855 "for any harm caused by using " 1856 "untested modules.\n", status); 1857 status = IXGBE_SUCCESS; 1858 } else { 1859 DEBUGOUT("QSFP module not supported\n"); 1860 hw->phy.type = 1861 ixgbe_phy_sfp_unsupported; 1862 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1863 } 1864 } 1865 } else { 1866 status = IXGBE_SUCCESS; 1867 } 1868 } 1869 1870 out: 1871 return status; 1872 1873 err_read_i2c_eeprom: 1874 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1875 hw->phy.id = 0; 1876 hw->phy.type = ixgbe_phy_unknown; 1877 1878 return IXGBE_ERR_SFP_NOT_PRESENT; 1879 } 1880 1881 1882 /** 1883 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1884 * @hw: pointer to hardware structure 1885 * @list_offset: offset to the SFP ID list 1886 * @data_offset: offset to the SFP data block 1887 * 1888 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1889 * so it returns the offsets to the phy init sequence block. 1890 **/ 1891 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1892 u16 *list_offset, 1893 u16 *data_offset) 1894 { 1895 u16 sfp_id; 1896 u16 sfp_type = hw->phy.sfp_type; 1897 1898 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1899 1900 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1901 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1902 1903 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1904 return IXGBE_ERR_SFP_NOT_PRESENT; 1905 1906 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1907 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1908 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1909 1910 /* 1911 * Limiting active cables and 1G Phys must be initialized as 1912 * SR modules 1913 */ 1914 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1915 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1916 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1917 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1918 sfp_type = ixgbe_sfp_type_srlr_core0; 1919 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1920 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1921 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1922 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1923 sfp_type = ixgbe_sfp_type_srlr_core1; 1924 1925 /* Read offset to PHY init contents */ 1926 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1927 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1928 "eeprom read at offset %d failed", 1929 IXGBE_PHY_INIT_OFFSET_NL); 1930 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1931 } 1932 1933 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1934 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1935 1936 /* Shift offset to first ID word */ 1937 (*list_offset)++; 1938 1939 /* 1940 * Find the matching SFP ID in the EEPROM 1941 * and program the init sequence 1942 */ 1943 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1944 goto err_phy; 1945 1946 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1947 if (sfp_id == sfp_type) { 1948 (*list_offset)++; 1949 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1950 goto err_phy; 1951 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1952 DEBUGOUT("SFP+ module not supported\n"); 1953 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1954 } else { 1955 break; 1956 } 1957 } else { 1958 (*list_offset) += 2; 1959 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1960 goto err_phy; 1961 } 1962 } 1963 1964 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1965 DEBUGOUT("No matching SFP+ module found\n"); 1966 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1967 } 1968 1969 return IXGBE_SUCCESS; 1970 1971 err_phy: 1972 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1973 "eeprom read at offset %d failed", *list_offset); 1974 return IXGBE_ERR_PHY; 1975 } 1976 1977 /** 1978 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1979 * @hw: pointer to hardware structure 1980 * @byte_offset: EEPROM byte offset to read 1981 * @eeprom_data: value read 1982 * 1983 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1984 **/ 1985 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1986 u8 *eeprom_data) 1987 { 1988 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1989 1990 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1991 IXGBE_I2C_EEPROM_DEV_ADDR, 1992 eeprom_data); 1993 } 1994 1995 /** 1996 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1997 * @hw: pointer to hardware structure 1998 * @byte_offset: byte offset at address 0xA2 1999 * @eeprom_data: value read 2000 * 2001 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2002 **/ 2003 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2004 u8 *sff8472_data) 2005 { 2006 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2007 IXGBE_I2C_EEPROM_DEV_ADDR2, 2008 sff8472_data); 2009 } 2010 2011 /** 2012 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2013 * @hw: pointer to hardware structure 2014 * @byte_offset: EEPROM byte offset to write 2015 * @eeprom_data: value to write 2016 * 2017 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2018 **/ 2019 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2020 u8 eeprom_data) 2021 { 2022 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2023 2024 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2025 IXGBE_I2C_EEPROM_DEV_ADDR, 2026 eeprom_data); 2027 } 2028 2029 /** 2030 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2031 * @hw: pointer to hardware structure 2032 * @offset: eeprom offset to be read 2033 * @addr: I2C address to be read 2034 */ 2035 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2036 { 2037 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2038 offset == IXGBE_SFF_IDENTIFIER && 2039 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2040 return TRUE; 2041 return FALSE; 2042 } 2043 2044 /** 2045 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2046 * @hw: pointer to hardware structure 2047 * @byte_offset: byte offset to read 2048 * @data: value read 2049 * @lock: TRUE if to take and release semaphore 2050 * 2051 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2052 * a specified device address. 2053 **/ 2054 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2055 u8 dev_addr, u8 *data, bool lock) 2056 { 2057 s32 status; 2058 u32 max_retry = 10; 2059 u32 retry = 0; 2060 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2061 bool nack = 1; 2062 *data = 0; 2063 2064 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2065 2066 if (hw->mac.type >= ixgbe_mac_X550) 2067 max_retry = 3; 2068 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2069 max_retry = IXGBE_SFP_DETECT_RETRIES; 2070 2071 do { 2072 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2073 return IXGBE_ERR_SWFW_SYNC; 2074 2075 ixgbe_i2c_start(hw); 2076 2077 /* Device Address and write indication */ 2078 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2079 if (status != IXGBE_SUCCESS) 2080 goto fail; 2081 2082 status = ixgbe_get_i2c_ack(hw); 2083 if (status != IXGBE_SUCCESS) 2084 goto fail; 2085 2086 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2087 if (status != IXGBE_SUCCESS) 2088 goto fail; 2089 2090 status = ixgbe_get_i2c_ack(hw); 2091 if (status != IXGBE_SUCCESS) 2092 goto fail; 2093 2094 ixgbe_i2c_start(hw); 2095 2096 /* Device Address and read indication */ 2097 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2098 if (status != IXGBE_SUCCESS) 2099 goto fail; 2100 2101 status = ixgbe_get_i2c_ack(hw); 2102 if (status != IXGBE_SUCCESS) 2103 goto fail; 2104 2105 status = ixgbe_clock_in_i2c_byte(hw, data); 2106 if (status != IXGBE_SUCCESS) 2107 goto fail; 2108 2109 status = ixgbe_clock_out_i2c_bit(hw, nack); 2110 if (status != IXGBE_SUCCESS) 2111 goto fail; 2112 2113 ixgbe_i2c_stop(hw); 2114 if (lock) 2115 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2116 return IXGBE_SUCCESS; 2117 2118 fail: 2119 ixgbe_i2c_bus_clear(hw); 2120 if (lock) { 2121 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2122 msec_delay(100); 2123 } 2124 retry++; 2125 if (retry < max_retry) 2126 DEBUGOUT("I2C byte read error - Retrying.\n"); 2127 else 2128 DEBUGOUT("I2C byte read error.\n"); 2129 2130 } while (retry < max_retry); 2131 2132 return status; 2133 } 2134 2135 /** 2136 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2137 * @hw: pointer to hardware structure 2138 * @byte_offset: byte offset to read 2139 * @data: value read 2140 * 2141 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2142 * a specified device address. 2143 **/ 2144 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2145 u8 dev_addr, u8 *data) 2146 { 2147 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2148 data, TRUE); 2149 } 2150 2151 /** 2152 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2153 * @hw: pointer to hardware structure 2154 * @byte_offset: byte offset to read 2155 * @data: value read 2156 * 2157 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2158 * a specified device address. 2159 **/ 2160 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2161 u8 dev_addr, u8 *data) 2162 { 2163 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2164 data, FALSE); 2165 } 2166 2167 /** 2168 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2169 * @hw: pointer to hardware structure 2170 * @byte_offset: byte offset to write 2171 * @data: value to write 2172 * @lock: TRUE if to take and release semaphore 2173 * 2174 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2175 * a specified device address. 2176 **/ 2177 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2178 u8 dev_addr, u8 data, bool lock) 2179 { 2180 s32 status; 2181 u32 max_retry = 1; 2182 u32 retry = 0; 2183 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2184 2185 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2186 2187 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2188 IXGBE_SUCCESS) 2189 return IXGBE_ERR_SWFW_SYNC; 2190 2191 do { 2192 ixgbe_i2c_start(hw); 2193 2194 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2195 if (status != IXGBE_SUCCESS) 2196 goto fail; 2197 2198 status = ixgbe_get_i2c_ack(hw); 2199 if (status != IXGBE_SUCCESS) 2200 goto fail; 2201 2202 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2203 if (status != IXGBE_SUCCESS) 2204 goto fail; 2205 2206 status = ixgbe_get_i2c_ack(hw); 2207 if (status != IXGBE_SUCCESS) 2208 goto fail; 2209 2210 status = ixgbe_clock_out_i2c_byte(hw, data); 2211 if (status != IXGBE_SUCCESS) 2212 goto fail; 2213 2214 status = ixgbe_get_i2c_ack(hw); 2215 if (status != IXGBE_SUCCESS) 2216 goto fail; 2217 2218 ixgbe_i2c_stop(hw); 2219 if (lock) 2220 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2221 return IXGBE_SUCCESS; 2222 2223 fail: 2224 ixgbe_i2c_bus_clear(hw); 2225 retry++; 2226 if (retry < max_retry) 2227 DEBUGOUT("I2C byte write error - Retrying.\n"); 2228 else 2229 DEBUGOUT("I2C byte write error.\n"); 2230 } while (retry < max_retry); 2231 2232 if (lock) 2233 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2234 2235 return status; 2236 } 2237 2238 /** 2239 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2240 * @hw: pointer to hardware structure 2241 * @byte_offset: byte offset to write 2242 * @data: value to write 2243 * 2244 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2245 * a specified device address. 2246 **/ 2247 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2248 u8 dev_addr, u8 data) 2249 { 2250 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2251 data, TRUE); 2252 } 2253 2254 /** 2255 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2256 * @hw: pointer to hardware structure 2257 * @byte_offset: byte offset to write 2258 * @data: value to write 2259 * 2260 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2261 * a specified device address. 2262 **/ 2263 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2264 u8 dev_addr, u8 data) 2265 { 2266 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2267 data, FALSE); 2268 } 2269 2270 /** 2271 * ixgbe_i2c_start - Sets I2C start condition 2272 * @hw: pointer to hardware structure 2273 * 2274 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2275 * Set bit-bang mode on X550 hardware. 2276 **/ 2277 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2278 { 2279 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2280 2281 DEBUGFUNC("ixgbe_i2c_start"); 2282 2283 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2284 2285 /* Start condition must begin with data and clock high */ 2286 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2287 ixgbe_raise_i2c_clk(hw, &i2cctl); 2288 2289 /* Setup time for start condition (4.7us) */ 2290 usec_delay(IXGBE_I2C_T_SU_STA); 2291 2292 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2293 2294 /* Hold time for start condition (4us) */ 2295 usec_delay(IXGBE_I2C_T_HD_STA); 2296 2297 ixgbe_lower_i2c_clk(hw, &i2cctl); 2298 2299 /* Minimum low period of clock is 4.7 us */ 2300 usec_delay(IXGBE_I2C_T_LOW); 2301 2302 } 2303 2304 /** 2305 * ixgbe_i2c_stop - Sets I2C stop condition 2306 * @hw: pointer to hardware structure 2307 * 2308 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2309 * Disables bit-bang mode and negates data output enable on X550 2310 * hardware. 2311 **/ 2312 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2313 { 2314 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2315 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2316 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2317 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2318 2319 DEBUGFUNC("ixgbe_i2c_stop"); 2320 2321 /* Stop condition must begin with data low and clock high */ 2322 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2323 ixgbe_raise_i2c_clk(hw, &i2cctl); 2324 2325 /* Setup time for stop condition (4us) */ 2326 usec_delay(IXGBE_I2C_T_SU_STO); 2327 2328 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2329 2330 /* bus free time between stop and start (4.7us)*/ 2331 usec_delay(IXGBE_I2C_T_BUF); 2332 2333 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2334 i2cctl &= ~bb_en_bit; 2335 i2cctl |= data_oe_bit | clk_oe_bit; 2336 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2337 IXGBE_WRITE_FLUSH(hw); 2338 } 2339 } 2340 2341 /** 2342 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2343 * @hw: pointer to hardware structure 2344 * @data: data byte to clock in 2345 * 2346 * Clocks in one byte data via I2C data/clock 2347 **/ 2348 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2349 { 2350 s32 i; 2351 bool bit = 0; 2352 2353 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2354 2355 *data = 0; 2356 for (i = 7; i >= 0; i--) { 2357 ixgbe_clock_in_i2c_bit(hw, &bit); 2358 *data |= bit << i; 2359 } 2360 2361 return IXGBE_SUCCESS; 2362 } 2363 2364 /** 2365 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2366 * @hw: pointer to hardware structure 2367 * @data: data byte clocked out 2368 * 2369 * Clocks out one byte data via I2C data/clock 2370 **/ 2371 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2372 { 2373 s32 status = IXGBE_SUCCESS; 2374 s32 i; 2375 u32 i2cctl; 2376 bool bit; 2377 2378 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2379 2380 for (i = 7; i >= 0; i--) { 2381 bit = (data >> i) & 0x1; 2382 status = ixgbe_clock_out_i2c_bit(hw, bit); 2383 2384 if (status != IXGBE_SUCCESS) 2385 break; 2386 } 2387 2388 /* Release SDA line (set high) */ 2389 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2390 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2391 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2392 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2393 IXGBE_WRITE_FLUSH(hw); 2394 2395 return status; 2396 } 2397 2398 /** 2399 * ixgbe_get_i2c_ack - Polls for I2C ACK 2400 * @hw: pointer to hardware structure 2401 * 2402 * Clocks in/out one bit via I2C data/clock 2403 **/ 2404 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2405 { 2406 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2407 s32 status = IXGBE_SUCCESS; 2408 u32 i = 0; 2409 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2410 u32 timeout = 10; 2411 bool ack = 1; 2412 2413 DEBUGFUNC("ixgbe_get_i2c_ack"); 2414 2415 if (data_oe_bit) { 2416 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2417 i2cctl |= data_oe_bit; 2418 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2419 IXGBE_WRITE_FLUSH(hw); 2420 } 2421 ixgbe_raise_i2c_clk(hw, &i2cctl); 2422 2423 /* Minimum high period of clock is 4us */ 2424 usec_delay(IXGBE_I2C_T_HIGH); 2425 2426 /* Poll for ACK. Note that ACK in I2C spec is 2427 * transition from 1 to 0 */ 2428 for (i = 0; i < timeout; i++) { 2429 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2430 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2431 2432 usec_delay(1); 2433 if (!ack) 2434 break; 2435 } 2436 2437 if (ack) { 2438 DEBUGOUT("I2C ack was not received.\n"); 2439 status = IXGBE_ERR_I2C; 2440 } 2441 2442 ixgbe_lower_i2c_clk(hw, &i2cctl); 2443 2444 /* Minimum low period of clock is 4.7 us */ 2445 usec_delay(IXGBE_I2C_T_LOW); 2446 2447 return status; 2448 } 2449 2450 /** 2451 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2452 * @hw: pointer to hardware structure 2453 * @data: read data value 2454 * 2455 * Clocks in one bit via I2C data/clock 2456 **/ 2457 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2458 { 2459 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2460 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2461 2462 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2463 2464 if (data_oe_bit) { 2465 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2466 i2cctl |= data_oe_bit; 2467 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2468 IXGBE_WRITE_FLUSH(hw); 2469 } 2470 ixgbe_raise_i2c_clk(hw, &i2cctl); 2471 2472 /* Minimum high period of clock is 4us */ 2473 usec_delay(IXGBE_I2C_T_HIGH); 2474 2475 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2476 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2477 2478 ixgbe_lower_i2c_clk(hw, &i2cctl); 2479 2480 /* Minimum low period of clock is 4.7 us */ 2481 usec_delay(IXGBE_I2C_T_LOW); 2482 2483 return IXGBE_SUCCESS; 2484 } 2485 2486 /** 2487 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2488 * @hw: pointer to hardware structure 2489 * @data: data value to write 2490 * 2491 * Clocks out one bit via I2C data/clock 2492 **/ 2493 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2494 { 2495 s32 status; 2496 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2497 2498 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2499 2500 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2501 if (status == IXGBE_SUCCESS) { 2502 ixgbe_raise_i2c_clk(hw, &i2cctl); 2503 2504 /* Minimum high period of clock is 4us */ 2505 usec_delay(IXGBE_I2C_T_HIGH); 2506 2507 ixgbe_lower_i2c_clk(hw, &i2cctl); 2508 2509 /* Minimum low period of clock is 4.7 us. 2510 * This also takes care of the data hold time. 2511 */ 2512 usec_delay(IXGBE_I2C_T_LOW); 2513 } else { 2514 status = IXGBE_ERR_I2C; 2515 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2516 "I2C data was not set to %X\n", data); 2517 } 2518 2519 return status; 2520 } 2521 2522 /** 2523 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2524 * @hw: pointer to hardware structure 2525 * @i2cctl: Current value of I2CCTL register 2526 * 2527 * Raises the I2C clock line '0'->'1' 2528 * Negates the I2C clock output enable on X550 hardware. 2529 **/ 2530 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2531 { 2532 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2533 u32 i = 0; 2534 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2535 u32 i2cctl_r = 0; 2536 2537 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2538 2539 if (clk_oe_bit) { 2540 *i2cctl |= clk_oe_bit; 2541 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2542 } 2543 2544 for (i = 0; i < timeout; i++) { 2545 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2546 2547 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2548 IXGBE_WRITE_FLUSH(hw); 2549 /* SCL rise time (1000ns) */ 2550 usec_delay(IXGBE_I2C_T_RISE); 2551 2552 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2553 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2554 break; 2555 } 2556 } 2557 2558 /** 2559 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2560 * @hw: pointer to hardware structure 2561 * @i2cctl: Current value of I2CCTL register 2562 * 2563 * Lowers the I2C clock line '1'->'0' 2564 * Asserts the I2C clock output enable on X550 hardware. 2565 **/ 2566 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2567 { 2568 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2569 2570 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2571 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2572 2573 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2574 IXGBE_WRITE_FLUSH(hw); 2575 2576 /* SCL fall time (300ns) */ 2577 usec_delay(IXGBE_I2C_T_FALL); 2578 } 2579 2580 /** 2581 * ixgbe_set_i2c_data - Sets the I2C data bit 2582 * @hw: pointer to hardware structure 2583 * @i2cctl: Current value of I2CCTL register 2584 * @data: I2C data value (0 or 1) to set 2585 * 2586 * Sets the I2C data bit 2587 * Asserts the I2C data output enable on X550 hardware. 2588 **/ 2589 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2590 { 2591 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2592 s32 status = IXGBE_SUCCESS; 2593 2594 DEBUGFUNC("ixgbe_set_i2c_data"); 2595 2596 if (data) 2597 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2598 else 2599 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2600 *i2cctl &= ~data_oe_bit; 2601 2602 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2603 IXGBE_WRITE_FLUSH(hw); 2604 2605 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2606 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2607 2608 if (!data) /* Can't verify data in this case */ 2609 return IXGBE_SUCCESS; 2610 if (data_oe_bit) { 2611 *i2cctl |= data_oe_bit; 2612 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2613 IXGBE_WRITE_FLUSH(hw); 2614 } 2615 2616 /* Verify data was set correctly */ 2617 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2618 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2619 status = IXGBE_ERR_I2C; 2620 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2621 "Error - I2C data was not set to %X.\n", 2622 data); 2623 } 2624 2625 return status; 2626 } 2627 2628 /** 2629 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2630 * @hw: pointer to hardware structure 2631 * @i2cctl: Current value of I2CCTL register 2632 * 2633 * Returns the I2C data bit value 2634 * Negates the I2C data output enable on X550 hardware. 2635 **/ 2636 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2637 { 2638 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2639 bool data; 2640 2641 DEBUGFUNC("ixgbe_get_i2c_data"); 2642 2643 if (data_oe_bit) { 2644 *i2cctl |= data_oe_bit; 2645 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2646 IXGBE_WRITE_FLUSH(hw); 2647 usec_delay(IXGBE_I2C_T_FALL); 2648 } 2649 2650 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2651 data = 1; 2652 else 2653 data = 0; 2654 2655 return data; 2656 } 2657 2658 /** 2659 * ixgbe_i2c_bus_clear - Clears the I2C bus 2660 * @hw: pointer to hardware structure 2661 * 2662 * Clears the I2C bus by sending nine clock pulses. 2663 * Used when data line is stuck low. 2664 **/ 2665 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2666 { 2667 u32 i2cctl; 2668 u32 i; 2669 2670 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2671 2672 ixgbe_i2c_start(hw); 2673 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2674 2675 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2676 2677 for (i = 0; i < 9; i++) { 2678 ixgbe_raise_i2c_clk(hw, &i2cctl); 2679 2680 /* Min high period of clock is 4us */ 2681 usec_delay(IXGBE_I2C_T_HIGH); 2682 2683 ixgbe_lower_i2c_clk(hw, &i2cctl); 2684 2685 /* Min low period of clock is 4.7us*/ 2686 usec_delay(IXGBE_I2C_T_LOW); 2687 } 2688 2689 ixgbe_i2c_start(hw); 2690 2691 /* Put the i2c bus back to default state */ 2692 ixgbe_i2c_stop(hw); 2693 } 2694 2695 /** 2696 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2697 * @hw: pointer to hardware structure 2698 * 2699 * Checks if the LASI temp alarm status was triggered due to overtemp 2700 **/ 2701 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2702 { 2703 s32 status = IXGBE_SUCCESS; 2704 u16 phy_data = 0; 2705 2706 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2707 2708 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2709 goto out; 2710 2711 /* Check that the LASI temp alarm status was triggered */ 2712 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2713 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2714 2715 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2716 goto out; 2717 2718 status = IXGBE_ERR_OVERTEMP; 2719 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2720 out: 2721 return status; 2722 } 2723 2724 /** 2725 * ixgbe_set_copper_phy_power - Control power for copper phy 2726 * @hw: pointer to hardware structure 2727 * @on: TRUE for on, FALSE for off 2728 */ 2729 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2730 { 2731 u32 status; 2732 u16 reg; 2733 2734 if (!on && ixgbe_mng_present(hw)) 2735 return 0; 2736 2737 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2738 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2739 ®); 2740 if (status) 2741 return status; 2742 2743 if (on) { 2744 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2745 } else { 2746 if (ixgbe_check_reset_blocked(hw)) 2747 return 0; 2748 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2749 } 2750 2751 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2752 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2753 reg); 2754 return status; 2755 } 2756