1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53 /** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61 { 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68 } 69 70 /** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78 { 79 ixgbe_clock_in_i2c_byte(hw, byte); 80 /* ACK */ 81 return ixgbe_clock_out_i2c_bit(hw, false); 82 } 83 84 /** 85 * ixgbe_ones_comp_byte_add - Perform one's complement addition 86 * @add1: addend 1 87 * @add2: addend 2 88 * 89 * Returns one's complement 8-bit sum. 90 */ 91 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 92 { 93 u16 sum = add1 + add2; 94 95 sum = (sum & 0xFF) + (sum >> 8); 96 return sum & 0xFF; 97 } 98 99 /** 100 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 101 * @hw: pointer to the hardware structure 102 * @addr: I2C bus address to read from 103 * @reg: I2C device register to read from 104 * @val: pointer to location to receive read value 105 * @lock: true if to take and release semaphore 106 * 107 * Returns an error code on error. 108 */ 109 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 110 u16 *val, bool lock) 111 { 112 u32 swfw_mask = hw->phy.phy_semaphore_mask; 113 int max_retry = 3; 114 int retry = 0; 115 u8 csum_byte; 116 u8 high_bits; 117 u8 low_bits; 118 u8 reg_high; 119 u8 csum; 120 121 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 122 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 123 csum = ~csum; 124 do { 125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 126 return IXGBE_ERR_SWFW_SYNC; 127 ixgbe_i2c_start(hw); 128 /* Device Address and write indication */ 129 if (ixgbe_out_i2c_byte_ack(hw, addr)) 130 goto fail; 131 /* Write bits 14:8 */ 132 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 133 goto fail; 134 /* Write bits 7:0 */ 135 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 136 goto fail; 137 /* Write csum */ 138 if (ixgbe_out_i2c_byte_ack(hw, csum)) 139 goto fail; 140 /* Re-start condition */ 141 ixgbe_i2c_start(hw); 142 /* Device Address and read indication */ 143 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 144 goto fail; 145 /* Get upper bits */ 146 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 147 goto fail; 148 /* Get low bits */ 149 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 150 goto fail; 151 /* Get csum */ 152 ixgbe_clock_in_i2c_byte(hw, &csum_byte); 153 /* NACK */ 154 if (ixgbe_clock_out_i2c_bit(hw, false)) 155 goto fail; 156 ixgbe_i2c_stop(hw); 157 if (lock) 158 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 159 *val = (high_bits << 8) | low_bits; 160 return 0; 161 162 fail: 163 ixgbe_i2c_bus_clear(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 if (retry < max_retry) 167 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 168 else 169 DEBUGOUT("I2C byte read combined error.\n"); 170 retry++; 171 } while (retry <= max_retry); 172 173 return IXGBE_ERR_I2C; 174 } 175 176 /** 177 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 178 * @hw: pointer to the hardware structure 179 * @addr: I2C bus address to write to 180 * @reg: I2C device register to write to 181 * @val: value to write 182 * @lock: true if to take and release semaphore 183 * 184 * Returns an error code on error. 185 */ 186 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 187 u16 val, bool lock) 188 { 189 u32 swfw_mask = hw->phy.phy_semaphore_mask; 190 int max_retry = 1; 191 int retry = 0; 192 u8 reg_high; 193 u8 csum; 194 195 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 196 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 197 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 198 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 199 csum = ~csum; 200 do { 201 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 202 return IXGBE_ERR_SWFW_SYNC; 203 ixgbe_i2c_start(hw); 204 /* Device Address and write indication */ 205 if (ixgbe_out_i2c_byte_ack(hw, addr)) 206 goto fail; 207 /* Write bits 14:8 */ 208 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 209 goto fail; 210 /* Write bits 7:0 */ 211 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 212 goto fail; 213 /* Write data 15:8 */ 214 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 215 goto fail; 216 /* Write data 7:0 */ 217 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 218 goto fail; 219 /* Write csum */ 220 if (ixgbe_out_i2c_byte_ack(hw, csum)) 221 goto fail; 222 ixgbe_i2c_stop(hw); 223 if (lock) 224 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 225 return 0; 226 227 fail: 228 ixgbe_i2c_bus_clear(hw); 229 if (lock) 230 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 231 if (retry < max_retry) 232 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 233 else 234 DEBUGOUT("I2C byte write combined error.\n"); 235 retry++; 236 } while (retry <= max_retry); 237 238 return IXGBE_ERR_I2C; 239 } 240 241 /** 242 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 243 * @hw: pointer to the hardware structure 244 * 245 * Initialize the function pointers. 246 **/ 247 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 248 { 249 struct ixgbe_phy_info *phy = &hw->phy; 250 251 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 252 253 /* PHY */ 254 phy->ops.identify = ixgbe_identify_phy_generic; 255 phy->ops.reset = ixgbe_reset_phy_generic; 256 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 257 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 260 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 261 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 262 phy->ops.check_link = NULL; 263 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 264 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 265 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 266 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 267 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 268 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 269 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 270 phy->ops.identify_sfp = ixgbe_identify_module_generic; 271 phy->sfp_type = ixgbe_sfp_type_unknown; 272 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 273 phy->ops.write_i2c_byte_unlocked = 274 ixgbe_write_i2c_byte_generic_unlocked; 275 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 276 return IXGBE_SUCCESS; 277 } 278 279 /** 280 * ixgbe_probe_phy - Probe a single address for a PHY 281 * @hw: pointer to hardware structure 282 * @phy_addr: PHY address to probe 283 * 284 * Returns true if PHY found 285 */ 286 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 287 { 288 u16 ext_ability = 0; 289 290 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 291 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 292 phy_addr); 293 return false; 294 } 295 296 if (ixgbe_get_phy_id(hw)) 297 return false; 298 299 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 300 301 if (hw->phy.type == ixgbe_phy_unknown) { 302 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 303 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 304 if (ext_ability & 305 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 306 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 307 hw->phy.type = ixgbe_phy_cu_unknown; 308 else 309 hw->phy.type = ixgbe_phy_generic; 310 } 311 312 return true; 313 } 314 315 /** 316 * ixgbe_identify_phy_generic - Get physical layer module 317 * @hw: pointer to hardware structure 318 * 319 * Determines the physical layer module found on the current adapter. 320 **/ 321 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 322 { 323 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 324 u16 phy_addr; 325 326 DEBUGFUNC("ixgbe_identify_phy_generic"); 327 328 if (!hw->phy.phy_semaphore_mask) { 329 if (hw->bus.lan_id) 330 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 331 else 332 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 333 } 334 335 if (hw->phy.type != ixgbe_phy_unknown) 336 return IXGBE_SUCCESS; 337 338 if (hw->phy.nw_mng_if_sel) { 339 phy_addr = (hw->phy.nw_mng_if_sel & 340 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 342 if (ixgbe_probe_phy(hw, phy_addr)) 343 return IXGBE_SUCCESS; 344 else 345 return IXGBE_ERR_PHY_ADDR_INVALID; 346 } 347 348 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 349 if (ixgbe_probe_phy(hw, phy_addr)) { 350 status = IXGBE_SUCCESS; 351 break; 352 } 353 } 354 355 /* Certain media types do not have a phy so an address will not 356 * be found and the code will take this path. Caller has to 357 * decide if it is an error or not. 358 */ 359 if (status != IXGBE_SUCCESS) 360 hw->phy.addr = 0; 361 362 return status; 363 } 364 365 /** 366 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 367 * @hw: pointer to the hardware structure 368 * 369 * This function checks the MMNGC.MNG_VETO bit to see if there are 370 * any constraints on link from manageability. For MAC's that don't 371 * have this bit just return faluse since the link can not be blocked 372 * via this method. 373 **/ 374 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 375 { 376 u32 mmngc; 377 378 DEBUGFUNC("ixgbe_check_reset_blocked"); 379 380 /* If we don't have this bit, it can't be blocking */ 381 if (hw->mac.type == ixgbe_mac_82598EB) 382 return false; 383 384 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 385 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 386 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 387 "MNG_VETO bit detected.\n"); 388 return true; 389 } 390 391 return false; 392 } 393 394 /** 395 * ixgbe_validate_phy_addr - Determines phy address is valid 396 * @hw: pointer to hardware structure 397 * @phy_addr: PHY address 398 * 399 **/ 400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 401 { 402 u16 phy_id = 0; 403 bool valid = false; 404 405 DEBUGFUNC("ixgbe_validate_phy_addr"); 406 407 hw->phy.addr = phy_addr; 408 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 409 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 410 411 if (phy_id != 0xFFFF && phy_id != 0x0) 412 valid = true; 413 414 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 415 416 return valid; 417 } 418 419 /** 420 * ixgbe_get_phy_id - Get the phy type 421 * @hw: pointer to hardware structure 422 * 423 **/ 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 425 { 426 u32 status; 427 u16 phy_id_high = 0; 428 u16 phy_id_low = 0; 429 430 DEBUGFUNC("ixgbe_get_phy_id"); 431 432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 433 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 434 &phy_id_high); 435 436 if (status == IXGBE_SUCCESS) { 437 hw->phy.id = (u32)(phy_id_high << 16); 438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 439 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 440 &phy_id_low); 441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 443 } 444 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 445 phy_id_high, phy_id_low); 446 447 return status; 448 } 449 450 /** 451 * ixgbe_get_phy_type_from_id - Get the phy type 452 * @phy_id: PHY ID information 453 * 454 **/ 455 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 456 { 457 enum ixgbe_phy_type phy_type; 458 459 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 460 461 switch (phy_id) { 462 case TN1010_PHY_ID: 463 phy_type = ixgbe_phy_tn; 464 break; 465 case X550_PHY_ID2: 466 case X550_PHY_ID3: 467 case X540_PHY_ID: 468 phy_type = ixgbe_phy_aq; 469 break; 470 case QT2022_PHY_ID: 471 phy_type = ixgbe_phy_qt; 472 break; 473 case ATH_PHY_ID: 474 phy_type = ixgbe_phy_nl; 475 break; 476 case X557_PHY_ID: 477 case X557_PHY_ID2: 478 phy_type = ixgbe_phy_x550em_ext_t; 479 break; 480 case IXGBE_M88E1500_E_PHY_ID: 481 case IXGBE_M88E1543_E_PHY_ID: 482 phy_type = ixgbe_phy_ext_1g_t; 483 break; 484 default: 485 phy_type = ixgbe_phy_unknown; 486 break; 487 } 488 return phy_type; 489 } 490 491 /** 492 * ixgbe_reset_phy_generic - Performs a PHY reset 493 * @hw: pointer to hardware structure 494 **/ 495 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 496 { 497 u32 i; 498 u16 ctrl = 0; 499 s32 status = IXGBE_SUCCESS; 500 501 DEBUGFUNC("ixgbe_reset_phy_generic"); 502 503 if (hw->phy.type == ixgbe_phy_unknown) 504 status = ixgbe_identify_phy_generic(hw); 505 506 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 507 goto out; 508 509 /* Don't reset PHY if it's shut down due to overtemp. */ 510 if (!hw->phy.reset_if_overtemp && 511 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 512 goto out; 513 514 /* Blocked by MNG FW so bail */ 515 if (ixgbe_check_reset_blocked(hw)) 516 goto out; 517 518 /* 519 * Perform soft PHY reset to the PHY_XS. 520 * This will cause a soft reset to the PHY 521 */ 522 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 523 IXGBE_MDIO_PHY_XS_DEV_TYPE, 524 IXGBE_MDIO_PHY_XS_RESET); 525 526 /* 527 * Poll for reset bit to self-clear indicating reset is complete. 528 * Some PHYs could take up to 3 seconds to complete and need about 529 * 1.7 usec delay after the reset is complete. 530 */ 531 for (i = 0; i < 30; i++) { 532 msec_delay(100); 533 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 534 status = hw->phy.ops.read_reg(hw, 535 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 536 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 537 &ctrl); 538 if (status != IXGBE_SUCCESS) 539 return status; 540 541 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 542 usec_delay(2); 543 break; 544 } 545 } else { 546 status = hw->phy.ops.read_reg(hw, 547 IXGBE_MDIO_PHY_XS_CONTROL, 548 IXGBE_MDIO_PHY_XS_DEV_TYPE, 549 &ctrl); 550 if (status != IXGBE_SUCCESS) 551 return status; 552 553 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 554 usec_delay(2); 555 break; 556 } 557 } 558 } 559 560 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 561 status = IXGBE_ERR_RESET_FAILED; 562 ERROR_REPORT1(IXGBE_ERROR_POLLING, 563 "PHY reset polling failed to complete.\n"); 564 } 565 566 out: 567 return status; 568 } 569 570 /** 571 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY 572 * @hw: pointer to hardware structure 573 **/ 574 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw) 575 { 576 u16 autoneg_reg; 577 578 /* Check if PHY reset is blocked by MNG FW */ 579 if (ixgbe_check_reset_blocked(hw)) 580 return; 581 582 /* Restart PHY auto-negotiation. */ 583 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 584 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 585 autoneg_reg |= IXGBE_MII_RESTART; 586 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 587 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 588 } 589 590 /** 591 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 592 * the SWFW lock 593 * @hw: pointer to hardware structure 594 * @reg_addr: 32 bit address of PHY register to read 595 * @device_type: 5 bit device type 596 * @phy_data: Pointer to read data from PHY register 597 **/ 598 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 599 u16 *phy_data) 600 { 601 u32 i, data, command; 602 603 /* Setup and write the address cycle command */ 604 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 605 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 606 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 607 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 608 609 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 610 611 /* 612 * Check every 10 usec to see if the address cycle completed. 613 * The MDI Command bit will clear when the operation is 614 * complete 615 */ 616 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 617 usec_delay(10); 618 619 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 620 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 621 break; 622 } 623 624 625 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 626 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 627 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 628 return IXGBE_ERR_PHY; 629 } 630 631 /* 632 * Address cycle complete, setup and write the read 633 * command 634 */ 635 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 636 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 637 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 638 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 639 640 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 641 642 /* 643 * Check every 10 usec to see if the address cycle 644 * completed. The MDI Command bit will clear when the 645 * operation is complete 646 */ 647 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 648 usec_delay(10); 649 650 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 651 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 652 break; 653 } 654 655 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 656 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 657 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 658 return IXGBE_ERR_PHY; 659 } 660 661 /* 662 * Read operation is complete. Get the data 663 * from MSRWD 664 */ 665 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 666 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 667 *phy_data = (u16)(data); 668 669 return IXGBE_SUCCESS; 670 } 671 672 /** 673 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 674 * using the SWFW lock - this function is needed in most cases 675 * @hw: pointer to hardware structure 676 * @reg_addr: 32 bit address of PHY register to read 677 * @device_type: 5 bit device type 678 * @phy_data: Pointer to read data from PHY register 679 **/ 680 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 681 u32 device_type, u16 *phy_data) 682 { 683 s32 status; 684 u32 gssr = hw->phy.phy_semaphore_mask; 685 686 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 687 688 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 689 return IXGBE_ERR_SWFW_SYNC; 690 691 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 692 693 hw->mac.ops.release_swfw_sync(hw, gssr); 694 695 return status; 696 } 697 698 /** 699 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 700 * without SWFW lock 701 * @hw: pointer to hardware structure 702 * @reg_addr: 32 bit PHY register to write 703 * @device_type: 5 bit device type 704 * @phy_data: Data to write to the PHY register 705 **/ 706 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 707 u32 device_type, u16 phy_data) 708 { 709 u32 i, command; 710 711 /* Put the data in the MDI single read and write data register*/ 712 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 713 714 /* Setup and write the address cycle command */ 715 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 716 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 717 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 718 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 719 720 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 721 722 /* 723 * Check every 10 usec to see if the address cycle completed. 724 * The MDI Command bit will clear when the operation is 725 * complete 726 */ 727 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 728 usec_delay(10); 729 730 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 731 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 732 break; 733 } 734 735 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 736 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 737 return IXGBE_ERR_PHY; 738 } 739 740 /* 741 * Address cycle complete, setup and write the write 742 * command 743 */ 744 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 745 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 746 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 747 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 748 749 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 750 751 /* 752 * Check every 10 usec to see if the address cycle 753 * completed. The MDI Command bit will clear when the 754 * operation is complete 755 */ 756 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 757 usec_delay(10); 758 759 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 760 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 761 break; 762 } 763 764 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 765 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 766 return IXGBE_ERR_PHY; 767 } 768 769 return IXGBE_SUCCESS; 770 } 771 772 /** 773 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 774 * using SWFW lock- this function is needed in most cases 775 * @hw: pointer to hardware structure 776 * @reg_addr: 32 bit PHY register to write 777 * @device_type: 5 bit device type 778 * @phy_data: Data to write to the PHY register 779 **/ 780 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 781 u32 device_type, u16 phy_data) 782 { 783 s32 status; 784 u32 gssr = hw->phy.phy_semaphore_mask; 785 786 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 787 788 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 789 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 790 phy_data); 791 hw->mac.ops.release_swfw_sync(hw, gssr); 792 } else { 793 status = IXGBE_ERR_SWFW_SYNC; 794 } 795 796 return status; 797 } 798 799 /** 800 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 801 * @hw: pointer to hardware structure 802 * 803 * Restart auto-negotiation and PHY and waits for completion. 804 **/ 805 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 806 { 807 s32 status = IXGBE_SUCCESS; 808 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 809 bool autoneg = false; 810 ixgbe_link_speed speed; 811 812 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 813 814 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 815 816 /* Set or unset auto-negotiation 10G advertisement */ 817 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 818 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 819 &autoneg_reg); 820 821 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 822 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 823 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 824 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 825 826 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 827 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 828 autoneg_reg); 829 830 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 831 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 832 &autoneg_reg); 833 834 if (hw->mac.type == ixgbe_mac_X550) { 835 /* Set or unset auto-negotiation 5G advertisement */ 836 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 837 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 838 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 839 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 840 841 /* Set or unset auto-negotiation 2.5G advertisement */ 842 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 843 if ((hw->phy.autoneg_advertised & 844 IXGBE_LINK_SPEED_2_5GB_FULL) && 845 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 846 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 847 } 848 849 /* Set or unset auto-negotiation 1G advertisement */ 850 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 851 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 852 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 853 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 854 855 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 856 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 857 autoneg_reg); 858 859 /* Set or unset auto-negotiation 100M advertisement */ 860 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 861 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 862 &autoneg_reg); 863 864 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 865 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 866 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 867 (speed & IXGBE_LINK_SPEED_100_FULL)) 868 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 869 870 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 871 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 872 autoneg_reg); 873 874 ixgbe_restart_auto_neg(hw); 875 return status; 876 } 877 878 /** 879 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 880 * @hw: pointer to hardware structure 881 * @speed: new link speed 882 * @autoneg_wait_to_complete: unused 883 **/ 884 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 885 ixgbe_link_speed speed, 886 bool autoneg_wait_to_complete) 887 { 888 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 889 890 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 891 892 /* 893 * Clear autoneg_advertised and set new values based on input link 894 * speed. 895 */ 896 hw->phy.autoneg_advertised = 0; 897 898 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 899 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 900 901 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 902 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 903 904 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 905 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 906 907 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 908 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 909 910 if (speed & IXGBE_LINK_SPEED_100_FULL) 911 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 912 913 if (speed & IXGBE_LINK_SPEED_10_FULL) 914 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 915 916 /* Setup link based on the new speed settings */ 917 ixgbe_setup_phy_link(hw); 918 919 return IXGBE_SUCCESS; 920 } 921 922 /** 923 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 924 * @hw: pointer to hardware structure 925 * 926 * Determines the supported link capabilities by reading the PHY auto 927 * negotiation register. 928 **/ 929 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 930 { 931 s32 status; 932 u16 speed_ability; 933 934 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 935 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 936 &speed_ability); 937 if (status) 938 return status; 939 940 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 941 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 942 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 944 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 945 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 946 947 switch (hw->mac.type) { 948 case ixgbe_mac_X550: 949 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 950 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 951 break; 952 case ixgbe_mac_X550EM_x: 953 case ixgbe_mac_X550EM_a: 954 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 955 break; 956 default: 957 break; 958 } 959 960 return status; 961 } 962 963 /** 964 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 965 * @hw: pointer to hardware structure 966 * @speed: pointer to link speed 967 * @autoneg: boolean auto-negotiation value 968 **/ 969 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 970 ixgbe_link_speed *speed, 971 bool *autoneg) 972 { 973 s32 status = IXGBE_SUCCESS; 974 975 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 976 977 *autoneg = true; 978 if (!hw->phy.speeds_supported) 979 status = ixgbe_get_copper_speeds_supported(hw); 980 981 *speed = hw->phy.speeds_supported; 982 return status; 983 } 984 985 /** 986 * ixgbe_check_phy_link_tnx - Determine link and speed status 987 * @hw: pointer to hardware structure 988 * @speed: current link speed 989 * @link_up: true is link is up, false otherwise 990 * 991 * Reads the VS1 register to determine if link is up and the current speed for 992 * the PHY. 993 **/ 994 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 995 bool *link_up) 996 { 997 s32 status = IXGBE_SUCCESS; 998 u32 time_out; 999 u32 max_time_out = 10; 1000 u16 phy_link = 0; 1001 u16 phy_speed = 0; 1002 u16 phy_data = 0; 1003 1004 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1005 1006 /* Initialize speed and link to default case */ 1007 *link_up = false; 1008 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1009 1010 /* 1011 * Check current speed and link status of the PHY register. 1012 * This is a vendor specific register and may have to 1013 * be changed for other copper PHYs. 1014 */ 1015 for (time_out = 0; time_out < max_time_out; time_out++) { 1016 usec_delay(10); 1017 status = hw->phy.ops.read_reg(hw, 1018 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1020 &phy_data); 1021 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1022 phy_speed = phy_data & 1023 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1024 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1025 *link_up = true; 1026 if (phy_speed == 1027 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1028 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1029 break; 1030 } 1031 } 1032 1033 return status; 1034 } 1035 1036 /** 1037 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1038 * @hw: pointer to hardware structure 1039 * 1040 * Restart auto-negotiation and PHY and waits for completion. 1041 **/ 1042 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1043 { 1044 s32 status = IXGBE_SUCCESS; 1045 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1046 bool autoneg = false; 1047 ixgbe_link_speed speed; 1048 1049 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1050 1051 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1052 1053 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1054 /* Set or unset auto-negotiation 10G advertisement */ 1055 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1056 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1057 &autoneg_reg); 1058 1059 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1060 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1061 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1062 1063 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1064 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1065 autoneg_reg); 1066 } 1067 1068 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1069 /* Set or unset auto-negotiation 1G advertisement */ 1070 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1071 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1072 &autoneg_reg); 1073 1074 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1075 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1076 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1077 1078 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1079 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1080 autoneg_reg); 1081 } 1082 1083 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1084 /* Set or unset auto-negotiation 100M advertisement */ 1085 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1086 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1087 &autoneg_reg); 1088 1089 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1090 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1091 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1092 1093 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1094 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1095 autoneg_reg); 1096 } 1097 1098 ixgbe_restart_auto_neg(hw); 1099 return status; 1100 } 1101 1102 /** 1103 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1104 * @hw: pointer to hardware structure 1105 * @firmware_version: pointer to the PHY Firmware Version 1106 **/ 1107 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1108 u16 *firmware_version) 1109 { 1110 s32 status; 1111 1112 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1113 1114 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1115 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1116 firmware_version); 1117 1118 return status; 1119 } 1120 1121 /** 1122 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1123 * @hw: pointer to hardware structure 1124 * @firmware_version: pointer to the PHY Firmware Version 1125 **/ 1126 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1127 u16 *firmware_version) 1128 { 1129 s32 status; 1130 1131 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1132 1133 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1134 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1135 firmware_version); 1136 1137 return status; 1138 } 1139 1140 /** 1141 * ixgbe_reset_phy_nl - Performs a PHY reset 1142 * @hw: pointer to hardware structure 1143 **/ 1144 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1145 { 1146 u16 phy_offset, control, eword, edata, block_crc; 1147 bool end_data = false; 1148 u16 list_offset, data_offset; 1149 u16 phy_data = 0; 1150 s32 ret_val = IXGBE_SUCCESS; 1151 u32 i; 1152 1153 DEBUGFUNC("ixgbe_reset_phy_nl"); 1154 1155 /* Blocked by MNG FW so bail */ 1156 if (ixgbe_check_reset_blocked(hw)) 1157 goto out; 1158 1159 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1160 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1161 1162 /* reset the PHY and poll for completion */ 1163 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1164 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1165 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1166 1167 for (i = 0; i < 100; i++) { 1168 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1169 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1170 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1171 break; 1172 msec_delay(10); 1173 } 1174 1175 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1176 DEBUGOUT("PHY reset did not complete.\n"); 1177 ret_val = IXGBE_ERR_PHY; 1178 goto out; 1179 } 1180 1181 /* Get init offsets */ 1182 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1183 &data_offset); 1184 if (ret_val != IXGBE_SUCCESS) 1185 goto out; 1186 1187 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1188 data_offset++; 1189 while (!end_data) { 1190 /* 1191 * Read control word from PHY init contents offset 1192 */ 1193 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1194 if (ret_val) 1195 goto err_eeprom; 1196 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1197 IXGBE_CONTROL_SHIFT_NL; 1198 edata = eword & IXGBE_DATA_MASK_NL; 1199 switch (control) { 1200 case IXGBE_DELAY_NL: 1201 data_offset++; 1202 DEBUGOUT1("DELAY: %d MS\n", edata); 1203 msec_delay(edata); 1204 break; 1205 case IXGBE_DATA_NL: 1206 DEBUGOUT("DATA:\n"); 1207 data_offset++; 1208 ret_val = hw->eeprom.ops.read(hw, data_offset, 1209 &phy_offset); 1210 if (ret_val) 1211 goto err_eeprom; 1212 data_offset++; 1213 for (i = 0; i < edata; i++) { 1214 ret_val = hw->eeprom.ops.read(hw, data_offset, 1215 &eword); 1216 if (ret_val) 1217 goto err_eeprom; 1218 hw->phy.ops.write_reg(hw, phy_offset, 1219 IXGBE_TWINAX_DEV, eword); 1220 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1221 phy_offset); 1222 data_offset++; 1223 phy_offset++; 1224 } 1225 break; 1226 case IXGBE_CONTROL_NL: 1227 data_offset++; 1228 DEBUGOUT("CONTROL:\n"); 1229 if (edata == IXGBE_CONTROL_EOL_NL) { 1230 DEBUGOUT("EOL\n"); 1231 end_data = true; 1232 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1233 DEBUGOUT("SOL\n"); 1234 } else { 1235 DEBUGOUT("Bad control value\n"); 1236 ret_val = IXGBE_ERR_PHY; 1237 goto out; 1238 } 1239 break; 1240 default: 1241 DEBUGOUT("Bad control type\n"); 1242 ret_val = IXGBE_ERR_PHY; 1243 goto out; 1244 } 1245 } 1246 1247 out: 1248 return ret_val; 1249 1250 err_eeprom: 1251 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1252 "eeprom read at offset %d failed", data_offset); 1253 return IXGBE_ERR_PHY; 1254 } 1255 1256 /** 1257 * ixgbe_identify_module_generic - Identifies module type 1258 * @hw: pointer to hardware structure 1259 * 1260 * Determines HW type and calls appropriate function. 1261 **/ 1262 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1263 { 1264 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1265 1266 DEBUGFUNC("ixgbe_identify_module_generic"); 1267 1268 switch (hw->mac.ops.get_media_type(hw)) { 1269 case ixgbe_media_type_fiber: 1270 status = ixgbe_identify_sfp_module_generic(hw); 1271 break; 1272 1273 case ixgbe_media_type_fiber_qsfp: 1274 status = ixgbe_identify_qsfp_module_generic(hw); 1275 break; 1276 1277 default: 1278 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1279 status = IXGBE_ERR_SFP_NOT_PRESENT; 1280 break; 1281 } 1282 1283 return status; 1284 } 1285 1286 /** 1287 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1288 * @hw: pointer to hardware structure 1289 * 1290 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1291 **/ 1292 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1293 { 1294 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1295 u32 vendor_oui = 0; 1296 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1297 u8 identifier = 0; 1298 u8 comp_codes_1g = 0; 1299 u8 comp_codes_10g = 0; 1300 u8 oui_bytes[3] = {0, 0, 0}; 1301 u8 cable_tech = 0; 1302 u8 cable_spec = 0; 1303 u16 enforce_sfp = 0; 1304 static bool warned_once = false; 1305 1306 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1307 1308 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1309 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1310 status = IXGBE_ERR_SFP_NOT_PRESENT; 1311 goto out; 1312 } 1313 1314 /* LAN ID is needed for I2C access */ 1315 hw->mac.ops.set_lan_id(hw); 1316 1317 status = hw->phy.ops.read_i2c_eeprom(hw, 1318 IXGBE_SFF_IDENTIFIER, 1319 &identifier); 1320 1321 if (status != IXGBE_SUCCESS) 1322 goto err_read_i2c_eeprom; 1323 1324 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1325 hw->phy.type = ixgbe_phy_sfp_unsupported; 1326 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1327 } else { 1328 status = hw->phy.ops.read_i2c_eeprom(hw, 1329 IXGBE_SFF_1GBE_COMP_CODES, 1330 &comp_codes_1g); 1331 1332 if (status != IXGBE_SUCCESS) 1333 goto err_read_i2c_eeprom; 1334 1335 status = hw->phy.ops.read_i2c_eeprom(hw, 1336 IXGBE_SFF_10GBE_COMP_CODES, 1337 &comp_codes_10g); 1338 1339 if (status != IXGBE_SUCCESS) 1340 goto err_read_i2c_eeprom; 1341 status = hw->phy.ops.read_i2c_eeprom(hw, 1342 IXGBE_SFF_CABLE_TECHNOLOGY, 1343 &cable_tech); 1344 1345 if (status != IXGBE_SUCCESS) 1346 goto err_read_i2c_eeprom; 1347 1348 /* ID Module 1349 * ========= 1350 * 0 SFP_DA_CU 1351 * 1 SFP_SR 1352 * 2 SFP_LR 1353 * 3 SFP_DA_CORE0 - 82599-specific 1354 * 4 SFP_DA_CORE1 - 82599-specific 1355 * 5 SFP_SR/LR_CORE0 - 82599-specific 1356 * 6 SFP_SR/LR_CORE1 - 82599-specific 1357 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1358 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1359 * 9 SFP_1g_cu_CORE0 - 82599-specific 1360 * 10 SFP_1g_cu_CORE1 - 82599-specific 1361 * 11 SFP_1g_sx_CORE0 - 82599-specific 1362 * 12 SFP_1g_sx_CORE1 - 82599-specific 1363 */ 1364 if (hw->mac.type == ixgbe_mac_82598EB) { 1365 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1366 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1367 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1368 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1369 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1370 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1371 else 1372 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1373 } else { 1374 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1375 if (hw->bus.lan_id == 0) 1376 hw->phy.sfp_type = 1377 ixgbe_sfp_type_da_cu_core0; 1378 else 1379 hw->phy.sfp_type = 1380 ixgbe_sfp_type_da_cu_core1; 1381 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1382 hw->phy.ops.read_i2c_eeprom( 1383 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1384 &cable_spec); 1385 if (cable_spec & 1386 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1387 if (hw->bus.lan_id == 0) 1388 hw->phy.sfp_type = 1389 ixgbe_sfp_type_da_act_lmt_core0; 1390 else 1391 hw->phy.sfp_type = 1392 ixgbe_sfp_type_da_act_lmt_core1; 1393 } else { 1394 hw->phy.sfp_type = 1395 ixgbe_sfp_type_unknown; 1396 } 1397 } else if (comp_codes_10g & 1398 (IXGBE_SFF_10GBASESR_CAPABLE | 1399 IXGBE_SFF_10GBASELR_CAPABLE)) { 1400 if (hw->bus.lan_id == 0) 1401 hw->phy.sfp_type = 1402 ixgbe_sfp_type_srlr_core0; 1403 else 1404 hw->phy.sfp_type = 1405 ixgbe_sfp_type_srlr_core1; 1406 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1407 if (hw->bus.lan_id == 0) 1408 hw->phy.sfp_type = 1409 ixgbe_sfp_type_1g_cu_core0; 1410 else 1411 hw->phy.sfp_type = 1412 ixgbe_sfp_type_1g_cu_core1; 1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1414 if (hw->bus.lan_id == 0) 1415 hw->phy.sfp_type = 1416 ixgbe_sfp_type_1g_sx_core0; 1417 else 1418 hw->phy.sfp_type = 1419 ixgbe_sfp_type_1g_sx_core1; 1420 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1421 if (hw->bus.lan_id == 0) 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_1g_lx_core0; 1424 else 1425 hw->phy.sfp_type = 1426 ixgbe_sfp_type_1g_lx_core1; 1427 } else { 1428 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1429 } 1430 } 1431 1432 if (hw->phy.sfp_type != stored_sfp_type) 1433 hw->phy.sfp_setup_needed = true; 1434 1435 /* Determine if the SFP+ PHY is dual speed or not. */ 1436 hw->phy.multispeed_fiber = false; 1437 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1438 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1439 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1440 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1441 hw->phy.multispeed_fiber = true; 1442 1443 /* Determine PHY vendor */ 1444 if (hw->phy.type != ixgbe_phy_nl) { 1445 hw->phy.id = identifier; 1446 status = hw->phy.ops.read_i2c_eeprom(hw, 1447 IXGBE_SFF_VENDOR_OUI_BYTE0, 1448 &oui_bytes[0]); 1449 1450 if (status != IXGBE_SUCCESS) 1451 goto err_read_i2c_eeprom; 1452 1453 status = hw->phy.ops.read_i2c_eeprom(hw, 1454 IXGBE_SFF_VENDOR_OUI_BYTE1, 1455 &oui_bytes[1]); 1456 1457 if (status != IXGBE_SUCCESS) 1458 goto err_read_i2c_eeprom; 1459 1460 status = hw->phy.ops.read_i2c_eeprom(hw, 1461 IXGBE_SFF_VENDOR_OUI_BYTE2, 1462 &oui_bytes[2]); 1463 1464 if (status != IXGBE_SUCCESS) 1465 goto err_read_i2c_eeprom; 1466 1467 vendor_oui = 1468 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1469 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1470 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1471 1472 switch (vendor_oui) { 1473 case IXGBE_SFF_VENDOR_OUI_TYCO: 1474 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1475 hw->phy.type = 1476 ixgbe_phy_sfp_passive_tyco; 1477 break; 1478 case IXGBE_SFF_VENDOR_OUI_FTL: 1479 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1480 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1481 else 1482 hw->phy.type = ixgbe_phy_sfp_ftl; 1483 break; 1484 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1485 hw->phy.type = ixgbe_phy_sfp_avago; 1486 break; 1487 case IXGBE_SFF_VENDOR_OUI_INTEL: 1488 hw->phy.type = ixgbe_phy_sfp_intel; 1489 break; 1490 default: 1491 hw->phy.type = ixgbe_phy_sfp_unknown; 1492 break; 1493 } 1494 } 1495 1496 /* Allow any DA cable vendor */ 1497 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1498 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1499 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1500 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1502 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1503 status = IXGBE_SUCCESS; 1504 goto out; 1505 } 1506 1507 /* Verify supported 1G SFP modules */ 1508 if (comp_codes_10g == 0 && 1509 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1515 hw->phy.type = ixgbe_phy_sfp_unsupported; 1516 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1517 goto out; 1518 } 1519 1520 /* Anything else 82598-based is supported */ 1521 if (hw->mac.type == ixgbe_mac_82598EB) { 1522 status = IXGBE_SUCCESS; 1523 goto out; 1524 } 1525 1526 ixgbe_get_device_caps(hw, &enforce_sfp); 1527 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1528 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1534 /* Make sure we're a supported PHY type */ 1535 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1536 status = IXGBE_SUCCESS; 1537 } else { 1538 if (hw->allow_unsupported_sfp == true) { 1539 if (!warned_once) 1540 EWARN(hw, 1541 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1542 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1543 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1544 warned_once = true; 1545 status = IXGBE_SUCCESS; 1546 } else { 1547 DEBUGOUT 1548 ("SFP+ module not supported\n"); 1549 hw->phy.type = 1550 ixgbe_phy_sfp_unsupported; 1551 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1552 } 1553 } 1554 } else { 1555 status = IXGBE_SUCCESS; 1556 } 1557 } 1558 1559 out: 1560 return status; 1561 1562 err_read_i2c_eeprom: 1563 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1564 if (hw->phy.type != ixgbe_phy_nl) { 1565 hw->phy.id = 0; 1566 hw->phy.type = ixgbe_phy_unknown; 1567 } 1568 return IXGBE_ERR_SFP_NOT_PRESENT; 1569 } 1570 1571 /** 1572 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1573 * @hw: pointer to hardware structure 1574 * 1575 * Determines physical layer capabilities of the current SFP. 1576 */ 1577 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1578 { 1579 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1580 u8 comp_codes_10g = 0; 1581 u8 comp_codes_1g = 0; 1582 1583 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1584 1585 hw->phy.ops.identify_sfp(hw); 1586 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1587 return physical_layer; 1588 1589 switch (hw->phy.type) { 1590 case ixgbe_phy_sfp_passive_tyco: 1591 case ixgbe_phy_sfp_passive_unknown: 1592 case ixgbe_phy_qsfp_passive_unknown: 1593 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1594 break; 1595 case ixgbe_phy_sfp_ftl_active: 1596 case ixgbe_phy_sfp_active_unknown: 1597 case ixgbe_phy_qsfp_active_unknown: 1598 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1599 break; 1600 case ixgbe_phy_sfp_avago: 1601 case ixgbe_phy_sfp_ftl: 1602 case ixgbe_phy_sfp_intel: 1603 case ixgbe_phy_sfp_unknown: 1604 hw->phy.ops.read_i2c_eeprom(hw, 1605 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1606 hw->phy.ops.read_i2c_eeprom(hw, 1607 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1608 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1609 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1610 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1611 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1612 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1613 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1614 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1615 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1616 break; 1617 case ixgbe_phy_qsfp_intel: 1618 case ixgbe_phy_qsfp_unknown: 1619 hw->phy.ops.read_i2c_eeprom(hw, 1620 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1621 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1622 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1623 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1624 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1625 break; 1626 default: 1627 break; 1628 } 1629 1630 return physical_layer; 1631 } 1632 1633 /** 1634 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1635 * @hw: pointer to hardware structure 1636 * 1637 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1638 **/ 1639 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1640 { 1641 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1642 u32 vendor_oui = 0; 1643 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1644 u8 identifier = 0; 1645 u8 comp_codes_1g = 0; 1646 u8 comp_codes_10g = 0; 1647 u8 oui_bytes[3] = {0, 0, 0}; 1648 u16 enforce_sfp = 0; 1649 u8 connector = 0; 1650 u8 cable_length = 0; 1651 u8 device_tech = 0; 1652 bool active_cable = false; 1653 static bool warned_once = false; 1654 1655 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1656 1657 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1658 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1659 status = IXGBE_ERR_SFP_NOT_PRESENT; 1660 goto out; 1661 } 1662 1663 /* LAN ID is needed for I2C access */ 1664 hw->mac.ops.set_lan_id(hw); 1665 1666 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1667 &identifier); 1668 1669 if (status != IXGBE_SUCCESS) 1670 goto err_read_i2c_eeprom; 1671 1672 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1673 hw->phy.type = ixgbe_phy_sfp_unsupported; 1674 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1675 goto out; 1676 } 1677 1678 hw->phy.id = identifier; 1679 1680 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1681 &comp_codes_10g); 1682 1683 if (status != IXGBE_SUCCESS) 1684 goto err_read_i2c_eeprom; 1685 1686 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1687 &comp_codes_1g); 1688 1689 if (status != IXGBE_SUCCESS) 1690 goto err_read_i2c_eeprom; 1691 1692 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1693 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1694 if (hw->bus.lan_id == 0) 1695 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1696 else 1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1698 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1699 IXGBE_SFF_10GBASELR_CAPABLE)) { 1700 if (hw->bus.lan_id == 0) 1701 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1702 else 1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1704 } else { 1705 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1706 active_cable = true; 1707 1708 if (!active_cable) { 1709 /* check for active DA cables that pre-date 1710 * SFF-8436 v3.6 */ 1711 hw->phy.ops.read_i2c_eeprom(hw, 1712 IXGBE_SFF_QSFP_CONNECTOR, 1713 &connector); 1714 1715 hw->phy.ops.read_i2c_eeprom(hw, 1716 IXGBE_SFF_QSFP_CABLE_LENGTH, 1717 &cable_length); 1718 1719 hw->phy.ops.read_i2c_eeprom(hw, 1720 IXGBE_SFF_QSFP_DEVICE_TECH, 1721 &device_tech); 1722 1723 if ((connector == 1724 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1725 (cable_length > 0) && 1726 ((device_tech >> 4) == 1727 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1728 active_cable = true; 1729 } 1730 1731 if (active_cable) { 1732 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1733 if (hw->bus.lan_id == 0) 1734 hw->phy.sfp_type = 1735 ixgbe_sfp_type_da_act_lmt_core0; 1736 else 1737 hw->phy.sfp_type = 1738 ixgbe_sfp_type_da_act_lmt_core1; 1739 } else { 1740 /* unsupported module type */ 1741 hw->phy.type = ixgbe_phy_sfp_unsupported; 1742 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1743 goto out; 1744 } 1745 } 1746 1747 if (hw->phy.sfp_type != stored_sfp_type) 1748 hw->phy.sfp_setup_needed = true; 1749 1750 /* Determine if the QSFP+ PHY is dual speed or not. */ 1751 hw->phy.multispeed_fiber = false; 1752 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1753 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1754 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1755 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1756 hw->phy.multispeed_fiber = true; 1757 1758 /* Determine PHY vendor for optical modules */ 1759 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1760 IXGBE_SFF_10GBASELR_CAPABLE)) { 1761 status = hw->phy.ops.read_i2c_eeprom(hw, 1762 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1763 &oui_bytes[0]); 1764 1765 if (status != IXGBE_SUCCESS) 1766 goto err_read_i2c_eeprom; 1767 1768 status = hw->phy.ops.read_i2c_eeprom(hw, 1769 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1770 &oui_bytes[1]); 1771 1772 if (status != IXGBE_SUCCESS) 1773 goto err_read_i2c_eeprom; 1774 1775 status = hw->phy.ops.read_i2c_eeprom(hw, 1776 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1777 &oui_bytes[2]); 1778 1779 if (status != IXGBE_SUCCESS) 1780 goto err_read_i2c_eeprom; 1781 1782 vendor_oui = 1783 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1784 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1785 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1786 1787 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1788 hw->phy.type = ixgbe_phy_qsfp_intel; 1789 else 1790 hw->phy.type = ixgbe_phy_qsfp_unknown; 1791 1792 ixgbe_get_device_caps(hw, &enforce_sfp); 1793 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1794 /* Make sure we're a supported PHY type */ 1795 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1796 status = IXGBE_SUCCESS; 1797 } else { 1798 if (hw->allow_unsupported_sfp == true) { 1799 if (!warned_once) 1800 EWARN(hw, 1801 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. " 1802 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1803 "Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1804 warned_once = true; 1805 status = IXGBE_SUCCESS; 1806 } else { 1807 DEBUGOUT("QSFP module not supported\n"); 1808 hw->phy.type = 1809 ixgbe_phy_sfp_unsupported; 1810 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1811 } 1812 } 1813 } else { 1814 status = IXGBE_SUCCESS; 1815 } 1816 } 1817 1818 out: 1819 return status; 1820 1821 err_read_i2c_eeprom: 1822 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1823 hw->phy.id = 0; 1824 hw->phy.type = ixgbe_phy_unknown; 1825 1826 return IXGBE_ERR_SFP_NOT_PRESENT; 1827 } 1828 1829 /** 1830 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1831 * @hw: pointer to hardware structure 1832 * @list_offset: offset to the SFP ID list 1833 * @data_offset: offset to the SFP data block 1834 * 1835 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1836 * so it returns the offsets to the phy init sequence block. 1837 **/ 1838 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1839 u16 *list_offset, 1840 u16 *data_offset) 1841 { 1842 u16 sfp_id; 1843 u16 sfp_type = hw->phy.sfp_type; 1844 1845 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1846 1847 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1848 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1849 1850 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1851 return IXGBE_ERR_SFP_NOT_PRESENT; 1852 1853 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1854 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1855 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1856 1857 /* 1858 * Limiting active cables and 1G Phys must be initialized as 1859 * SR modules 1860 */ 1861 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1862 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1863 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1864 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1865 sfp_type = ixgbe_sfp_type_srlr_core0; 1866 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1867 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1868 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1869 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1870 sfp_type = ixgbe_sfp_type_srlr_core1; 1871 1872 /* Read offset to PHY init contents */ 1873 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1874 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1875 "eeprom read at offset %d failed", 1876 IXGBE_PHY_INIT_OFFSET_NL); 1877 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1878 } 1879 1880 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1881 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1882 1883 /* Shift offset to first ID word */ 1884 (*list_offset)++; 1885 1886 /* 1887 * Find the matching SFP ID in the EEPROM 1888 * and program the init sequence 1889 */ 1890 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1891 goto err_phy; 1892 1893 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1894 if (sfp_id == sfp_type) { 1895 (*list_offset)++; 1896 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1897 goto err_phy; 1898 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1899 DEBUGOUT("SFP+ module not supported\n"); 1900 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1901 } else { 1902 break; 1903 } 1904 } else { 1905 (*list_offset) += 2; 1906 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1907 goto err_phy; 1908 } 1909 } 1910 1911 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1912 DEBUGOUT("No matching SFP+ module found\n"); 1913 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1914 } 1915 1916 return IXGBE_SUCCESS; 1917 1918 err_phy: 1919 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1920 "eeprom read at offset %d failed", *list_offset); 1921 return IXGBE_ERR_PHY; 1922 } 1923 1924 /** 1925 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1926 * @hw: pointer to hardware structure 1927 * @byte_offset: EEPROM byte offset to read 1928 * @eeprom_data: value read 1929 * 1930 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1931 **/ 1932 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1933 u8 *eeprom_data) 1934 { 1935 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1936 1937 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1938 IXGBE_I2C_EEPROM_DEV_ADDR, 1939 eeprom_data); 1940 } 1941 1942 /** 1943 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1944 * @hw: pointer to hardware structure 1945 * @byte_offset: byte offset at address 0xA2 1946 * @sff8472_data: value read 1947 * 1948 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1949 **/ 1950 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1951 u8 *sff8472_data) 1952 { 1953 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1954 IXGBE_I2C_EEPROM_DEV_ADDR2, 1955 sff8472_data); 1956 } 1957 1958 /** 1959 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1960 * @hw: pointer to hardware structure 1961 * @byte_offset: EEPROM byte offset to write 1962 * @eeprom_data: value to write 1963 * 1964 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1965 **/ 1966 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1967 u8 eeprom_data) 1968 { 1969 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1970 1971 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1972 IXGBE_I2C_EEPROM_DEV_ADDR, 1973 eeprom_data); 1974 } 1975 1976 /** 1977 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 1978 * @hw: pointer to hardware structure 1979 * @offset: eeprom offset to be read 1980 * @addr: I2C address to be read 1981 */ 1982 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1983 { 1984 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1985 offset == IXGBE_SFF_IDENTIFIER && 1986 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1987 return true; 1988 return false; 1989 } 1990 1991 /** 1992 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1993 * @hw: pointer to hardware structure 1994 * @byte_offset: byte offset to read 1995 * @dev_addr: address to read from 1996 * @data: value read 1997 * @lock: true if to take and release semaphore 1998 * 1999 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2000 * a specified device address. 2001 **/ 2002 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2003 u8 dev_addr, u8 *data, bool lock) 2004 { 2005 s32 status; 2006 u32 max_retry = 10; 2007 u32 retry = 0; 2008 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2009 bool nack = 1; 2010 *data = 0; 2011 2012 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2013 2014 if (hw->mac.type >= ixgbe_mac_X550) 2015 max_retry = 3; 2016 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2017 max_retry = IXGBE_SFP_DETECT_RETRIES; 2018 2019 do { 2020 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2021 return IXGBE_ERR_SWFW_SYNC; 2022 2023 ixgbe_i2c_start(hw); 2024 2025 /* Device Address and write indication */ 2026 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2027 if (status != IXGBE_SUCCESS) 2028 goto fail; 2029 2030 status = ixgbe_get_i2c_ack(hw); 2031 if (status != IXGBE_SUCCESS) 2032 goto fail; 2033 2034 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2035 if (status != IXGBE_SUCCESS) 2036 goto fail; 2037 2038 status = ixgbe_get_i2c_ack(hw); 2039 if (status != IXGBE_SUCCESS) 2040 goto fail; 2041 2042 ixgbe_i2c_start(hw); 2043 2044 /* Device Address and read indication */ 2045 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2046 if (status != IXGBE_SUCCESS) 2047 goto fail; 2048 2049 status = ixgbe_get_i2c_ack(hw); 2050 if (status != IXGBE_SUCCESS) 2051 goto fail; 2052 2053 ixgbe_clock_in_i2c_byte(hw, data); 2054 2055 status = ixgbe_clock_out_i2c_bit(hw, nack); 2056 if (status != IXGBE_SUCCESS) 2057 goto fail; 2058 2059 ixgbe_i2c_stop(hw); 2060 if (lock) 2061 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2062 return IXGBE_SUCCESS; 2063 2064 fail: 2065 ixgbe_i2c_bus_clear(hw); 2066 if (lock) { 2067 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2068 msec_delay(100); 2069 } 2070 if (retry < max_retry) 2071 DEBUGOUT("I2C byte read error - Retrying.\n"); 2072 else 2073 DEBUGOUT("I2C byte read error.\n"); 2074 retry++; 2075 } while (retry <= max_retry); 2076 2077 return status; 2078 } 2079 2080 /** 2081 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2082 * @hw: pointer to hardware structure 2083 * @byte_offset: byte offset to read 2084 * @dev_addr: address to read from 2085 * @data: value read 2086 * 2087 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2088 * a specified device address. 2089 **/ 2090 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2091 u8 dev_addr, u8 *data) 2092 { 2093 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2094 data, true); 2095 } 2096 2097 /** 2098 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2099 * @hw: pointer to hardware structure 2100 * @byte_offset: byte offset to read 2101 * @dev_addr: address to read from 2102 * @data: value read 2103 * 2104 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2105 * a specified device address. 2106 **/ 2107 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2108 u8 dev_addr, u8 *data) 2109 { 2110 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2111 data, false); 2112 } 2113 2114 /** 2115 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2116 * @hw: pointer to hardware structure 2117 * @byte_offset: byte offset to write 2118 * @dev_addr: address to write to 2119 * @data: value to write 2120 * @lock: true if to take and release semaphore 2121 * 2122 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2123 * a specified device address. 2124 **/ 2125 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2126 u8 dev_addr, u8 data, bool lock) 2127 { 2128 s32 status; 2129 u32 max_retry = 1; 2130 u32 retry = 0; 2131 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2132 2133 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2134 2135 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2136 IXGBE_SUCCESS) 2137 return IXGBE_ERR_SWFW_SYNC; 2138 2139 do { 2140 ixgbe_i2c_start(hw); 2141 2142 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2143 if (status != IXGBE_SUCCESS) 2144 goto fail; 2145 2146 status = ixgbe_get_i2c_ack(hw); 2147 if (status != IXGBE_SUCCESS) 2148 goto fail; 2149 2150 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2151 if (status != IXGBE_SUCCESS) 2152 goto fail; 2153 2154 status = ixgbe_get_i2c_ack(hw); 2155 if (status != IXGBE_SUCCESS) 2156 goto fail; 2157 2158 status = ixgbe_clock_out_i2c_byte(hw, data); 2159 if (status != IXGBE_SUCCESS) 2160 goto fail; 2161 2162 status = ixgbe_get_i2c_ack(hw); 2163 if (status != IXGBE_SUCCESS) 2164 goto fail; 2165 2166 ixgbe_i2c_stop(hw); 2167 if (lock) 2168 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2169 return IXGBE_SUCCESS; 2170 2171 fail: 2172 ixgbe_i2c_bus_clear(hw); 2173 if (retry < max_retry) 2174 DEBUGOUT("I2C byte write error - Retrying.\n"); 2175 else 2176 DEBUGOUT("I2C byte write error.\n"); 2177 retry++; 2178 } while (retry <= max_retry); 2179 2180 if (lock) 2181 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2182 2183 return status; 2184 } 2185 2186 /** 2187 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2188 * @hw: pointer to hardware structure 2189 * @byte_offset: byte offset to write 2190 * @dev_addr: address to write to 2191 * @data: value to write 2192 * 2193 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2194 * a specified device address. 2195 **/ 2196 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2197 u8 dev_addr, u8 data) 2198 { 2199 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2200 data, true); 2201 } 2202 2203 /** 2204 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2205 * @hw: pointer to hardware structure 2206 * @byte_offset: byte offset to write 2207 * @dev_addr: address to write to 2208 * @data: value to write 2209 * 2210 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2211 * a specified device address. 2212 **/ 2213 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2214 u8 dev_addr, u8 data) 2215 { 2216 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2217 data, false); 2218 } 2219 2220 /** 2221 * ixgbe_i2c_start - Sets I2C start condition 2222 * @hw: pointer to hardware structure 2223 * 2224 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2225 * Set bit-bang mode on X550 hardware. 2226 **/ 2227 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2228 { 2229 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2230 2231 DEBUGFUNC("ixgbe_i2c_start"); 2232 2233 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2234 2235 /* Start condition must begin with data and clock high */ 2236 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2237 ixgbe_raise_i2c_clk(hw, &i2cctl); 2238 2239 /* Setup time for start condition (4.7us) */ 2240 usec_delay(IXGBE_I2C_T_SU_STA); 2241 2242 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2243 2244 /* Hold time for start condition (4us) */ 2245 usec_delay(IXGBE_I2C_T_HD_STA); 2246 2247 ixgbe_lower_i2c_clk(hw, &i2cctl); 2248 2249 /* Minimum low period of clock is 4.7 us */ 2250 usec_delay(IXGBE_I2C_T_LOW); 2251 2252 } 2253 2254 /** 2255 * ixgbe_i2c_stop - Sets I2C stop condition 2256 * @hw: pointer to hardware structure 2257 * 2258 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2259 * Disables bit-bang mode and negates data output enable on X550 2260 * hardware. 2261 **/ 2262 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2263 { 2264 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2265 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2266 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2267 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2268 2269 DEBUGFUNC("ixgbe_i2c_stop"); 2270 2271 /* Stop condition must begin with data low and clock high */ 2272 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2273 ixgbe_raise_i2c_clk(hw, &i2cctl); 2274 2275 /* Setup time for stop condition (4us) */ 2276 usec_delay(IXGBE_I2C_T_SU_STO); 2277 2278 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2279 2280 /* bus free time between stop and start (4.7us)*/ 2281 usec_delay(IXGBE_I2C_T_BUF); 2282 2283 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2284 i2cctl &= ~bb_en_bit; 2285 i2cctl |= data_oe_bit | clk_oe_bit; 2286 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2287 IXGBE_WRITE_FLUSH(hw); 2288 } 2289 } 2290 2291 /** 2292 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2293 * @hw: pointer to hardware structure 2294 * @data: data byte to clock in 2295 * 2296 * Clocks in one byte data via I2C data/clock 2297 **/ 2298 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2299 { 2300 s32 i; 2301 bool bit = 0; 2302 2303 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2304 2305 *data = 0; 2306 for (i = 7; i >= 0; i--) { 2307 ixgbe_clock_in_i2c_bit(hw, &bit); 2308 *data |= bit << i; 2309 } 2310 } 2311 2312 /** 2313 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2314 * @hw: pointer to hardware structure 2315 * @data: data byte clocked out 2316 * 2317 * Clocks out one byte data via I2C data/clock 2318 **/ 2319 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2320 { 2321 s32 status = IXGBE_SUCCESS; 2322 s32 i; 2323 u32 i2cctl; 2324 bool bit; 2325 2326 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2327 2328 for (i = 7; i >= 0; i--) { 2329 bit = (data >> i) & 0x1; 2330 status = ixgbe_clock_out_i2c_bit(hw, bit); 2331 2332 if (status != IXGBE_SUCCESS) 2333 break; 2334 } 2335 2336 /* Release SDA line (set high) */ 2337 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2338 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2339 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2340 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2341 IXGBE_WRITE_FLUSH(hw); 2342 2343 return status; 2344 } 2345 2346 /** 2347 * ixgbe_get_i2c_ack - Polls for I2C ACK 2348 * @hw: pointer to hardware structure 2349 * 2350 * Clocks in/out one bit via I2C data/clock 2351 **/ 2352 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2353 { 2354 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2355 s32 status = IXGBE_SUCCESS; 2356 u32 i = 0; 2357 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2358 u32 timeout = 10; 2359 bool ack = 1; 2360 2361 DEBUGFUNC("ixgbe_get_i2c_ack"); 2362 2363 if (data_oe_bit) { 2364 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2365 i2cctl |= data_oe_bit; 2366 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2367 IXGBE_WRITE_FLUSH(hw); 2368 } 2369 ixgbe_raise_i2c_clk(hw, &i2cctl); 2370 2371 /* Minimum high period of clock is 4us */ 2372 usec_delay(IXGBE_I2C_T_HIGH); 2373 2374 /* Poll for ACK. Note that ACK in I2C spec is 2375 * transition from 1 to 0 */ 2376 for (i = 0; i < timeout; i++) { 2377 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2378 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2379 2380 usec_delay(1); 2381 if (!ack) 2382 break; 2383 } 2384 2385 if (ack) { 2386 DEBUGOUT("I2C ack was not received.\n"); 2387 status = IXGBE_ERR_I2C; 2388 } 2389 2390 ixgbe_lower_i2c_clk(hw, &i2cctl); 2391 2392 /* Minimum low period of clock is 4.7 us */ 2393 usec_delay(IXGBE_I2C_T_LOW); 2394 2395 return status; 2396 } 2397 2398 /** 2399 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2400 * @hw: pointer to hardware structure 2401 * @data: read data value 2402 * 2403 * Clocks in one bit via I2C data/clock 2404 **/ 2405 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2406 { 2407 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2408 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2409 2410 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2411 2412 if (data_oe_bit) { 2413 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2414 i2cctl |= data_oe_bit; 2415 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2416 IXGBE_WRITE_FLUSH(hw); 2417 } 2418 ixgbe_raise_i2c_clk(hw, &i2cctl); 2419 2420 /* Minimum high period of clock is 4us */ 2421 usec_delay(IXGBE_I2C_T_HIGH); 2422 2423 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2424 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2425 2426 ixgbe_lower_i2c_clk(hw, &i2cctl); 2427 2428 /* Minimum low period of clock is 4.7 us */ 2429 usec_delay(IXGBE_I2C_T_LOW); 2430 } 2431 2432 /** 2433 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2434 * @hw: pointer to hardware structure 2435 * @data: data value to write 2436 * 2437 * Clocks out one bit via I2C data/clock 2438 **/ 2439 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2440 { 2441 s32 status; 2442 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2443 2444 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2445 2446 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2447 if (status == IXGBE_SUCCESS) { 2448 ixgbe_raise_i2c_clk(hw, &i2cctl); 2449 2450 /* Minimum high period of clock is 4us */ 2451 usec_delay(IXGBE_I2C_T_HIGH); 2452 2453 ixgbe_lower_i2c_clk(hw, &i2cctl); 2454 2455 /* Minimum low period of clock is 4.7 us. 2456 * This also takes care of the data hold time. 2457 */ 2458 usec_delay(IXGBE_I2C_T_LOW); 2459 } else { 2460 status = IXGBE_ERR_I2C; 2461 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2462 "I2C data was not set to %X\n", data); 2463 } 2464 2465 return status; 2466 } 2467 2468 /** 2469 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2470 * @hw: pointer to hardware structure 2471 * @i2cctl: Current value of I2CCTL register 2472 * 2473 * Raises the I2C clock line '0'->'1' 2474 * Negates the I2C clock output enable on X550 hardware. 2475 **/ 2476 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2477 { 2478 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2479 u32 i = 0; 2480 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2481 u32 i2cctl_r = 0; 2482 2483 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2484 2485 if (clk_oe_bit) { 2486 *i2cctl |= clk_oe_bit; 2487 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2488 } 2489 2490 for (i = 0; i < timeout; i++) { 2491 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2492 2493 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2494 IXGBE_WRITE_FLUSH(hw); 2495 /* SCL rise time (1000ns) */ 2496 usec_delay(IXGBE_I2C_T_RISE); 2497 2498 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2499 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2500 break; 2501 } 2502 } 2503 2504 /** 2505 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2506 * @hw: pointer to hardware structure 2507 * @i2cctl: Current value of I2CCTL register 2508 * 2509 * Lowers the I2C clock line '1'->'0' 2510 * Asserts the I2C clock output enable on X550 hardware. 2511 **/ 2512 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2513 { 2514 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2515 2516 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2517 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2518 2519 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2520 IXGBE_WRITE_FLUSH(hw); 2521 2522 /* SCL fall time (300ns) */ 2523 usec_delay(IXGBE_I2C_T_FALL); 2524 } 2525 2526 /** 2527 * ixgbe_set_i2c_data - Sets the I2C data bit 2528 * @hw: pointer to hardware structure 2529 * @i2cctl: Current value of I2CCTL register 2530 * @data: I2C data value (0 or 1) to set 2531 * 2532 * Sets the I2C data bit 2533 * Asserts the I2C data output enable on X550 hardware. 2534 **/ 2535 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2536 { 2537 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2538 s32 status = IXGBE_SUCCESS; 2539 2540 DEBUGFUNC("ixgbe_set_i2c_data"); 2541 2542 if (data) 2543 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2544 else 2545 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2546 *i2cctl &= ~data_oe_bit; 2547 2548 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2549 IXGBE_WRITE_FLUSH(hw); 2550 2551 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2552 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2553 2554 if (!data) /* Can't verify data in this case */ 2555 return IXGBE_SUCCESS; 2556 if (data_oe_bit) { 2557 *i2cctl |= data_oe_bit; 2558 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2559 IXGBE_WRITE_FLUSH(hw); 2560 } 2561 2562 /* Verify data was set correctly */ 2563 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2564 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2565 status = IXGBE_ERR_I2C; 2566 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2567 "Error - I2C data was not set to %X.\n", 2568 data); 2569 } 2570 2571 return status; 2572 } 2573 2574 /** 2575 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2576 * @hw: pointer to hardware structure 2577 * @i2cctl: Current value of I2CCTL register 2578 * 2579 * Returns the I2C data bit value 2580 * Negates the I2C data output enable on X550 hardware. 2581 **/ 2582 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2583 { 2584 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2585 bool data; 2586 2587 DEBUGFUNC("ixgbe_get_i2c_data"); 2588 2589 if (data_oe_bit) { 2590 *i2cctl |= data_oe_bit; 2591 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2592 IXGBE_WRITE_FLUSH(hw); 2593 usec_delay(IXGBE_I2C_T_FALL); 2594 } 2595 2596 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2597 data = 1; 2598 else 2599 data = 0; 2600 2601 return data; 2602 } 2603 2604 /** 2605 * ixgbe_i2c_bus_clear - Clears the I2C bus 2606 * @hw: pointer to hardware structure 2607 * 2608 * Clears the I2C bus by sending nine clock pulses. 2609 * Used when data line is stuck low. 2610 **/ 2611 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2612 { 2613 u32 i2cctl; 2614 u32 i; 2615 2616 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2617 2618 ixgbe_i2c_start(hw); 2619 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2620 2621 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2622 2623 for (i = 0; i < 9; i++) { 2624 ixgbe_raise_i2c_clk(hw, &i2cctl); 2625 2626 /* Min high period of clock is 4us */ 2627 usec_delay(IXGBE_I2C_T_HIGH); 2628 2629 ixgbe_lower_i2c_clk(hw, &i2cctl); 2630 2631 /* Min low period of clock is 4.7us*/ 2632 usec_delay(IXGBE_I2C_T_LOW); 2633 } 2634 2635 ixgbe_i2c_start(hw); 2636 2637 /* Put the i2c bus back to default state */ 2638 ixgbe_i2c_stop(hw); 2639 } 2640 2641 /** 2642 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2643 * @hw: pointer to hardware structure 2644 * 2645 * Checks if the LASI temp alarm status was triggered due to overtemp 2646 **/ 2647 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2648 { 2649 s32 status = IXGBE_SUCCESS; 2650 u16 phy_data = 0; 2651 2652 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2653 2654 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2655 goto out; 2656 2657 /* Check that the LASI temp alarm status was triggered */ 2658 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2659 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2660 2661 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2662 goto out; 2663 2664 status = IXGBE_ERR_OVERTEMP; 2665 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2666 out: 2667 return status; 2668 } 2669 2670 /** 2671 * ixgbe_set_copper_phy_power - Control power for copper phy 2672 * @hw: pointer to hardware structure 2673 * @on: true for on, false for off 2674 */ 2675 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2676 { 2677 u32 status; 2678 u16 reg; 2679 2680 if (!on && ixgbe_mng_present(hw)) 2681 return 0; 2682 2683 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2684 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2685 ®); 2686 if (status) 2687 return status; 2688 2689 if (on) { 2690 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2691 } else { 2692 if (ixgbe_check_reset_blocked(hw)) 2693 return 0; 2694 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2695 } 2696 2697 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2698 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2699 reg); 2700 return status; 2701 } 2702