1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #ifndef _IXGBE_DCB_82599_H_ 37 #define _IXGBE_DCB_82599_H_ 38 39 /* DCB register definitions */ 40 #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, 41 * 1 WSP - Weighted Strict Priority 42 */ 43 #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, 44 * 1 WRR - Weighted Round Robin 45 */ 46 #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ 47 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ 48 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must 49 * clear! 50 */ 51 #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ 52 53 /* Receive UP2TC mapping */ 54 #define IXGBE_RTRUP2TC_UP_SHIFT 3 55 #define IXGBE_RTRUP2TC_UP_MASK 7 56 /* Transmit UP2TC mapping */ 57 #define IXGBE_RTTUP2TC_UP_SHIFT 3 58 59 #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 60 #define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ 61 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ 62 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ 63 64 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 65 * buffers enable 66 */ 67 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 68 * (RSS) enable 69 */ 70 71 /* RTRPCS Bit Masks */ 72 #define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 73 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 74 #define IXGBE_RTRPCS_RAC 0x00000004 75 #define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 76 77 /* RTTDT2C Bit Masks */ 78 #define IXGBE_RTTDT2C_MCL_SHIFT 12 79 #define IXGBE_RTTDT2C_BWG_SHIFT 9 80 #define IXGBE_RTTDT2C_GSP 0x40000000 81 #define IXGBE_RTTDT2C_LSP 0x80000000 82 83 #define IXGBE_RTTPT2C_MCL_SHIFT 12 84 #define IXGBE_RTTPT2C_BWG_SHIFT 9 85 #define IXGBE_RTTPT2C_GSP 0x40000000 86 #define IXGBE_RTTPT2C_LSP 0x80000000 87 88 /* RTTPCS Bit Masks */ 89 #define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, 90 * 1 SP - Strict Priority 91 */ 92 #define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ 93 #define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ 94 #define IXGBE_RTTPCS_ARBD_SHIFT 22 95 #define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ 96 97 #define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ 98 99 /* SECTXMINIFG DCB */ 100 #define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */ 101 102 /* BCN register definitions */ 103 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 104 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 105 106 #define IXGBE_RTTBCNCR_MNG_CMTGI 0x00000001 107 #define IXGBE_RTTBCNCR_MGN_BCNA_MODE 0x00000002 108 #define IXGBE_RTTBCNCR_RSV7_11_SHIFT 5 109 #define IXGBE_RTTBCNCR_G 0x00000400 110 #define IXGBE_RTTBCNCR_I 0x00000800 111 #define IXGBE_RTTBCNCR_H 0x00001000 112 #define IXGBE_RTTBCNCR_VER_SHIFT 14 113 #define IXGBE_RTTBCNCR_CMT_ETH_SHIFT 16 114 115 #define IXGBE_RTTBCNACL_SMAC_L_SHIFT 16 116 117 #define IXGBE_RTTBCNTG_BCNA_MODE 0x80000000 118 119 #define IXGBE_RTTBCNRTT_TS_SHIFT 3 120 #define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT 16 121 122 #define IXGBE_RTTBCNRD_BCN_CLEAR_ALL 0x00000002 123 #define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT 2 124 #define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT 16 125 #define IXGBE_RTTBCNRD_DRIFT_ENA 0x80000000 126 127 128 /* DCB driver APIs */ 129 130 /* DCB PFC */ 131 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *); 132 133 /* DCB stats */ 134 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *, 135 struct ixgbe_dcb_config *); 136 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *, 137 struct ixgbe_hw_stats *, u8); 138 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *, 139 struct ixgbe_hw_stats *, u8); 140 141 /* DCB config arbiters */ 142 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 143 u8 *, u8 *); 144 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 145 u8 *, u8 *, u8 *); 146 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *, 147 u8 *, u8 *); 148 149 /* DCB initialization */ 150 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *, 151 struct ixgbe_dcb_config *); 152 153 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, 154 u8 *, u8 *); 155 #endif /* _IXGBE_DCB_82959_H_ */ 156