1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 #include "ixgbe_dcb.h" 38 #include "ixgbe_dcb_82599.h" 39 #include "ixgbe_api.h" 40 41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 47 u16 count); 48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 52 53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 55 u16 *san_mac_offset); 56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 57 u16 words, u16 *data); 58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 59 u16 words, u16 *data); 60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 61 u16 offset); 62 63 /** 64 * ixgbe_init_ops_generic - Inits function ptrs 65 * @hw: pointer to the hardware structure 66 * 67 * Initialize the function pointers. 68 **/ 69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 70 { 71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 72 struct ixgbe_mac_info *mac = &hw->mac; 73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 74 75 DEBUGFUNC("ixgbe_init_ops_generic"); 76 77 /* EEPROM */ 78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 80 if (eec & IXGBE_EEC_PRES) { 81 eeprom->ops.read = ixgbe_read_eerd_generic; 82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 83 } else { 84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 85 eeprom->ops.read_buffer = 86 ixgbe_read_eeprom_buffer_bit_bang_generic; 87 } 88 eeprom->ops.write = ixgbe_write_eeprom_generic; 89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 90 eeprom->ops.validate_checksum = 91 ixgbe_validate_eeprom_checksum_generic; 92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 94 eeprom->ops.read_pba_string = ixgbe_read_pba_string_generic; 95 96 /* MAC */ 97 mac->ops.init_hw = ixgbe_init_hw_generic; 98 mac->ops.reset_hw = NULL; 99 mac->ops.start_hw = ixgbe_start_hw_generic; 100 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 101 mac->ops.get_media_type = NULL; 102 mac->ops.get_supported_physical_layer = NULL; 103 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 104 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 105 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 106 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 107 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 108 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 109 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 110 mac->ops.prot_autoc_read = prot_autoc_read_generic; 111 mac->ops.prot_autoc_write = prot_autoc_write_generic; 112 113 /* LEDs */ 114 mac->ops.led_on = ixgbe_led_on_generic; 115 mac->ops.led_off = ixgbe_led_off_generic; 116 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 117 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 118 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 119 120 /* RAR, Multicast, VLAN */ 121 mac->ops.set_rar = ixgbe_set_rar_generic; 122 mac->ops.clear_rar = ixgbe_clear_rar_generic; 123 mac->ops.insert_mac_addr = NULL; 124 mac->ops.set_vmdq = NULL; 125 mac->ops.clear_vmdq = NULL; 126 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 127 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 128 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 129 mac->ops.enable_mc = ixgbe_enable_mc_generic; 130 mac->ops.disable_mc = ixgbe_disable_mc_generic; 131 mac->ops.clear_vfta = NULL; 132 mac->ops.set_vfta = NULL; 133 mac->ops.set_vlvf = NULL; 134 mac->ops.init_uta_tables = NULL; 135 mac->ops.enable_rx = ixgbe_enable_rx_generic; 136 mac->ops.disable_rx = ixgbe_disable_rx_generic; 137 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic; 138 139 /* Flow Control */ 140 mac->ops.fc_enable = ixgbe_fc_enable_generic; 141 mac->ops.setup_fc = ixgbe_setup_fc_generic; 142 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 143 144 /* Link */ 145 mac->ops.get_link_capabilities = NULL; 146 mac->ops.setup_link = NULL; 147 mac->ops.check_link = NULL; 148 mac->ops.dmac_config = NULL; 149 mac->ops.dmac_update_tcs = NULL; 150 mac->ops.dmac_config_tcs = NULL; 151 152 return IXGBE_SUCCESS; 153 } 154 155 /** 156 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 157 * of flow control 158 * @hw: pointer to hardware structure 159 * 160 * This function returns true if the device supports flow control 161 * autonegotiation, and false if it does not. 162 * 163 **/ 164 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 165 { 166 bool supported = false; 167 ixgbe_link_speed speed; 168 bool link_up; 169 170 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 171 172 switch (hw->phy.media_type) { 173 case ixgbe_media_type_fiber_fixed: 174 case ixgbe_media_type_fiber_qsfp: 175 case ixgbe_media_type_fiber: 176 /* flow control autoneg block list */ 177 switch (hw->device_id) { 178 case IXGBE_DEV_ID_X550EM_A_SFP: 179 case IXGBE_DEV_ID_X550EM_A_SFP_N: 180 case IXGBE_DEV_ID_X550EM_A_QSFP: 181 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 182 case IXGBE_DEV_ID_E610_SFP: 183 supported = false; 184 break; 185 default: 186 hw->mac.ops.check_link(hw, &speed, &link_up, false); 187 /* if link is down, assume supported */ 188 if (link_up) 189 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 190 true : false; 191 else 192 supported = true; 193 } 194 195 break; 196 case ixgbe_media_type_backplane: 197 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 198 supported = false; 199 else 200 supported = true; 201 break; 202 case ixgbe_media_type_copper: 203 /* only some copper devices support flow control autoneg */ 204 switch (hw->device_id) { 205 case IXGBE_DEV_ID_82599_T3_LOM: 206 case IXGBE_DEV_ID_X540T: 207 case IXGBE_DEV_ID_X540T1: 208 case IXGBE_DEV_ID_X540_BYPASS: 209 case IXGBE_DEV_ID_X550T: 210 case IXGBE_DEV_ID_X550T1: 211 case IXGBE_DEV_ID_X550EM_X_10G_T: 212 case IXGBE_DEV_ID_X550EM_A_10G_T: 213 case IXGBE_DEV_ID_X550EM_A_1G_T: 214 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 215 case IXGBE_DEV_ID_E610_10G_T: 216 case IXGBE_DEV_ID_E610_2_5G_T: 217 supported = true; 218 break; 219 default: 220 supported = false; 221 } 222 default: 223 break; 224 } 225 226 if (!supported) 227 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 228 "Device %x does not support flow control autoneg", 229 hw->device_id); 230 231 return supported; 232 } 233 234 /** 235 * ixgbe_setup_fc_generic - Set up flow control 236 * @hw: pointer to hardware structure 237 * 238 * Called at init time to set up flow control. 239 **/ 240 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 241 { 242 s32 ret_val = IXGBE_SUCCESS; 243 u32 reg = 0, reg_bp = 0; 244 u16 reg_cu = 0; 245 bool locked = false; 246 247 DEBUGFUNC("ixgbe_setup_fc_generic"); 248 249 /* Validate the requested mode */ 250 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 251 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 252 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 253 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 254 goto out; 255 } 256 257 /* 258 * 10gig parts do not have a word in the EEPROM to determine the 259 * default flow control setting, so we explicitly set it to full. 260 */ 261 if (hw->fc.requested_mode == ixgbe_fc_default) 262 hw->fc.requested_mode = ixgbe_fc_full; 263 264 /* 265 * Set up the 1G and 10G flow control advertisement registers so the 266 * HW will be able to do fc autoneg once the cable is plugged in. If 267 * we link at 10G, the 1G advertisement is harmless and vice versa. 268 */ 269 switch (hw->phy.media_type) { 270 case ixgbe_media_type_backplane: 271 /* some MAC's need RMW protection on AUTOC */ 272 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 273 if (ret_val != IXGBE_SUCCESS) 274 goto out; 275 276 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 277 break; 278 case ixgbe_media_type_fiber_fixed: 279 case ixgbe_media_type_fiber_qsfp: 280 case ixgbe_media_type_fiber: 281 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 282 283 break; 284 case ixgbe_media_type_copper: 285 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 286 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 287 break; 288 default: 289 break; 290 } 291 292 /* 293 * The possible values of fc.requested_mode are: 294 * 0: Flow control is completely disabled 295 * 1: Rx flow control is enabled (we can receive pause frames, 296 * but not send pause frames). 297 * 2: Tx flow control is enabled (we can send pause frames but 298 * we do not support receiving pause frames). 299 * 3: Both Rx and Tx flow control (symmetric) are enabled. 300 * other: Invalid. 301 */ 302 switch (hw->fc.requested_mode) { 303 case ixgbe_fc_none: 304 /* Flow control completely disabled by software override. */ 305 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 306 if (hw->phy.media_type == ixgbe_media_type_backplane) 307 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 308 IXGBE_AUTOC_ASM_PAUSE); 309 else if (hw->phy.media_type == ixgbe_media_type_copper) 310 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 311 break; 312 case ixgbe_fc_tx_pause: 313 /* 314 * Tx Flow control is enabled, and Rx Flow control is 315 * disabled by software override. 316 */ 317 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 318 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 319 if (hw->phy.media_type == ixgbe_media_type_backplane) { 320 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 321 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 322 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 323 reg_cu |= IXGBE_TAF_ASM_PAUSE; 324 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 325 } 326 break; 327 case ixgbe_fc_rx_pause: 328 /* 329 * Rx Flow control is enabled and Tx Flow control is 330 * disabled by software override. Since there really 331 * isn't a way to advertise that we are capable of RX 332 * Pause ONLY, we will advertise that we support both 333 * symmetric and asymmetric Rx PAUSE, as such we fall 334 * through to the fc_full statement. Later, we will 335 * disable the adapter's ability to send PAUSE frames. 336 */ 337 case ixgbe_fc_full: 338 /* Flow control (both Rx and Tx) is enabled by SW override. */ 339 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 340 if (hw->phy.media_type == ixgbe_media_type_backplane) 341 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 342 IXGBE_AUTOC_ASM_PAUSE; 343 else if (hw->phy.media_type == ixgbe_media_type_copper) 344 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 345 break; 346 default: 347 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 348 "Flow control param set incorrectly\n"); 349 ret_val = IXGBE_ERR_CONFIG; 350 goto out; 351 break; 352 } 353 354 if (hw->mac.type < ixgbe_mac_X540) { 355 /* 356 * Enable auto-negotiation between the MAC & PHY; 357 * the MAC will advertise clause 37 flow control. 358 */ 359 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 360 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 361 362 /* Disable AN timeout */ 363 if (hw->fc.strict_ieee) 364 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 365 366 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 367 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 368 } 369 370 /* 371 * AUTOC restart handles negotiation of 1G and 10G on backplane 372 * and copper. There is no need to set the PCS1GCTL register. 373 * 374 */ 375 if (hw->phy.media_type == ixgbe_media_type_backplane) { 376 reg_bp |= IXGBE_AUTOC_AN_RESTART; 377 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 378 if (ret_val) 379 goto out; 380 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 381 (ixgbe_device_supports_autoneg_fc(hw))) { 382 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 383 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 384 } 385 386 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 387 out: 388 return ret_val; 389 } 390 391 /** 392 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 393 * @hw: pointer to hardware structure 394 * 395 * Starts the hardware by filling the bus info structure and media type, clears 396 * all on chip counters, initializes receive address registers, multicast 397 * table, VLAN filter table, calls routine to set up link and flow control 398 * settings, and leaves transmit and receive units disabled and uninitialized 399 **/ 400 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 401 { 402 s32 ret_val; 403 u32 ctrl_ext; 404 u16 device_caps; 405 406 DEBUGFUNC("ixgbe_start_hw_generic"); 407 408 /* Set the media type */ 409 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 410 411 /* PHY ops initialization must be done in reset_hw() */ 412 413 /* Clear the VLAN filter table */ 414 hw->mac.ops.clear_vfta(hw); 415 416 /* Clear statistics registers */ 417 hw->mac.ops.clear_hw_cntrs(hw); 418 419 /* Set No Snoop Disable */ 420 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 421 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 422 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 423 IXGBE_WRITE_FLUSH(hw); 424 425 /* Setup flow control */ 426 ret_val = ixgbe_setup_fc(hw); 427 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 428 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 429 return ret_val; 430 } 431 432 /* Cache bit indicating need for crosstalk fix */ 433 switch (hw->mac.type) { 434 case ixgbe_mac_82599EB: 435 case ixgbe_mac_X550EM_x: 436 case ixgbe_mac_X550EM_a: 437 hw->mac.ops.get_device_caps(hw, &device_caps); 438 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 439 hw->need_crosstalk_fix = false; 440 else 441 hw->need_crosstalk_fix = true; 442 break; 443 default: 444 hw->need_crosstalk_fix = false; 445 break; 446 } 447 448 /* Clear adapter stopped flag */ 449 hw->adapter_stopped = false; 450 451 return IXGBE_SUCCESS; 452 } 453 454 /** 455 * ixgbe_start_hw_gen2 - Init sequence for common device family 456 * @hw: pointer to hw structure 457 * 458 * Performs the init sequence common to the second generation 459 * of 10 GbE devices. 460 * Devices in the second generation: 461 * 82599 462 * X540 463 **/ 464 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 465 { 466 u32 i; 467 u32 regval; 468 469 /* Clear the rate limiters */ 470 for (i = 0; i < hw->mac.max_tx_queues; i++) { 471 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 472 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 473 } 474 IXGBE_WRITE_FLUSH(hw); 475 476 /* Disable relaxed ordering */ 477 for (i = 0; i < hw->mac.max_tx_queues; i++) { 478 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 479 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 480 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 481 } 482 483 for (i = 0; i < hw->mac.max_rx_queues; i++) { 484 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 485 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 486 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 487 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 488 } 489 } 490 491 /** 492 * ixgbe_init_hw_generic - Generic hardware initialization 493 * @hw: pointer to hardware structure 494 * 495 * Initialize the hardware by resetting the hardware, filling the bus info 496 * structure and media type, clears all on chip counters, initializes receive 497 * address registers, multicast table, VLAN filter table, calls routine to set 498 * up link and flow control settings, and leaves transmit and receive units 499 * disabled and uninitialized 500 **/ 501 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 502 { 503 s32 status; 504 505 DEBUGFUNC("ixgbe_init_hw_generic"); 506 507 /* Reset the hardware */ 508 status = hw->mac.ops.reset_hw(hw); 509 510 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 511 /* Start the HW */ 512 status = hw->mac.ops.start_hw(hw); 513 } 514 515 /* Initialize the LED link active for LED blink support */ 516 if (hw->mac.ops.init_led_link_act) 517 hw->mac.ops.init_led_link_act(hw); 518 519 if (status != IXGBE_SUCCESS) 520 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 521 522 return status; 523 } 524 525 /** 526 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 527 * @hw: pointer to hardware structure 528 * 529 * Clears all hardware statistics counters by reading them from the hardware 530 * Statistics counters are clear on read. 531 **/ 532 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 533 { 534 u16 i = 0; 535 536 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 537 538 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 539 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 540 IXGBE_READ_REG(hw, IXGBE_ERRBC); 541 IXGBE_READ_REG(hw, IXGBE_MSPDC); 542 for (i = 0; i < 8; i++) 543 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 544 545 IXGBE_READ_REG(hw, IXGBE_MLFC); 546 IXGBE_READ_REG(hw, IXGBE_MRFC); 547 IXGBE_READ_REG(hw, IXGBE_RLEC); 548 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 549 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 550 if (hw->mac.type >= ixgbe_mac_82599EB) { 551 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 552 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 553 } else { 554 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 555 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 556 } 557 558 for (i = 0; i < 8; i++) { 559 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 560 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 561 if (hw->mac.type >= ixgbe_mac_82599EB) { 562 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 563 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 564 } else { 565 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 566 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 567 } 568 } 569 if (hw->mac.type >= ixgbe_mac_82599EB) 570 for (i = 0; i < 8; i++) 571 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 572 IXGBE_READ_REG(hw, IXGBE_PRC64); 573 IXGBE_READ_REG(hw, IXGBE_PRC127); 574 IXGBE_READ_REG(hw, IXGBE_PRC255); 575 IXGBE_READ_REG(hw, IXGBE_PRC511); 576 IXGBE_READ_REG(hw, IXGBE_PRC1023); 577 IXGBE_READ_REG(hw, IXGBE_PRC1522); 578 IXGBE_READ_REG(hw, IXGBE_GPRC); 579 IXGBE_READ_REG(hw, IXGBE_BPRC); 580 IXGBE_READ_REG(hw, IXGBE_MPRC); 581 IXGBE_READ_REG(hw, IXGBE_GPTC); 582 IXGBE_READ_REG(hw, IXGBE_GORCL); 583 IXGBE_READ_REG(hw, IXGBE_GORCH); 584 IXGBE_READ_REG(hw, IXGBE_GOTCL); 585 IXGBE_READ_REG(hw, IXGBE_GOTCH); 586 if (hw->mac.type == ixgbe_mac_82598EB) 587 for (i = 0; i < 8; i++) 588 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 589 IXGBE_READ_REG(hw, IXGBE_RUC); 590 IXGBE_READ_REG(hw, IXGBE_RFC); 591 IXGBE_READ_REG(hw, IXGBE_ROC); 592 IXGBE_READ_REG(hw, IXGBE_RJC); 593 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 594 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 595 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 596 IXGBE_READ_REG(hw, IXGBE_TORL); 597 IXGBE_READ_REG(hw, IXGBE_TORH); 598 IXGBE_READ_REG(hw, IXGBE_TPR); 599 IXGBE_READ_REG(hw, IXGBE_TPT); 600 IXGBE_READ_REG(hw, IXGBE_PTC64); 601 IXGBE_READ_REG(hw, IXGBE_PTC127); 602 IXGBE_READ_REG(hw, IXGBE_PTC255); 603 IXGBE_READ_REG(hw, IXGBE_PTC511); 604 IXGBE_READ_REG(hw, IXGBE_PTC1023); 605 IXGBE_READ_REG(hw, IXGBE_PTC1522); 606 IXGBE_READ_REG(hw, IXGBE_MPTC); 607 IXGBE_READ_REG(hw, IXGBE_BPTC); 608 for (i = 0; i < 16; i++) { 609 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 610 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 611 if (hw->mac.type >= ixgbe_mac_82599EB) { 612 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 613 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 614 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 615 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 616 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 617 } else { 618 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 619 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 620 } 621 } 622 623 if (hw->mac.type == ixgbe_mac_X540 || 624 hw->mac.type == ixgbe_mac_X550) { 625 if (hw->phy.id == 0) 626 ixgbe_identify_phy(hw); 627 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 628 IXGBE_MDIO_PCS_DEV_TYPE, &i); 629 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 630 IXGBE_MDIO_PCS_DEV_TYPE, &i); 631 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 632 IXGBE_MDIO_PCS_DEV_TYPE, &i); 633 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 634 IXGBE_MDIO_PCS_DEV_TYPE, &i); 635 } 636 637 return IXGBE_SUCCESS; 638 } 639 640 /** 641 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 642 * @hw: pointer to hardware structure 643 * @pba_num: stores the part number string from the EEPROM 644 * @pba_num_size: part number string buffer length 645 * 646 * Reads the part number string from the EEPROM. 647 **/ 648 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 649 u32 pba_num_size) 650 { 651 s32 ret_val; 652 u16 data; 653 u16 pba_ptr; 654 u16 offset; 655 u16 length; 656 657 DEBUGFUNC("ixgbe_read_pba_string_generic"); 658 659 if (pba_num == NULL) { 660 DEBUGOUT("PBA string buffer was null\n"); 661 return IXGBE_ERR_INVALID_ARGUMENT; 662 } 663 664 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 665 if (ret_val) { 666 DEBUGOUT("NVM Read Error\n"); 667 return ret_val; 668 } 669 670 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 671 if (ret_val) { 672 DEBUGOUT("NVM Read Error\n"); 673 return ret_val; 674 } 675 676 /* 677 * if data is not ptr guard the PBA must be in legacy format which 678 * means pba_ptr is actually our second data word for the PBA number 679 * and we can decode it into an ascii string 680 */ 681 if (data != IXGBE_PBANUM_PTR_GUARD) { 682 DEBUGOUT("NVM PBA number is not stored as string\n"); 683 684 /* we will need 11 characters to store the PBA */ 685 if (pba_num_size < 11) { 686 DEBUGOUT("PBA string buffer too small\n"); 687 return IXGBE_ERR_NO_SPACE; 688 } 689 690 /* extract hex string from data and pba_ptr */ 691 pba_num[0] = (data >> 12) & 0xF; 692 pba_num[1] = (data >> 8) & 0xF; 693 pba_num[2] = (data >> 4) & 0xF; 694 pba_num[3] = data & 0xF; 695 pba_num[4] = (pba_ptr >> 12) & 0xF; 696 pba_num[5] = (pba_ptr >> 8) & 0xF; 697 pba_num[6] = '-'; 698 pba_num[7] = 0; 699 pba_num[8] = (pba_ptr >> 4) & 0xF; 700 pba_num[9] = pba_ptr & 0xF; 701 702 /* put a null character on the end of our string */ 703 pba_num[10] = '\0'; 704 705 /* switch all the data but the '-' to hex char */ 706 for (offset = 0; offset < 10; offset++) { 707 if (pba_num[offset] < 0xA) 708 pba_num[offset] += '0'; 709 else if (pba_num[offset] < 0x10) 710 pba_num[offset] += 'A' - 0xA; 711 } 712 713 return IXGBE_SUCCESS; 714 } 715 716 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 717 if (ret_val) { 718 DEBUGOUT("NVM Read Error\n"); 719 return ret_val; 720 } 721 722 if (length == 0xFFFF || length == 0 || length > hw->eeprom.word_size) { 723 DEBUGOUT("NVM PBA number section invalid length\n"); 724 return IXGBE_ERR_PBA_SECTION; 725 } 726 727 /* check if pba_num buffer is big enough */ 728 if (pba_num_size < (((u32)length * 2) - 1)) { 729 DEBUGOUT("PBA string buffer too small\n"); 730 return IXGBE_ERR_NO_SPACE; 731 } 732 733 /* trim pba length from start of string */ 734 pba_ptr++; 735 length--; 736 737 for (offset = 0; offset < length; offset++) { 738 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 739 if (ret_val) { 740 DEBUGOUT("NVM Read Error\n"); 741 return ret_val; 742 } 743 pba_num[offset * 2] = (u8)(data >> 8); 744 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 745 } 746 pba_num[offset * 2] = '\0'; 747 748 return IXGBE_SUCCESS; 749 } 750 751 /** 752 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 753 * @hw: pointer to hardware structure 754 * @pba_num: stores the part number from the EEPROM 755 * 756 * Reads the part number from the EEPROM. 757 **/ 758 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 759 { 760 s32 ret_val; 761 u16 data; 762 763 DEBUGFUNC("ixgbe_read_pba_num_generic"); 764 765 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 766 if (ret_val) { 767 DEBUGOUT("NVM Read Error\n"); 768 return ret_val; 769 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 770 DEBUGOUT("NVM Not supported\n"); 771 return IXGBE_NOT_IMPLEMENTED; 772 } 773 *pba_num = (u32)(data << 16); 774 775 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 776 if (ret_val) { 777 DEBUGOUT("NVM Read Error\n"); 778 return ret_val; 779 } 780 *pba_num |= (u32)data; 781 782 return IXGBE_SUCCESS; 783 } 784 785 /** 786 * ixgbe_read_pba_raw 787 * @hw: pointer to the HW structure 788 * @eeprom_buf: optional pointer to EEPROM image 789 * @eeprom_buf_size: size of EEPROM image in words 790 * @max_pba_block_size: PBA block size limit 791 * @pba: pointer to output PBA structure 792 * 793 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 794 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 795 * 796 **/ 797 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 798 u32 eeprom_buf_size, u16 max_pba_block_size, 799 struct ixgbe_pba *pba) 800 { 801 s32 ret_val; 802 u16 pba_block_size; 803 804 if (pba == NULL) 805 return IXGBE_ERR_PARAM; 806 807 if (eeprom_buf == NULL) { 808 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 809 &pba->word[0]); 810 if (ret_val) 811 return ret_val; 812 } else { 813 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 814 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 815 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 816 } else { 817 return IXGBE_ERR_PARAM; 818 } 819 } 820 821 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 822 if (pba->pba_block == NULL) 823 return IXGBE_ERR_PARAM; 824 825 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 826 eeprom_buf_size, 827 &pba_block_size); 828 if (ret_val) 829 return ret_val; 830 831 if (pba_block_size > max_pba_block_size) 832 return IXGBE_ERR_PARAM; 833 834 if (eeprom_buf == NULL) { 835 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 836 pba_block_size, 837 pba->pba_block); 838 if (ret_val) 839 return ret_val; 840 } else { 841 if (eeprom_buf_size > (u32)(pba->word[1] + 842 pba_block_size)) { 843 memcpy(pba->pba_block, 844 &eeprom_buf[pba->word[1]], 845 pba_block_size * sizeof(u16)); 846 } else { 847 return IXGBE_ERR_PARAM; 848 } 849 } 850 } 851 852 return IXGBE_SUCCESS; 853 } 854 855 /** 856 * ixgbe_write_pba_raw 857 * @hw: pointer to the HW structure 858 * @eeprom_buf: optional pointer to EEPROM image 859 * @eeprom_buf_size: size of EEPROM image in words 860 * @pba: pointer to PBA structure 861 * 862 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 863 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 864 * 865 **/ 866 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 867 u32 eeprom_buf_size, struct ixgbe_pba *pba) 868 { 869 s32 ret_val; 870 871 if (pba == NULL) 872 return IXGBE_ERR_PARAM; 873 874 if (eeprom_buf == NULL) { 875 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 876 &pba->word[0]); 877 if (ret_val) 878 return ret_val; 879 } else { 880 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 881 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 882 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 883 } else { 884 return IXGBE_ERR_PARAM; 885 } 886 } 887 888 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 889 if (pba->pba_block == NULL) 890 return IXGBE_ERR_PARAM; 891 892 if (eeprom_buf == NULL) { 893 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 894 pba->pba_block[0], 895 pba->pba_block); 896 if (ret_val) 897 return ret_val; 898 } else { 899 if (eeprom_buf_size > (u32)(pba->word[1] + 900 pba->pba_block[0])) { 901 memcpy(&eeprom_buf[pba->word[1]], 902 pba->pba_block, 903 pba->pba_block[0] * sizeof(u16)); 904 } else { 905 return IXGBE_ERR_PARAM; 906 } 907 } 908 } 909 910 return IXGBE_SUCCESS; 911 } 912 913 /** 914 * ixgbe_get_pba_block_size 915 * @hw: pointer to the HW structure 916 * @eeprom_buf: optional pointer to EEPROM image 917 * @eeprom_buf_size: size of EEPROM image in words 918 * @pba_data_size: pointer to output variable 919 * 920 * Returns the size of the PBA block in words. Function operates on EEPROM 921 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 922 * EEPROM device. 923 * 924 **/ 925 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 926 u32 eeprom_buf_size, u16 *pba_block_size) 927 { 928 s32 ret_val; 929 u16 pba_word[2]; 930 u16 length; 931 932 DEBUGFUNC("ixgbe_get_pba_block_size"); 933 934 if (eeprom_buf == NULL) { 935 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 936 &pba_word[0]); 937 if (ret_val) 938 return ret_val; 939 } else { 940 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 941 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 942 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 943 } else { 944 return IXGBE_ERR_PARAM; 945 } 946 } 947 948 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 949 if (eeprom_buf == NULL) { 950 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 951 &length); 952 if (ret_val) 953 return ret_val; 954 } else { 955 if (eeprom_buf_size > pba_word[1]) 956 length = eeprom_buf[pba_word[1] + 0]; 957 else 958 return IXGBE_ERR_PARAM; 959 } 960 961 if (length == 0xFFFF || length == 0) 962 return IXGBE_ERR_PBA_SECTION; 963 } else { 964 /* PBA number in legacy format, there is no PBA Block. */ 965 length = 0; 966 } 967 968 if (pba_block_size != NULL) 969 *pba_block_size = length; 970 971 return IXGBE_SUCCESS; 972 } 973 974 /** 975 * ixgbe_get_mac_addr_generic - Generic get MAC address 976 * @hw: pointer to hardware structure 977 * @mac_addr: Adapter MAC address 978 * 979 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 980 * A reset of the adapter must be performed prior to calling this function 981 * in order for the MAC address to have been loaded from the EEPROM into RAR0 982 **/ 983 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 984 { 985 u32 rar_high; 986 u32 rar_low; 987 u16 i; 988 989 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 990 991 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 992 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 993 994 for (i = 0; i < 4; i++) 995 mac_addr[i] = (u8)(rar_low >> (i*8)); 996 997 for (i = 0; i < 2; i++) 998 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 999 1000 return IXGBE_SUCCESS; 1001 } 1002 1003 /** 1004 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 1005 * @hw: pointer to hardware structure 1006 * @link_status: the link status returned by the PCI config space 1007 * 1008 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1009 **/ 1010 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1011 { 1012 struct ixgbe_mac_info *mac = &hw->mac; 1013 1014 if (hw->bus.type == ixgbe_bus_type_unknown) 1015 hw->bus.type = ixgbe_bus_type_pci_express; 1016 1017 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1018 case IXGBE_PCI_LINK_WIDTH_1: 1019 hw->bus.width = ixgbe_bus_width_pcie_x1; 1020 break; 1021 case IXGBE_PCI_LINK_WIDTH_2: 1022 hw->bus.width = ixgbe_bus_width_pcie_x2; 1023 break; 1024 case IXGBE_PCI_LINK_WIDTH_4: 1025 hw->bus.width = ixgbe_bus_width_pcie_x4; 1026 break; 1027 case IXGBE_PCI_LINK_WIDTH_8: 1028 hw->bus.width = ixgbe_bus_width_pcie_x8; 1029 break; 1030 default: 1031 hw->bus.width = ixgbe_bus_width_unknown; 1032 break; 1033 } 1034 1035 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1036 case IXGBE_PCI_LINK_SPEED_2500: 1037 hw->bus.speed = ixgbe_bus_speed_2500; 1038 break; 1039 case IXGBE_PCI_LINK_SPEED_5000: 1040 hw->bus.speed = ixgbe_bus_speed_5000; 1041 break; 1042 case IXGBE_PCI_LINK_SPEED_8000: 1043 hw->bus.speed = ixgbe_bus_speed_8000; 1044 break; 1045 case IXGBE_PCI_LINK_SPEED_16000: 1046 hw->bus.speed = ixgbe_bus_speed_16000; 1047 break; 1048 default: 1049 hw->bus.speed = ixgbe_bus_speed_unknown; 1050 break; 1051 } 1052 1053 mac->ops.set_lan_id(hw); 1054 } 1055 1056 /** 1057 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1058 * @hw: pointer to hardware structure 1059 * 1060 * Gets the PCI bus info (speed, width, type) then calls helper function to 1061 * store this data within the ixgbe_hw structure. 1062 **/ 1063 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1064 { 1065 u16 link_status; 1066 1067 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1068 1069 /* Get the negotiated link width and speed from PCI config space */ 1070 link_status = IXGBE_READ_PCIE_WORD(hw, hw->mac.type == ixgbe_mac_E610 ? 1071 IXGBE_PCI_LINK_STATUS_E610 : 1072 IXGBE_PCI_LINK_STATUS); 1073 1074 ixgbe_set_pci_config_data_generic(hw, link_status); 1075 1076 return IXGBE_SUCCESS; 1077 } 1078 1079 /** 1080 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1081 * @hw: pointer to the HW structure 1082 * 1083 * Determines the LAN function id by reading memory-mapped registers and swaps 1084 * the port value if requested, and set MAC instance for devices that share 1085 * CS4227. 1086 **/ 1087 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1088 { 1089 struct ixgbe_bus_info *bus = &hw->bus; 1090 u32 reg; 1091 u16 ee_ctrl_4; 1092 1093 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1094 1095 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1096 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1097 bus->lan_id = (u8)bus->func; 1098 1099 /* check for a port swap */ 1100 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1101 if (reg & IXGBE_FACTPS_LFS) 1102 bus->func ^= 0x1; 1103 1104 /* Get MAC instance from EEPROM for configuring CS4227 */ 1105 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1106 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1107 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1108 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1109 } 1110 } 1111 1112 /** 1113 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1114 * @hw: pointer to hardware structure 1115 * 1116 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1117 * disables transmit and receive units. The adapter_stopped flag is used by 1118 * the shared code and drivers to determine if the adapter is in a stopped 1119 * state and should not touch the hardware. 1120 **/ 1121 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1122 { 1123 u32 reg_val; 1124 u16 i; 1125 1126 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1127 1128 /* 1129 * Set the adapter_stopped flag so other driver functions stop touching 1130 * the hardware 1131 */ 1132 hw->adapter_stopped = true; 1133 1134 /* Disable the receive unit */ 1135 ixgbe_disable_rx(hw); 1136 1137 /* Clear interrupt mask to stop interrupts from being generated */ 1138 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1139 1140 /* Clear any pending interrupts, flush previous writes */ 1141 IXGBE_READ_REG(hw, IXGBE_EICR); 1142 1143 /* Disable the transmit unit. Each queue must be disabled. */ 1144 for (i = 0; i < hw->mac.max_tx_queues; i++) 1145 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1146 1147 /* Disable the receive unit by stopping each queue */ 1148 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1149 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1150 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1151 reg_val |= IXGBE_RXDCTL_SWFLSH; 1152 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1153 } 1154 1155 /* flush all queues disables */ 1156 IXGBE_WRITE_FLUSH(hw); 1157 msec_delay(2); 1158 1159 /* 1160 * Prevent the PCI-E bus from hanging by disabling PCI-E primary 1161 * access and verify no pending requests 1162 */ 1163 return ixgbe_disable_pcie_primary(hw); 1164 } 1165 1166 /** 1167 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1168 * @hw: pointer to hardware structure 1169 * 1170 * Store the index for the link active LED. This will be used to support 1171 * blinking the LED. 1172 **/ 1173 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1174 { 1175 struct ixgbe_mac_info *mac = &hw->mac; 1176 u32 led_reg, led_mode; 1177 u8 i; 1178 1179 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1180 1181 /* Get LED link active from the LEDCTL register */ 1182 for (i = 0; i < 4; i++) { 1183 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1184 1185 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1186 IXGBE_LED_LINK_ACTIVE) { 1187 mac->led_link_act = i; 1188 return IXGBE_SUCCESS; 1189 } 1190 } 1191 1192 /* 1193 * If LEDCTL register does not have the LED link active set, then use 1194 * known MAC defaults. 1195 */ 1196 switch (hw->mac.type) { 1197 case ixgbe_mac_X550EM_a: 1198 case ixgbe_mac_X550EM_x: 1199 mac->led_link_act = 1; 1200 break; 1201 default: 1202 mac->led_link_act = 2; 1203 } 1204 return IXGBE_SUCCESS; 1205 } 1206 1207 /** 1208 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1209 * @hw: pointer to hardware structure 1210 * @index: led number to turn on 1211 **/ 1212 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1213 { 1214 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1215 1216 DEBUGFUNC("ixgbe_led_on_generic"); 1217 1218 if (index > 3) 1219 return IXGBE_ERR_PARAM; 1220 1221 /* To turn on the LED, set mode to ON. */ 1222 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1223 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1224 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1225 IXGBE_WRITE_FLUSH(hw); 1226 1227 return IXGBE_SUCCESS; 1228 } 1229 1230 /** 1231 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1232 * @hw: pointer to hardware structure 1233 * @index: led number to turn off 1234 **/ 1235 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1236 { 1237 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1238 1239 DEBUGFUNC("ixgbe_led_off_generic"); 1240 1241 if (index > 3) 1242 return IXGBE_ERR_PARAM; 1243 1244 /* To turn off the LED, set mode to OFF. */ 1245 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1246 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1247 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1248 IXGBE_WRITE_FLUSH(hw); 1249 1250 return IXGBE_SUCCESS; 1251 } 1252 1253 /** 1254 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1255 * @hw: pointer to hardware structure 1256 * 1257 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1258 * ixgbe_hw struct in order to set up EEPROM access. 1259 **/ 1260 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1261 { 1262 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1263 u32 eec; 1264 u16 eeprom_size; 1265 1266 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1267 1268 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1269 eeprom->type = ixgbe_eeprom_none; 1270 /* Set default semaphore delay to 10ms which is a well 1271 * tested value */ 1272 eeprom->semaphore_delay = 10; 1273 /* Clear EEPROM page size, it will be initialized as needed */ 1274 eeprom->word_page_size = 0; 1275 1276 /* 1277 * Check for EEPROM present first. 1278 * If not present leave as none 1279 */ 1280 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1281 if (eec & IXGBE_EEC_PRES) { 1282 eeprom->type = ixgbe_eeprom_spi; 1283 1284 /* 1285 * SPI EEPROM is assumed here. This code would need to 1286 * change if a future EEPROM is not SPI. 1287 */ 1288 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1289 IXGBE_EEC_SIZE_SHIFT); 1290 eeprom->word_size = 1 << (eeprom_size + 1291 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1292 } 1293 1294 if (eec & IXGBE_EEC_ADDR_SIZE) 1295 eeprom->address_bits = 16; 1296 else 1297 eeprom->address_bits = 8; 1298 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1299 "%d\n", eeprom->type, eeprom->word_size, 1300 eeprom->address_bits); 1301 } 1302 1303 return IXGBE_SUCCESS; 1304 } 1305 1306 /** 1307 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1308 * @hw: pointer to hardware structure 1309 * @offset: offset within the EEPROM to write 1310 * @words: number of word(s) 1311 * @data: 16 bit word(s) to write to EEPROM 1312 * 1313 * Reads 16 bit word(s) from EEPROM through bit-bang method 1314 **/ 1315 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1316 u16 words, u16 *data) 1317 { 1318 s32 status = IXGBE_SUCCESS; 1319 u16 i, count; 1320 1321 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1322 1323 hw->eeprom.ops.init_params(hw); 1324 1325 if (words == 0) { 1326 status = IXGBE_ERR_INVALID_ARGUMENT; 1327 goto out; 1328 } 1329 1330 if (offset + words > hw->eeprom.word_size) { 1331 status = IXGBE_ERR_EEPROM; 1332 goto out; 1333 } 1334 1335 /* 1336 * The EEPROM page size cannot be queried from the chip. We do lazy 1337 * initialization. It is worth to do that when we write large buffer. 1338 */ 1339 if ((hw->eeprom.word_page_size == 0) && 1340 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1341 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1342 1343 /* 1344 * We cannot hold synchronization semaphores for too long 1345 * to avoid other entity starvation. However it is more efficient 1346 * to read in bursts than synchronizing access for each word. 1347 */ 1348 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1349 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1350 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1351 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1352 count, &data[i]); 1353 1354 if (status != IXGBE_SUCCESS) 1355 break; 1356 } 1357 1358 out: 1359 return status; 1360 } 1361 1362 /** 1363 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1364 * @hw: pointer to hardware structure 1365 * @offset: offset within the EEPROM to be written to 1366 * @words: number of word(s) 1367 * @data: 16 bit word(s) to be written to the EEPROM 1368 * 1369 * If ixgbe_eeprom_update_checksum is not called after this function, the 1370 * EEPROM will most likely contain an invalid checksum. 1371 **/ 1372 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1373 u16 words, u16 *data) 1374 { 1375 s32 status; 1376 u16 word; 1377 u16 page_size; 1378 u16 i; 1379 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1380 1381 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1382 1383 /* Prepare the EEPROM for writing */ 1384 status = ixgbe_acquire_eeprom(hw); 1385 1386 if (status == IXGBE_SUCCESS) { 1387 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1388 ixgbe_release_eeprom(hw); 1389 status = IXGBE_ERR_EEPROM; 1390 } 1391 } 1392 1393 if (status == IXGBE_SUCCESS) { 1394 for (i = 0; i < words; i++) { 1395 ixgbe_standby_eeprom(hw); 1396 1397 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1398 ixgbe_shift_out_eeprom_bits(hw, 1399 IXGBE_EEPROM_WREN_OPCODE_SPI, 1400 IXGBE_EEPROM_OPCODE_BITS); 1401 1402 ixgbe_standby_eeprom(hw); 1403 1404 /* 1405 * Some SPI eeproms use the 8th address bit embedded 1406 * in the opcode 1407 */ 1408 if ((hw->eeprom.address_bits == 8) && 1409 ((offset + i) >= 128)) 1410 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1411 1412 /* Send the Write command (8-bit opcode + addr) */ 1413 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1414 IXGBE_EEPROM_OPCODE_BITS); 1415 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1416 hw->eeprom.address_bits); 1417 1418 page_size = hw->eeprom.word_page_size; 1419 1420 /* Send the data in burst via SPI*/ 1421 do { 1422 word = data[i]; 1423 word = (word >> 8) | (word << 8); 1424 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1425 1426 if (page_size == 0) 1427 break; 1428 1429 /* do not wrap around page */ 1430 if (((offset + i) & (page_size - 1)) == 1431 (page_size - 1)) 1432 break; 1433 } while (++i < words); 1434 1435 ixgbe_standby_eeprom(hw); 1436 msec_delay(10); 1437 } 1438 /* Done with writing - release the EEPROM */ 1439 ixgbe_release_eeprom(hw); 1440 } 1441 1442 return status; 1443 } 1444 1445 /** 1446 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1447 * @hw: pointer to hardware structure 1448 * @offset: offset within the EEPROM to be written to 1449 * @data: 16 bit word to be written to the EEPROM 1450 * 1451 * If ixgbe_eeprom_update_checksum is not called after this function, the 1452 * EEPROM will most likely contain an invalid checksum. 1453 **/ 1454 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1455 { 1456 s32 status; 1457 1458 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1459 1460 hw->eeprom.ops.init_params(hw); 1461 1462 if (offset >= hw->eeprom.word_size) { 1463 status = IXGBE_ERR_EEPROM; 1464 goto out; 1465 } 1466 1467 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1468 1469 out: 1470 return status; 1471 } 1472 1473 /** 1474 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1475 * @hw: pointer to hardware structure 1476 * @offset: offset within the EEPROM to be read 1477 * @data: read 16 bit words(s) from EEPROM 1478 * @words: number of word(s) 1479 * 1480 * Reads 16 bit word(s) from EEPROM through bit-bang method 1481 **/ 1482 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1483 u16 words, u16 *data) 1484 { 1485 s32 status = IXGBE_SUCCESS; 1486 u16 i, count; 1487 1488 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1489 1490 hw->eeprom.ops.init_params(hw); 1491 1492 if (words == 0) { 1493 status = IXGBE_ERR_INVALID_ARGUMENT; 1494 goto out; 1495 } 1496 1497 if (offset + words > hw->eeprom.word_size) { 1498 status = IXGBE_ERR_EEPROM; 1499 goto out; 1500 } 1501 1502 /* 1503 * We cannot hold synchronization semaphores for too long 1504 * to avoid other entity starvation. However it is more efficient 1505 * to read in bursts than synchronizing access for each word. 1506 */ 1507 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1508 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1509 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1510 1511 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1512 count, &data[i]); 1513 1514 if (status != IXGBE_SUCCESS) 1515 break; 1516 } 1517 1518 out: 1519 return status; 1520 } 1521 1522 /** 1523 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1524 * @hw: pointer to hardware structure 1525 * @offset: offset within the EEPROM to be read 1526 * @words: number of word(s) 1527 * @data: read 16 bit word(s) from EEPROM 1528 * 1529 * Reads 16 bit word(s) from EEPROM through bit-bang method 1530 **/ 1531 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1532 u16 words, u16 *data) 1533 { 1534 s32 status; 1535 u16 word_in; 1536 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1537 u16 i; 1538 1539 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1540 1541 /* Prepare the EEPROM for reading */ 1542 status = ixgbe_acquire_eeprom(hw); 1543 1544 if (status == IXGBE_SUCCESS) { 1545 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1546 ixgbe_release_eeprom(hw); 1547 status = IXGBE_ERR_EEPROM; 1548 } 1549 } 1550 1551 if (status == IXGBE_SUCCESS) { 1552 for (i = 0; i < words; i++) { 1553 ixgbe_standby_eeprom(hw); 1554 /* 1555 * Some SPI eeproms use the 8th address bit embedded 1556 * in the opcode 1557 */ 1558 if ((hw->eeprom.address_bits == 8) && 1559 ((offset + i) >= 128)) 1560 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1561 1562 /* Send the READ command (opcode + addr) */ 1563 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1564 IXGBE_EEPROM_OPCODE_BITS); 1565 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1566 hw->eeprom.address_bits); 1567 1568 /* Read the data. */ 1569 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1570 data[i] = (word_in >> 8) | (word_in << 8); 1571 } 1572 1573 /* End this read operation */ 1574 ixgbe_release_eeprom(hw); 1575 } 1576 1577 return status; 1578 } 1579 1580 /** 1581 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1582 * @hw: pointer to hardware structure 1583 * @offset: offset within the EEPROM to be read 1584 * @data: read 16 bit value from EEPROM 1585 * 1586 * Reads 16 bit value from EEPROM through bit-bang method 1587 **/ 1588 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1589 u16 *data) 1590 { 1591 s32 status; 1592 1593 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1594 1595 hw->eeprom.ops.init_params(hw); 1596 1597 if (offset >= hw->eeprom.word_size) { 1598 status = IXGBE_ERR_EEPROM; 1599 goto out; 1600 } 1601 1602 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1603 1604 out: 1605 return status; 1606 } 1607 1608 /** 1609 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1610 * @hw: pointer to hardware structure 1611 * @offset: offset of word in the EEPROM to read 1612 * @words: number of word(s) 1613 * @data: 16 bit word(s) from the EEPROM 1614 * 1615 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1616 **/ 1617 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1618 u16 words, u16 *data) 1619 { 1620 u32 eerd; 1621 s32 status = IXGBE_SUCCESS; 1622 u32 i; 1623 1624 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1625 1626 hw->eeprom.ops.init_params(hw); 1627 1628 if (words == 0) { 1629 status = IXGBE_ERR_INVALID_ARGUMENT; 1630 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1631 goto out; 1632 } 1633 1634 if (offset >= hw->eeprom.word_size) { 1635 status = IXGBE_ERR_EEPROM; 1636 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1637 goto out; 1638 } 1639 1640 for (i = 0; i < words; i++) { 1641 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1642 IXGBE_EEPROM_RW_REG_START; 1643 1644 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1645 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1646 1647 if (status == IXGBE_SUCCESS) { 1648 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1649 IXGBE_EEPROM_RW_REG_DATA); 1650 } else { 1651 DEBUGOUT("Eeprom read timed out\n"); 1652 goto out; 1653 } 1654 } 1655 out: 1656 return status; 1657 } 1658 1659 /** 1660 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1661 * @hw: pointer to hardware structure 1662 * @offset: offset within the EEPROM to be used as a scratch pad 1663 * 1664 * Discover EEPROM page size by writing marching data at given offset. 1665 * This function is called only when we are writing a new large buffer 1666 * at given offset so the data would be overwritten anyway. 1667 **/ 1668 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1669 u16 offset) 1670 { 1671 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1672 s32 status = IXGBE_SUCCESS; 1673 u16 i; 1674 1675 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1676 1677 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1678 data[i] = i; 1679 1680 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1681 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1682 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1683 hw->eeprom.word_page_size = 0; 1684 if (status != IXGBE_SUCCESS) 1685 goto out; 1686 1687 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1688 if (status != IXGBE_SUCCESS) 1689 goto out; 1690 1691 /* 1692 * When writing in burst more than the actual page size 1693 * EEPROM address wraps around current page. 1694 */ 1695 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1696 1697 DEBUGOUT1("Detected EEPROM page size = %d words.", 1698 hw->eeprom.word_page_size); 1699 out: 1700 return status; 1701 } 1702 1703 /** 1704 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1705 * @hw: pointer to hardware structure 1706 * @offset: offset of word in the EEPROM to read 1707 * @data: word read from the EEPROM 1708 * 1709 * Reads a 16 bit word from the EEPROM using the EERD register. 1710 **/ 1711 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1712 { 1713 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1714 } 1715 1716 /** 1717 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1718 * @hw: pointer to hardware structure 1719 * @offset: offset of word in the EEPROM to write 1720 * @words: number of word(s) 1721 * @data: word(s) write to the EEPROM 1722 * 1723 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1724 **/ 1725 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1726 u16 words, u16 *data) 1727 { 1728 u32 eewr; 1729 s32 status = IXGBE_SUCCESS; 1730 u16 i; 1731 1732 DEBUGFUNC("ixgbe_write_eewr_generic"); 1733 1734 hw->eeprom.ops.init_params(hw); 1735 1736 if (words == 0) { 1737 status = IXGBE_ERR_INVALID_ARGUMENT; 1738 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1739 goto out; 1740 } 1741 1742 if (offset >= hw->eeprom.word_size) { 1743 status = IXGBE_ERR_EEPROM; 1744 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1745 goto out; 1746 } 1747 1748 for (i = 0; i < words; i++) { 1749 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1750 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1751 IXGBE_EEPROM_RW_REG_START; 1752 1753 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1754 if (status != IXGBE_SUCCESS) { 1755 DEBUGOUT("Eeprom write EEWR timed out\n"); 1756 goto out; 1757 } 1758 1759 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1760 1761 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1762 if (status != IXGBE_SUCCESS) { 1763 DEBUGOUT("Eeprom write EEWR timed out\n"); 1764 goto out; 1765 } 1766 } 1767 1768 out: 1769 return status; 1770 } 1771 1772 /** 1773 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1774 * @hw: pointer to hardware structure 1775 * @offset: offset of word in the EEPROM to write 1776 * @data: word write to the EEPROM 1777 * 1778 * Write a 16 bit word to the EEPROM using the EEWR register. 1779 **/ 1780 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1781 { 1782 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1783 } 1784 1785 /** 1786 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1787 * @hw: pointer to hardware structure 1788 * @ee_reg: EEPROM flag for polling 1789 * 1790 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1791 * read or write is done respectively. 1792 **/ 1793 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1794 { 1795 u32 i; 1796 u32 reg; 1797 s32 status = IXGBE_ERR_EEPROM; 1798 1799 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1800 1801 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1802 if (ee_reg == IXGBE_NVM_POLL_READ) 1803 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1804 else 1805 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1806 1807 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1808 status = IXGBE_SUCCESS; 1809 break; 1810 } 1811 usec_delay(5); 1812 } 1813 1814 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1815 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1816 "EEPROM read/write done polling timed out"); 1817 1818 return status; 1819 } 1820 1821 /** 1822 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1823 * @hw: pointer to hardware structure 1824 * 1825 * Prepares EEPROM for access using bit-bang method. This function should 1826 * be called before issuing a command to the EEPROM. 1827 **/ 1828 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1829 { 1830 s32 status = IXGBE_SUCCESS; 1831 u32 eec; 1832 u32 i; 1833 1834 DEBUGFUNC("ixgbe_acquire_eeprom"); 1835 1836 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1837 != IXGBE_SUCCESS) 1838 status = IXGBE_ERR_SWFW_SYNC; 1839 1840 if (status == IXGBE_SUCCESS) { 1841 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1842 1843 /* Request EEPROM Access */ 1844 eec |= IXGBE_EEC_REQ; 1845 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1846 1847 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1848 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1849 if (eec & IXGBE_EEC_GNT) 1850 break; 1851 usec_delay(5); 1852 } 1853 1854 /* Release if grant not acquired */ 1855 if (!(eec & IXGBE_EEC_GNT)) { 1856 eec &= ~IXGBE_EEC_REQ; 1857 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1858 DEBUGOUT("Could not acquire EEPROM grant\n"); 1859 1860 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1861 status = IXGBE_ERR_EEPROM; 1862 } 1863 1864 /* Setup EEPROM for Read/Write */ 1865 if (status == IXGBE_SUCCESS) { 1866 /* Clear CS and SK */ 1867 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1868 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1869 IXGBE_WRITE_FLUSH(hw); 1870 usec_delay(1); 1871 } 1872 } 1873 return status; 1874 } 1875 1876 /** 1877 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1878 * @hw: pointer to hardware structure 1879 * 1880 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1881 **/ 1882 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1883 { 1884 s32 status = IXGBE_ERR_EEPROM; 1885 u32 timeout = 2000; 1886 u32 i; 1887 u32 swsm; 1888 1889 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1890 1891 /* Get SMBI software semaphore between device drivers first */ 1892 for (i = 0; i < timeout; i++) { 1893 /* 1894 * If the SMBI bit is 0 when we read it, then the bit will be 1895 * set and we have the semaphore 1896 */ 1897 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1898 if (!(swsm & IXGBE_SWSM_SMBI)) { 1899 status = IXGBE_SUCCESS; 1900 break; 1901 } 1902 usec_delay(50); 1903 } 1904 1905 if (i == timeout) { 1906 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1907 "not granted.\n"); 1908 /* 1909 * this release is particularly important because our attempts 1910 * above to get the semaphore may have succeeded, and if there 1911 * was a timeout, we should unconditionally clear the semaphore 1912 * bits to free the driver to make progress 1913 */ 1914 ixgbe_release_eeprom_semaphore(hw); 1915 1916 usec_delay(50); 1917 /* 1918 * one last try 1919 * If the SMBI bit is 0 when we read it, then the bit will be 1920 * set and we have the semaphore 1921 */ 1922 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1923 if (!(swsm & IXGBE_SWSM_SMBI)) 1924 status = IXGBE_SUCCESS; 1925 } 1926 1927 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1928 if (status == IXGBE_SUCCESS) { 1929 for (i = 0; i < timeout; i++) { 1930 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1931 1932 /* Set the SW EEPROM semaphore bit to request access */ 1933 swsm |= IXGBE_SWSM_SWESMBI; 1934 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1935 1936 /* 1937 * If we set the bit successfully then we got the 1938 * semaphore. 1939 */ 1940 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1941 if (swsm & IXGBE_SWSM_SWESMBI) 1942 break; 1943 1944 usec_delay(50); 1945 } 1946 1947 /* 1948 * Release semaphores and return error if SW EEPROM semaphore 1949 * was not granted because we don't have access to the EEPROM 1950 */ 1951 if (i >= timeout) { 1952 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1953 "SWESMBI Software EEPROM semaphore not granted.\n"); 1954 ixgbe_release_eeprom_semaphore(hw); 1955 status = IXGBE_ERR_EEPROM; 1956 } 1957 } else { 1958 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1959 "Software semaphore SMBI between device drivers " 1960 "not granted.\n"); 1961 } 1962 1963 return status; 1964 } 1965 1966 /** 1967 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1968 * @hw: pointer to hardware structure 1969 * 1970 * This function clears hardware semaphore bits. 1971 **/ 1972 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1973 { 1974 u32 swsm; 1975 1976 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1977 1978 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1979 1980 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1981 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1982 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1983 IXGBE_WRITE_FLUSH(hw); 1984 } 1985 1986 /** 1987 * ixgbe_ready_eeprom - Polls for EEPROM ready 1988 * @hw: pointer to hardware structure 1989 **/ 1990 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1991 { 1992 s32 status = IXGBE_SUCCESS; 1993 u16 i; 1994 u8 spi_stat_reg; 1995 1996 DEBUGFUNC("ixgbe_ready_eeprom"); 1997 1998 /* 1999 * Read "Status Register" repeatedly until the LSB is cleared. The 2000 * EEPROM will signal that the command has been completed by clearing 2001 * bit 0 of the internal status register. If it's not cleared within 2002 * 5 milliseconds, then error out. 2003 */ 2004 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 2005 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 2006 IXGBE_EEPROM_OPCODE_BITS); 2007 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 2008 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 2009 break; 2010 2011 usec_delay(5); 2012 ixgbe_standby_eeprom(hw); 2013 } 2014 2015 /* 2016 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2017 * devices (and only 0-5mSec on 5V devices) 2018 */ 2019 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2020 DEBUGOUT("SPI EEPROM Status error\n"); 2021 status = IXGBE_ERR_EEPROM; 2022 } 2023 2024 return status; 2025 } 2026 2027 /** 2028 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2029 * @hw: pointer to hardware structure 2030 **/ 2031 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2032 { 2033 u32 eec; 2034 2035 DEBUGFUNC("ixgbe_standby_eeprom"); 2036 2037 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2038 2039 /* Toggle CS to flush commands */ 2040 eec |= IXGBE_EEC_CS; 2041 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2042 IXGBE_WRITE_FLUSH(hw); 2043 usec_delay(1); 2044 eec &= ~IXGBE_EEC_CS; 2045 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2046 IXGBE_WRITE_FLUSH(hw); 2047 usec_delay(1); 2048 } 2049 2050 /** 2051 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2052 * @hw: pointer to hardware structure 2053 * @data: data to send to the EEPROM 2054 * @count: number of bits to shift out 2055 **/ 2056 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2057 u16 count) 2058 { 2059 u32 eec; 2060 u32 mask; 2061 u32 i; 2062 2063 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2064 2065 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2066 2067 /* 2068 * Mask is used to shift "count" bits of "data" out to the EEPROM 2069 * one bit at a time. Determine the starting bit based on count 2070 */ 2071 mask = 0x01 << (count - 1); 2072 2073 for (i = 0; i < count; i++) { 2074 /* 2075 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2076 * "1", and then raising and then lowering the clock (the SK 2077 * bit controls the clock input to the EEPROM). A "0" is 2078 * shifted out to the EEPROM by setting "DI" to "0" and then 2079 * raising and then lowering the clock. 2080 */ 2081 if (data & mask) 2082 eec |= IXGBE_EEC_DI; 2083 else 2084 eec &= ~IXGBE_EEC_DI; 2085 2086 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2087 IXGBE_WRITE_FLUSH(hw); 2088 2089 usec_delay(1); 2090 2091 ixgbe_raise_eeprom_clk(hw, &eec); 2092 ixgbe_lower_eeprom_clk(hw, &eec); 2093 2094 /* 2095 * Shift mask to signify next bit of data to shift in to the 2096 * EEPROM 2097 */ 2098 mask = mask >> 1; 2099 } 2100 2101 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2102 eec &= ~IXGBE_EEC_DI; 2103 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2104 IXGBE_WRITE_FLUSH(hw); 2105 } 2106 2107 /** 2108 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2109 * @hw: pointer to hardware structure 2110 * @count: number of bits to shift 2111 **/ 2112 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2113 { 2114 u32 eec; 2115 u32 i; 2116 u16 data = 0; 2117 2118 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2119 2120 /* 2121 * In order to read a register from the EEPROM, we need to shift 2122 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2123 * the clock input to the EEPROM (setting the SK bit), and then reading 2124 * the value of the "DO" bit. During this "shifting in" process the 2125 * "DI" bit should always be clear. 2126 */ 2127 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2128 2129 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2130 2131 for (i = 0; i < count; i++) { 2132 data = data << 1; 2133 ixgbe_raise_eeprom_clk(hw, &eec); 2134 2135 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2136 2137 eec &= ~(IXGBE_EEC_DI); 2138 if (eec & IXGBE_EEC_DO) 2139 data |= 1; 2140 2141 ixgbe_lower_eeprom_clk(hw, &eec); 2142 } 2143 2144 return data; 2145 } 2146 2147 /** 2148 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2149 * @hw: pointer to hardware structure 2150 * @eec: EEC register's current value 2151 **/ 2152 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2153 { 2154 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2155 2156 /* 2157 * Raise the clock input to the EEPROM 2158 * (setting the SK bit), then delay 2159 */ 2160 *eec = *eec | IXGBE_EEC_SK; 2161 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2162 IXGBE_WRITE_FLUSH(hw); 2163 usec_delay(1); 2164 } 2165 2166 /** 2167 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2168 * @hw: pointer to hardware structure 2169 * @eec: EEC's current value 2170 **/ 2171 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2172 { 2173 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2174 2175 /* 2176 * Lower the clock input to the EEPROM (clearing the SK bit), then 2177 * delay 2178 */ 2179 *eec = *eec & ~IXGBE_EEC_SK; 2180 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2181 IXGBE_WRITE_FLUSH(hw); 2182 usec_delay(1); 2183 } 2184 2185 /** 2186 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2187 * @hw: pointer to hardware structure 2188 **/ 2189 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2190 { 2191 u32 eec; 2192 2193 DEBUGFUNC("ixgbe_release_eeprom"); 2194 2195 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2196 2197 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2198 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2199 2200 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2201 IXGBE_WRITE_FLUSH(hw); 2202 2203 usec_delay(1); 2204 2205 /* Stop requesting EEPROM access */ 2206 eec &= ~IXGBE_EEC_REQ; 2207 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2208 2209 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2210 2211 /* Delay before attempt to obtain semaphore again to allow FW access */ 2212 msec_delay(hw->eeprom.semaphore_delay); 2213 } 2214 2215 /** 2216 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2217 * @hw: pointer to hardware structure 2218 * 2219 * Returns a negative error code on error, or the 16-bit checksum 2220 **/ 2221 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2222 { 2223 u16 i; 2224 u16 j; 2225 u16 checksum = 0; 2226 u16 length = 0; 2227 u16 pointer = 0; 2228 u16 word = 0; 2229 2230 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2231 2232 /* Include 0x0-0x3F in the checksum */ 2233 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2234 if (hw->eeprom.ops.read(hw, i, &word)) { 2235 DEBUGOUT("EEPROM read failed\n"); 2236 return IXGBE_ERR_EEPROM; 2237 } 2238 checksum += word; 2239 } 2240 2241 /* Include all data from pointers except for the fw pointer */ 2242 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2243 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2244 DEBUGOUT("EEPROM read failed\n"); 2245 return IXGBE_ERR_EEPROM; 2246 } 2247 2248 /* If the pointer seems invalid */ 2249 if (pointer == 0xFFFF || pointer == 0) 2250 continue; 2251 2252 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2253 DEBUGOUT("EEPROM read failed\n"); 2254 return IXGBE_ERR_EEPROM; 2255 } 2256 2257 if (length == 0xFFFF || length == 0) 2258 continue; 2259 2260 for (j = pointer + 1; j <= pointer + length; j++) { 2261 if (hw->eeprom.ops.read(hw, j, &word)) { 2262 DEBUGOUT("EEPROM read failed\n"); 2263 return IXGBE_ERR_EEPROM; 2264 } 2265 checksum += word; 2266 } 2267 } 2268 2269 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2270 2271 return (s32)checksum; 2272 } 2273 2274 /** 2275 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2276 * @hw: pointer to hardware structure 2277 * @checksum_val: calculated checksum 2278 * 2279 * Performs checksum calculation and validates the EEPROM checksum. If the 2280 * caller does not need checksum_val, the value can be NULL. 2281 **/ 2282 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2283 u16 *checksum_val) 2284 { 2285 s32 status; 2286 u16 checksum; 2287 u16 read_checksum = 0; 2288 2289 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2290 2291 /* Read the first word from the EEPROM. If this times out or fails, do 2292 * not continue or we could be in for a very long wait while every 2293 * EEPROM read fails 2294 */ 2295 status = hw->eeprom.ops.read(hw, 0, &checksum); 2296 if (status) { 2297 DEBUGOUT("EEPROM read failed\n"); 2298 return status; 2299 } 2300 2301 status = hw->eeprom.ops.calc_checksum(hw); 2302 if (status < 0) 2303 return status; 2304 2305 checksum = (u16)(status & 0xffff); 2306 2307 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2308 if (status) { 2309 DEBUGOUT("EEPROM read failed\n"); 2310 return status; 2311 } 2312 2313 /* Verify read checksum from EEPROM is the same as 2314 * calculated checksum 2315 */ 2316 if (read_checksum != checksum) 2317 status = IXGBE_ERR_EEPROM_CHECKSUM; 2318 2319 /* If the user cares, return the calculated checksum */ 2320 if (checksum_val) 2321 *checksum_val = checksum; 2322 2323 return status; 2324 } 2325 2326 /** 2327 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2328 * @hw: pointer to hardware structure 2329 **/ 2330 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2331 { 2332 s32 status; 2333 u16 checksum; 2334 2335 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2336 2337 /* Read the first word from the EEPROM. If this times out or fails, do 2338 * not continue or we could be in for a very long wait while every 2339 * EEPROM read fails 2340 */ 2341 status = hw->eeprom.ops.read(hw, 0, &checksum); 2342 if (status) { 2343 DEBUGOUT("EEPROM read failed\n"); 2344 return status; 2345 } 2346 2347 status = hw->eeprom.ops.calc_checksum(hw); 2348 if (status < 0) 2349 return status; 2350 2351 checksum = (u16)(status & 0xffff); 2352 2353 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2354 2355 return status; 2356 } 2357 2358 /** 2359 * ixgbe_validate_mac_addr - Validate MAC address 2360 * @mac_addr: pointer to MAC address. 2361 * 2362 * Tests a MAC address to ensure it is a valid Individual Address. 2363 **/ 2364 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2365 { 2366 s32 status = IXGBE_SUCCESS; 2367 2368 DEBUGFUNC("ixgbe_validate_mac_addr"); 2369 2370 /* Make sure it is not a multicast address */ 2371 if (IXGBE_IS_MULTICAST(mac_addr)) { 2372 status = IXGBE_ERR_INVALID_MAC_ADDR; 2373 /* Not a broadcast address */ 2374 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2375 status = IXGBE_ERR_INVALID_MAC_ADDR; 2376 /* Reject the zero address */ 2377 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2378 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2379 status = IXGBE_ERR_INVALID_MAC_ADDR; 2380 } 2381 return status; 2382 } 2383 2384 /** 2385 * ixgbe_set_rar_generic - Set Rx address register 2386 * @hw: pointer to hardware structure 2387 * @index: Receive address register to write 2388 * @addr: Address to put into receive address register 2389 * @vmdq: VMDq "set" or "pool" index 2390 * @enable_addr: set flag that address is active 2391 * 2392 * Puts an ethernet address into a receive address register. 2393 **/ 2394 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2395 u32 enable_addr) 2396 { 2397 u32 rar_low, rar_high; 2398 u32 rar_entries = hw->mac.num_rar_entries; 2399 2400 DEBUGFUNC("ixgbe_set_rar_generic"); 2401 2402 /* Make sure we are using a valid rar index range */ 2403 if (index >= rar_entries) { 2404 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2405 "RAR index %d is out of range.\n", index); 2406 return IXGBE_ERR_INVALID_ARGUMENT; 2407 } 2408 2409 /* setup VMDq pool selection before this RAR gets enabled */ 2410 hw->mac.ops.set_vmdq(hw, index, vmdq); 2411 2412 /* 2413 * HW expects these in little endian so we reverse the byte 2414 * order from network order (big endian) to little endian 2415 */ 2416 rar_low = ((u32)addr[0] | 2417 ((u32)addr[1] << 8) | 2418 ((u32)addr[2] << 16) | 2419 ((u32)addr[3] << 24)); 2420 /* 2421 * Some parts put the VMDq setting in the extra RAH bits, 2422 * so save everything except the lower 16 bits that hold part 2423 * of the address and the address valid bit. 2424 */ 2425 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2426 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2427 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2428 2429 if (enable_addr != 0) 2430 rar_high |= IXGBE_RAH_AV; 2431 2432 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2433 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2434 2435 return IXGBE_SUCCESS; 2436 } 2437 2438 /** 2439 * ixgbe_clear_rar_generic - Remove Rx address register 2440 * @hw: pointer to hardware structure 2441 * @index: Receive address register to write 2442 * 2443 * Clears an ethernet address from a receive address register. 2444 **/ 2445 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2446 { 2447 u32 rar_high; 2448 u32 rar_entries = hw->mac.num_rar_entries; 2449 2450 DEBUGFUNC("ixgbe_clear_rar_generic"); 2451 2452 /* Make sure we are using a valid rar index range */ 2453 if (index >= rar_entries) { 2454 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2455 "RAR index %d is out of range.\n", index); 2456 return IXGBE_ERR_INVALID_ARGUMENT; 2457 } 2458 2459 /* 2460 * Some parts put the VMDq setting in the extra RAH bits, 2461 * so save everything except the lower 16 bits that hold part 2462 * of the address and the address valid bit. 2463 */ 2464 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2465 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2466 2467 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2468 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2469 2470 /* clear VMDq pool/queue selection for this RAR */ 2471 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2472 2473 return IXGBE_SUCCESS; 2474 } 2475 2476 /** 2477 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2478 * @hw: pointer to hardware structure 2479 * 2480 * Places the MAC address in receive address register 0 and clears the rest 2481 * of the receive address registers. Clears the multicast table. Assumes 2482 * the receiver is in reset when the routine is called. 2483 **/ 2484 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2485 { 2486 u32 i; 2487 u32 rar_entries = hw->mac.num_rar_entries; 2488 2489 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2490 2491 /* 2492 * If the current mac address is valid, assume it is a software override 2493 * to the permanent address. 2494 * Otherwise, use the permanent address from the eeprom. 2495 */ 2496 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2497 IXGBE_ERR_INVALID_MAC_ADDR) { 2498 /* Get the MAC address from the RAR0 for later reference */ 2499 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2500 2501 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2502 hw->mac.addr[0], hw->mac.addr[1], 2503 hw->mac.addr[2]); 2504 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2505 hw->mac.addr[4], hw->mac.addr[5]); 2506 } else { 2507 /* Setup the receive address. */ 2508 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2509 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2510 hw->mac.addr[0], hw->mac.addr[1], 2511 hw->mac.addr[2]); 2512 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2513 hw->mac.addr[4], hw->mac.addr[5]); 2514 2515 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2516 } 2517 2518 /* clear VMDq pool/queue selection for RAR 0 */ 2519 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2520 2521 hw->addr_ctrl.overflow_promisc = 0; 2522 2523 hw->addr_ctrl.rar_used_count = 1; 2524 2525 /* Zero out the other receive addresses. */ 2526 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2527 for (i = 1; i < rar_entries; i++) { 2528 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2529 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2530 } 2531 2532 /* Clear the MTA */ 2533 hw->addr_ctrl.mta_in_use = 0; 2534 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2535 2536 DEBUGOUT(" Clearing MTA\n"); 2537 for (i = 0; i < hw->mac.mcft_size; i++) 2538 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2539 2540 ixgbe_init_uta_tables(hw); 2541 2542 return IXGBE_SUCCESS; 2543 } 2544 2545 /** 2546 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2547 * @hw: pointer to hardware structure 2548 * @addr: new address 2549 * @vmdq: VMDq "set" or "pool" index 2550 * 2551 * Adds it to unused receive address register or goes into promiscuous mode. 2552 **/ 2553 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2554 { 2555 u32 rar_entries = hw->mac.num_rar_entries; 2556 u32 rar; 2557 2558 DEBUGFUNC("ixgbe_add_uc_addr"); 2559 2560 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2561 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2562 2563 /* 2564 * Place this address in the RAR if there is room, 2565 * else put the controller into promiscuous mode 2566 */ 2567 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2568 rar = hw->addr_ctrl.rar_used_count; 2569 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2570 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2571 hw->addr_ctrl.rar_used_count++; 2572 } else { 2573 hw->addr_ctrl.overflow_promisc++; 2574 } 2575 2576 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2577 } 2578 2579 /** 2580 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2581 * @hw: pointer to hardware structure 2582 * @addr_list: the list of new addresses 2583 * @addr_count: number of addresses 2584 * @next: iterator function to walk the address list 2585 * 2586 * The given list replaces any existing list. Clears the secondary addrs from 2587 * receive address registers. Uses unused receive address registers for the 2588 * first secondary addresses, and falls back to promiscuous mode as needed. 2589 * 2590 * Drivers using secondary unicast addresses must set user_set_promisc when 2591 * manually putting the device into promiscuous mode. 2592 **/ 2593 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2594 u32 addr_count, ixgbe_mc_addr_itr next) 2595 { 2596 u8 *addr; 2597 u32 i; 2598 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2599 u32 uc_addr_in_use; 2600 u32 fctrl; 2601 u32 vmdq; 2602 2603 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2604 2605 /* 2606 * Clear accounting of old secondary address list, 2607 * don't count RAR[0] 2608 */ 2609 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2610 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2611 hw->addr_ctrl.overflow_promisc = 0; 2612 2613 /* Zero out the other receive addresses */ 2614 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2615 for (i = 0; i < uc_addr_in_use; i++) { 2616 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2617 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2618 } 2619 2620 /* Add the new addresses */ 2621 for (i = 0; i < addr_count; i++) { 2622 DEBUGOUT(" Adding the secondary addresses:\n"); 2623 addr = next(hw, &addr_list, &vmdq); 2624 ixgbe_add_uc_addr(hw, addr, vmdq); 2625 } 2626 2627 if (hw->addr_ctrl.overflow_promisc) { 2628 /* enable promisc if not already in overflow or set by user */ 2629 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2630 DEBUGOUT(" Entering address overflow promisc mode\n"); 2631 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2632 fctrl |= IXGBE_FCTRL_UPE; 2633 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2634 } 2635 } else { 2636 /* only disable if set by overflow, not by user */ 2637 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2638 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2639 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2640 fctrl &= ~IXGBE_FCTRL_UPE; 2641 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2642 } 2643 } 2644 2645 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2646 return IXGBE_SUCCESS; 2647 } 2648 2649 /** 2650 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2651 * @hw: pointer to hardware structure 2652 * @mc_addr: the multicast address 2653 * 2654 * Extracts the 12 bits, from a multicast address, to determine which 2655 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2656 * incoming rx multicast addresses, to determine the bit-vector to check in 2657 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2658 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2659 * to mc_filter_type. 2660 **/ 2661 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2662 { 2663 u32 vector = 0; 2664 2665 DEBUGFUNC("ixgbe_mta_vector"); 2666 2667 switch (hw->mac.mc_filter_type) { 2668 case 0: /* use bits [47:36] of the address */ 2669 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2670 break; 2671 case 1: /* use bits [46:35] of the address */ 2672 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2673 break; 2674 case 2: /* use bits [45:34] of the address */ 2675 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2676 break; 2677 case 3: /* use bits [43:32] of the address */ 2678 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2679 break; 2680 default: /* Invalid mc_filter_type */ 2681 DEBUGOUT("MC filter type param set incorrectly\n"); 2682 ASSERT(0); 2683 break; 2684 } 2685 2686 /* vector can only be 12-bits or boundary will be exceeded */ 2687 vector &= 0xFFF; 2688 return vector; 2689 } 2690 2691 /** 2692 * ixgbe_set_mta - Set bit-vector in multicast table 2693 * @hw: pointer to hardware structure 2694 * @mc_addr: Multicast address 2695 * 2696 * Sets the bit-vector in the multicast table. 2697 **/ 2698 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2699 { 2700 u32 vector; 2701 u32 vector_bit; 2702 u32 vector_reg; 2703 2704 DEBUGFUNC("ixgbe_set_mta"); 2705 2706 hw->addr_ctrl.mta_in_use++; 2707 2708 vector = ixgbe_mta_vector(hw, mc_addr); 2709 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2710 2711 /* 2712 * The MTA is a register array of 128 32-bit registers. It is treated 2713 * like an array of 4096 bits. We want to set bit 2714 * BitArray[vector_value]. So we figure out what register the bit is 2715 * in, read it, OR in the new bit, then write back the new value. The 2716 * register is determined by the upper 7 bits of the vector value and 2717 * the bit within that register are determined by the lower 5 bits of 2718 * the value. 2719 */ 2720 vector_reg = (vector >> 5) & 0x7F; 2721 vector_bit = vector & 0x1F; 2722 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2723 } 2724 2725 /** 2726 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2727 * @hw: pointer to hardware structure 2728 * @mc_addr_list: the list of new multicast addresses 2729 * @mc_addr_count: number of addresses 2730 * @next: iterator function to walk the multicast address list 2731 * @clear: flag, when set clears the table beforehand 2732 * 2733 * When the clear flag is set, the given list replaces any existing list. 2734 * Hashes the given addresses into the multicast table. 2735 **/ 2736 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2737 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2738 bool clear) 2739 { 2740 u32 i; 2741 u32 vmdq; 2742 2743 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2744 2745 /* 2746 * Set the new number of MC addresses that we are being requested to 2747 * use. 2748 */ 2749 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2750 hw->addr_ctrl.mta_in_use = 0; 2751 2752 /* Clear mta_shadow */ 2753 if (clear) { 2754 DEBUGOUT(" Clearing MTA\n"); 2755 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2756 } 2757 2758 /* Update mta_shadow */ 2759 for (i = 0; i < mc_addr_count; i++) { 2760 DEBUGOUT(" Adding the multicast addresses:\n"); 2761 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2762 } 2763 2764 /* Enable mta */ 2765 for (i = 0; i < hw->mac.mcft_size; i++) 2766 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2767 hw->mac.mta_shadow[i]); 2768 2769 if (hw->addr_ctrl.mta_in_use > 0) 2770 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2771 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2772 2773 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2774 return IXGBE_SUCCESS; 2775 } 2776 2777 /** 2778 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2779 * @hw: pointer to hardware structure 2780 * 2781 * Enables multicast address in RAR and the use of the multicast hash table. 2782 **/ 2783 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2784 { 2785 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2786 2787 DEBUGFUNC("ixgbe_enable_mc_generic"); 2788 2789 if (a->mta_in_use > 0) 2790 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2791 hw->mac.mc_filter_type); 2792 2793 return IXGBE_SUCCESS; 2794 } 2795 2796 /** 2797 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2798 * @hw: pointer to hardware structure 2799 * 2800 * Disables multicast address in RAR and the use of the multicast hash table. 2801 **/ 2802 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2803 { 2804 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2805 2806 DEBUGFUNC("ixgbe_disable_mc_generic"); 2807 2808 if (a->mta_in_use > 0) 2809 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2810 2811 return IXGBE_SUCCESS; 2812 } 2813 2814 /** 2815 * ixgbe_fc_enable_generic - Enable flow control 2816 * @hw: pointer to hardware structure 2817 * 2818 * Enable flow control according to the current settings. 2819 **/ 2820 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2821 { 2822 s32 ret_val = IXGBE_SUCCESS; 2823 u32 mflcn_reg, fccfg_reg; 2824 u32 reg; 2825 u32 fcrtl, fcrth; 2826 int i; 2827 2828 DEBUGFUNC("ixgbe_fc_enable_generic"); 2829 2830 /* Validate the water mark configuration */ 2831 if (!hw->fc.pause_time) { 2832 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2833 goto out; 2834 } 2835 2836 /* Low water mark of zero causes XOFF floods */ 2837 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2838 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2839 hw->fc.high_water[i]) { 2840 if (!hw->fc.low_water[i] || 2841 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2842 DEBUGOUT("Invalid water mark configuration\n"); 2843 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2844 goto out; 2845 } 2846 } 2847 } 2848 2849 /* Negotiate the fc mode to use */ 2850 hw->mac.ops.fc_autoneg(hw); 2851 2852 /* Disable any previous flow control settings */ 2853 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2854 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2855 2856 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2857 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2858 2859 /* 2860 * The possible values of fc.current_mode are: 2861 * 0: Flow control is completely disabled 2862 * 1: Rx flow control is enabled (we can receive pause frames, 2863 * but not send pause frames). 2864 * 2: Tx flow control is enabled (we can send pause frames but 2865 * we do not support receiving pause frames). 2866 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2867 * other: Invalid. 2868 */ 2869 switch (hw->fc.current_mode) { 2870 case ixgbe_fc_none: 2871 /* 2872 * Flow control is disabled by software override or autoneg. 2873 * The code below will actually disable it in the HW. 2874 */ 2875 break; 2876 case ixgbe_fc_rx_pause: 2877 /* 2878 * Rx Flow control is enabled and Tx Flow control is 2879 * disabled by software override. Since there really 2880 * isn't a way to advertise that we are capable of RX 2881 * Pause ONLY, we will advertise that we support both 2882 * symmetric and asymmetric Rx PAUSE. Later, we will 2883 * disable the adapter's ability to send PAUSE frames. 2884 */ 2885 mflcn_reg |= IXGBE_MFLCN_RFCE; 2886 break; 2887 case ixgbe_fc_tx_pause: 2888 /* 2889 * Tx Flow control is enabled, and Rx Flow control is 2890 * disabled by software override. 2891 */ 2892 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2893 break; 2894 case ixgbe_fc_full: 2895 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2896 mflcn_reg |= IXGBE_MFLCN_RFCE; 2897 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2898 break; 2899 default: 2900 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2901 "Flow control param set incorrectly\n"); 2902 ret_val = IXGBE_ERR_CONFIG; 2903 goto out; 2904 break; 2905 } 2906 2907 /* Set 802.3x based flow control settings. */ 2908 mflcn_reg |= IXGBE_MFLCN_DPF; 2909 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2910 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2911 2912 2913 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2914 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2915 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2916 hw->fc.high_water[i]) { 2917 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2918 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2919 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2920 } else { 2921 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2922 /* 2923 * In order to prevent Tx hangs when the internal Tx 2924 * switch is enabled we must set the high water mark 2925 * to the Rx packet buffer size - 24KB. This allows 2926 * the Tx switch to function even under heavy Rx 2927 * workloads. 2928 */ 2929 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2930 } 2931 2932 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2933 } 2934 2935 /* Configure pause time (2 TCs per register) */ 2936 reg = hw->fc.pause_time * 0x00010001U; 2937 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2938 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2939 2940 /* Configure flow control refresh threshold value */ 2941 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2942 2943 out: 2944 return ret_val; 2945 } 2946 2947 /** 2948 * ixgbe_negotiate_fc - Negotiate flow control 2949 * @hw: pointer to hardware structure 2950 * @adv_reg: flow control advertised settings 2951 * @lp_reg: link partner's flow control settings 2952 * @adv_sym: symmetric pause bit in advertisement 2953 * @adv_asm: asymmetric pause bit in advertisement 2954 * @lp_sym: symmetric pause bit in link partner advertisement 2955 * @lp_asm: asymmetric pause bit in link partner advertisement 2956 * 2957 * Find the intersection between advertised settings and link partner's 2958 * advertised settings 2959 **/ 2960 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2961 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2962 { 2963 if ((!(adv_reg)) || (!(lp_reg))) { 2964 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2965 "Local or link partner's advertised flow control " 2966 "settings are NULL. Local: %x, link partner: %x\n", 2967 adv_reg, lp_reg); 2968 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2969 } 2970 2971 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2972 /* 2973 * Now we need to check if the user selected Rx ONLY 2974 * of pause frames. In this case, we had to advertise 2975 * FULL flow control because we could not advertise RX 2976 * ONLY. Hence, we must now check to see if we need to 2977 * turn OFF the TRANSMISSION of PAUSE frames. 2978 */ 2979 if (hw->fc.requested_mode == ixgbe_fc_full) { 2980 hw->fc.current_mode = ixgbe_fc_full; 2981 DEBUGOUT("Flow Control = FULL.\n"); 2982 } else { 2983 hw->fc.current_mode = ixgbe_fc_rx_pause; 2984 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2985 } 2986 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2987 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2988 hw->fc.current_mode = ixgbe_fc_tx_pause; 2989 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2990 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2991 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2992 hw->fc.current_mode = ixgbe_fc_rx_pause; 2993 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2994 } else { 2995 hw->fc.current_mode = ixgbe_fc_none; 2996 DEBUGOUT("Flow Control = NONE.\n"); 2997 } 2998 return IXGBE_SUCCESS; 2999 } 3000 3001 /** 3002 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 3003 * @hw: pointer to hardware structure 3004 * 3005 * Enable flow control according on 1 gig fiber. 3006 **/ 3007 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 3008 { 3009 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 3010 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3011 3012 /* 3013 * On multispeed fiber at 1g, bail out if 3014 * - link is up but AN did not complete, or if 3015 * - link is up and AN completed but timed out 3016 */ 3017 3018 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3019 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3020 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3021 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3022 goto out; 3023 } 3024 3025 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3026 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3027 3028 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3029 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3030 IXGBE_PCS1GANA_ASM_PAUSE, 3031 IXGBE_PCS1GANA_SYM_PAUSE, 3032 IXGBE_PCS1GANA_ASM_PAUSE); 3033 3034 out: 3035 return ret_val; 3036 } 3037 3038 /** 3039 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3040 * @hw: pointer to hardware structure 3041 * 3042 * Enable flow control according to IEEE clause 37. 3043 **/ 3044 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3045 { 3046 u32 links2, anlp1_reg, autoc_reg, links; 3047 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3048 3049 /* 3050 * On backplane, bail out if 3051 * - backplane autoneg was not completed, or if 3052 * - we are 82599 and link partner is not AN enabled 3053 */ 3054 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3055 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3056 DEBUGOUT("Auto-Negotiation did not complete\n"); 3057 goto out; 3058 } 3059 3060 if (hw->mac.type == ixgbe_mac_82599EB) { 3061 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3062 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3063 DEBUGOUT("Link partner is not AN enabled\n"); 3064 goto out; 3065 } 3066 } 3067 /* 3068 * Read the 10g AN autoc and LP ability registers and resolve 3069 * local flow control settings accordingly 3070 */ 3071 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3072 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3073 3074 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3075 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3076 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3077 3078 out: 3079 return ret_val; 3080 } 3081 3082 /** 3083 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3084 * @hw: pointer to hardware structure 3085 * 3086 * Enable flow control according to IEEE clause 37. 3087 **/ 3088 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3089 { 3090 u16 technology_ability_reg = 0; 3091 u16 lp_technology_ability_reg = 0; 3092 3093 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3094 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3095 &technology_ability_reg); 3096 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3097 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3098 &lp_technology_ability_reg); 3099 3100 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3101 (u32)lp_technology_ability_reg, 3102 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3103 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3104 } 3105 3106 /** 3107 * ixgbe_fc_autoneg - Configure flow control 3108 * @hw: pointer to hardware structure 3109 * 3110 * Compares our advertised flow control capabilities to those advertised by 3111 * our link partner, and determines the proper flow control mode to use. 3112 **/ 3113 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3114 { 3115 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3116 ixgbe_link_speed speed; 3117 bool link_up; 3118 3119 DEBUGFUNC("ixgbe_fc_autoneg"); 3120 3121 /* 3122 * AN should have completed when the cable was plugged in. 3123 * Look for reasons to bail out. Bail out if: 3124 * - FC autoneg is disabled, or if 3125 * - link is not up. 3126 */ 3127 if (hw->fc.disable_fc_autoneg) { 3128 /* TODO: This should be just an informative log */ 3129 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 3130 "Flow control autoneg is disabled"); 3131 goto out; 3132 } 3133 3134 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3135 if (!link_up) { 3136 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3137 goto out; 3138 } 3139 3140 switch (hw->phy.media_type) { 3141 /* Autoneg flow control on fiber adapters */ 3142 case ixgbe_media_type_fiber_fixed: 3143 case ixgbe_media_type_fiber_qsfp: 3144 case ixgbe_media_type_fiber: 3145 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3146 ret_val = ixgbe_fc_autoneg_fiber(hw); 3147 break; 3148 3149 /* Autoneg flow control on backplane adapters */ 3150 case ixgbe_media_type_backplane: 3151 ret_val = ixgbe_fc_autoneg_backplane(hw); 3152 break; 3153 3154 /* Autoneg flow control on copper adapters */ 3155 case ixgbe_media_type_copper: 3156 if (ixgbe_device_supports_autoneg_fc(hw)) 3157 ret_val = ixgbe_fc_autoneg_copper(hw); 3158 break; 3159 3160 default: 3161 break; 3162 } 3163 3164 out: 3165 if (ret_val == IXGBE_SUCCESS) { 3166 hw->fc.fc_was_autonegged = true; 3167 } else { 3168 hw->fc.fc_was_autonegged = false; 3169 hw->fc.current_mode = hw->fc.requested_mode; 3170 } 3171 } 3172 3173 /* 3174 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3175 * @hw: pointer to hardware structure 3176 * 3177 * System-wide timeout range is encoded in PCIe Device Control2 register. 3178 * 3179 * Add 10% to specified maximum and return the number of times to poll for 3180 * completion timeout, in units of 100 microsec. Never return less than 3181 * 800 = 80 millisec. 3182 */ 3183 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3184 { 3185 s16 devctl2; 3186 u32 pollcnt; 3187 3188 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3189 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3190 3191 switch (devctl2) { 3192 case IXGBE_PCIDEVCTRL2_65_130ms: 3193 pollcnt = 1300; /* 130 millisec */ 3194 break; 3195 case IXGBE_PCIDEVCTRL2_260_520ms: 3196 pollcnt = 5200; /* 520 millisec */ 3197 break; 3198 case IXGBE_PCIDEVCTRL2_1_2s: 3199 pollcnt = 20000; /* 2 sec */ 3200 break; 3201 case IXGBE_PCIDEVCTRL2_4_8s: 3202 pollcnt = 80000; /* 8 sec */ 3203 break; 3204 case IXGBE_PCIDEVCTRL2_17_34s: 3205 pollcnt = 34000; /* 34 sec */ 3206 break; 3207 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3208 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3209 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3210 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3211 default: 3212 pollcnt = 800; /* 80 millisec minimum */ 3213 break; 3214 } 3215 3216 /* add 10% to spec maximum */ 3217 return (pollcnt * 11) / 10; 3218 } 3219 3220 /** 3221 * ixgbe_disable_pcie_primary - Disable PCI-express primary access 3222 * @hw: pointer to hardware structure 3223 * 3224 * Disables PCI-Express primary access and verifies there are no pending 3225 * requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable 3226 * bit hasn't caused the primary requests to be disabled, else IXGBE_SUCCESS 3227 * is returned signifying primary requests disabled. 3228 **/ 3229 s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) 3230 { 3231 s32 status = IXGBE_SUCCESS; 3232 u32 i, poll; 3233 u16 value; 3234 3235 DEBUGFUNC("ixgbe_disable_pcie_primary"); 3236 3237 /* Always set this bit to ensure any future transactions are blocked */ 3238 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3239 3240 /* Exit if primary requests are blocked */ 3241 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3242 IXGBE_REMOVED(hw->hw_addr)) 3243 goto out; 3244 3245 /* Poll for primary request bit to clear */ 3246 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { 3247 usec_delay(100); 3248 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3249 goto out; 3250 } 3251 3252 /* 3253 * Two consecutive resets are required via CTRL.RST per datasheet 3254 * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine 3255 * of this need. The first reset prevents new primary requests from 3256 * being issued by our device. We then must wait 1usec or more for any 3257 * remaining completions from the PCIe bus to trickle in, and then reset 3258 * again to clear out any effects they may have had on our device. 3259 */ 3260 DEBUGOUT("GIO Primary Disable bit didn't clear - requesting resets\n"); 3261 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3262 3263 if (hw->mac.type >= ixgbe_mac_X550) 3264 goto out; 3265 3266 /* 3267 * Before proceeding, make sure that the PCIe block does not have 3268 * transactions pending. 3269 */ 3270 poll = ixgbe_pcie_timeout_poll(hw); 3271 for (i = 0; i < poll; i++) { 3272 usec_delay(100); 3273 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3274 if (IXGBE_REMOVED(hw->hw_addr)) 3275 goto out; 3276 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3277 goto out; 3278 } 3279 3280 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3281 "PCIe transaction pending bit also did not clear.\n"); 3282 status = IXGBE_ERR_PRIMARY_REQUESTS_PENDING; 3283 3284 out: 3285 return status; 3286 } 3287 3288 /** 3289 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3290 * @hw: pointer to hardware structure 3291 * @mask: Mask to specify which semaphore to acquire 3292 * 3293 * Acquires the SWFW semaphore through the GSSR register for the specified 3294 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3295 **/ 3296 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3297 { 3298 u32 gssr = 0; 3299 u32 swmask = mask; 3300 u32 fwmask = mask << 5; 3301 u32 timeout = 200; 3302 u32 i; 3303 3304 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3305 3306 for (i = 0; i < timeout; i++) { 3307 /* 3308 * SW NVM semaphore bit is used for access to all 3309 * SW_FW_SYNC bits (not just NVM) 3310 */ 3311 if (ixgbe_get_eeprom_semaphore(hw)) 3312 return IXGBE_ERR_SWFW_SYNC; 3313 3314 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3315 if (!(gssr & (fwmask | swmask))) { 3316 gssr |= swmask; 3317 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3318 ixgbe_release_eeprom_semaphore(hw); 3319 return IXGBE_SUCCESS; 3320 } else { 3321 /* Resource is currently in use by FW or SW */ 3322 ixgbe_release_eeprom_semaphore(hw); 3323 msec_delay(5); 3324 } 3325 } 3326 3327 /* If time expired clear the bits holding the lock and retry */ 3328 if (gssr & (fwmask | swmask)) 3329 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3330 3331 msec_delay(5); 3332 return IXGBE_ERR_SWFW_SYNC; 3333 } 3334 3335 /** 3336 * ixgbe_release_swfw_sync - Release SWFW semaphore 3337 * @hw: pointer to hardware structure 3338 * @mask: Mask to specify which semaphore to release 3339 * 3340 * Releases the SWFW semaphore through the GSSR register for the specified 3341 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3342 **/ 3343 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3344 { 3345 u32 gssr; 3346 u32 swmask = mask; 3347 3348 DEBUGFUNC("ixgbe_release_swfw_sync"); 3349 3350 ixgbe_get_eeprom_semaphore(hw); 3351 3352 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3353 gssr &= ~swmask; 3354 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3355 3356 ixgbe_release_eeprom_semaphore(hw); 3357 } 3358 3359 /** 3360 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3361 * @hw: pointer to hardware structure 3362 * 3363 * Stops the receive data path and waits for the HW to internally empty 3364 * the Rx security block 3365 **/ 3366 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3367 { 3368 #define IXGBE_MAX_SECRX_POLL 4000 3369 3370 int i; 3371 int secrxreg; 3372 3373 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3374 3375 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3376 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3377 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3378 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3379 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3380 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3381 break; 3382 else 3383 /* Use interrupt-safe sleep just in case */ 3384 usec_delay(10); 3385 } 3386 3387 /* For informational purposes only */ 3388 if (i >= IXGBE_MAX_SECRX_POLL) 3389 DEBUGOUT("Rx unit being enabled before security " 3390 "path fully disabled. Continuing with init.\n"); 3391 3392 return IXGBE_SUCCESS; 3393 } 3394 3395 /** 3396 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3397 * @hw: pointer to hardware structure 3398 * @locked: bool to indicate whether the SW/FW lock was taken 3399 * @reg_val: Value we read from AUTOC 3400 * 3401 * The default case requires no protection so just to the register read. 3402 */ 3403 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3404 { 3405 *locked = false; 3406 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3407 return IXGBE_SUCCESS; 3408 } 3409 3410 /** 3411 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3412 * @hw: pointer to hardware structure 3413 * @reg_val: value to write to AUTOC 3414 * @locked: bool to indicate whether the SW/FW lock was already taken by 3415 * previous read. 3416 * 3417 * The default case requires no protection so just to the register write. 3418 */ 3419 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3420 { 3421 UNREFERENCED_1PARAMETER(locked); 3422 3423 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3424 return IXGBE_SUCCESS; 3425 } 3426 3427 /** 3428 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3429 * @hw: pointer to hardware structure 3430 * 3431 * Enables the receive data path. 3432 **/ 3433 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3434 { 3435 u32 secrxreg; 3436 3437 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3438 3439 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3440 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3441 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3442 IXGBE_WRITE_FLUSH(hw); 3443 3444 return IXGBE_SUCCESS; 3445 } 3446 3447 /** 3448 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3449 * @hw: pointer to hardware structure 3450 * @regval: register value to write to RXCTRL 3451 * 3452 * Enables the Rx DMA unit 3453 **/ 3454 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3455 { 3456 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3457 3458 if (regval & IXGBE_RXCTRL_RXEN) 3459 ixgbe_enable_rx(hw); 3460 else 3461 ixgbe_disable_rx(hw); 3462 3463 return IXGBE_SUCCESS; 3464 } 3465 3466 /** 3467 * ixgbe_blink_led_start_generic - Blink LED based on index. 3468 * @hw: pointer to hardware structure 3469 * @index: led number to blink 3470 **/ 3471 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3472 { 3473 ixgbe_link_speed speed = 0; 3474 bool link_up = 0; 3475 u32 autoc_reg = 0; 3476 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3477 s32 ret_val = IXGBE_SUCCESS; 3478 bool locked = false; 3479 3480 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3481 3482 if (index > 3) 3483 return IXGBE_ERR_PARAM; 3484 3485 /* 3486 * Link must be up to auto-blink the LEDs; 3487 * Force it if link is down. 3488 */ 3489 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3490 3491 if (!link_up) { 3492 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3493 if (ret_val != IXGBE_SUCCESS) 3494 goto out; 3495 3496 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3497 autoc_reg |= IXGBE_AUTOC_FLU; 3498 3499 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3500 if (ret_val != IXGBE_SUCCESS) 3501 goto out; 3502 3503 IXGBE_WRITE_FLUSH(hw); 3504 msec_delay(10); 3505 } 3506 3507 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3508 led_reg |= IXGBE_LED_BLINK(index); 3509 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3510 IXGBE_WRITE_FLUSH(hw); 3511 3512 out: 3513 return ret_val; 3514 } 3515 3516 /** 3517 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3518 * @hw: pointer to hardware structure 3519 * @index: led number to stop blinking 3520 **/ 3521 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3522 { 3523 u32 autoc_reg = 0; 3524 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3525 s32 ret_val = IXGBE_SUCCESS; 3526 bool locked = false; 3527 3528 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3529 3530 if (index > 3) 3531 return IXGBE_ERR_PARAM; 3532 3533 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3534 if (ret_val != IXGBE_SUCCESS) 3535 goto out; 3536 3537 autoc_reg &= ~IXGBE_AUTOC_FLU; 3538 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3539 3540 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3541 if (ret_val != IXGBE_SUCCESS) 3542 goto out; 3543 3544 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3545 led_reg &= ~IXGBE_LED_BLINK(index); 3546 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3547 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3548 IXGBE_WRITE_FLUSH(hw); 3549 3550 out: 3551 return ret_val; 3552 } 3553 3554 /** 3555 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3556 * @hw: pointer to hardware structure 3557 * @san_mac_offset: SAN MAC address offset 3558 * 3559 * This function will read the EEPROM location for the SAN MAC address 3560 * pointer, and returns the value at that location. This is used in both 3561 * get and set mac_addr routines. 3562 **/ 3563 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3564 u16 *san_mac_offset) 3565 { 3566 s32 ret_val; 3567 3568 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3569 3570 /* 3571 * First read the EEPROM pointer to see if the MAC addresses are 3572 * available. 3573 */ 3574 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3575 san_mac_offset); 3576 if (ret_val) { 3577 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3578 "eeprom at offset %d failed", 3579 IXGBE_SAN_MAC_ADDR_PTR); 3580 } 3581 3582 return ret_val; 3583 } 3584 3585 /** 3586 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3587 * @hw: pointer to hardware structure 3588 * @san_mac_addr: SAN MAC address 3589 * 3590 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3591 * per-port, so set_lan_id() must be called before reading the addresses. 3592 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3593 * upon for non-SFP connections, so we must call it here. 3594 **/ 3595 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3596 { 3597 u16 san_mac_data, san_mac_offset; 3598 u8 i; 3599 s32 ret_val; 3600 3601 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3602 3603 /* 3604 * First read the EEPROM pointer to see if the MAC addresses are 3605 * available. If they're not, no point in calling set_lan_id() here. 3606 */ 3607 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3608 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3609 goto san_mac_addr_out; 3610 3611 /* make sure we know which port we need to program */ 3612 hw->mac.ops.set_lan_id(hw); 3613 /* apply the port offset to the address offset */ 3614 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3615 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3616 for (i = 0; i < 3; i++) { 3617 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3618 &san_mac_data); 3619 if (ret_val) { 3620 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3621 "eeprom read at offset %d failed", 3622 san_mac_offset); 3623 goto san_mac_addr_out; 3624 } 3625 san_mac_addr[i * 2] = (u8)(san_mac_data); 3626 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3627 san_mac_offset++; 3628 } 3629 return IXGBE_SUCCESS; 3630 3631 san_mac_addr_out: 3632 /* 3633 * No addresses available in this EEPROM. It's not an 3634 * error though, so just wipe the local address and return. 3635 */ 3636 for (i = 0; i < 6; i++) 3637 san_mac_addr[i] = 0xFF; 3638 return IXGBE_SUCCESS; 3639 } 3640 3641 /** 3642 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3643 * @hw: pointer to hardware structure 3644 * @san_mac_addr: SAN MAC address 3645 * 3646 * Write a SAN MAC address to the EEPROM. 3647 **/ 3648 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3649 { 3650 s32 ret_val; 3651 u16 san_mac_data, san_mac_offset; 3652 u8 i; 3653 3654 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3655 3656 /* Look for SAN mac address pointer. If not defined, return */ 3657 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3658 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3659 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3660 3661 /* Make sure we know which port we need to write */ 3662 hw->mac.ops.set_lan_id(hw); 3663 /* Apply the port offset to the address offset */ 3664 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3665 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3666 3667 for (i = 0; i < 3; i++) { 3668 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3669 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3670 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3671 san_mac_offset++; 3672 } 3673 3674 return IXGBE_SUCCESS; 3675 } 3676 3677 /** 3678 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3679 * @hw: pointer to hardware structure 3680 * 3681 * Read PCIe configuration space, and get the MSI-X vector count from 3682 * the capabilities table. 3683 **/ 3684 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3685 { 3686 u16 msix_count = 1; 3687 u16 max_msix_count; 3688 u16 pcie_offset; 3689 3690 switch (hw->mac.type) { 3691 case ixgbe_mac_82598EB: 3692 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3693 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3694 break; 3695 case ixgbe_mac_82599EB: 3696 case ixgbe_mac_X540: 3697 case ixgbe_mac_X550: 3698 case ixgbe_mac_X550EM_x: 3699 case ixgbe_mac_X550EM_a: 3700 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3701 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3702 break; 3703 case ixgbe_mac_E610: 3704 pcie_offset = IXGBE_PCIE_MSIX_E610_CAPS; 3705 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3706 break; 3707 default: 3708 return msix_count; 3709 } 3710 3711 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3712 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3713 if (IXGBE_REMOVED(hw->hw_addr)) 3714 msix_count = 0; 3715 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3716 3717 /* MSI-X count is zero-based in HW */ 3718 msix_count++; 3719 3720 if (msix_count > max_msix_count) 3721 msix_count = max_msix_count; 3722 3723 return msix_count; 3724 } 3725 3726 /** 3727 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3728 * @hw: pointer to hardware structure 3729 * @addr: Address to put into receive address register 3730 * @vmdq: VMDq pool to assign 3731 * 3732 * Puts an ethernet address into a receive address register, or 3733 * finds the rar that it is already in; adds to the pool list 3734 **/ 3735 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3736 { 3737 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3738 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3739 u32 rar; 3740 u32 rar_low, rar_high; 3741 u32 addr_low, addr_high; 3742 3743 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3744 3745 /* swap bytes for HW little endian */ 3746 addr_low = addr[0] | (addr[1] << 8) 3747 | (addr[2] << 16) 3748 | (addr[3] << 24); 3749 addr_high = addr[4] | (addr[5] << 8); 3750 3751 /* 3752 * Either find the mac_id in rar or find the first empty space. 3753 * rar_highwater points to just after the highest currently used 3754 * rar in order to shorten the search. It grows when we add a new 3755 * rar to the top. 3756 */ 3757 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3758 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3759 3760 if (((IXGBE_RAH_AV & rar_high) == 0) 3761 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3762 first_empty_rar = rar; 3763 } else if ((rar_high & 0xFFFF) == addr_high) { 3764 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3765 if (rar_low == addr_low) 3766 break; /* found it already in the rars */ 3767 } 3768 } 3769 3770 if (rar < hw->mac.rar_highwater) { 3771 /* already there so just add to the pool bits */ 3772 ixgbe_set_vmdq(hw, rar, vmdq); 3773 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3774 /* stick it into first empty RAR slot we found */ 3775 rar = first_empty_rar; 3776 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3777 } else if (rar == hw->mac.rar_highwater) { 3778 /* add it to the top of the list and inc the highwater mark */ 3779 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3780 hw->mac.rar_highwater++; 3781 } else if (rar >= hw->mac.num_rar_entries) { 3782 return IXGBE_ERR_INVALID_MAC_ADDR; 3783 } 3784 3785 /* 3786 * If we found rar[0], make sure the default pool bit (we use pool 0) 3787 * remains cleared to be sure default pool packets will get delivered 3788 */ 3789 if (rar == 0) 3790 ixgbe_clear_vmdq(hw, rar, 0); 3791 3792 return rar; 3793 } 3794 3795 /** 3796 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3797 * @hw: pointer to hardware struct 3798 * @rar: receive address register index to disassociate 3799 * @vmdq: VMDq pool index to remove from the rar 3800 **/ 3801 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3802 { 3803 u32 mpsar_lo, mpsar_hi; 3804 u32 rar_entries = hw->mac.num_rar_entries; 3805 3806 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3807 3808 /* Make sure we are using a valid rar index range */ 3809 if (rar >= rar_entries) { 3810 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3811 "RAR index %d is out of range.\n", rar); 3812 return IXGBE_ERR_INVALID_ARGUMENT; 3813 } 3814 3815 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3816 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3817 3818 if (IXGBE_REMOVED(hw->hw_addr)) 3819 goto done; 3820 3821 if (!mpsar_lo && !mpsar_hi) 3822 goto done; 3823 3824 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3825 if (mpsar_lo) { 3826 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3827 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3828 } 3829 if (mpsar_hi) { 3830 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3831 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3832 } 3833 } else if (vmdq < 32) { 3834 mpsar_lo &= ~(1 << vmdq); 3835 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3836 } else { 3837 mpsar_hi &= ~(1 << (vmdq - 32)); 3838 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3839 } 3840 3841 /* was that the last pool using this rar? */ 3842 if (mpsar_lo == 0 && mpsar_hi == 0 && 3843 rar != 0 && rar != hw->mac.san_mac_rar_index) 3844 hw->mac.ops.clear_rar(hw, rar); 3845 done: 3846 return IXGBE_SUCCESS; 3847 } 3848 3849 /** 3850 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3851 * @hw: pointer to hardware struct 3852 * @rar: receive address register index to associate with a VMDq index 3853 * @vmdq: VMDq pool index 3854 **/ 3855 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3856 { 3857 u32 mpsar; 3858 u32 rar_entries = hw->mac.num_rar_entries; 3859 3860 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3861 3862 /* Make sure we are using a valid rar index range */ 3863 if (rar >= rar_entries) { 3864 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3865 "RAR index %d is out of range.\n", rar); 3866 return IXGBE_ERR_INVALID_ARGUMENT; 3867 } 3868 3869 if (vmdq < 32) { 3870 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3871 mpsar |= 1 << vmdq; 3872 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3873 } else { 3874 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3875 mpsar |= 1 << (vmdq - 32); 3876 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3877 } 3878 return IXGBE_SUCCESS; 3879 } 3880 3881 /** 3882 * ixgbe_set_vmdq_san_mac_generic - Associate default VMDq pool index with 3883 * a rx address 3884 * @hw: pointer to hardware struct 3885 * @vmdq: VMDq pool index 3886 * 3887 * This function should only be involved in the IOV mode. 3888 * In IOV mode, Default pool is next pool after the number of 3889 * VFs advertized and not 0. 3890 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3891 **/ 3892 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3893 { 3894 u32 rar = hw->mac.san_mac_rar_index; 3895 3896 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3897 3898 if (vmdq < 32) { 3899 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3900 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3901 } else { 3902 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3903 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3904 } 3905 3906 return IXGBE_SUCCESS; 3907 } 3908 3909 /** 3910 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3911 * @hw: pointer to hardware structure 3912 **/ 3913 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3914 { 3915 int i; 3916 3917 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3918 DEBUGOUT(" Clearing UTA\n"); 3919 3920 for (i = 0; i < 128; i++) 3921 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3922 3923 return IXGBE_SUCCESS; 3924 } 3925 3926 /** 3927 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3928 * @hw: pointer to hardware structure 3929 * @vlan: VLAN id to write to VLAN filter 3930 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 3931 * vlanid not found 3932 * 3933 * 3934 * return the VLVF index where this VLAN id should be placed 3935 * 3936 **/ 3937 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3938 { 3939 s32 regindex, first_empty_slot; 3940 u32 bits; 3941 3942 /* short cut the special case */ 3943 if (vlan == 0) 3944 return 0; 3945 3946 /* if vlvf_bypass is set we don't want to use an empty slot, we 3947 * will simply bypass the VLVF if there are no entries present in the 3948 * VLVF that contain our VLAN 3949 */ 3950 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3951 3952 /* add VLAN enable bit for comparison */ 3953 vlan |= IXGBE_VLVF_VIEN; 3954 3955 /* Search for the vlan id in the VLVF entries. Save off the first empty 3956 * slot found along the way. 3957 * 3958 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3959 */ 3960 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3961 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3962 if (bits == vlan) 3963 return regindex; 3964 if (!first_empty_slot && !bits) 3965 first_empty_slot = regindex; 3966 } 3967 3968 /* If we are here then we didn't find the VLAN. Return first empty 3969 * slot we found during our search, else error. 3970 */ 3971 if (!first_empty_slot) 3972 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3973 3974 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3975 } 3976 3977 /** 3978 * ixgbe_set_vfta_generic - Set VLAN filter table 3979 * @hw: pointer to hardware structure 3980 * @vlan: VLAN id to write to VLAN filter 3981 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3982 * @vlan_on: boolean flag to turn on/off VLAN 3983 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3984 * 3985 * Turn on/off specified VLAN in the VLAN filter table. 3986 **/ 3987 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3988 bool vlan_on, bool vlvf_bypass) 3989 { 3990 u32 regidx, vfta_delta, vfta; 3991 s32 ret_val; 3992 3993 DEBUGFUNC("ixgbe_set_vfta_generic"); 3994 3995 if (vlan > 4095 || vind > 63) 3996 return IXGBE_ERR_PARAM; 3997 3998 /* 3999 * this is a 2 part operation - first the VFTA, then the 4000 * VLVF and VLVFB if VT Mode is set 4001 * We don't write the VFTA until we know the VLVF part succeeded. 4002 */ 4003 4004 /* Part 1 4005 * The VFTA is a bitstring made up of 128 32-bit registers 4006 * that enable the particular VLAN id, much like the MTA: 4007 * bits[11-5]: which register 4008 * bits[4-0]: which bit in the register 4009 */ 4010 regidx = vlan / 32; 4011 vfta_delta = 1 << (vlan % 32); 4012 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 4013 4014 /* 4015 * vfta_delta represents the difference between the current value 4016 * of vfta and the value we want in the register. Since the diff 4017 * is an XOR mask we can just update the vfta using an XOR 4018 */ 4019 vfta_delta &= vlan_on ? ~vfta : vfta; 4020 vfta ^= vfta_delta; 4021 4022 /* Part 2 4023 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4024 */ 4025 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4026 vfta, vlvf_bypass); 4027 if (ret_val != IXGBE_SUCCESS) { 4028 if (vlvf_bypass) 4029 goto vfta_update; 4030 return ret_val; 4031 } 4032 4033 vfta_update: 4034 /* Update VFTA now that we are ready for traffic */ 4035 if (vfta_delta) 4036 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4037 4038 return IXGBE_SUCCESS; 4039 } 4040 4041 /** 4042 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4043 * @hw: pointer to hardware structure 4044 * @vlan: VLAN id to write to VLAN filter 4045 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4046 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4047 * @vfta_delta: pointer to the difference between the current value of VFTA 4048 * and the desired value 4049 * @vfta: the desired value of the VFTA 4050 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4051 * 4052 * Turn on/off specified bit in VLVF table. 4053 **/ 4054 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4055 bool vlan_on, u32 *vfta_delta, u32 vfta, 4056 bool vlvf_bypass) 4057 { 4058 u32 bits; 4059 s32 vlvf_index; 4060 4061 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4062 4063 if (vlan > 4095 || vind > 63) 4064 return IXGBE_ERR_PARAM; 4065 4066 /* If VT Mode is set 4067 * Either vlan_on 4068 * make sure the vlan is in VLVF 4069 * set the vind bit in the matching VLVFB 4070 * Or !vlan_on 4071 * clear the pool bit and possibly the vind 4072 */ 4073 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4074 return IXGBE_SUCCESS; 4075 4076 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4077 if (vlvf_index < 0) 4078 return vlvf_index; 4079 4080 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4081 4082 /* set the pool bit */ 4083 bits |= 1 << (vind % 32); 4084 if (vlan_on) 4085 goto vlvf_update; 4086 4087 /* clear the pool bit */ 4088 bits ^= 1 << (vind % 32); 4089 4090 if (!bits && 4091 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4092 /* Clear VFTA first, then disable VLVF. Otherwise 4093 * we run the risk of stray packets leaking into 4094 * the PF via the default pool 4095 */ 4096 if (*vfta_delta) 4097 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4098 4099 /* disable VLVF and clear remaining bit from pool */ 4100 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4101 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4102 4103 return IXGBE_SUCCESS; 4104 } 4105 4106 /* If there are still bits set in the VLVFB registers 4107 * for the VLAN ID indicated we need to see if the 4108 * caller is requesting that we clear the VFTA entry bit. 4109 * If the caller has requested that we clear the VFTA 4110 * entry bit but there are still pools/VFs using this VLAN 4111 * ID entry then ignore the request. We're not worried 4112 * about the case where we're turning the VFTA VLAN ID 4113 * entry bit on, only when requested to turn it off as 4114 * there may be multiple pools and/or VFs using the 4115 * VLAN ID entry. In that case we cannot clear the 4116 * VFTA bit until all pools/VFs using that VLAN ID have also 4117 * been cleared. This will be indicated by "bits" being 4118 * zero. 4119 */ 4120 *vfta_delta = 0; 4121 4122 vlvf_update: 4123 /* record pool change and enable VLAN ID if not already enabled */ 4124 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4125 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4126 4127 return IXGBE_SUCCESS; 4128 } 4129 4130 /** 4131 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4132 * @hw: pointer to hardware structure 4133 * 4134 * Clears the VLAN filter table, and the VMDq index associated with the filter 4135 **/ 4136 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4137 { 4138 u32 offset; 4139 4140 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4141 4142 for (offset = 0; offset < hw->mac.vft_size; offset++) 4143 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4144 4145 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4146 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4147 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4148 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 4149 } 4150 4151 return IXGBE_SUCCESS; 4152 } 4153 4154 /** 4155 * ixgbe_toggle_txdctl_generic - Toggle VF's queues 4156 * @hw: pointer to hardware structure 4157 * @vf_number: VF number 4158 * 4159 * Enable and disable each queue in VF. 4160 */ 4161 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number) 4162 { 4163 u8 queue_count, i; 4164 u32 offset, reg; 4165 4166 if (vf_number > 63) 4167 return IXGBE_ERR_PARAM; 4168 4169 /* 4170 * Determine number of queues by checking 4171 * number of virtual functions 4172 */ 4173 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4174 switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) { 4175 case IXGBE_GCR_EXT_VT_MODE_64: 4176 queue_count = 2; 4177 break; 4178 case IXGBE_GCR_EXT_VT_MODE_32: 4179 queue_count = 4; 4180 break; 4181 case IXGBE_GCR_EXT_VT_MODE_16: 4182 queue_count = 8; 4183 break; 4184 default: 4185 return IXGBE_ERR_CONFIG; 4186 } 4187 4188 /* Toggle queues */ 4189 for (i = 0; i < queue_count; ++i) { 4190 /* Calculate offset of current queue */ 4191 offset = queue_count * vf_number + i; 4192 4193 /* Enable queue */ 4194 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4195 reg |= IXGBE_TXDCTL_ENABLE; 4196 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4197 IXGBE_WRITE_FLUSH(hw); 4198 4199 /* Disable queue */ 4200 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4201 reg &= ~IXGBE_TXDCTL_ENABLE; 4202 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4203 IXGBE_WRITE_FLUSH(hw); 4204 } 4205 4206 return IXGBE_SUCCESS; 4207 } 4208 4209 /** 4210 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4211 * @hw: pointer to hardware structure 4212 * 4213 * Contains the logic to identify if we need to verify link for the 4214 * crosstalk fix 4215 **/ 4216 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4217 { 4218 4219 /* Does FW say we need the fix */ 4220 if (!hw->need_crosstalk_fix) 4221 return false; 4222 4223 /* Only consider SFP+ PHYs i.e. media type fiber */ 4224 switch (hw->mac.ops.get_media_type(hw)) { 4225 case ixgbe_media_type_fiber: 4226 case ixgbe_media_type_fiber_qsfp: 4227 break; 4228 default: 4229 return false; 4230 } 4231 4232 return true; 4233 } 4234 4235 /** 4236 * ixgbe_check_mac_link_generic - Determine link and speed status 4237 * @hw: pointer to hardware structure 4238 * @speed: pointer to link speed 4239 * @link_up: true when link is up 4240 * @link_up_wait_to_complete: bool used to wait for link up or not 4241 * 4242 * Reads the links register to determine if link is up and the current speed 4243 **/ 4244 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4245 bool *link_up, bool link_up_wait_to_complete) 4246 { 4247 u32 links_reg, links_orig; 4248 u32 i; 4249 4250 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4251 4252 /* If Crosstalk fix enabled do the sanity check of making sure 4253 * the SFP+ cage is full. 4254 */ 4255 if (ixgbe_need_crosstalk_fix(hw)) { 4256 u32 sfp_cage_full; 4257 4258 switch (hw->mac.type) { 4259 case ixgbe_mac_82599EB: 4260 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4261 IXGBE_ESDP_SDP2; 4262 break; 4263 case ixgbe_mac_X550EM_x: 4264 case ixgbe_mac_X550EM_a: 4265 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4266 IXGBE_ESDP_SDP0; 4267 break; 4268 default: 4269 /* sanity check - No SFP+ devices here */ 4270 sfp_cage_full = false; 4271 break; 4272 } 4273 4274 if (!sfp_cage_full) { 4275 *link_up = false; 4276 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4277 return IXGBE_SUCCESS; 4278 } 4279 } 4280 4281 /* clear the old state */ 4282 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4283 4284 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4285 4286 if (links_orig != links_reg) { 4287 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4288 links_orig, links_reg); 4289 } 4290 4291 if (link_up_wait_to_complete) { 4292 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4293 if (links_reg & IXGBE_LINKS_UP) { 4294 *link_up = true; 4295 break; 4296 } else { 4297 *link_up = false; 4298 } 4299 msec_delay(100); 4300 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4301 } 4302 } else { 4303 if (links_reg & IXGBE_LINKS_UP) { 4304 if (ixgbe_need_crosstalk_fix(hw)) { 4305 /* Check the link state again after a delay 4306 * to filter out spurious link up 4307 * notifications. 4308 */ 4309 msec_delay(5); 4310 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4311 if (!(links_reg & IXGBE_LINKS_UP)) { 4312 *link_up = false; 4313 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4314 return IXGBE_SUCCESS; 4315 } 4316 4317 } 4318 *link_up = true; 4319 } else { 4320 *link_up = false; 4321 } 4322 } 4323 4324 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4325 case IXGBE_LINKS_SPEED_10G_82599: 4326 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4327 if (hw->mac.type >= ixgbe_mac_X550) { 4328 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4329 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4330 } 4331 break; 4332 case IXGBE_LINKS_SPEED_1G_82599: 4333 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4334 break; 4335 case IXGBE_LINKS_SPEED_100_82599: 4336 *speed = IXGBE_LINK_SPEED_100_FULL; 4337 if (hw->mac.type == ixgbe_mac_X550 || 4338 hw->mac.type == ixgbe_mac_E610) { 4339 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4340 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4341 } 4342 break; 4343 case IXGBE_LINKS_SPEED_10_X550EM_A: 4344 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4345 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4346 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4347 *speed = IXGBE_LINK_SPEED_10_FULL; 4348 break; 4349 default: 4350 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4351 } 4352 4353 return IXGBE_SUCCESS; 4354 } 4355 4356 /** 4357 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4358 * the EEPROM 4359 * @hw: pointer to hardware structure 4360 * @wwnn_prefix: the alternative WWNN prefix 4361 * @wwpn_prefix: the alternative WWPN prefix 4362 * 4363 * This function will read the EEPROM from the alternative SAN MAC address 4364 * block to check the support for the alternative WWNN/WWPN prefix support. 4365 **/ 4366 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4367 u16 *wwpn_prefix) 4368 { 4369 u16 offset, caps; 4370 u16 alt_san_mac_blk_offset; 4371 4372 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4373 4374 /* clear output first */ 4375 *wwnn_prefix = 0xFFFF; 4376 *wwpn_prefix = 0xFFFF; 4377 4378 /* check if alternative SAN MAC is supported */ 4379 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4380 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4381 goto wwn_prefix_err; 4382 4383 if ((alt_san_mac_blk_offset == 0) || 4384 (alt_san_mac_blk_offset == 0xFFFF)) 4385 goto wwn_prefix_out; 4386 4387 /* check capability in alternative san mac address block */ 4388 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4389 if (hw->eeprom.ops.read(hw, offset, &caps)) 4390 goto wwn_prefix_err; 4391 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4392 goto wwn_prefix_out; 4393 4394 /* get the corresponding prefix for WWNN/WWPN */ 4395 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4396 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4397 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4398 "eeprom read at offset %d failed", offset); 4399 } 4400 4401 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4402 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4403 goto wwn_prefix_err; 4404 4405 wwn_prefix_out: 4406 return IXGBE_SUCCESS; 4407 4408 wwn_prefix_err: 4409 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4410 "eeprom read at offset %d failed", offset); 4411 return IXGBE_SUCCESS; 4412 } 4413 4414 /** 4415 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4416 * @hw: pointer to hardware structure 4417 * @bs: the fcoe boot status 4418 * 4419 * This function will read the FCOE boot status from the iSCSI FCOE block 4420 **/ 4421 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4422 { 4423 u16 offset, caps, flags; 4424 s32 status; 4425 4426 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4427 4428 /* clear output first */ 4429 *bs = ixgbe_fcoe_bootstatus_unavailable; 4430 4431 /* check if FCOE IBA block is present */ 4432 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4433 status = hw->eeprom.ops.read(hw, offset, &caps); 4434 if (status != IXGBE_SUCCESS) 4435 goto out; 4436 4437 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4438 goto out; 4439 4440 /* check if iSCSI FCOE block is populated */ 4441 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4442 if (status != IXGBE_SUCCESS) 4443 goto out; 4444 4445 if ((offset == 0) || (offset == 0xFFFF)) 4446 goto out; 4447 4448 /* read fcoe flags in iSCSI FCOE block */ 4449 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4450 status = hw->eeprom.ops.read(hw, offset, &flags); 4451 if (status != IXGBE_SUCCESS) 4452 goto out; 4453 4454 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4455 *bs = ixgbe_fcoe_bootstatus_enabled; 4456 else 4457 *bs = ixgbe_fcoe_bootstatus_disabled; 4458 4459 out: 4460 return status; 4461 } 4462 4463 /** 4464 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4465 * @hw: pointer to hardware structure 4466 * @enable: enable or disable switch for MAC anti-spoofing 4467 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4468 * 4469 **/ 4470 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4471 { 4472 int vf_target_reg = vf >> 3; 4473 int vf_target_shift = vf % 8; 4474 u32 pfvfspoof; 4475 4476 if (hw->mac.type == ixgbe_mac_82598EB) 4477 return; 4478 4479 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4480 if (enable) 4481 pfvfspoof |= (1 << vf_target_shift); 4482 else 4483 pfvfspoof &= ~(1 << vf_target_shift); 4484 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4485 } 4486 4487 /** 4488 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4489 * @hw: pointer to hardware structure 4490 * @enable: enable or disable switch for VLAN anti-spoofing 4491 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4492 * 4493 **/ 4494 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4495 { 4496 int vf_target_reg = vf >> 3; 4497 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4498 u32 pfvfspoof; 4499 4500 if (hw->mac.type == ixgbe_mac_82598EB) 4501 return; 4502 4503 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4504 if (enable) 4505 pfvfspoof |= (1 << vf_target_shift); 4506 else 4507 pfvfspoof &= ~(1 << vf_target_shift); 4508 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4509 } 4510 4511 /** 4512 * ixgbe_get_device_caps_generic - Get additional device capabilities 4513 * @hw: pointer to hardware structure 4514 * @device_caps: the EEPROM word with the extra device capabilities 4515 * 4516 * This function will read the EEPROM location for the device capabilities, 4517 * and return the word through device_caps. 4518 **/ 4519 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4520 { 4521 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4522 4523 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4524 4525 return IXGBE_SUCCESS; 4526 } 4527 4528 /** 4529 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4530 * @hw: pointer to hardware structure 4531 * 4532 **/ 4533 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4534 { 4535 u32 regval; 4536 u32 i; 4537 4538 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4539 4540 /* Enable relaxed ordering */ 4541 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4542 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4543 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4544 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4545 } 4546 4547 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4548 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4549 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4550 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4551 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4552 } 4553 4554 } 4555 4556 /** 4557 * ixgbe_calculate_checksum - Calculate checksum for buffer 4558 * @buffer: pointer to EEPROM 4559 * @length: size of EEPROM to calculate a checksum for 4560 * Calculates the checksum for some buffer on a specified length. The 4561 * checksum calculated is returned. 4562 **/ 4563 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4564 { 4565 u32 i; 4566 u8 sum = 0; 4567 4568 DEBUGFUNC("ixgbe_calculate_checksum"); 4569 4570 if (!buffer) 4571 return 0; 4572 4573 for (i = 0; i < length; i++) 4574 sum += buffer[i]; 4575 4576 return (u8) (0 - sum); 4577 } 4578 4579 /** 4580 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4581 * @hw: pointer to the HW structure 4582 * @buffer: command to write and where the return status will be placed 4583 * @length: length of buffer, must be multiple of 4 bytes 4584 * @timeout: time in ms to wait for command completion 4585 * 4586 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4587 * else returns semaphore error when encountering an error acquiring 4588 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4589 * 4590 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4591 * by the caller. 4592 **/ 4593 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4594 u32 timeout) 4595 { 4596 u32 hicr, i, fwsts; 4597 u16 dword_len; 4598 4599 DEBUGFUNC("ixgbe_hic_unlocked"); 4600 4601 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4602 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4603 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4604 } 4605 4606 /* Set bit 9 of FWSTS clearing FW reset indication */ 4607 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4608 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4609 4610 /* Check that the host interface is enabled. */ 4611 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4612 if (!(hicr & IXGBE_HICR_EN)) { 4613 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4614 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4615 } 4616 4617 /* Calculate length in DWORDs. We must be DWORD aligned */ 4618 if (length % sizeof(u32)) { 4619 DEBUGOUT("Buffer length failure, not aligned to dword"); 4620 return IXGBE_ERR_INVALID_ARGUMENT; 4621 } 4622 4623 dword_len = length >> 2; 4624 4625 /* The device driver writes the relevant command block 4626 * into the ram area. 4627 */ 4628 for (i = 0; i < dword_len; i++) 4629 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4630 i, IXGBE_CPU_TO_LE32(buffer[i])); 4631 4632 /* Setting this bit tells the ARC that a new command is pending. */ 4633 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4634 4635 for (i = 0; i < timeout * 1000; i++) { 4636 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4637 if (!(hicr & IXGBE_HICR_C)) 4638 break; 4639 usec_delay(1); 4640 } 4641 4642 /* For each command except "Apply Update" perform 4643 * status checks in the HICR registry. 4644 */ 4645 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) == 4646 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD) 4647 return IXGBE_SUCCESS; 4648 4649 /* Check command completion */ 4650 if ((timeout && i == timeout * 1000) || 4651 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4652 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4653 "Command has failed with no status valid.\n"); 4654 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4655 } 4656 4657 return IXGBE_SUCCESS; 4658 } 4659 4660 /** 4661 * ixgbe_host_interface_command - Issue command to manageability block 4662 * @hw: pointer to the HW structure 4663 * @buffer: contains the command to write and where the return status will 4664 * be placed 4665 * @length: length of buffer, must be multiple of 4 bytes 4666 * @timeout: time in ms to wait for command completion 4667 * @return_data: read and return data from the buffer (true) or not (false) 4668 * Needed because FW structures are big endian and decoding of 4669 * these fields can be 8 bit or 16 bit based on command. Decoding 4670 * is not easily understood without making a table of commands. 4671 * So we will leave this up to the caller to read back the data 4672 * in these cases. 4673 * 4674 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4675 * else returns semaphore error when encountering an error acquiring 4676 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4677 **/ 4678 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4679 u32 length, u32 timeout, bool return_data) 4680 { 4681 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4682 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4683 u16 buf_len; 4684 s32 status; 4685 u32 bi; 4686 u32 dword_len; 4687 4688 DEBUGFUNC("ixgbe_host_interface_command"); 4689 4690 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4691 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4692 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4693 } 4694 4695 /* Take management host interface semaphore */ 4696 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4697 if (status) 4698 return status; 4699 4700 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4701 if (status) 4702 goto rel_out; 4703 4704 if (!return_data) 4705 goto rel_out; 4706 4707 /* Calculate length in DWORDs */ 4708 dword_len = hdr_size >> 2; 4709 4710 /* first pull in the header so we know the buffer length */ 4711 for (bi = 0; bi < dword_len; bi++) { 4712 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4713 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4714 } 4715 4716 /* 4717 * If there is any thing in data position pull it in 4718 * Read Flash command requires reading buffer length from 4719 * two byes instead of one byte 4720 */ 4721 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD || 4722 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) { 4723 for (; bi < dword_len + 2; bi++) { 4724 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4725 bi); 4726 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4727 } 4728 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4729 & 0xF00) | resp->buf_len; 4730 hdr_size += (2 << 2); 4731 } else { 4732 buf_len = resp->buf_len; 4733 } 4734 if (!buf_len) 4735 goto rel_out; 4736 4737 if (length < buf_len + hdr_size) { 4738 DEBUGOUT("Buffer not large enough for reply message.\n"); 4739 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4740 goto rel_out; 4741 } 4742 4743 /* Calculate length in DWORDs, add 3 for odd lengths */ 4744 dword_len = (buf_len + 3) >> 2; 4745 4746 /* Pull in the rest of the buffer (bi is where we left off) */ 4747 for (; bi <= dword_len; bi++) { 4748 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4749 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4750 } 4751 4752 rel_out: 4753 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4754 4755 return status; 4756 } 4757 4758 /** 4759 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4760 * @hw: pointer to the HW structure 4761 * @maj: driver version major number 4762 * @min: driver version minor number 4763 * @build: driver version build number 4764 * @sub: driver version sub build number 4765 * @len: unused 4766 * @driver_ver: unused 4767 * 4768 * Sends driver version number to firmware through the manageability 4769 * block. On success return IXGBE_SUCCESS 4770 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4771 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4772 **/ 4773 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4774 u8 build, u8 sub, u16 len, 4775 const char *driver_ver) 4776 { 4777 struct ixgbe_hic_drv_info fw_cmd; 4778 int i; 4779 s32 ret_val = IXGBE_SUCCESS; 4780 4781 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4782 UNREFERENCED_2PARAMETER(len, driver_ver); 4783 4784 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4785 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4786 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4787 fw_cmd.port_num = (u8)hw->bus.func; 4788 fw_cmd.ver_maj = maj; 4789 fw_cmd.ver_min = min; 4790 fw_cmd.ver_build = build; 4791 fw_cmd.ver_sub = sub; 4792 fw_cmd.hdr.checksum = 0; 4793 fw_cmd.pad = 0; 4794 fw_cmd.pad2 = 0; 4795 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4796 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4797 4798 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4799 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4800 sizeof(fw_cmd), 4801 IXGBE_HI_COMMAND_TIMEOUT, 4802 true); 4803 if (ret_val != IXGBE_SUCCESS) 4804 continue; 4805 4806 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4807 FW_CEM_RESP_STATUS_SUCCESS) 4808 ret_val = IXGBE_SUCCESS; 4809 else 4810 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4811 4812 break; 4813 } 4814 4815 return ret_val; 4816 } 4817 4818 /** 4819 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4820 * @hw: pointer to hardware structure 4821 * @num_pb: number of packet buffers to allocate 4822 * @headroom: reserve n KB of headroom 4823 * @strategy: packet buffer allocation strategy 4824 **/ 4825 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4826 int strategy) 4827 { 4828 u32 pbsize = hw->mac.rx_pb_size; 4829 int i = 0; 4830 u32 rxpktsize, txpktsize, txpbthresh; 4831 4832 /* Reserve headroom */ 4833 pbsize -= headroom; 4834 4835 if (!num_pb) 4836 num_pb = 1; 4837 4838 /* Divide remaining packet buffer space amongst the number of packet 4839 * buffers requested using supplied strategy. 4840 */ 4841 switch (strategy) { 4842 case PBA_STRATEGY_WEIGHTED: 4843 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4844 * buffer with 5/8 of the packet buffer space. 4845 */ 4846 rxpktsize = (pbsize * 5) / (num_pb * 4); 4847 pbsize -= rxpktsize * (num_pb / 2); 4848 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4849 for (; i < (num_pb / 2); i++) 4850 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4851 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4852 for (; i < num_pb; i++) 4853 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4854 break; 4855 case PBA_STRATEGY_EQUAL: 4856 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4857 for (; i < num_pb; i++) 4858 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4859 break; 4860 default: 4861 break; 4862 } 4863 4864 /* Only support an equally distributed Tx packet buffer strategy. */ 4865 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4866 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4867 for (i = 0; i < num_pb; i++) { 4868 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4869 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4870 } 4871 4872 /* Clear unused TCs, if any, to zero buffer size*/ 4873 for (; i < IXGBE_MAX_PB; i++) { 4874 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4875 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4876 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4877 } 4878 } 4879 4880 /** 4881 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4882 * @hw: pointer to the hardware structure 4883 * 4884 * The 82599 and x540 MACs can experience issues if TX work is still pending 4885 * when a reset occurs. This function prevents this by flushing the PCIe 4886 * buffers on the system. 4887 **/ 4888 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4889 { 4890 u32 gcr_ext, hlreg0, i, poll; 4891 u16 value; 4892 4893 /* 4894 * If double reset is not requested then all transactions should 4895 * already be clear and as such there is no work to do 4896 */ 4897 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4898 return; 4899 4900 /* 4901 * Set loopback enable to prevent any transmits from being sent 4902 * should the link come up. This assumes that the RXCTRL.RXEN bit 4903 * has already been cleared. 4904 */ 4905 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4906 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4907 4908 /* Wait for a last completion before clearing buffers */ 4909 IXGBE_WRITE_FLUSH(hw); 4910 msec_delay(3); 4911 4912 /* 4913 * Before proceeding, make sure that the PCIe block does not have 4914 * transactions pending. 4915 */ 4916 poll = ixgbe_pcie_timeout_poll(hw); 4917 for (i = 0; i < poll; i++) { 4918 usec_delay(100); 4919 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4920 if (IXGBE_REMOVED(hw->hw_addr)) 4921 goto out; 4922 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4923 goto out; 4924 } 4925 4926 out: 4927 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4928 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4929 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4930 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4931 4932 /* Flush all writes and allow 20usec for all transactions to clear */ 4933 IXGBE_WRITE_FLUSH(hw); 4934 usec_delay(20); 4935 4936 /* restore previous register values */ 4937 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4938 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4939 } 4940 4941 static const u8 ixgbe_emc_temp_data[4] = { 4942 IXGBE_EMC_INTERNAL_DATA, 4943 IXGBE_EMC_DIODE1_DATA, 4944 IXGBE_EMC_DIODE2_DATA, 4945 IXGBE_EMC_DIODE3_DATA 4946 }; 4947 static const u8 ixgbe_emc_therm_limit[4] = { 4948 IXGBE_EMC_INTERNAL_THERM_LIMIT, 4949 IXGBE_EMC_DIODE1_THERM_LIMIT, 4950 IXGBE_EMC_DIODE2_THERM_LIMIT, 4951 IXGBE_EMC_DIODE3_THERM_LIMIT 4952 }; 4953 4954 /** 4955 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data 4956 * @hw: pointer to hardware structure 4957 * 4958 * Returns the thermal sensor data structure 4959 **/ 4960 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 4961 { 4962 s32 status = IXGBE_SUCCESS; 4963 u16 ets_offset; 4964 u16 ets_cfg; 4965 u16 ets_sensor; 4966 u8 num_sensors; 4967 u8 sensor_index; 4968 u8 sensor_location; 4969 u8 i; 4970 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 4971 4972 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic"); 4973 4974 /* Only support thermal sensors attached to 82599 physical port 0 */ 4975 if ((hw->mac.type != ixgbe_mac_82599EB) || 4976 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) { 4977 status = IXGBE_NOT_IMPLEMENTED; 4978 goto out; 4979 } 4980 4981 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset); 4982 if (status) 4983 goto out; 4984 4985 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) { 4986 status = IXGBE_NOT_IMPLEMENTED; 4987 goto out; 4988 } 4989 4990 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg); 4991 if (status) 4992 goto out; 4993 4994 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 4995 != IXGBE_ETS_TYPE_EMC) { 4996 status = IXGBE_NOT_IMPLEMENTED; 4997 goto out; 4998 } 4999 5000 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 5001 if (num_sensors > IXGBE_MAX_SENSORS) 5002 num_sensors = IXGBE_MAX_SENSORS; 5003 5004 for (i = 0; i < num_sensors; i++) { 5005 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 5006 &ets_sensor); 5007 if (status) 5008 goto out; 5009 5010 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 5011 IXGBE_ETS_DATA_INDEX_SHIFT); 5012 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 5013 IXGBE_ETS_DATA_LOC_SHIFT); 5014 5015 if (sensor_location != 0) { 5016 status = hw->phy.ops.read_i2c_byte(hw, 5017 ixgbe_emc_temp_data[sensor_index], 5018 IXGBE_I2C_THERMAL_SENSOR_ADDR, 5019 &data->sensor[i].temp); 5020 if (status) 5021 goto out; 5022 } 5023 } 5024 out: 5025 return status; 5026 } 5027 5028 /** 5029 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 5030 * @hw: pointer to hardware structure 5031 * 5032 * Inits the thermal sensor thresholds according to the NVM map 5033 * and save off the threshold and location values into mac.thermal_sensor_data 5034 **/ 5035 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 5036 { 5037 s32 status = IXGBE_SUCCESS; 5038 u16 offset; 5039 u16 ets_offset; 5040 u16 ets_cfg; 5041 u16 ets_sensor; 5042 u8 low_thresh_delta; 5043 u8 num_sensors; 5044 u8 sensor_index; 5045 u8 sensor_location; 5046 u8 therm_limit; 5047 u8 i; 5048 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 5049 5050 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic"); 5051 5052 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 5053 5054 /* Only support thermal sensors attached to 82599 physical port 0 */ 5055 if ((hw->mac.type != ixgbe_mac_82599EB) || 5056 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 5057 return IXGBE_NOT_IMPLEMENTED; 5058 5059 offset = IXGBE_ETS_CFG; 5060 if (hw->eeprom.ops.read(hw, offset, &ets_offset)) 5061 goto eeprom_err; 5062 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 5063 return IXGBE_NOT_IMPLEMENTED; 5064 5065 offset = ets_offset; 5066 if (hw->eeprom.ops.read(hw, offset, &ets_cfg)) 5067 goto eeprom_err; 5068 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 5069 != IXGBE_ETS_TYPE_EMC) 5070 return IXGBE_NOT_IMPLEMENTED; 5071 5072 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 5073 IXGBE_ETS_LTHRES_DELTA_SHIFT); 5074 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 5075 5076 for (i = 0; i < num_sensors; i++) { 5077 offset = ets_offset + 1 + i; 5078 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) { 5079 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 5080 "eeprom read at offset %d failed", 5081 offset); 5082 continue; 5083 } 5084 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 5085 IXGBE_ETS_DATA_INDEX_SHIFT); 5086 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 5087 IXGBE_ETS_DATA_LOC_SHIFT); 5088 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 5089 5090 hw->phy.ops.write_i2c_byte(hw, 5091 ixgbe_emc_therm_limit[sensor_index], 5092 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 5093 5094 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) { 5095 data->sensor[i].location = sensor_location; 5096 data->sensor[i].caution_thresh = therm_limit; 5097 data->sensor[i].max_op_thresh = therm_limit - 5098 low_thresh_delta; 5099 } 5100 } 5101 return status; 5102 5103 eeprom_err: 5104 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 5105 "eeprom read at offset %d failed", offset); 5106 return IXGBE_NOT_IMPLEMENTED; 5107 } 5108 5109 /** 5110 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 5111 * 5112 * @hw: pointer to hardware structure 5113 * @cmd: Command we send to the FW 5114 * @status: The reply from the FW 5115 * 5116 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 5117 **/ 5118 #define IXGBE_BYPASS_BB_WAIT 1 5119 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 5120 { 5121 int i; 5122 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 5123 u32 esdp; 5124 5125 if (!status) 5126 return IXGBE_ERR_PARAM; 5127 5128 *status = 0; 5129 5130 /* SDP vary by MAC type */ 5131 switch (hw->mac.type) { 5132 case ixgbe_mac_82599EB: 5133 sck = IXGBE_ESDP_SDP7; 5134 sdi = IXGBE_ESDP_SDP0; 5135 sdo = IXGBE_ESDP_SDP6; 5136 dir_sck = IXGBE_ESDP_SDP7_DIR; 5137 dir_sdi = IXGBE_ESDP_SDP0_DIR; 5138 dir_sdo = IXGBE_ESDP_SDP6_DIR; 5139 break; 5140 case ixgbe_mac_X540: 5141 sck = IXGBE_ESDP_SDP2; 5142 sdi = IXGBE_ESDP_SDP0; 5143 sdo = IXGBE_ESDP_SDP1; 5144 dir_sck = IXGBE_ESDP_SDP2_DIR; 5145 dir_sdi = IXGBE_ESDP_SDP0_DIR; 5146 dir_sdo = IXGBE_ESDP_SDP1_DIR; 5147 break; 5148 default: 5149 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 5150 } 5151 5152 /* Set SDP pins direction */ 5153 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5154 esdp |= dir_sck; /* SCK as output */ 5155 esdp |= dir_sdi; /* SDI as output */ 5156 esdp &= ~dir_sdo; /* SDO as input */ 5157 esdp |= sck; 5158 esdp |= sdi; 5159 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5160 IXGBE_WRITE_FLUSH(hw); 5161 msec_delay(IXGBE_BYPASS_BB_WAIT); 5162 5163 /* Generate start condition */ 5164 esdp &= ~sdi; 5165 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5166 IXGBE_WRITE_FLUSH(hw); 5167 msec_delay(IXGBE_BYPASS_BB_WAIT); 5168 5169 esdp &= ~sck; 5170 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5171 IXGBE_WRITE_FLUSH(hw); 5172 msec_delay(IXGBE_BYPASS_BB_WAIT); 5173 5174 /* Clock out the new control word and clock in the status */ 5175 for (i = 0; i < 32; i++) { 5176 if ((cmd >> (31 - i)) & 0x01) { 5177 esdp |= sdi; 5178 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5179 } else { 5180 esdp &= ~sdi; 5181 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5182 } 5183 IXGBE_WRITE_FLUSH(hw); 5184 msec_delay(IXGBE_BYPASS_BB_WAIT); 5185 5186 esdp |= sck; 5187 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5188 IXGBE_WRITE_FLUSH(hw); 5189 msec_delay(IXGBE_BYPASS_BB_WAIT); 5190 5191 esdp &= ~sck; 5192 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5193 IXGBE_WRITE_FLUSH(hw); 5194 msec_delay(IXGBE_BYPASS_BB_WAIT); 5195 5196 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5197 if (esdp & sdo) 5198 *status = (*status << 1) | 0x01; 5199 else 5200 *status = (*status << 1) | 0x00; 5201 msec_delay(IXGBE_BYPASS_BB_WAIT); 5202 } 5203 5204 /* stop condition */ 5205 esdp |= sck; 5206 esdp &= ~sdi; 5207 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5208 IXGBE_WRITE_FLUSH(hw); 5209 msec_delay(IXGBE_BYPASS_BB_WAIT); 5210 5211 esdp |= sdi; 5212 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5213 IXGBE_WRITE_FLUSH(hw); 5214 5215 /* set the page bits to match the cmd that the status it belongs to */ 5216 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 5217 5218 return IXGBE_SUCCESS; 5219 } 5220 5221 /** 5222 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 5223 * @in_reg: The register cmd for the bit-bang read. 5224 * @out_reg: The register returned from a bit-bang read. 5225 * 5226 * If we send a write we can't be sure it took until we can read back 5227 * that same register. It can be a problem as some of the fields may 5228 * for valid reasons change inbetween the time wrote the register and 5229 * we read it again to verify. So this function check everything we 5230 * can check and then assumes it worked. 5231 **/ 5232 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 5233 { 5234 u32 mask; 5235 5236 /* Page must match for all control pages */ 5237 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 5238 return false; 5239 5240 switch (in_reg & BYPASS_PAGE_M) { 5241 case BYPASS_PAGE_CTL0: 5242 /* All the following can't change since the last write 5243 * - All the event actions 5244 * - The timeout value 5245 */ 5246 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 5247 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 5248 BYPASS_WDTIMEOUT_M | 5249 BYPASS_WDT_VALUE_M; 5250 if ((out_reg & mask) != (in_reg & mask)) 5251 return false; 5252 5253 /* 0x0 is never a valid value for bypass status */ 5254 if (!(out_reg & BYPASS_STATUS_OFF_M)) 5255 return false; 5256 break; 5257 case BYPASS_PAGE_CTL1: 5258 /* All the following can't change since the last write 5259 * - time valid bit 5260 * - time we last sent 5261 */ 5262 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 5263 if ((out_reg & mask) != (in_reg & mask)) 5264 return false; 5265 break; 5266 case BYPASS_PAGE_CTL2: 5267 /* All we can check in this page is control number 5268 * which is already done above. 5269 */ 5270 break; 5271 } 5272 5273 /* We are as sure as we can be return true */ 5274 return true; 5275 } 5276 5277 /** 5278 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 5279 * 5280 * @hw: pointer to hardware structure 5281 * @ctrl: The control word we are setting. 5282 * @event: The event we are setting in the FW. This also happens to 5283 * be the mask for the event we are setting (handy) 5284 * @action: The action we set the event to in the FW. This is in a 5285 * bit field that happens to be what we want to put in 5286 * the event spot (also handy) 5287 **/ 5288 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5289 u32 action) 5290 { 5291 u32 by_ctl = 0; 5292 u32 cmd, verify; 5293 u32 count = 0; 5294 5295 /* Get current values */ 5296 cmd = ctrl; /* just reading only need control number */ 5297 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5298 return IXGBE_ERR_INVALID_ARGUMENT; 5299 5300 /* Set to new action */ 5301 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5302 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5303 return IXGBE_ERR_INVALID_ARGUMENT; 5304 5305 /* Page 0 force a FW eeprom write which is slow so verify */ 5306 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5307 verify = BYPASS_PAGE_CTL0; 5308 do { 5309 if (count++ > 5) 5310 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5311 5312 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5313 return IXGBE_ERR_INVALID_ARGUMENT; 5314 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5315 } else { 5316 /* We have give the FW time for the write to stick */ 5317 msec_delay(100); 5318 } 5319 5320 return IXGBE_SUCCESS; 5321 } 5322 5323 /** 5324 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5325 * 5326 * @hw: pointer to hardware structure 5327 * @addr: The bypass eeprom address to read. 5328 * @value: The 8b of data at the address above. 5329 **/ 5330 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5331 { 5332 u32 cmd; 5333 u32 status; 5334 5335 5336 /* send the request */ 5337 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5338 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5339 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5340 return IXGBE_ERR_INVALID_ARGUMENT; 5341 5342 /* We have give the FW time for the write to stick */ 5343 msec_delay(100); 5344 5345 /* now read the results */ 5346 cmd &= ~BYPASS_WE; 5347 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5348 return IXGBE_ERR_INVALID_ARGUMENT; 5349 5350 *value = status & BYPASS_CTL2_DATA_M; 5351 5352 return IXGBE_SUCCESS; 5353 } 5354 5355 /** 5356 * ixgbe_get_orom_version - Return option ROM from EEPROM 5357 * 5358 * @hw: pointer to hardware structure 5359 * @nvm_ver: pointer to output structure 5360 * 5361 * if valid option ROM version, nvm_ver->or_valid set to true 5362 * else nvm_ver->or_valid is false. 5363 **/ 5364 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5365 struct ixgbe_nvm_version *nvm_ver) 5366 { 5367 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5368 5369 nvm_ver->or_valid = false; 5370 /* Option Rom may or may not be present. Start with pointer */ 5371 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5372 5373 /* make sure offset is valid */ 5374 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5375 return; 5376 5377 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5378 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5379 5380 /* option rom exists and is valid */ 5381 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5382 eeprom_cfg_blkl == NVM_VER_INVALID || 5383 eeprom_cfg_blkh == NVM_VER_INVALID) 5384 return; 5385 5386 nvm_ver->or_valid = true; 5387 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5388 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5389 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5390 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5391 } 5392 5393 /** 5394 * ixgbe_get_oem_prod_version - Return OEM Product version 5395 * 5396 * @hw: pointer to hardware structure 5397 * @nvm_ver: pointer to output structure 5398 * 5399 * if valid OEM product version, nvm_ver->oem_valid set to true 5400 * else nvm_ver->oem_valid is false. 5401 **/ 5402 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5403 struct ixgbe_nvm_version *nvm_ver) 5404 { 5405 u16 rel_num, prod_ver, mod_len, cap, offset; 5406 5407 nvm_ver->oem_valid = false; 5408 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5409 5410 /* Return if offset to OEM Product Version block is invalid */ 5411 if (offset == 0x0 || offset == NVM_INVALID_PTR) 5412 return; 5413 5414 /* Read product version block */ 5415 hw->eeprom.ops.read(hw, offset, &mod_len); 5416 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5417 5418 /* Return if OEM product version block is invalid */ 5419 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5420 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5421 return; 5422 5423 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5424 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5425 5426 /* Return if version is invalid */ 5427 if ((rel_num | prod_ver) == 0x0 || 5428 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5429 return; 5430 5431 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5432 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5433 nvm_ver->oem_release = rel_num; 5434 nvm_ver->oem_valid = true; 5435 } 5436 5437 /** 5438 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5439 * 5440 * @hw: pointer to hardware structure 5441 * @nvm_ver: pointer to output structure 5442 * 5443 * word read errors will return 0xFFFF 5444 **/ 5445 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5446 { 5447 u16 etk_id_l, etk_id_h; 5448 5449 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5450 etk_id_l = NVM_VER_INVALID; 5451 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5452 etk_id_h = NVM_VER_INVALID; 5453 5454 /* The word order for the version format is determined by high order 5455 * word bit 15. 5456 */ 5457 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5458 nvm_ver->etk_id = (u32)etk_id_h; 5459 nvm_ver->etk_id |= (u32)etk_id_l << NVM_ETK_SHIFT; 5460 } else { 5461 nvm_ver->etk_id = (u32)etk_id_l; 5462 nvm_ver->etk_id |= (u32)etk_id_h << NVM_ETK_SHIFT; 5463 } 5464 } 5465 5466 /** 5467 * ixgbe_get_nvm_version - Return version of NVM and its components 5468 * 5469 * @hw: pointer to hardware structure 5470 * @nvm_ver: pointer to output structure 5471 * 5472 * irrelevant component fields will return 0, read errors will return 0xff 5473 **/ 5474 void ixgbe_get_nvm_version(struct ixgbe_hw *hw, 5475 struct ixgbe_nvm_version *nvm_ver) 5476 { 5477 u16 word, phy_ver; 5478 5479 DEBUGFUNC("ixgbe_get_nvm_version"); 5480 5481 memset(nvm_ver, 0, sizeof(struct ixgbe_nvm_version)); 5482 5483 /* eeprom version is mac-type specific */ 5484 switch (hw->mac.type) { 5485 case ixgbe_mac_82598EB: 5486 /* version of eeprom section */ 5487 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_82598, &word)) 5488 word = NVM_VER_INVALID; 5489 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5490 >> NVM_EEP_MAJ_SHIFT); 5491 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) 5492 >> NVM_EEP_MIN_SHIFT); 5493 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); 5494 break; 5495 case ixgbe_mac_X540: 5496 /* version of eeprom section */ 5497 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) 5498 word = NVM_VER_INVALID; 5499 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5500 >> NVM_EEP_MAJ_SHIFT); 5501 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) 5502 >> NVM_EEP_MIN_SHIFT); 5503 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); 5504 break; 5505 5506 case ixgbe_mac_X550: 5507 case ixgbe_mac_X550EM_x: 5508 case ixgbe_mac_X550EM_a: 5509 case ixgbe_mac_E610: 5510 /* version of eeprom section */ 5511 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) 5512 word = NVM_VER_INVALID; 5513 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5514 >> NVM_EEP_MAJ_SHIFT); 5515 nvm_ver->nvm_minor = (word & NVM_EEP_X550_MINOR_MASK); 5516 5517 break; 5518 default: 5519 break; 5520 } 5521 5522 /* phy version is mac-type specific */ 5523 switch (hw->mac.type) { 5524 case ixgbe_mac_X540: 5525 case ixgbe_mac_X550: 5526 case ixgbe_mac_X550EM_x: 5527 case ixgbe_mac_X550EM_a: 5528 case ixgbe_mac_E610: 5529 /* intel phy firmware version */ 5530 if (ixgbe_read_eeprom(hw, NVM_EEP_PHY_OFF_X540, &word)) 5531 word = NVM_VER_INVALID; 5532 nvm_ver->phy_fw_maj = ((word & NVM_PHY_MAJOR_MASK) 5533 >> NVM_PHY_MAJ_SHIFT); 5534 nvm_ver->phy_fw_min = ((word & NVM_PHY_MINOR_MASK) 5535 >> NVM_PHY_MIN_SHIFT); 5536 nvm_ver->phy_fw_id = (word & NVM_PHY_ID_MASK); 5537 break; 5538 default: 5539 break; 5540 } 5541 5542 ixgbe_get_etk_id(hw, nvm_ver); 5543 5544 /* devstarter image */ 5545 if (ixgbe_read_eeprom(hw, NVM_DS_OFFSET, &word)) 5546 word = NVM_VER_INVALID; 5547 nvm_ver->devstart_major = ((word & NVM_DS_MAJOR_MASK) >> NVM_DS_SHIFT); 5548 nvm_ver->devstart_minor = (word & NVM_DS_MINOR_MASK); 5549 5550 /* OEM customization word */ 5551 if (ixgbe_read_eeprom(hw, NVM_OEM_OFFSET, &nvm_ver->oem_specific)) 5552 nvm_ver->oem_specific = NVM_VER_INVALID; 5553 5554 /* vendor (not intel) phy firmware version */ 5555 if (ixgbe_get_phy_firmware_version(hw, &phy_ver)) 5556 phy_ver = NVM_VER_INVALID; 5557 nvm_ver->phy_vend_maj = ((phy_ver & NVM_PHYVEND_MAJOR_MASK) 5558 >> NVM_PHYVEND_SHIFT); 5559 nvm_ver->phy_vend_min = (phy_ver & NVM_PHYVEND_MINOR_MASK); 5560 5561 /* Option Rom may or may not be present. Start with pointer */ 5562 ixgbe_get_orom_version(hw, nvm_ver); 5563 return; 5564 } 5565 5566 /** 5567 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5568 * @hw: pointer to hardware structure 5569 * @map: pointer to u8 arr for returning map 5570 * 5571 * Read the rtrup2tc HW register and resolve its content into map 5572 **/ 5573 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5574 { 5575 u32 reg, i; 5576 5577 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5578 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5579 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5580 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5581 return; 5582 } 5583 5584 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5585 { 5586 u32 pfdtxgswc; 5587 u32 rxctrl; 5588 5589 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5590 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5591 if (hw->mac.type != ixgbe_mac_82598EB) { 5592 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5593 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5594 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5595 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5596 hw->mac.set_lben = true; 5597 } else { 5598 hw->mac.set_lben = false; 5599 } 5600 } 5601 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5602 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5603 } 5604 } 5605 5606 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5607 { 5608 u32 pfdtxgswc; 5609 u32 rxctrl; 5610 5611 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5612 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5613 5614 if (hw->mac.type != ixgbe_mac_82598EB) { 5615 if (hw->mac.set_lben) { 5616 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5617 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5618 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5619 hw->mac.set_lben = false; 5620 } 5621 } 5622 } 5623 5624 /** 5625 * ixgbe_mng_present - returns true when management capability is present 5626 * @hw: pointer to hardware structure 5627 */ 5628 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5629 { 5630 u32 fwsm; 5631 5632 if (hw->mac.type < ixgbe_mac_82599EB) 5633 return false; 5634 5635 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5636 5637 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5638 } 5639 5640 /** 5641 * ixgbe_mng_enabled - Is the manageability engine enabled? 5642 * @hw: pointer to hardware structure 5643 * 5644 * Returns true if the manageability engine is enabled. 5645 **/ 5646 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5647 { 5648 u32 fwsm, manc, factps; 5649 5650 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5651 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5652 return false; 5653 5654 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5655 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5656 return false; 5657 5658 if (hw->mac.type <= ixgbe_mac_X540) { 5659 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5660 if (factps & IXGBE_FACTPS_MNGCG) 5661 return false; 5662 } 5663 5664 return true; 5665 } 5666 5667 /** 5668 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5669 * @hw: pointer to hardware structure 5670 * @speed: new link speed 5671 * @autoneg_wait_to_complete: true when waiting for completion is needed 5672 * 5673 * Set the link speed in the MAC and/or PHY register and restarts link. 5674 **/ 5675 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5676 ixgbe_link_speed speed, 5677 bool autoneg_wait_to_complete) 5678 { 5679 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5680 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5681 s32 status = IXGBE_SUCCESS; 5682 u32 speedcnt = 0; 5683 u32 i = 0; 5684 bool autoneg, link_up = false; 5685 5686 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5687 5688 /* Mask off requested but non-supported speeds */ 5689 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5690 if (status != IXGBE_SUCCESS) 5691 return status; 5692 5693 speed &= link_speed; 5694 5695 /* Try each speed one by one, highest priority first. We do this in 5696 * software because 10Gb fiber doesn't support speed autonegotiation. 5697 */ 5698 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5699 speedcnt++; 5700 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5701 5702 /* Set the module link speed */ 5703 switch (hw->phy.media_type) { 5704 case ixgbe_media_type_fiber_fixed: 5705 case ixgbe_media_type_fiber: 5706 ixgbe_set_rate_select_speed(hw, 5707 IXGBE_LINK_SPEED_10GB_FULL); 5708 break; 5709 case ixgbe_media_type_fiber_qsfp: 5710 /* QSFP module automatically detects MAC link speed */ 5711 break; 5712 default: 5713 DEBUGOUT("Unexpected media type.\n"); 5714 break; 5715 } 5716 5717 /* Allow module to change analog characteristics (1G->10G) */ 5718 msec_delay(40); 5719 5720 status = ixgbe_setup_mac_link(hw, 5721 IXGBE_LINK_SPEED_10GB_FULL, 5722 autoneg_wait_to_complete); 5723 if (status != IXGBE_SUCCESS) 5724 return status; 5725 5726 /* Flap the Tx laser if it has not already been done */ 5727 ixgbe_flap_tx_laser(hw); 5728 5729 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5730 * Section 73.10.2, we may have to wait up to 1000ms if KR is 5731 * attempted. 82599 uses the same timing for 10g SFI. 5732 */ 5733 for (i = 0; i < 10; i++) { 5734 /* Wait for the link partner to also set speed */ 5735 msec_delay(100); 5736 5737 /* If we have link, just jump out */ 5738 status = ixgbe_check_link(hw, &link_speed, 5739 &link_up, false); 5740 if (status != IXGBE_SUCCESS) 5741 return status; 5742 5743 if (link_up) 5744 goto out; 5745 } 5746 } 5747 5748 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5749 speedcnt++; 5750 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5751 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5752 5753 /* Set the module link speed */ 5754 switch (hw->phy.media_type) { 5755 case ixgbe_media_type_fiber_fixed: 5756 case ixgbe_media_type_fiber: 5757 ixgbe_set_rate_select_speed(hw, 5758 IXGBE_LINK_SPEED_1GB_FULL); 5759 break; 5760 case ixgbe_media_type_fiber_qsfp: 5761 /* QSFP module automatically detects link speed */ 5762 break; 5763 default: 5764 DEBUGOUT("Unexpected media type.\n"); 5765 break; 5766 } 5767 5768 /* Allow module to change analog characteristics (10G->1G) */ 5769 msec_delay(40); 5770 5771 status = ixgbe_setup_mac_link(hw, 5772 IXGBE_LINK_SPEED_1GB_FULL, 5773 autoneg_wait_to_complete); 5774 if (status != IXGBE_SUCCESS) 5775 return status; 5776 5777 /* Flap the Tx laser if it has not already been done */ 5778 ixgbe_flap_tx_laser(hw); 5779 5780 /* Wait for the link partner to also set speed */ 5781 msec_delay(100); 5782 5783 /* If we have link, just jump out */ 5784 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 5785 if (status != IXGBE_SUCCESS) 5786 return status; 5787 5788 if (link_up) 5789 goto out; 5790 } 5791 5792 /* We didn't get link. Configure back to the highest speed we tried, 5793 * (if there was more than one). We call ourselves back with just the 5794 * single highest speed that the user requested. 5795 */ 5796 if (speedcnt > 1) 5797 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5798 highest_link_speed, 5799 autoneg_wait_to_complete); 5800 5801 out: 5802 /* Set autoneg_advertised value based on input link speed */ 5803 hw->phy.autoneg_advertised = 0; 5804 5805 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5806 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5807 5808 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5809 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5810 5811 return status; 5812 } 5813 5814 /** 5815 * ixgbe_set_soft_rate_select_speed - Set module link speed 5816 * @hw: pointer to hardware structure 5817 * @speed: link speed to set 5818 * 5819 * Set module link speed via the soft rate select. 5820 */ 5821 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5822 ixgbe_link_speed speed) 5823 { 5824 s32 status; 5825 u8 rs, eeprom_data; 5826 5827 switch (speed) { 5828 case IXGBE_LINK_SPEED_10GB_FULL: 5829 /* one bit mask same as setting on */ 5830 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5831 break; 5832 case IXGBE_LINK_SPEED_1GB_FULL: 5833 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5834 break; 5835 default: 5836 DEBUGOUT("Invalid fixed module speed\n"); 5837 return; 5838 } 5839 5840 /* Set RS0 */ 5841 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5842 IXGBE_I2C_EEPROM_DEV_ADDR2, 5843 &eeprom_data); 5844 if (status) { 5845 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5846 goto out; 5847 } 5848 5849 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5850 5851 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5852 IXGBE_I2C_EEPROM_DEV_ADDR2, 5853 eeprom_data); 5854 if (status) { 5855 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5856 goto out; 5857 } 5858 5859 /* Set RS1 */ 5860 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5861 IXGBE_I2C_EEPROM_DEV_ADDR2, 5862 &eeprom_data); 5863 if (status) { 5864 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5865 goto out; 5866 } 5867 5868 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5869 5870 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5871 IXGBE_I2C_EEPROM_DEV_ADDR2, 5872 eeprom_data); 5873 if (status) { 5874 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5875 goto out; 5876 } 5877 out: 5878 return; 5879 } 5880