1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_api.h" 37 38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 52 u16 *san_mac_offset); 53 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan); 54 55 /** 56 * ixgbe_init_ops_generic - Inits function ptrs 57 * @hw: pointer to the hardware structure 58 * 59 * Initialize the function pointers. 60 **/ 61 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 62 { 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 struct ixgbe_mac_info *mac = &hw->mac; 65 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 66 67 DEBUGFUNC("ixgbe_init_ops_generic"); 68 69 /* EEPROM */ 70 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 71 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 72 if (eec & (1 << 8)) 73 eeprom->ops.read = &ixgbe_read_eerd_generic; 74 else 75 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 76 eeprom->ops.write = &ixgbe_write_eeprom_generic; 77 eeprom->ops.validate_checksum = 78 &ixgbe_validate_eeprom_checksum_generic; 79 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 80 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic; 81 82 /* MAC */ 83 mac->ops.init_hw = &ixgbe_init_hw_generic; 84 mac->ops.reset_hw = NULL; 85 mac->ops.start_hw = &ixgbe_start_hw_generic; 86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 87 mac->ops.get_media_type = NULL; 88 mac->ops.get_supported_physical_layer = NULL; 89 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 90 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 91 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 92 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 93 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 94 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 95 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 96 97 /* LEDs */ 98 mac->ops.led_on = &ixgbe_led_on_generic; 99 mac->ops.led_off = &ixgbe_led_off_generic; 100 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 101 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 102 103 /* RAR, Multicast, VLAN */ 104 mac->ops.set_rar = &ixgbe_set_rar_generic; 105 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 106 mac->ops.insert_mac_addr = NULL; 107 mac->ops.set_vmdq = NULL; 108 mac->ops.clear_vmdq = NULL; 109 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 110 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 111 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 112 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 113 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 114 mac->ops.clear_vfta = NULL; 115 mac->ops.set_vfta = NULL; 116 mac->ops.init_uta_tables = NULL; 117 118 /* Flow Control */ 119 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 120 121 /* Link */ 122 mac->ops.get_link_capabilities = NULL; 123 mac->ops.setup_link = NULL; 124 mac->ops.check_link = NULL; 125 126 return IXGBE_SUCCESS; 127 } 128 129 /** 130 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 131 * @hw: pointer to hardware structure 132 * 133 * Starts the hardware by filling the bus info structure and media type, clears 134 * all on chip counters, initializes receive address registers, multicast 135 * table, VLAN filter table, calls routine to set up link and flow control 136 * settings, and leaves transmit and receive units disabled and uninitialized 137 **/ 138 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 139 { 140 u32 ctrl_ext; 141 s32 ret_val = IXGBE_SUCCESS; 142 143 DEBUGFUNC("ixgbe_start_hw_generic"); 144 145 /* Set the media type */ 146 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 147 148 /* PHY ops initialization must be done in reset_hw() */ 149 150 /* Clear the VLAN filter table */ 151 hw->mac.ops.clear_vfta(hw); 152 153 /* Clear statistics registers */ 154 hw->mac.ops.clear_hw_cntrs(hw); 155 156 /* Set No Snoop Disable */ 157 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 158 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 159 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 160 IXGBE_WRITE_FLUSH(hw); 161 162 /* Setup flow control */ 163 ixgbe_setup_fc(hw, 0); 164 165 /* Clear adapter stopped flag */ 166 hw->adapter_stopped = FALSE; 167 168 return ret_val; 169 } 170 171 /** 172 * ixgbe_init_hw_generic - Generic hardware initialization 173 * @hw: pointer to hardware structure 174 * 175 * Initialize the hardware by resetting the hardware, filling the bus info 176 * structure and media type, clears all on chip counters, initializes receive 177 * address registers, multicast table, VLAN filter table, calls routine to set 178 * up link and flow control settings, and leaves transmit and receive units 179 * disabled and uninitialized 180 **/ 181 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 182 { 183 s32 status = IXGBE_SUCCESS; 184 185 DEBUGFUNC("ixgbe_init_hw_generic"); 186 187 /* Reset the hardware */ 188 status = hw->mac.ops.reset_hw(hw); 189 190 if (status == IXGBE_SUCCESS) { 191 /* Start the HW */ 192 status = hw->mac.ops.start_hw(hw); 193 } 194 195 return status; 196 } 197 198 /** 199 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 200 * @hw: pointer to hardware structure 201 * 202 * Clears all hardware statistics counters by reading them from the hardware 203 * Statistics counters are clear on read. 204 **/ 205 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 206 { 207 u16 i = 0; 208 209 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 210 211 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 212 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 213 IXGBE_READ_REG(hw, IXGBE_ERRBC); 214 IXGBE_READ_REG(hw, IXGBE_MSPDC); 215 for (i = 0; i < 8; i++) 216 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 217 218 IXGBE_READ_REG(hw, IXGBE_MLFC); 219 IXGBE_READ_REG(hw, IXGBE_MRFC); 220 IXGBE_READ_REG(hw, IXGBE_RLEC); 221 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 222 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 223 if (hw->mac.type >= ixgbe_mac_82599EB) { 224 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 225 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 226 } else { 227 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 228 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 229 } 230 231 for (i = 0; i < 8; i++) { 232 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 233 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 234 if (hw->mac.type >= ixgbe_mac_82599EB) { 235 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 236 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 237 } else { 238 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 239 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 240 } 241 } 242 if (hw->mac.type >= ixgbe_mac_82599EB) 243 for (i = 0; i < 8; i++) 244 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 245 IXGBE_READ_REG(hw, IXGBE_PRC64); 246 IXGBE_READ_REG(hw, IXGBE_PRC127); 247 IXGBE_READ_REG(hw, IXGBE_PRC255); 248 IXGBE_READ_REG(hw, IXGBE_PRC511); 249 IXGBE_READ_REG(hw, IXGBE_PRC1023); 250 IXGBE_READ_REG(hw, IXGBE_PRC1522); 251 IXGBE_READ_REG(hw, IXGBE_GPRC); 252 IXGBE_READ_REG(hw, IXGBE_BPRC); 253 IXGBE_READ_REG(hw, IXGBE_MPRC); 254 IXGBE_READ_REG(hw, IXGBE_GPTC); 255 IXGBE_READ_REG(hw, IXGBE_GORCL); 256 IXGBE_READ_REG(hw, IXGBE_GORCH); 257 IXGBE_READ_REG(hw, IXGBE_GOTCL); 258 IXGBE_READ_REG(hw, IXGBE_GOTCH); 259 for (i = 0; i < 8; i++) 260 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 261 IXGBE_READ_REG(hw, IXGBE_RUC); 262 IXGBE_READ_REG(hw, IXGBE_RFC); 263 IXGBE_READ_REG(hw, IXGBE_ROC); 264 IXGBE_READ_REG(hw, IXGBE_RJC); 265 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 266 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 267 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 268 IXGBE_READ_REG(hw, IXGBE_TORL); 269 IXGBE_READ_REG(hw, IXGBE_TORH); 270 IXGBE_READ_REG(hw, IXGBE_TPR); 271 IXGBE_READ_REG(hw, IXGBE_TPT); 272 IXGBE_READ_REG(hw, IXGBE_PTC64); 273 IXGBE_READ_REG(hw, IXGBE_PTC127); 274 IXGBE_READ_REG(hw, IXGBE_PTC255); 275 IXGBE_READ_REG(hw, IXGBE_PTC511); 276 IXGBE_READ_REG(hw, IXGBE_PTC1023); 277 IXGBE_READ_REG(hw, IXGBE_PTC1522); 278 IXGBE_READ_REG(hw, IXGBE_MPTC); 279 IXGBE_READ_REG(hw, IXGBE_BPTC); 280 for (i = 0; i < 16; i++) { 281 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 282 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 283 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 284 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 285 } 286 287 return IXGBE_SUCCESS; 288 } 289 290 /** 291 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 292 * @hw: pointer to hardware structure 293 * @pba_num: stores the part number from the EEPROM 294 * 295 * Reads the part number from the EEPROM. 296 **/ 297 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 298 { 299 s32 ret_val; 300 u16 data; 301 302 DEBUGFUNC("ixgbe_read_pba_num_generic"); 303 304 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 305 if (ret_val) { 306 DEBUGOUT("NVM Read Error\n"); 307 return ret_val; 308 } 309 *pba_num = (u32)(data << 16); 310 311 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 312 if (ret_val) { 313 DEBUGOUT("NVM Read Error\n"); 314 return ret_val; 315 } 316 *pba_num |= data; 317 318 return IXGBE_SUCCESS; 319 } 320 321 /** 322 * ixgbe_get_mac_addr_generic - Generic get MAC address 323 * @hw: pointer to hardware structure 324 * @mac_addr: Adapter MAC address 325 * 326 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 327 * A reset of the adapter must be performed prior to calling this function 328 * in order for the MAC address to have been loaded from the EEPROM into RAR0 329 **/ 330 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 331 { 332 u32 rar_high; 333 u32 rar_low; 334 u16 i; 335 336 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 337 338 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 339 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 340 341 for (i = 0; i < 4; i++) 342 mac_addr[i] = (u8)(rar_low >> (i*8)); 343 344 for (i = 0; i < 2; i++) 345 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 346 347 return IXGBE_SUCCESS; 348 } 349 350 /** 351 * ixgbe_get_bus_info_generic - Generic set PCI bus info 352 * @hw: pointer to hardware structure 353 * 354 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 355 **/ 356 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 357 { 358 struct ixgbe_mac_info *mac = &hw->mac; 359 u16 link_status; 360 361 DEBUGFUNC("ixgbe_get_bus_info_generic"); 362 363 hw->bus.type = ixgbe_bus_type_pci_express; 364 365 /* Get the negotiated link width and speed from PCI config space */ 366 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 367 368 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 369 case IXGBE_PCI_LINK_WIDTH_1: 370 hw->bus.width = ixgbe_bus_width_pcie_x1; 371 break; 372 case IXGBE_PCI_LINK_WIDTH_2: 373 hw->bus.width = ixgbe_bus_width_pcie_x2; 374 break; 375 case IXGBE_PCI_LINK_WIDTH_4: 376 hw->bus.width = ixgbe_bus_width_pcie_x4; 377 break; 378 case IXGBE_PCI_LINK_WIDTH_8: 379 hw->bus.width = ixgbe_bus_width_pcie_x8; 380 break; 381 default: 382 hw->bus.width = ixgbe_bus_width_unknown; 383 break; 384 } 385 386 switch (link_status & IXGBE_PCI_LINK_SPEED) { 387 case IXGBE_PCI_LINK_SPEED_2500: 388 hw->bus.speed = ixgbe_bus_speed_2500; 389 break; 390 case IXGBE_PCI_LINK_SPEED_5000: 391 hw->bus.speed = ixgbe_bus_speed_5000; 392 break; 393 default: 394 hw->bus.speed = ixgbe_bus_speed_unknown; 395 break; 396 } 397 398 mac->ops.set_lan_id(hw); 399 400 return IXGBE_SUCCESS; 401 } 402 403 /** 404 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 405 * @hw: pointer to the HW structure 406 * 407 * Determines the LAN function id by reading memory-mapped registers 408 * and swaps the port value if requested. 409 **/ 410 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 411 { 412 struct ixgbe_bus_info *bus = &hw->bus; 413 u32 reg; 414 415 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 416 417 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 418 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 419 bus->lan_id = bus->func; 420 421 /* check for a port swap */ 422 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 423 if (reg & IXGBE_FACTPS_LFS) 424 bus->func ^= 0x1; 425 } 426 427 /** 428 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 429 * @hw: pointer to hardware structure 430 * 431 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 432 * disables transmit and receive units. The adapter_stopped flag is used by 433 * the shared code and drivers to determine if the adapter is in a stopped 434 * state and should not touch the hardware. 435 **/ 436 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 437 { 438 u32 number_of_queues; 439 u32 reg_val; 440 u16 i; 441 442 DEBUGFUNC("ixgbe_stop_adapter_generic"); 443 444 /* 445 * Set the adapter_stopped flag so other driver functions stop touching 446 * the hardware 447 */ 448 hw->adapter_stopped = TRUE; 449 450 /* Disable the receive unit */ 451 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 452 reg_val &= ~(IXGBE_RXCTRL_RXEN); 453 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 454 IXGBE_WRITE_FLUSH(hw); 455 msec_delay(2); 456 457 /* Clear interrupt mask to stop from interrupts being generated */ 458 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 459 460 /* Clear any pending interrupts */ 461 IXGBE_READ_REG(hw, IXGBE_EICR); 462 463 /* Disable the transmit unit. Each queue must be disabled. */ 464 number_of_queues = hw->mac.max_tx_queues; 465 for (i = 0; i < number_of_queues; i++) { 466 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 467 if (reg_val & IXGBE_TXDCTL_ENABLE) { 468 reg_val &= ~IXGBE_TXDCTL_ENABLE; 469 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 470 } 471 } 472 473 /* 474 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 475 * access and verify no pending requests 476 */ 477 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) 478 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 479 480 return IXGBE_SUCCESS; 481 } 482 483 /** 484 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 485 * @hw: pointer to hardware structure 486 * @index: led number to turn on 487 **/ 488 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 489 { 490 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 491 492 DEBUGFUNC("ixgbe_led_on_generic"); 493 494 /* To turn on the LED, set mode to ON. */ 495 led_reg &= ~IXGBE_LED_MODE_MASK(index); 496 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 497 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 498 IXGBE_WRITE_FLUSH(hw); 499 500 return IXGBE_SUCCESS; 501 } 502 503 /** 504 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 505 * @hw: pointer to hardware structure 506 * @index: led number to turn off 507 **/ 508 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 509 { 510 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 511 512 DEBUGFUNC("ixgbe_led_off_generic"); 513 514 /* To turn off the LED, set mode to OFF. */ 515 led_reg &= ~IXGBE_LED_MODE_MASK(index); 516 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 517 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 518 IXGBE_WRITE_FLUSH(hw); 519 520 return IXGBE_SUCCESS; 521 } 522 523 /** 524 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 525 * @hw: pointer to hardware structure 526 * 527 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 528 * ixgbe_hw struct in order to set up EEPROM access. 529 **/ 530 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 531 { 532 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 533 u32 eec; 534 u16 eeprom_size; 535 536 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 537 538 if (eeprom->type == ixgbe_eeprom_uninitialized) { 539 eeprom->type = ixgbe_eeprom_none; 540 /* Set default semaphore delay to 10ms which is a well 541 * tested value */ 542 eeprom->semaphore_delay = 10; 543 544 /* 545 * Check for EEPROM present first. 546 * If not present leave as none 547 */ 548 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 549 if (eec & IXGBE_EEC_PRES) { 550 eeprom->type = ixgbe_eeprom_spi; 551 552 /* 553 * SPI EEPROM is assumed here. This code would need to 554 * change if a future EEPROM is not SPI. 555 */ 556 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 557 IXGBE_EEC_SIZE_SHIFT); 558 eeprom->word_size = 1 << (eeprom_size + 559 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT); 560 } 561 562 if (eec & IXGBE_EEC_ADDR_SIZE) 563 eeprom->address_bits = 16; 564 else 565 eeprom->address_bits = 8; 566 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 567 "%d\n", eeprom->type, eeprom->word_size, 568 eeprom->address_bits); 569 } 570 571 return IXGBE_SUCCESS; 572 } 573 574 /** 575 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 576 * @hw: pointer to hardware structure 577 * @offset: offset within the EEPROM to be written to 578 * @data: 16 bit word to be written to the EEPROM 579 * 580 * If ixgbe_eeprom_update_checksum is not called after this function, the 581 * EEPROM will most likely contain an invalid checksum. 582 **/ 583 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 584 { 585 s32 status; 586 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 587 588 DEBUGFUNC("ixgbe_write_eeprom_generic"); 589 590 hw->eeprom.ops.init_params(hw); 591 592 if (offset >= hw->eeprom.word_size) { 593 status = IXGBE_ERR_EEPROM; 594 goto out; 595 } 596 597 /* Prepare the EEPROM for writing */ 598 status = ixgbe_acquire_eeprom(hw); 599 600 if (status == IXGBE_SUCCESS) { 601 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 602 ixgbe_release_eeprom(hw); 603 status = IXGBE_ERR_EEPROM; 604 } 605 } 606 607 if (status == IXGBE_SUCCESS) { 608 ixgbe_standby_eeprom(hw); 609 610 /* Send the WRITE ENABLE command (8 bit opcode ) */ 611 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 612 IXGBE_EEPROM_OPCODE_BITS); 613 614 ixgbe_standby_eeprom(hw); 615 616 /* 617 * Some SPI eeproms use the 8th address bit embedded in the 618 * opcode 619 */ 620 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 621 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 622 623 /* Send the Write command (8-bit opcode + addr) */ 624 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 625 IXGBE_EEPROM_OPCODE_BITS); 626 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 627 hw->eeprom.address_bits); 628 629 /* Send the data */ 630 data = (data >> 8) | (data << 8); 631 ixgbe_shift_out_eeprom_bits(hw, data, 16); 632 ixgbe_standby_eeprom(hw); 633 634 /* Done with writing - release the EEPROM */ 635 ixgbe_release_eeprom(hw); 636 } 637 638 out: 639 return status; 640 } 641 642 /** 643 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 644 * @hw: pointer to hardware structure 645 * @offset: offset within the EEPROM to be read 646 * @data: read 16 bit value from EEPROM 647 * 648 * Reads 16 bit value from EEPROM through bit-bang method 649 **/ 650 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 651 u16 *data) 652 { 653 s32 status; 654 u16 word_in; 655 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 656 657 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 658 659 hw->eeprom.ops.init_params(hw); 660 661 if (offset >= hw->eeprom.word_size) { 662 status = IXGBE_ERR_EEPROM; 663 goto out; 664 } 665 666 /* Prepare the EEPROM for reading */ 667 status = ixgbe_acquire_eeprom(hw); 668 669 if (status == IXGBE_SUCCESS) { 670 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 671 ixgbe_release_eeprom(hw); 672 status = IXGBE_ERR_EEPROM; 673 } 674 } 675 676 if (status == IXGBE_SUCCESS) { 677 ixgbe_standby_eeprom(hw); 678 679 /* 680 * Some SPI eeproms use the 8th address bit embedded in the 681 * opcode 682 */ 683 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 684 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 685 686 /* Send the READ command (opcode + addr) */ 687 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 688 IXGBE_EEPROM_OPCODE_BITS); 689 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 690 hw->eeprom.address_bits); 691 692 /* Read the data. */ 693 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 694 *data = (word_in >> 8) | (word_in << 8); 695 696 /* End this read operation */ 697 ixgbe_release_eeprom(hw); 698 } 699 700 out: 701 return status; 702 } 703 704 /** 705 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 706 * @hw: pointer to hardware structure 707 * @offset: offset of word in the EEPROM to read 708 * @data: word read from the EEPROM 709 * 710 * Reads a 16 bit word from the EEPROM using the EERD register. 711 **/ 712 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 713 { 714 u32 eerd; 715 s32 status; 716 717 DEBUGFUNC("ixgbe_read_eerd_generic"); 718 719 hw->eeprom.ops.init_params(hw); 720 721 if (offset >= hw->eeprom.word_size) { 722 status = IXGBE_ERR_EEPROM; 723 goto out; 724 } 725 726 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) + 727 IXGBE_EEPROM_RW_REG_START; 728 729 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 730 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 731 732 if (status == IXGBE_SUCCESS) 733 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 734 IXGBE_EEPROM_RW_REG_DATA); 735 else 736 DEBUGOUT("Eeprom read timed out\n"); 737 738 out: 739 return status; 740 } 741 742 /** 743 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 744 * @hw: pointer to hardware structure 745 * @ee_reg: EEPROM flag for polling 746 * 747 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 748 * read or write is done respectively. 749 **/ 750 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 751 { 752 u32 i; 753 u32 reg; 754 s32 status = IXGBE_ERR_EEPROM; 755 756 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 757 758 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 759 if (ee_reg == IXGBE_NVM_POLL_READ) 760 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 761 else 762 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 763 764 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 765 status = IXGBE_SUCCESS; 766 break; 767 } 768 usec_delay(5); 769 } 770 return status; 771 } 772 773 /** 774 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 775 * @hw: pointer to hardware structure 776 * 777 * Prepares EEPROM for access using bit-bang method. This function should 778 * be called before issuing a command to the EEPROM. 779 **/ 780 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 781 { 782 s32 status = IXGBE_SUCCESS; 783 u32 eec; 784 u32 i; 785 786 DEBUGFUNC("ixgbe_acquire_eeprom"); 787 788 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 789 status = IXGBE_ERR_SWFW_SYNC; 790 791 if (status == IXGBE_SUCCESS) { 792 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 793 794 /* Request EEPROM Access */ 795 eec |= IXGBE_EEC_REQ; 796 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 797 798 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 799 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 800 if (eec & IXGBE_EEC_GNT) 801 break; 802 usec_delay(5); 803 } 804 805 /* Release if grant not acquired */ 806 if (!(eec & IXGBE_EEC_GNT)) { 807 eec &= ~IXGBE_EEC_REQ; 808 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 809 DEBUGOUT("Could not acquire EEPROM grant\n"); 810 811 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 812 status = IXGBE_ERR_EEPROM; 813 } 814 } 815 816 /* Setup EEPROM for Read/Write */ 817 if (status == IXGBE_SUCCESS) { 818 /* Clear CS and SK */ 819 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 820 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 821 IXGBE_WRITE_FLUSH(hw); 822 usec_delay(1); 823 } 824 return status; 825 } 826 827 /** 828 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 829 * @hw: pointer to hardware structure 830 * 831 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 832 **/ 833 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 834 { 835 s32 status = IXGBE_ERR_EEPROM; 836 u32 timeout = 2000; 837 u32 i; 838 u32 swsm; 839 840 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 841 842 /* Get SMBI software semaphore between device drivers first */ 843 for (i = 0; i < timeout; i++) { 844 /* 845 * If the SMBI bit is 0 when we read it, then the bit will be 846 * set and we have the semaphore 847 */ 848 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 849 if (!(swsm & IXGBE_SWSM_SMBI)) { 850 status = IXGBE_SUCCESS; 851 break; 852 } 853 usec_delay(50); 854 } 855 856 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 857 if (status == IXGBE_SUCCESS) { 858 for (i = 0; i < timeout; i++) { 859 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 860 861 /* Set the SW EEPROM semaphore bit to request access */ 862 swsm |= IXGBE_SWSM_SWESMBI; 863 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 864 865 /* 866 * If we set the bit successfully then we got the 867 * semaphore. 868 */ 869 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 870 if (swsm & IXGBE_SWSM_SWESMBI) 871 break; 872 873 usec_delay(50); 874 } 875 876 /* 877 * Release semaphores and return error if SW EEPROM semaphore 878 * was not granted because we don't have access to the EEPROM 879 */ 880 if (i >= timeout) { 881 DEBUGOUT("SWESMBI Software EEPROM semaphore " 882 "not granted.\n"); 883 ixgbe_release_eeprom_semaphore(hw); 884 status = IXGBE_ERR_EEPROM; 885 } 886 } else { 887 DEBUGOUT("Software semaphore SMBI between device drivers " 888 "not granted.\n"); 889 } 890 891 return status; 892 } 893 894 /** 895 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 896 * @hw: pointer to hardware structure 897 * 898 * This function clears hardware semaphore bits. 899 **/ 900 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 901 { 902 u32 swsm; 903 904 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 905 906 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 907 908 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 909 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 910 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 911 IXGBE_WRITE_FLUSH(hw); 912 } 913 914 /** 915 * ixgbe_ready_eeprom - Polls for EEPROM ready 916 * @hw: pointer to hardware structure 917 **/ 918 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 919 { 920 s32 status = IXGBE_SUCCESS; 921 u16 i; 922 u8 spi_stat_reg; 923 924 DEBUGFUNC("ixgbe_ready_eeprom"); 925 926 /* 927 * Read "Status Register" repeatedly until the LSB is cleared. The 928 * EEPROM will signal that the command has been completed by clearing 929 * bit 0 of the internal status register. If it's not cleared within 930 * 5 milliseconds, then error out. 931 */ 932 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 933 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 934 IXGBE_EEPROM_OPCODE_BITS); 935 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 936 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 937 break; 938 939 usec_delay(5); 940 ixgbe_standby_eeprom(hw); 941 }; 942 943 /* 944 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 945 * devices (and only 0-5mSec on 5V devices) 946 */ 947 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 948 DEBUGOUT("SPI EEPROM Status error\n"); 949 status = IXGBE_ERR_EEPROM; 950 } 951 952 return status; 953 } 954 955 /** 956 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 957 * @hw: pointer to hardware structure 958 **/ 959 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 960 { 961 u32 eec; 962 963 DEBUGFUNC("ixgbe_standby_eeprom"); 964 965 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 966 967 /* Toggle CS to flush commands */ 968 eec |= IXGBE_EEC_CS; 969 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 970 IXGBE_WRITE_FLUSH(hw); 971 usec_delay(1); 972 eec &= ~IXGBE_EEC_CS; 973 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 974 IXGBE_WRITE_FLUSH(hw); 975 usec_delay(1); 976 } 977 978 /** 979 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 980 * @hw: pointer to hardware structure 981 * @data: data to send to the EEPROM 982 * @count: number of bits to shift out 983 **/ 984 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 985 u16 count) 986 { 987 u32 eec; 988 u32 mask; 989 u32 i; 990 991 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 992 993 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 994 995 /* 996 * Mask is used to shift "count" bits of "data" out to the EEPROM 997 * one bit at a time. Determine the starting bit based on count 998 */ 999 mask = 0x01 << (count - 1); 1000 1001 for (i = 0; i < count; i++) { 1002 /* 1003 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1004 * "1", and then raising and then lowering the clock (the SK 1005 * bit controls the clock input to the EEPROM). A "0" is 1006 * shifted out to the EEPROM by setting "DI" to "0" and then 1007 * raising and then lowering the clock. 1008 */ 1009 if (data & mask) 1010 eec |= IXGBE_EEC_DI; 1011 else 1012 eec &= ~IXGBE_EEC_DI; 1013 1014 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1015 IXGBE_WRITE_FLUSH(hw); 1016 1017 usec_delay(1); 1018 1019 ixgbe_raise_eeprom_clk(hw, &eec); 1020 ixgbe_lower_eeprom_clk(hw, &eec); 1021 1022 /* 1023 * Shift mask to signify next bit of data to shift in to the 1024 * EEPROM 1025 */ 1026 mask = mask >> 1; 1027 }; 1028 1029 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1030 eec &= ~IXGBE_EEC_DI; 1031 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1032 IXGBE_WRITE_FLUSH(hw); 1033 } 1034 1035 /** 1036 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1037 * @hw: pointer to hardware structure 1038 **/ 1039 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1040 { 1041 u32 eec; 1042 u32 i; 1043 u16 data = 0; 1044 1045 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 1046 1047 /* 1048 * In order to read a register from the EEPROM, we need to shift 1049 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1050 * the clock input to the EEPROM (setting the SK bit), and then reading 1051 * the value of the "DO" bit. During this "shifting in" process the 1052 * "DI" bit should always be clear. 1053 */ 1054 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1055 1056 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1057 1058 for (i = 0; i < count; i++) { 1059 data = data << 1; 1060 ixgbe_raise_eeprom_clk(hw, &eec); 1061 1062 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1063 1064 eec &= ~(IXGBE_EEC_DI); 1065 if (eec & IXGBE_EEC_DO) 1066 data |= 1; 1067 1068 ixgbe_lower_eeprom_clk(hw, &eec); 1069 } 1070 1071 return data; 1072 } 1073 1074 /** 1075 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1076 * @hw: pointer to hardware structure 1077 * @eec: EEC register's current value 1078 **/ 1079 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1080 { 1081 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 1082 1083 /* 1084 * Raise the clock input to the EEPROM 1085 * (setting the SK bit), then delay 1086 */ 1087 *eec = *eec | IXGBE_EEC_SK; 1088 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1089 IXGBE_WRITE_FLUSH(hw); 1090 usec_delay(1); 1091 } 1092 1093 /** 1094 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1095 * @hw: pointer to hardware structure 1096 * @eecd: EECD's current value 1097 **/ 1098 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1099 { 1100 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 1101 1102 /* 1103 * Lower the clock input to the EEPROM (clearing the SK bit), then 1104 * delay 1105 */ 1106 *eec = *eec & ~IXGBE_EEC_SK; 1107 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1108 IXGBE_WRITE_FLUSH(hw); 1109 usec_delay(1); 1110 } 1111 1112 /** 1113 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1114 * @hw: pointer to hardware structure 1115 **/ 1116 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1117 { 1118 u32 eec; 1119 1120 DEBUGFUNC("ixgbe_release_eeprom"); 1121 1122 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1123 1124 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1125 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1126 1127 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1128 IXGBE_WRITE_FLUSH(hw); 1129 1130 usec_delay(1); 1131 1132 /* Stop requesting EEPROM access */ 1133 eec &= ~IXGBE_EEC_REQ; 1134 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1135 1136 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1137 1138 /* Delay before attempt to obtain semaphore again to allow FW access */ 1139 msec_delay(hw->eeprom.semaphore_delay); 1140 } 1141 1142 /** 1143 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1144 * @hw: pointer to hardware structure 1145 **/ 1146 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1147 { 1148 u16 i; 1149 u16 j; 1150 u16 checksum = 0; 1151 u16 length = 0; 1152 u16 pointer = 0; 1153 u16 word = 0; 1154 1155 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 1156 1157 /* Include 0x0-0x3F in the checksum */ 1158 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1159 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1160 DEBUGOUT("EEPROM read failed\n"); 1161 break; 1162 } 1163 checksum += word; 1164 } 1165 1166 /* Include all data from pointers except for the fw pointer */ 1167 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1168 hw->eeprom.ops.read(hw, i, &pointer); 1169 1170 /* Make sure the pointer seems valid */ 1171 if (pointer != 0xFFFF && pointer != 0) { 1172 hw->eeprom.ops.read(hw, pointer, &length); 1173 1174 if (length != 0xFFFF && length != 0) { 1175 for (j = pointer+1; j <= pointer+length; j++) { 1176 hw->eeprom.ops.read(hw, j, &word); 1177 checksum += word; 1178 } 1179 } 1180 } 1181 } 1182 1183 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1184 1185 return checksum; 1186 } 1187 1188 /** 1189 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1190 * @hw: pointer to hardware structure 1191 * @checksum_val: calculated checksum 1192 * 1193 * Performs checksum calculation and validates the EEPROM checksum. If the 1194 * caller does not need checksum_val, the value can be NULL. 1195 **/ 1196 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1197 u16 *checksum_val) 1198 { 1199 s32 status; 1200 u16 checksum; 1201 u16 read_checksum = 0; 1202 1203 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 1204 1205 /* 1206 * Read the first word from the EEPROM. If this times out or fails, do 1207 * not continue or we could be in for a very long wait while every 1208 * EEPROM read fails 1209 */ 1210 status = hw->eeprom.ops.read(hw, 0, &checksum); 1211 1212 if (status == IXGBE_SUCCESS) { 1213 checksum = hw->eeprom.ops.calc_checksum(hw); 1214 1215 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1216 1217 /* 1218 * Verify read checksum from EEPROM is the same as 1219 * calculated checksum 1220 */ 1221 if (read_checksum != checksum) 1222 status = IXGBE_ERR_EEPROM_CHECKSUM; 1223 1224 /* If the user cares, return the calculated checksum */ 1225 if (checksum_val) 1226 *checksum_val = checksum; 1227 } else { 1228 DEBUGOUT("EEPROM read failed\n"); 1229 } 1230 1231 return status; 1232 } 1233 1234 /** 1235 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1236 * @hw: pointer to hardware structure 1237 **/ 1238 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1239 { 1240 s32 status; 1241 u16 checksum; 1242 1243 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 1244 1245 /* 1246 * Read the first word from the EEPROM. If this times out or fails, do 1247 * not continue or we could be in for a very long wait while every 1248 * EEPROM read fails 1249 */ 1250 status = hw->eeprom.ops.read(hw, 0, &checksum); 1251 1252 if (status == IXGBE_SUCCESS) { 1253 checksum = hw->eeprom.ops.calc_checksum(hw); 1254 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1255 checksum); 1256 } else { 1257 DEBUGOUT("EEPROM read failed\n"); 1258 } 1259 1260 return status; 1261 } 1262 1263 /** 1264 * ixgbe_validate_mac_addr - Validate MAC address 1265 * @mac_addr: pointer to MAC address. 1266 * 1267 * Tests a MAC address to ensure it is a valid Individual Address 1268 **/ 1269 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1270 { 1271 s32 status = IXGBE_SUCCESS; 1272 1273 DEBUGFUNC("ixgbe_validate_mac_addr"); 1274 1275 /* Make sure it is not a multicast address */ 1276 if (IXGBE_IS_MULTICAST(mac_addr)) { 1277 DEBUGOUT("MAC address is multicast\n"); 1278 status = IXGBE_ERR_INVALID_MAC_ADDR; 1279 /* Not a broadcast address */ 1280 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1281 DEBUGOUT("MAC address is broadcast\n"); 1282 status = IXGBE_ERR_INVALID_MAC_ADDR; 1283 /* Reject the zero address */ 1284 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1285 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1286 DEBUGOUT("MAC address is all zeros\n"); 1287 status = IXGBE_ERR_INVALID_MAC_ADDR; 1288 } 1289 return status; 1290 } 1291 1292 /** 1293 * ixgbe_set_rar_generic - Set Rx address register 1294 * @hw: pointer to hardware structure 1295 * @index: Receive address register to write 1296 * @addr: Address to put into receive address register 1297 * @vmdq: VMDq "set" or "pool" index 1298 * @enable_addr: set flag that address is active 1299 * 1300 * Puts an ethernet address into a receive address register. 1301 **/ 1302 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1303 u32 enable_addr) 1304 { 1305 u32 rar_low, rar_high; 1306 u32 rar_entries = hw->mac.num_rar_entries; 1307 1308 DEBUGFUNC("ixgbe_set_rar_generic"); 1309 1310 /* setup VMDq pool selection before this RAR gets enabled */ 1311 hw->mac.ops.set_vmdq(hw, index, vmdq); 1312 1313 /* Make sure we are using a valid rar index range */ 1314 if (index < rar_entries) { 1315 /* 1316 * HW expects these in little endian so we reverse the byte 1317 * order from network order (big endian) to little endian 1318 */ 1319 rar_low = ((u32)addr[0] | 1320 ((u32)addr[1] << 8) | 1321 ((u32)addr[2] << 16) | 1322 ((u32)addr[3] << 24)); 1323 /* 1324 * Some parts put the VMDq setting in the extra RAH bits, 1325 * so save everything except the lower 16 bits that hold part 1326 * of the address and the address valid bit. 1327 */ 1328 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1329 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1330 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1331 1332 if (enable_addr != 0) 1333 rar_high |= IXGBE_RAH_AV; 1334 1335 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1336 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1337 } else { 1338 DEBUGOUT1("RAR index %d is out of range.\n", index); 1339 } 1340 1341 return IXGBE_SUCCESS; 1342 } 1343 1344 /** 1345 * ixgbe_clear_rar_generic - Remove Rx address register 1346 * @hw: pointer to hardware structure 1347 * @index: Receive address register to write 1348 * 1349 * Clears an ethernet address from a receive address register. 1350 **/ 1351 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1352 { 1353 u32 rar_high; 1354 u32 rar_entries = hw->mac.num_rar_entries; 1355 1356 DEBUGFUNC("ixgbe_clear_rar_generic"); 1357 1358 /* Make sure we are using a valid rar index range */ 1359 if (index < rar_entries) { 1360 /* 1361 * Some parts put the VMDq setting in the extra RAH bits, 1362 * so save everything except the lower 16 bits that hold part 1363 * of the address and the address valid bit. 1364 */ 1365 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1366 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1367 1368 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1369 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1370 } else { 1371 DEBUGOUT1("RAR index %d is out of range.\n", index); 1372 } 1373 1374 /* clear VMDq pool/queue selection for this RAR */ 1375 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1376 1377 return IXGBE_SUCCESS; 1378 } 1379 1380 /** 1381 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1382 * @hw: pointer to hardware structure 1383 * 1384 * Places the MAC address in receive address register 0 and clears the rest 1385 * of the receive address registers. Clears the multicast table. Assumes 1386 * the receiver is in reset when the routine is called. 1387 **/ 1388 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1389 { 1390 u32 i; 1391 u32 rar_entries = hw->mac.num_rar_entries; 1392 1393 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 1394 1395 /* 1396 * If the current mac address is valid, assume it is a software override 1397 * to the permanent address. 1398 * Otherwise, use the permanent address from the eeprom. 1399 */ 1400 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1401 IXGBE_ERR_INVALID_MAC_ADDR) { 1402 /* Get the MAC address from the RAR0 for later reference */ 1403 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1404 1405 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1406 hw->mac.addr[0], hw->mac.addr[1], 1407 hw->mac.addr[2]); 1408 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1409 hw->mac.addr[4], hw->mac.addr[5]); 1410 } else { 1411 /* Setup the receive address. */ 1412 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1413 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1414 hw->mac.addr[0], hw->mac.addr[1], 1415 hw->mac.addr[2]); 1416 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1417 hw->mac.addr[4], hw->mac.addr[5]); 1418 1419 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1420 } 1421 hw->addr_ctrl.overflow_promisc = 0; 1422 1423 hw->addr_ctrl.rar_used_count = 1; 1424 1425 /* Zero out the other receive addresses. */ 1426 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1427 for (i = 1; i < rar_entries; i++) { 1428 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1429 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1430 } 1431 1432 /* Clear the MTA */ 1433 hw->addr_ctrl.mta_in_use = 0; 1434 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1435 1436 DEBUGOUT(" Clearing MTA\n"); 1437 for (i = 0; i < hw->mac.mcft_size; i++) 1438 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1439 1440 ixgbe_init_uta_tables(hw); 1441 1442 return IXGBE_SUCCESS; 1443 } 1444 1445 /** 1446 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1447 * @hw: pointer to hardware structure 1448 * @addr: new address 1449 * 1450 * Adds it to unused receive address register or goes into promiscuous mode. 1451 **/ 1452 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1453 { 1454 u32 rar_entries = hw->mac.num_rar_entries; 1455 u32 rar; 1456 1457 DEBUGFUNC("ixgbe_add_uc_addr"); 1458 1459 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1460 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1461 1462 /* 1463 * Place this address in the RAR if there is room, 1464 * else put the controller into promiscuous mode 1465 */ 1466 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1467 rar = hw->addr_ctrl.rar_used_count; 1468 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1469 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1470 hw->addr_ctrl.rar_used_count++; 1471 } else { 1472 hw->addr_ctrl.overflow_promisc++; 1473 } 1474 1475 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1476 } 1477 1478 /** 1479 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1480 * @hw: pointer to hardware structure 1481 * @addr_list: the list of new addresses 1482 * @addr_count: number of addresses 1483 * @next: iterator function to walk the address list 1484 * 1485 * The given list replaces any existing list. Clears the secondary addrs from 1486 * receive address registers. Uses unused receive address registers for the 1487 * first secondary addresses, and falls back to promiscuous mode as needed. 1488 * 1489 * Drivers using secondary unicast addresses must set user_set_promisc when 1490 * manually putting the device into promiscuous mode. 1491 **/ 1492 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1493 u32 addr_count, ixgbe_mc_addr_itr next) 1494 { 1495 u8 *addr; 1496 u32 i; 1497 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1498 u32 uc_addr_in_use; 1499 u32 fctrl; 1500 u32 vmdq; 1501 1502 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 1503 1504 /* 1505 * Clear accounting of old secondary address list, 1506 * don't count RAR[0] 1507 */ 1508 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1509 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1510 hw->addr_ctrl.overflow_promisc = 0; 1511 1512 /* Zero out the other receive addresses */ 1513 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 1514 for (i = 0; i < uc_addr_in_use; i++) { 1515 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 1516 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 1517 } 1518 1519 /* Add the new addresses */ 1520 for (i = 0; i < addr_count; i++) { 1521 DEBUGOUT(" Adding the secondary addresses:\n"); 1522 addr = next(hw, &addr_list, &vmdq); 1523 ixgbe_add_uc_addr(hw, addr, vmdq); 1524 } 1525 1526 if (hw->addr_ctrl.overflow_promisc) { 1527 /* enable promisc if not already in overflow or set by user */ 1528 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1529 DEBUGOUT(" Entering address overflow promisc mode\n"); 1530 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1531 fctrl |= IXGBE_FCTRL_UPE; 1532 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1533 } 1534 } else { 1535 /* only disable if set by overflow, not by user */ 1536 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1537 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1538 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1539 fctrl &= ~IXGBE_FCTRL_UPE; 1540 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1541 } 1542 } 1543 1544 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1545 return IXGBE_SUCCESS; 1546 } 1547 1548 /** 1549 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1550 * @hw: pointer to hardware structure 1551 * @mc_addr: the multicast address 1552 * 1553 * Extracts the 12 bits, from a multicast address, to determine which 1554 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1555 * incoming rx multicast addresses, to determine the bit-vector to check in 1556 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1557 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1558 * to mc_filter_type. 1559 **/ 1560 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1561 { 1562 u32 vector = 0; 1563 1564 DEBUGFUNC("ixgbe_mta_vector"); 1565 1566 switch (hw->mac.mc_filter_type) { 1567 case 0: /* use bits [47:36] of the address */ 1568 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1569 break; 1570 case 1: /* use bits [46:35] of the address */ 1571 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1572 break; 1573 case 2: /* use bits [45:34] of the address */ 1574 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1575 break; 1576 case 3: /* use bits [43:32] of the address */ 1577 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1578 break; 1579 default: /* Invalid mc_filter_type */ 1580 DEBUGOUT("MC filter type param set incorrectly\n"); 1581 ASSERT(0); 1582 break; 1583 } 1584 1585 /* vector can only be 12-bits or boundary will be exceeded */ 1586 vector &= 0xFFF; 1587 return vector; 1588 } 1589 1590 /** 1591 * ixgbe_set_mta - Set bit-vector in multicast table 1592 * @hw: pointer to hardware structure 1593 * @hash_value: Multicast address hash value 1594 * 1595 * Sets the bit-vector in the multicast table. 1596 **/ 1597 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1598 { 1599 u32 vector; 1600 u32 vector_bit; 1601 u32 vector_reg; 1602 u32 mta_reg; 1603 1604 DEBUGFUNC("ixgbe_set_mta"); 1605 1606 hw->addr_ctrl.mta_in_use++; 1607 1608 vector = ixgbe_mta_vector(hw, mc_addr); 1609 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1610 1611 /* 1612 * The MTA is a register array of 128 32-bit registers. It is treated 1613 * like an array of 4096 bits. We want to set bit 1614 * BitArray[vector_value]. So we figure out what register the bit is 1615 * in, read it, OR in the new bit, then write back the new value. The 1616 * register is determined by the upper 7 bits of the vector value and 1617 * the bit within that register are determined by the lower 5 bits of 1618 * the value. 1619 */ 1620 vector_reg = (vector >> 5) & 0x7F; 1621 vector_bit = vector & 0x1F; 1622 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1623 mta_reg |= (1 << vector_bit); 1624 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1625 } 1626 1627 /** 1628 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1629 * @hw: pointer to hardware structure 1630 * @mc_addr_list: the list of new multicast addresses 1631 * @mc_addr_count: number of addresses 1632 * @next: iterator function to walk the multicast address list 1633 * 1634 * The given list replaces any existing list. Clears the MC addrs from receive 1635 * address registers and the multicast table. Uses unused receive address 1636 * registers for the first multicast addresses, and hashes the rest into the 1637 * multicast table. 1638 **/ 1639 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1640 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1641 { 1642 u32 i; 1643 u32 vmdq; 1644 1645 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 1646 1647 /* 1648 * Set the new number of MC addresses that we are being requested to 1649 * use. 1650 */ 1651 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1652 hw->addr_ctrl.mta_in_use = 0; 1653 1654 /* Clear the MTA */ 1655 DEBUGOUT(" Clearing MTA\n"); 1656 for (i = 0; i < hw->mac.mcft_size; i++) 1657 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1658 1659 /* Add the new addresses */ 1660 for (i = 0; i < mc_addr_count; i++) { 1661 DEBUGOUT(" Adding the multicast addresses:\n"); 1662 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1663 } 1664 1665 /* Enable mta */ 1666 if (hw->addr_ctrl.mta_in_use > 0) 1667 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1668 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1669 1670 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1671 return IXGBE_SUCCESS; 1672 } 1673 1674 /** 1675 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1676 * @hw: pointer to hardware structure 1677 * 1678 * Enables multicast address in RAR and the use of the multicast hash table. 1679 **/ 1680 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1681 { 1682 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1683 1684 DEBUGFUNC("ixgbe_enable_mc_generic"); 1685 1686 if (a->mta_in_use > 0) 1687 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1688 hw->mac.mc_filter_type); 1689 1690 return IXGBE_SUCCESS; 1691 } 1692 1693 /** 1694 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1695 * @hw: pointer to hardware structure 1696 * 1697 * Disables multicast address in RAR and the use of the multicast hash table. 1698 **/ 1699 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1700 { 1701 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1702 1703 DEBUGFUNC("ixgbe_disable_mc_generic"); 1704 1705 if (a->mta_in_use > 0) 1706 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1707 1708 return IXGBE_SUCCESS; 1709 } 1710 1711 /** 1712 * ixgbe_fc_enable_generic - Enable flow control 1713 * @hw: pointer to hardware structure 1714 * @packetbuf_num: packet buffer number (0-7) 1715 * 1716 * Enable flow control according to the current settings. 1717 **/ 1718 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1719 { 1720 s32 ret_val = IXGBE_SUCCESS; 1721 u32 mflcn_reg, fccfg_reg; 1722 u32 reg; 1723 u32 rx_pba_size; 1724 1725 DEBUGFUNC("ixgbe_fc_enable_generic"); 1726 1727 /* Negotiate the fc mode to use */ 1728 ret_val = ixgbe_fc_autoneg(hw); 1729 if (ret_val) 1730 goto out; 1731 1732 /* Disable any previous flow control settings */ 1733 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1734 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1735 1736 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1737 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1738 1739 /* 1740 * The possible values of fc.current_mode are: 1741 * 0: Flow control is completely disabled 1742 * 1: Rx flow control is enabled (we can receive pause frames, 1743 * but not send pause frames). 1744 * 2: Tx flow control is enabled (we can send pause frames but 1745 * we do not support receiving pause frames). 1746 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1747 * other: Invalid. 1748 */ 1749 switch (hw->fc.current_mode) { 1750 case ixgbe_fc_none: 1751 /* Flow control is disabled by software override or autoneg. 1752 * The code below will actually disable it in the HW. 1753 */ 1754 break; 1755 case ixgbe_fc_rx_pause: 1756 /* 1757 * Rx Flow control is enabled and Tx Flow control is 1758 * disabled by software override. Since there really 1759 * isn't a way to advertise that we are capable of RX 1760 * Pause ONLY, we will advertise that we support both 1761 * symmetric and asymmetric Rx PAUSE. Later, we will 1762 * disable the adapter's ability to send PAUSE frames. 1763 */ 1764 mflcn_reg |= IXGBE_MFLCN_RFCE; 1765 break; 1766 case ixgbe_fc_tx_pause: 1767 /* 1768 * Tx Flow control is enabled, and Rx Flow control is 1769 * disabled by software override. 1770 */ 1771 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1772 break; 1773 case ixgbe_fc_full: 1774 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1775 mflcn_reg |= IXGBE_MFLCN_RFCE; 1776 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1777 break; 1778 default: 1779 DEBUGOUT("Flow control param set incorrectly\n"); 1780 ret_val = IXGBE_ERR_CONFIG; 1781 goto out; 1782 break; 1783 } 1784 1785 /* Set 802.3x based flow control settings. */ 1786 mflcn_reg |= IXGBE_MFLCN_DPF; 1787 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1788 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1789 1790 reg = IXGBE_READ_REG(hw, IXGBE_MTQC); 1791 /* Thresholds are different for link flow control when in DCB mode */ 1792 if (reg & IXGBE_MTQC_RT_ENA) { 1793 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); 1794 1795 /* Always disable XON for LFC when in DCB mode */ 1796 reg = (rx_pba_size >> 5) & 0xFFE0; 1797 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg); 1798 1799 reg = (rx_pba_size >> 2) & 0xFFE0; 1800 if (hw->fc.current_mode & ixgbe_fc_tx_pause) 1801 reg |= IXGBE_FCRTH_FCEN; 1802 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); 1803 } else { 1804 /* Set up and enable Rx high/low water mark thresholds, 1805 * enable XON. */ 1806 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 1807 if (hw->fc.send_xon) { 1808 IXGBE_WRITE_REG(hw, 1809 IXGBE_FCRTL_82599(packetbuf_num), 1810 (hw->fc.low_water | 1811 IXGBE_FCRTL_XONE)); 1812 } else { 1813 IXGBE_WRITE_REG(hw, 1814 IXGBE_FCRTL_82599(packetbuf_num), 1815 hw->fc.low_water); 1816 } 1817 1818 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), 1819 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 1820 } 1821 } 1822 1823 /* Configure pause time (2 TCs per register) */ 1824 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 1825 if ((packetbuf_num & 1) == 0) 1826 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 1827 else 1828 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 1829 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 1830 1831 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1832 1833 out: 1834 return ret_val; 1835 } 1836 1837 /** 1838 * ixgbe_fc_autoneg - Configure flow control 1839 * @hw: pointer to hardware structure 1840 * 1841 * Compares our advertised flow control capabilities to those advertised by 1842 * our link partner, and determines the proper flow control mode to use. 1843 **/ 1844 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1845 { 1846 s32 ret_val = IXGBE_SUCCESS; 1847 ixgbe_link_speed speed; 1848 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1849 u32 links2, anlp1_reg, autoc_reg, links; 1850 bool link_up; 1851 1852 DEBUGFUNC("ixgbe_fc_autoneg"); 1853 1854 /* 1855 * AN should have completed when the cable was plugged in. 1856 * Look for reasons to bail out. Bail out if: 1857 * - FC autoneg is disabled, or if 1858 * - link is not up. 1859 * 1860 * Since we're being called from an LSC, link is already known to be up. 1861 * So use link_up_wait_to_complete=FALSE. 1862 */ 1863 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1864 1865 if (hw->fc.disable_fc_autoneg || (!link_up)) { 1866 hw->fc.fc_was_autonegged = FALSE; 1867 hw->fc.current_mode = hw->fc.requested_mode; 1868 goto out; 1869 } 1870 1871 /* 1872 * On backplane, bail out if 1873 * - backplane autoneg was not completed, or if 1874 * - we are 82599 and link partner is not AN enabled 1875 */ 1876 if (hw->phy.media_type == ixgbe_media_type_backplane) { 1877 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 1878 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 1879 hw->fc.fc_was_autonegged = FALSE; 1880 hw->fc.current_mode = hw->fc.requested_mode; 1881 goto out; 1882 } 1883 1884 if (hw->mac.type == ixgbe_mac_82599EB) { 1885 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 1886 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 1887 hw->fc.fc_was_autonegged = FALSE; 1888 hw->fc.current_mode = hw->fc.requested_mode; 1889 goto out; 1890 } 1891 } 1892 } 1893 1894 /* 1895 * On multispeed fiber at 1g, bail out if 1896 * - link is up but AN did not complete, or if 1897 * - link is up and AN completed but timed out 1898 */ 1899 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { 1900 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1901 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1902 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1903 hw->fc.fc_was_autonegged = FALSE; 1904 hw->fc.current_mode = hw->fc.requested_mode; 1905 goto out; 1906 } 1907 } 1908 1909 /* 1910 * Bail out on 1911 * - copper or CX4 adapters 1912 * - fiber adapters running at 10gig 1913 */ 1914 if ((hw->phy.media_type == ixgbe_media_type_copper) || 1915 (hw->phy.media_type == ixgbe_media_type_cx4) || 1916 ((hw->phy.media_type == ixgbe_media_type_fiber) && 1917 (speed == IXGBE_LINK_SPEED_10GB_FULL))) { 1918 hw->fc.fc_was_autonegged = FALSE; 1919 hw->fc.current_mode = hw->fc.requested_mode; 1920 goto out; 1921 } 1922 1923 /* 1924 * Read the AN advertisement and LP ability registers and resolve 1925 * local flow control settings accordingly 1926 */ 1927 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1928 (hw->phy.media_type != ixgbe_media_type_backplane)) { 1929 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1930 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1931 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1932 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1933 /* 1934 * Now we need to check if the user selected Rx ONLY 1935 * of pause frames. In this case, we had to advertise 1936 * FULL flow control because we could not advertise RX 1937 * ONLY. Hence, we must now check to see if we need to 1938 * turn OFF the TRANSMISSION of PAUSE frames. 1939 */ 1940 if (hw->fc.requested_mode == ixgbe_fc_full) { 1941 hw->fc.current_mode = ixgbe_fc_full; 1942 DEBUGOUT("Flow Control = FULL.\n"); 1943 } else { 1944 hw->fc.current_mode = ixgbe_fc_rx_pause; 1945 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 1946 } 1947 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1948 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1949 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1950 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1951 hw->fc.current_mode = ixgbe_fc_tx_pause; 1952 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1953 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1954 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1955 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1956 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1957 hw->fc.current_mode = ixgbe_fc_rx_pause; 1958 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1959 } else { 1960 hw->fc.current_mode = ixgbe_fc_none; 1961 DEBUGOUT("Flow Control = NONE.\n"); 1962 } 1963 } 1964 1965 if (hw->phy.media_type == ixgbe_media_type_backplane) { 1966 /* 1967 * Read the 10g AN autoc and LP ability registers and resolve 1968 * local flow control settings accordingly 1969 */ 1970 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1971 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 1972 1973 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1974 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { 1975 /* 1976 * Now we need to check if the user selected Rx ONLY 1977 * of pause frames. In this case, we had to advertise 1978 * FULL flow control because we could not advertise RX 1979 * ONLY. Hence, we must now check to see if we need to 1980 * turn OFF the TRANSMISSION of PAUSE frames. 1981 */ 1982 if (hw->fc.requested_mode == ixgbe_fc_full) { 1983 hw->fc.current_mode = ixgbe_fc_full; 1984 DEBUGOUT("Flow Control = FULL.\n"); 1985 } else { 1986 hw->fc.current_mode = ixgbe_fc_rx_pause; 1987 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 1988 } 1989 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1990 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 1991 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 1992 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 1993 hw->fc.current_mode = ixgbe_fc_tx_pause; 1994 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1995 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1996 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 1997 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 1998 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 1999 hw->fc.current_mode = ixgbe_fc_rx_pause; 2000 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2001 } else { 2002 hw->fc.current_mode = ixgbe_fc_none; 2003 DEBUGOUT("Flow Control = NONE.\n"); 2004 } 2005 } 2006 /* Record that current_mode is the result of a successful autoneg */ 2007 hw->fc.fc_was_autonegged = TRUE; 2008 2009 out: 2010 return ret_val; 2011 } 2012 2013 /** 2014 * ixgbe_setup_fc - Set up flow control 2015 * @hw: pointer to hardware structure 2016 * 2017 * Called at init time to set up flow control. 2018 **/ 2019 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 2020 { 2021 s32 ret_val = IXGBE_SUCCESS; 2022 u32 reg; 2023 2024 DEBUGFUNC("ixgbe_setup_fc"); 2025 2026 2027 /* Validate the packetbuf configuration */ 2028 if (packetbuf_num < 0 || packetbuf_num > 7) { 2029 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 2030 " 0-7\n", packetbuf_num); 2031 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2032 goto out; 2033 } 2034 2035 /* 2036 * Validate the water mark configuration. Zero water marks are invalid 2037 * because it causes the controller to just blast out fc packets. 2038 */ 2039 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 2040 DEBUGOUT("Invalid water mark configuration\n"); 2041 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2042 goto out; 2043 } 2044 2045 /* 2046 * Validate the requested mode. Strict IEEE mode does not allow 2047 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 2048 */ 2049 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2050 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2051 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2052 goto out; 2053 } 2054 2055 /* 2056 * 10gig parts do not have a word in the EEPROM to determine the 2057 * default flow control setting, so we explicitly set it to full. 2058 */ 2059 if (hw->fc.requested_mode == ixgbe_fc_default) 2060 hw->fc.requested_mode = ixgbe_fc_full; 2061 2062 /* 2063 * Set up the 1G flow control advertisement registers so the HW will be 2064 * able to do fc autoneg once the cable is plugged in. If we end up 2065 * using 10g instead, this is harmless. 2066 */ 2067 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2068 2069 /* 2070 * The possible values of fc.requested_mode are: 2071 * 0: Flow control is completely disabled 2072 * 1: Rx flow control is enabled (we can receive pause frames, 2073 * but not send pause frames). 2074 * 2: Tx flow control is enabled (we can send pause frames but 2075 * we do not support receiving pause frames). 2076 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2077 * other: Invalid. 2078 */ 2079 switch (hw->fc.requested_mode) { 2080 case ixgbe_fc_none: 2081 /* Flow control completely disabled by software override. */ 2082 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2083 break; 2084 case ixgbe_fc_rx_pause: 2085 /* 2086 * Rx Flow control is enabled and Tx Flow control is 2087 * disabled by software override. Since there really 2088 * isn't a way to advertise that we are capable of RX 2089 * Pause ONLY, we will advertise that we support both 2090 * symmetric and asymmetric Rx PAUSE. Later, we will 2091 * disable the adapter's ability to send PAUSE frames. 2092 */ 2093 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2094 break; 2095 case ixgbe_fc_tx_pause: 2096 /* 2097 * Tx Flow control is enabled, and Rx Flow control is 2098 * disabled by software override. 2099 */ 2100 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 2101 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 2102 break; 2103 case ixgbe_fc_full: 2104 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2105 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2106 break; 2107 default: 2108 DEBUGOUT("Flow control param set incorrectly\n"); 2109 ret_val = IXGBE_ERR_CONFIG; 2110 goto out; 2111 break; 2112 } 2113 2114 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 2115 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 2116 2117 /* Disable AN timeout */ 2118 if (hw->fc.strict_ieee) 2119 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 2120 2121 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2122 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 2123 2124 /* 2125 * Set up the 10G flow control advertisement registers so the HW 2126 * can do fc autoneg once the cable is plugged in. If we end up 2127 * using 1g instead, this is harmless. 2128 */ 2129 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2130 2131 /* 2132 * The possible values of fc.requested_mode are: 2133 * 0: Flow control is completely disabled 2134 * 1: Rx flow control is enabled (we can receive pause frames, 2135 * but not send pause frames). 2136 * 2: Tx flow control is enabled (we can send pause frames but 2137 * we do not support receiving pause frames). 2138 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2139 * other: Invalid. 2140 */ 2141 switch (hw->fc.requested_mode) { 2142 case ixgbe_fc_none: 2143 /* Flow control completely disabled by software override. */ 2144 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2145 break; 2146 case ixgbe_fc_rx_pause: 2147 /* 2148 * Rx Flow control is enabled and Tx Flow control is 2149 * disabled by software override. Since there really 2150 * isn't a way to advertise that we are capable of RX 2151 * Pause ONLY, we will advertise that we support both 2152 * symmetric and asymmetric Rx PAUSE. Later, we will 2153 * disable the adapter's ability to send PAUSE frames. 2154 */ 2155 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2156 break; 2157 case ixgbe_fc_tx_pause: 2158 /* 2159 * Tx Flow control is enabled, and Rx Flow control is 2160 * disabled by software override. 2161 */ 2162 reg |= (IXGBE_AUTOC_ASM_PAUSE); 2163 reg &= ~(IXGBE_AUTOC_SYM_PAUSE); 2164 break; 2165 case ixgbe_fc_full: 2166 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2167 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2168 break; 2169 default: 2170 DEBUGOUT("Flow control param set incorrectly\n"); 2171 ret_val = IXGBE_ERR_CONFIG; 2172 goto out; 2173 break; 2174 } 2175 /* 2176 * AUTOC restart handles negotiation of 1G and 10G. There is 2177 * no need to set the PCS1GCTL register. 2178 */ 2179 reg |= IXGBE_AUTOC_AN_RESTART; 2180 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); 2181 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 2182 2183 out: 2184 return ret_val; 2185 } 2186 2187 /** 2188 * ixgbe_disable_pcie_master - Disable PCI-express master access 2189 * @hw: pointer to hardware structure 2190 * 2191 * Disables PCI-Express master access and verifies there are no pending 2192 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2193 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 2194 * is returned signifying master requests disabled. 2195 **/ 2196 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2197 { 2198 u32 i; 2199 u32 reg_val; 2200 u32 number_of_queues; 2201 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2202 2203 DEBUGFUNC("ixgbe_disable_pcie_master"); 2204 2205 /* Disable the receive unit by stopping each queue */ 2206 number_of_queues = hw->mac.max_rx_queues; 2207 for (i = 0; i < number_of_queues; i++) { 2208 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 2209 if (reg_val & IXGBE_RXDCTL_ENABLE) { 2210 reg_val &= ~IXGBE_RXDCTL_ENABLE; 2211 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 2212 } 2213 } 2214 2215 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2216 reg_val |= IXGBE_CTRL_GIO_DIS; 2217 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2218 2219 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2220 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 2221 status = IXGBE_SUCCESS; 2222 break; 2223 } 2224 usec_delay(100); 2225 } 2226 2227 return status; 2228 } 2229 2230 2231 /** 2232 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2233 * @hw: pointer to hardware structure 2234 * @mask: Mask to specify which semaphore to acquire 2235 * 2236 * Acquires the SWFW semaphore thought the GSSR register for the specified 2237 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2238 **/ 2239 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2240 { 2241 u32 gssr; 2242 u32 swmask = mask; 2243 u32 fwmask = mask << 5; 2244 s32 timeout = 200; 2245 2246 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 2247 2248 while (timeout) { 2249 /* 2250 * SW EEPROM semaphore bit is used for access to all 2251 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2252 */ 2253 if (ixgbe_get_eeprom_semaphore(hw)) 2254 return IXGBE_ERR_SWFW_SYNC; 2255 2256 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2257 if (!(gssr & (fwmask | swmask))) 2258 break; 2259 2260 /* 2261 * Firmware currently using resource (fwmask) or other software 2262 * thread currently using resource (swmask) 2263 */ 2264 ixgbe_release_eeprom_semaphore(hw); 2265 msec_delay(5); 2266 timeout--; 2267 } 2268 2269 if (!timeout) { 2270 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2271 return IXGBE_ERR_SWFW_SYNC; 2272 } 2273 2274 gssr |= swmask; 2275 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2276 2277 ixgbe_release_eeprom_semaphore(hw); 2278 return IXGBE_SUCCESS; 2279 } 2280 2281 /** 2282 * ixgbe_release_swfw_sync - Release SWFW semaphore 2283 * @hw: pointer to hardware structure 2284 * @mask: Mask to specify which semaphore to release 2285 * 2286 * Releases the SWFW semaphore thought the GSSR register for the specified 2287 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2288 **/ 2289 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2290 { 2291 u32 gssr; 2292 u32 swmask = mask; 2293 2294 DEBUGFUNC("ixgbe_release_swfw_sync"); 2295 2296 ixgbe_get_eeprom_semaphore(hw); 2297 2298 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2299 gssr &= ~swmask; 2300 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2301 2302 ixgbe_release_eeprom_semaphore(hw); 2303 } 2304 2305 /** 2306 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2307 * @hw: pointer to hardware structure 2308 * @regval: register value to write to RXCTRL 2309 * 2310 * Enables the Rx DMA unit 2311 **/ 2312 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2313 { 2314 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 2315 2316 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2317 2318 return IXGBE_SUCCESS; 2319 } 2320 2321 /** 2322 * ixgbe_blink_led_start_generic - Blink LED based on index. 2323 * @hw: pointer to hardware structure 2324 * @index: led number to blink 2325 **/ 2326 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2327 { 2328 ixgbe_link_speed speed = 0; 2329 bool link_up = 0; 2330 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2331 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2332 2333 DEBUGFUNC("ixgbe_blink_led_start_generic"); 2334 2335 /* 2336 * Link must be up to auto-blink the LEDs; 2337 * Force it if link is down. 2338 */ 2339 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 2340 2341 if (!link_up) { 2342 2343 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2344 autoc_reg |= IXGBE_AUTOC_FLU; 2345 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2346 msec_delay(10); 2347 } 2348 2349 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2350 led_reg |= IXGBE_LED_BLINK(index); 2351 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2352 IXGBE_WRITE_FLUSH(hw); 2353 2354 return IXGBE_SUCCESS; 2355 } 2356 2357 /** 2358 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2359 * @hw: pointer to hardware structure 2360 * @index: led number to stop blinking 2361 **/ 2362 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2363 { 2364 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2365 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2366 2367 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 2368 2369 2370 autoc_reg &= ~IXGBE_AUTOC_FLU; 2371 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2372 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2373 2374 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2375 led_reg &= ~IXGBE_LED_BLINK(index); 2376 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2377 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2378 IXGBE_WRITE_FLUSH(hw); 2379 2380 return IXGBE_SUCCESS; 2381 } 2382 2383 /** 2384 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2385 * @hw: pointer to hardware structure 2386 * @san_mac_offset: SAN MAC address offset 2387 * 2388 * This function will read the EEPROM location for the SAN MAC address 2389 * pointer, and returns the value at that location. This is used in both 2390 * get and set mac_addr routines. 2391 **/ 2392 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2393 u16 *san_mac_offset) 2394 { 2395 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 2396 2397 /* 2398 * First read the EEPROM pointer to see if the MAC addresses are 2399 * available. 2400 */ 2401 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2402 2403 return IXGBE_SUCCESS; 2404 } 2405 2406 /** 2407 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2408 * @hw: pointer to hardware structure 2409 * @san_mac_addr: SAN MAC address 2410 * 2411 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2412 * per-port, so set_lan_id() must be called before reading the addresses. 2413 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2414 * upon for non-SFP connections, so we must call it here. 2415 **/ 2416 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2417 { 2418 u16 san_mac_data, san_mac_offset; 2419 u8 i; 2420 2421 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 2422 2423 /* 2424 * First read the EEPROM pointer to see if the MAC addresses are 2425 * available. If they're not, no point in calling set_lan_id() here. 2426 */ 2427 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2428 2429 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2430 /* 2431 * No addresses available in this EEPROM. It's not an 2432 * error though, so just wipe the local address and return. 2433 */ 2434 for (i = 0; i < 6; i++) 2435 san_mac_addr[i] = 0xFF; 2436 2437 goto san_mac_addr_out; 2438 } 2439 2440 /* make sure we know which port we need to program */ 2441 hw->mac.ops.set_lan_id(hw); 2442 /* apply the port offset to the address offset */ 2443 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2444 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2445 for (i = 0; i < 3; i++) { 2446 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2447 san_mac_addr[i * 2] = (u8)(san_mac_data); 2448 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2449 san_mac_offset++; 2450 } 2451 2452 san_mac_addr_out: 2453 return IXGBE_SUCCESS; 2454 } 2455 2456 /** 2457 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 2458 * @hw: pointer to hardware structure 2459 * @san_mac_addr: SAN MAC address 2460 * 2461 * Write a SAN MAC address to the EEPROM. 2462 **/ 2463 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2464 { 2465 s32 status = IXGBE_SUCCESS; 2466 u16 san_mac_data, san_mac_offset; 2467 u8 i; 2468 2469 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 2470 2471 /* Look for SAN mac address pointer. If not defined, return */ 2472 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2473 2474 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2475 status = IXGBE_ERR_NO_SAN_ADDR_PTR; 2476 goto san_mac_addr_out; 2477 } 2478 2479 /* Make sure we know which port we need to write */ 2480 hw->mac.ops.set_lan_id(hw); 2481 /* Apply the port offset to the address offset */ 2482 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2483 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2484 2485 for (i = 0; i < 3; i++) { 2486 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 2487 san_mac_data |= (u16)(san_mac_addr[i * 2]); 2488 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 2489 san_mac_offset++; 2490 } 2491 2492 san_mac_addr_out: 2493 return status; 2494 } 2495 2496 /** 2497 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2498 * @hw: pointer to hardware structure 2499 * 2500 * Read PCIe configuration space, and get the MSI-X vector count from 2501 * the capabilities table. 2502 **/ 2503 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2504 { 2505 u32 msix_count = 64; 2506 2507 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 2508 if (hw->mac.msix_vectors_from_pcie) { 2509 msix_count = IXGBE_READ_PCIE_WORD(hw, 2510 IXGBE_PCIE_MSIX_82599_CAPS); 2511 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2512 2513 /* MSI-X count is zero-based in HW, so increment to give 2514 * proper value */ 2515 msix_count++; 2516 } 2517 2518 return msix_count; 2519 } 2520 2521 /** 2522 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 2523 * @hw: pointer to hardware structure 2524 * @addr: Address to put into receive address register 2525 * @vmdq: VMDq pool to assign 2526 * 2527 * Puts an ethernet address into a receive address register, or 2528 * finds the rar that it is aleady in; adds to the pool list 2529 **/ 2530 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2531 { 2532 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 2533 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 2534 u32 rar; 2535 u32 rar_low, rar_high; 2536 u32 addr_low, addr_high; 2537 2538 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 2539 2540 /* swap bytes for HW little endian */ 2541 addr_low = addr[0] | (addr[1] << 8) 2542 | (addr[2] << 16) 2543 | (addr[3] << 24); 2544 addr_high = addr[4] | (addr[5] << 8); 2545 2546 /* 2547 * Either find the mac_id in rar or find the first empty space. 2548 * rar_highwater points to just after the highest currently used 2549 * rar in order to shorten the search. It grows when we add a new 2550 * rar to the top. 2551 */ 2552 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 2553 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 2554 2555 if (((IXGBE_RAH_AV & rar_high) == 0) 2556 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 2557 first_empty_rar = rar; 2558 } else if ((rar_high & 0xFFFF) == addr_high) { 2559 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 2560 if (rar_low == addr_low) 2561 break; /* found it already in the rars */ 2562 } 2563 } 2564 2565 if (rar < hw->mac.rar_highwater) { 2566 /* already there so just add to the pool bits */ 2567 ixgbe_set_vmdq(hw, rar, vmdq); 2568 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 2569 /* stick it into first empty RAR slot we found */ 2570 rar = first_empty_rar; 2571 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2572 } else if (rar == hw->mac.rar_highwater) { 2573 /* add it to the top of the list and inc the highwater mark */ 2574 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2575 hw->mac.rar_highwater++; 2576 } else if (rar >= hw->mac.num_rar_entries) { 2577 return IXGBE_ERR_INVALID_MAC_ADDR; 2578 } 2579 2580 /* 2581 * If we found rar[0], make sure the default pool bit (we use pool 0) 2582 * remains cleared to be sure default pool packets will get delivered 2583 */ 2584 if (rar == 0) 2585 ixgbe_clear_vmdq(hw, rar, 0); 2586 2587 return rar; 2588 } 2589 2590 /** 2591 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2592 * @hw: pointer to hardware struct 2593 * @rar: receive address register index to disassociate 2594 * @vmdq: VMDq pool index to remove from the rar 2595 **/ 2596 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2597 { 2598 u32 mpsar_lo, mpsar_hi; 2599 u32 rar_entries = hw->mac.num_rar_entries; 2600 2601 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 2602 2603 if (rar < rar_entries) { 2604 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2605 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2606 2607 if (!mpsar_lo && !mpsar_hi) 2608 goto done; 2609 2610 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2611 if (mpsar_lo) { 2612 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2613 mpsar_lo = 0; 2614 } 2615 if (mpsar_hi) { 2616 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2617 mpsar_hi = 0; 2618 } 2619 } else if (vmdq < 32) { 2620 mpsar_lo &= ~(1 << vmdq); 2621 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2622 } else { 2623 mpsar_hi &= ~(1 << (vmdq - 32)); 2624 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2625 } 2626 2627 /* was that the last pool using this rar? */ 2628 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2629 hw->mac.ops.clear_rar(hw, rar); 2630 } else { 2631 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2632 } 2633 2634 done: 2635 return IXGBE_SUCCESS; 2636 } 2637 2638 /** 2639 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2640 * @hw: pointer to hardware struct 2641 * @rar: receive address register index to associate with a VMDq index 2642 * @vmdq: VMDq pool index 2643 **/ 2644 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2645 { 2646 u32 mpsar; 2647 u32 rar_entries = hw->mac.num_rar_entries; 2648 2649 DEBUGFUNC("ixgbe_set_vmdq_generic"); 2650 2651 if (rar < rar_entries) { 2652 if (vmdq < 32) { 2653 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2654 mpsar |= 1 << vmdq; 2655 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2656 } else { 2657 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2658 mpsar |= 1 << (vmdq - 32); 2659 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2660 } 2661 } else { 2662 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2663 } 2664 return IXGBE_SUCCESS; 2665 } 2666 2667 /** 2668 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 2669 * @hw: pointer to hardware structure 2670 **/ 2671 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 2672 { 2673 int i; 2674 2675 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 2676 DEBUGOUT(" Clearing UTA\n"); 2677 2678 for (i = 0; i < 128; i++) 2679 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2680 2681 return IXGBE_SUCCESS; 2682 } 2683 2684 /** 2685 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 2686 * @hw: pointer to hardware structure 2687 * @vlan: VLAN id to write to VLAN filter 2688 * 2689 * return the VLVF index where this VLAN id should be placed 2690 * 2691 **/ 2692 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 2693 { 2694 u32 bits = 0; 2695 u32 first_empty_slot = 0; 2696 s32 regindex; 2697 2698 /* 2699 * Search for the vlan id in the VLVF entries. Save off the first empty 2700 * slot found along the way 2701 */ 2702 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 2703 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 2704 if (!bits && !(first_empty_slot)) 2705 first_empty_slot = regindex; 2706 else if ((bits & 0x0FFF) == vlan) 2707 break; 2708 } 2709 2710 /* 2711 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 2712 * in the VLVF. Else use the first empty VLVF register for this 2713 * vlan id. 2714 */ 2715 if (regindex >= IXGBE_VLVF_ENTRIES) { 2716 if (first_empty_slot) 2717 regindex = first_empty_slot; 2718 else { 2719 DEBUGOUT("No space in VLVF.\n"); 2720 regindex = -1; 2721 } 2722 } 2723 2724 return regindex; 2725 } 2726 2727 /** 2728 * ixgbe_set_vfta_generic - Set VLAN filter table 2729 * @hw: pointer to hardware structure 2730 * @vlan: VLAN id to write to VLAN filter 2731 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2732 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2733 * 2734 * Turn on/off specified VLAN in the VLAN filter table. 2735 **/ 2736 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 2737 bool vlan_on) 2738 { 2739 s32 regindex; 2740 u32 bitindex; 2741 u32 bits; 2742 u32 vt; 2743 2744 DEBUGFUNC("ixgbe_set_vfta_generic"); 2745 2746 if (vlan > 4095) 2747 return IXGBE_ERR_PARAM; 2748 2749 /* 2750 * this is a 2 part operation - first the VFTA, then the 2751 * VLVF and VLVFB if VT Mode is set 2752 */ 2753 2754 /* Part 1 2755 * The VFTA is a bitstring made up of 128 32-bit registers 2756 * that enable the particular VLAN id, much like the MTA: 2757 * bits[11-5]: which register 2758 * bits[4-0]: which bit in the register 2759 */ 2760 regindex = (vlan >> 5) & 0x7F; 2761 bitindex = vlan & 0x1F; 2762 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 2763 if (vlan_on) 2764 bits |= (1 << bitindex); 2765 else 2766 bits &= ~(1 << bitindex); 2767 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 2768 2769 2770 /* Part 2 2771 * If VT Mode is set 2772 * Either vlan_on 2773 * make sure the vlan is in VLVF 2774 * set the vind bit in the matching VLVFB 2775 * Or !vlan_on 2776 * clear the pool bit and possibly the vind 2777 */ 2778 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2779 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 2780 if (vlan == 0) { 2781 regindex = 0; 2782 } else { 2783 regindex = ixgbe_find_vlvf_slot(hw, vlan); 2784 if (regindex < 0) 2785 goto out; 2786 } 2787 2788 if (vlan_on) { 2789 /* set the pool bit */ 2790 if (vind < 32) { 2791 bits = IXGBE_READ_REG(hw, 2792 IXGBE_VLVFB(regindex*2)); 2793 bits |= (1 << vind); 2794 IXGBE_WRITE_REG(hw, 2795 IXGBE_VLVFB(regindex*2), 2796 bits); 2797 } else { 2798 bits = IXGBE_READ_REG(hw, 2799 IXGBE_VLVFB((regindex*2)+1)); 2800 bits |= (1 << vind); 2801 IXGBE_WRITE_REG(hw, 2802 IXGBE_VLVFB((regindex*2)+1), 2803 bits); 2804 } 2805 } else { 2806 /* clear the pool bit */ 2807 if (vind < 32) { 2808 bits = IXGBE_READ_REG(hw, 2809 IXGBE_VLVFB(regindex*2)); 2810 bits &= ~(1 << vind); 2811 IXGBE_WRITE_REG(hw, 2812 IXGBE_VLVFB(regindex*2), 2813 bits); 2814 bits |= IXGBE_READ_REG(hw, 2815 IXGBE_VLVFB((regindex*2)+1)); 2816 } else { 2817 bits = IXGBE_READ_REG(hw, 2818 IXGBE_VLVFB((regindex*2)+1)); 2819 bits &= ~(1 << vind); 2820 IXGBE_WRITE_REG(hw, 2821 IXGBE_VLVFB((regindex*2)+1), 2822 bits); 2823 bits |= IXGBE_READ_REG(hw, 2824 IXGBE_VLVFB(regindex*2)); 2825 } 2826 } 2827 2828 if (bits) 2829 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 2830 (IXGBE_VLVF_VIEN | vlan)); 2831 else 2832 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0); 2833 } 2834 out: 2835 return IXGBE_SUCCESS; 2836 } 2837 2838 /** 2839 * ixgbe_clear_vfta_generic - Clear VLAN filter table 2840 * @hw: pointer to hardware structure 2841 * 2842 * Clears the VLAN filer table, and the VMDq index associated with the filter 2843 **/ 2844 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 2845 { 2846 u32 offset; 2847 2848 DEBUGFUNC("ixgbe_clear_vfta_generic"); 2849 2850 for (offset = 0; offset < hw->mac.vft_size; offset++) 2851 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 2852 2853 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 2854 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 2855 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 2856 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 2857 } 2858 2859 return IXGBE_SUCCESS; 2860 } 2861 2862 /** 2863 * ixgbe_check_mac_link_generic - Determine link and speed status 2864 * @hw: pointer to hardware structure 2865 * @speed: pointer to link speed 2866 * @link_up: TRUE when link is up 2867 * @link_up_wait_to_complete: bool used to wait for link up or not 2868 * 2869 * Reads the links register to determine if link is up and the current speed 2870 **/ 2871 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 2872 bool *link_up, bool link_up_wait_to_complete) 2873 { 2874 u32 links_reg; 2875 u32 i; 2876 2877 DEBUGFUNC("ixgbe_check_mac_link_generic"); 2878 2879 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 2880 if (link_up_wait_to_complete) { 2881 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 2882 if (links_reg & IXGBE_LINKS_UP) { 2883 *link_up = TRUE; 2884 break; 2885 } else { 2886 *link_up = FALSE; 2887 } 2888 msec_delay(100); 2889 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 2890 } 2891 } else { 2892 if (links_reg & IXGBE_LINKS_UP) 2893 *link_up = TRUE; 2894 else 2895 *link_up = FALSE; 2896 } 2897 2898 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 2899 IXGBE_LINKS_SPEED_10G_82599) 2900 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2901 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 2902 IXGBE_LINKS_SPEED_1G_82599) 2903 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2904 else 2905 *speed = IXGBE_LINK_SPEED_100_FULL; 2906 2907 /* if link is down, zero out the current_mode */ 2908 if (*link_up == FALSE) { 2909 hw->fc.current_mode = ixgbe_fc_none; 2910 hw->fc.fc_was_autonegged = FALSE; 2911 } 2912 2913 return IXGBE_SUCCESS; 2914 } 2915 2916 /** 2917 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 2918 * the EEPROM 2919 * @hw: pointer to hardware structure 2920 * @wwnn_prefix: the alternative WWNN prefix 2921 * @wwpn_prefix: the alternative WWPN prefix 2922 * 2923 * This function will read the EEPROM from the alternative SAN MAC address 2924 * block to check the support for the alternative WWNN/WWPN prefix support. 2925 **/ 2926 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 2927 u16 *wwpn_prefix) 2928 { 2929 u16 offset, caps; 2930 u16 alt_san_mac_blk_offset; 2931 2932 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 2933 2934 /* clear output first */ 2935 *wwnn_prefix = 0xFFFF; 2936 *wwpn_prefix = 0xFFFF; 2937 2938 /* check if alternative SAN MAC is supported */ 2939 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 2940 &alt_san_mac_blk_offset); 2941 2942 if ((alt_san_mac_blk_offset == 0) || 2943 (alt_san_mac_blk_offset == 0xFFFF)) 2944 goto wwn_prefix_out; 2945 2946 /* check capability in alternative san mac address block */ 2947 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 2948 hw->eeprom.ops.read(hw, offset, &caps); 2949 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 2950 goto wwn_prefix_out; 2951 2952 /* get the corresponding prefix for WWNN/WWPN */ 2953 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 2954 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 2955 2956 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 2957 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 2958 2959 wwn_prefix_out: 2960 return IXGBE_SUCCESS; 2961 } 2962