1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 #include "ixgbe_dcb.h" 38 #include "ixgbe_dcb_82599.h" 39 #include "ixgbe_api.h" 40 41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 47 u16 count); 48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 52 53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 55 u16 *san_mac_offset); 56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 57 u16 words, u16 *data); 58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 59 u16 words, u16 *data); 60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 61 u16 offset); 62 63 /** 64 * ixgbe_init_ops_generic - Inits function ptrs 65 * @hw: pointer to the hardware structure 66 * 67 * Initialize the function pointers. 68 **/ 69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 70 { 71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 72 struct ixgbe_mac_info *mac = &hw->mac; 73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 74 75 DEBUGFUNC("ixgbe_init_ops_generic"); 76 77 /* EEPROM */ 78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 80 if (eec & IXGBE_EEC_PRES) { 81 eeprom->ops.read = ixgbe_read_eerd_generic; 82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 83 } else { 84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 85 eeprom->ops.read_buffer = 86 ixgbe_read_eeprom_buffer_bit_bang_generic; 87 } 88 eeprom->ops.write = ixgbe_write_eeprom_generic; 89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 90 eeprom->ops.validate_checksum = 91 ixgbe_validate_eeprom_checksum_generic; 92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 94 eeprom->ops.read_pba_string = ixgbe_read_pba_string_generic; 95 96 /* MAC */ 97 mac->ops.init_hw = ixgbe_init_hw_generic; 98 mac->ops.reset_hw = NULL; 99 mac->ops.start_hw = ixgbe_start_hw_generic; 100 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 101 mac->ops.get_media_type = NULL; 102 mac->ops.get_supported_physical_layer = NULL; 103 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 104 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 105 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 106 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 107 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 108 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 109 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 110 mac->ops.prot_autoc_read = prot_autoc_read_generic; 111 mac->ops.prot_autoc_write = prot_autoc_write_generic; 112 113 /* LEDs */ 114 mac->ops.led_on = ixgbe_led_on_generic; 115 mac->ops.led_off = ixgbe_led_off_generic; 116 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 117 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 118 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 119 120 /* RAR, Multicast, VLAN */ 121 mac->ops.set_rar = ixgbe_set_rar_generic; 122 mac->ops.clear_rar = ixgbe_clear_rar_generic; 123 mac->ops.insert_mac_addr = NULL; 124 mac->ops.set_vmdq = NULL; 125 mac->ops.clear_vmdq = NULL; 126 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 127 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 128 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 129 mac->ops.enable_mc = ixgbe_enable_mc_generic; 130 mac->ops.disable_mc = ixgbe_disable_mc_generic; 131 mac->ops.clear_vfta = NULL; 132 mac->ops.set_vfta = NULL; 133 mac->ops.set_vlvf = NULL; 134 mac->ops.init_uta_tables = NULL; 135 mac->ops.enable_rx = ixgbe_enable_rx_generic; 136 mac->ops.disable_rx = ixgbe_disable_rx_generic; 137 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic; 138 139 /* Flow Control */ 140 mac->ops.fc_enable = ixgbe_fc_enable_generic; 141 mac->ops.setup_fc = ixgbe_setup_fc_generic; 142 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 143 144 /* Link */ 145 mac->ops.get_link_capabilities = NULL; 146 mac->ops.setup_link = NULL; 147 mac->ops.check_link = NULL; 148 mac->ops.dmac_config = NULL; 149 mac->ops.dmac_update_tcs = NULL; 150 mac->ops.dmac_config_tcs = NULL; 151 152 return IXGBE_SUCCESS; 153 } 154 155 /** 156 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 157 * of flow control 158 * @hw: pointer to hardware structure 159 * 160 * This function returns true if the device supports flow control 161 * autonegotiation, and false if it does not. 162 * 163 **/ 164 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 165 { 166 bool supported = false; 167 ixgbe_link_speed speed; 168 bool link_up; 169 170 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 171 172 switch (hw->phy.media_type) { 173 case ixgbe_media_type_fiber_fixed: 174 case ixgbe_media_type_fiber_qsfp: 175 case ixgbe_media_type_fiber: 176 /* flow control autoneg block list */ 177 switch (hw->device_id) { 178 case IXGBE_DEV_ID_X550EM_A_SFP: 179 case IXGBE_DEV_ID_X550EM_A_SFP_N: 180 case IXGBE_DEV_ID_X550EM_A_QSFP: 181 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 182 case IXGBE_DEV_ID_E610_SFP: 183 supported = false; 184 break; 185 default: 186 hw->mac.ops.check_link(hw, &speed, &link_up, false); 187 /* if link is down, assume supported */ 188 if (link_up) 189 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 190 true : false; 191 else 192 supported = true; 193 } 194 195 break; 196 case ixgbe_media_type_backplane: 197 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 198 supported = false; 199 else 200 supported = true; 201 break; 202 case ixgbe_media_type_copper: 203 /* only some copper devices support flow control autoneg */ 204 switch (hw->device_id) { 205 case IXGBE_DEV_ID_82599_T3_LOM: 206 case IXGBE_DEV_ID_X540T: 207 case IXGBE_DEV_ID_X540T1: 208 case IXGBE_DEV_ID_X540_BYPASS: 209 case IXGBE_DEV_ID_X550T: 210 case IXGBE_DEV_ID_X550T1: 211 case IXGBE_DEV_ID_X550EM_X_10G_T: 212 case IXGBE_DEV_ID_X550EM_A_10G_T: 213 case IXGBE_DEV_ID_X550EM_A_1G_T: 214 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 215 case IXGBE_DEV_ID_E610_10G_T: 216 case IXGBE_DEV_ID_E610_2_5G_T: 217 supported = true; 218 break; 219 default: 220 supported = false; 221 } 222 default: 223 break; 224 } 225 226 if (!supported) 227 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 228 "Device %x does not support flow control autoneg", 229 hw->device_id); 230 231 return supported; 232 } 233 234 /** 235 * ixgbe_setup_fc_generic - Set up flow control 236 * @hw: pointer to hardware structure 237 * 238 * Called at init time to set up flow control. 239 **/ 240 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 241 { 242 s32 ret_val = IXGBE_SUCCESS; 243 u32 reg = 0, reg_bp = 0; 244 u16 reg_cu = 0; 245 bool locked = false; 246 247 DEBUGFUNC("ixgbe_setup_fc_generic"); 248 249 /* Validate the requested mode */ 250 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 251 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 252 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 253 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 254 goto out; 255 } 256 257 /* 258 * 10gig parts do not have a word in the EEPROM to determine the 259 * default flow control setting, so we explicitly set it to full. 260 */ 261 if (hw->fc.requested_mode == ixgbe_fc_default) 262 hw->fc.requested_mode = ixgbe_fc_full; 263 264 /* 265 * Set up the 1G and 10G flow control advertisement registers so the 266 * HW will be able to do fc autoneg once the cable is plugged in. If 267 * we link at 10G, the 1G advertisement is harmless and vice versa. 268 */ 269 switch (hw->phy.media_type) { 270 case ixgbe_media_type_backplane: 271 /* some MAC's need RMW protection on AUTOC */ 272 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 273 if (ret_val != IXGBE_SUCCESS) 274 goto out; 275 276 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 277 break; 278 case ixgbe_media_type_fiber_fixed: 279 case ixgbe_media_type_fiber_qsfp: 280 case ixgbe_media_type_fiber: 281 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 282 283 break; 284 case ixgbe_media_type_copper: 285 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 286 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 287 break; 288 default: 289 break; 290 } 291 292 /* 293 * The possible values of fc.requested_mode are: 294 * 0: Flow control is completely disabled 295 * 1: Rx flow control is enabled (we can receive pause frames, 296 * but not send pause frames). 297 * 2: Tx flow control is enabled (we can send pause frames but 298 * we do not support receiving pause frames). 299 * 3: Both Rx and Tx flow control (symmetric) are enabled. 300 * other: Invalid. 301 */ 302 switch (hw->fc.requested_mode) { 303 case ixgbe_fc_none: 304 /* Flow control completely disabled by software override. */ 305 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 306 if (hw->phy.media_type == ixgbe_media_type_backplane) 307 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 308 IXGBE_AUTOC_ASM_PAUSE); 309 else if (hw->phy.media_type == ixgbe_media_type_copper) 310 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 311 break; 312 case ixgbe_fc_tx_pause: 313 /* 314 * Tx Flow control is enabled, and Rx Flow control is 315 * disabled by software override. 316 */ 317 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 318 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 319 if (hw->phy.media_type == ixgbe_media_type_backplane) { 320 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 321 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 322 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 323 reg_cu |= IXGBE_TAF_ASM_PAUSE; 324 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 325 } 326 break; 327 case ixgbe_fc_rx_pause: 328 /* 329 * Rx Flow control is enabled and Tx Flow control is 330 * disabled by software override. Since there really 331 * isn't a way to advertise that we are capable of RX 332 * Pause ONLY, we will advertise that we support both 333 * symmetric and asymmetric Rx PAUSE, as such we fall 334 * through to the fc_full statement. Later, we will 335 * disable the adapter's ability to send PAUSE frames. 336 */ 337 case ixgbe_fc_full: 338 /* Flow control (both Rx and Tx) is enabled by SW override. */ 339 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 340 if (hw->phy.media_type == ixgbe_media_type_backplane) 341 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 342 IXGBE_AUTOC_ASM_PAUSE; 343 else if (hw->phy.media_type == ixgbe_media_type_copper) 344 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 345 break; 346 default: 347 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 348 "Flow control param set incorrectly\n"); 349 ret_val = IXGBE_ERR_CONFIG; 350 goto out; 351 break; 352 } 353 354 if (hw->mac.type < ixgbe_mac_X540) { 355 /* 356 * Enable auto-negotiation between the MAC & PHY; 357 * the MAC will advertise clause 37 flow control. 358 */ 359 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 360 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 361 362 /* Disable AN timeout */ 363 if (hw->fc.strict_ieee) 364 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 365 366 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 367 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 368 } 369 370 /* 371 * AUTOC restart handles negotiation of 1G and 10G on backplane 372 * and copper. There is no need to set the PCS1GCTL register. 373 * 374 */ 375 if (hw->phy.media_type == ixgbe_media_type_backplane) { 376 reg_bp |= IXGBE_AUTOC_AN_RESTART; 377 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 378 if (ret_val) 379 goto out; 380 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 381 (ixgbe_device_supports_autoneg_fc(hw))) { 382 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 383 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 384 } 385 386 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 387 out: 388 return ret_val; 389 } 390 391 /** 392 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 393 * @hw: pointer to hardware structure 394 * 395 * Starts the hardware by filling the bus info structure and media type, clears 396 * all on chip counters, initializes receive address registers, multicast 397 * table, VLAN filter table, calls routine to set up link and flow control 398 * settings, and leaves transmit and receive units disabled and uninitialized 399 **/ 400 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 401 { 402 s32 ret_val; 403 u32 ctrl_ext; 404 u16 device_caps; 405 406 DEBUGFUNC("ixgbe_start_hw_generic"); 407 408 /* Set the media type */ 409 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 410 411 /* PHY ops initialization must be done in reset_hw() */ 412 413 /* Clear the VLAN filter table */ 414 hw->mac.ops.clear_vfta(hw); 415 416 /* Clear statistics registers */ 417 hw->mac.ops.clear_hw_cntrs(hw); 418 419 /* Set No Snoop Disable */ 420 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 421 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 422 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 423 IXGBE_WRITE_FLUSH(hw); 424 425 /* Setup flow control */ 426 ret_val = ixgbe_setup_fc(hw); 427 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 428 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 429 return ret_val; 430 } 431 432 /* Cache bit indicating need for crosstalk fix */ 433 switch (hw->mac.type) { 434 case ixgbe_mac_82599EB: 435 case ixgbe_mac_X550EM_x: 436 case ixgbe_mac_X550EM_a: 437 hw->mac.ops.get_device_caps(hw, &device_caps); 438 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 439 hw->need_crosstalk_fix = false; 440 else 441 hw->need_crosstalk_fix = true; 442 break; 443 default: 444 hw->need_crosstalk_fix = false; 445 break; 446 } 447 448 /* Clear adapter stopped flag */ 449 hw->adapter_stopped = false; 450 451 return IXGBE_SUCCESS; 452 } 453 454 /** 455 * ixgbe_start_hw_gen2 - Init sequence for common device family 456 * @hw: pointer to hw structure 457 * 458 * Performs the init sequence common to the second generation 459 * of 10 GbE devices. 460 * Devices in the second generation: 461 * 82599 462 * X540 463 **/ 464 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 465 { 466 u32 i; 467 u32 regval; 468 469 /* Clear the rate limiters */ 470 for (i = 0; i < hw->mac.max_tx_queues; i++) { 471 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 472 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 473 } 474 IXGBE_WRITE_FLUSH(hw); 475 476 /* Disable relaxed ordering */ 477 for (i = 0; i < hw->mac.max_tx_queues; i++) { 478 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 479 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 480 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 481 } 482 483 for (i = 0; i < hw->mac.max_rx_queues; i++) { 484 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 485 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 486 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 487 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 488 } 489 } 490 491 /** 492 * ixgbe_init_hw_generic - Generic hardware initialization 493 * @hw: pointer to hardware structure 494 * 495 * Initialize the hardware by resetting the hardware, filling the bus info 496 * structure and media type, clears all on chip counters, initializes receive 497 * address registers, multicast table, VLAN filter table, calls routine to set 498 * up link and flow control settings, and leaves transmit and receive units 499 * disabled and uninitialized 500 **/ 501 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 502 { 503 s32 status; 504 505 DEBUGFUNC("ixgbe_init_hw_generic"); 506 507 /* Reset the hardware */ 508 status = hw->mac.ops.reset_hw(hw); 509 510 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 511 /* Start the HW */ 512 status = hw->mac.ops.start_hw(hw); 513 } 514 515 /* Initialize the LED link active for LED blink support */ 516 if (hw->mac.ops.init_led_link_act) 517 hw->mac.ops.init_led_link_act(hw); 518 519 if (status != IXGBE_SUCCESS) 520 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 521 522 return status; 523 } 524 525 /** 526 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 527 * @hw: pointer to hardware structure 528 * 529 * Clears all hardware statistics counters by reading them from the hardware 530 * Statistics counters are clear on read. 531 **/ 532 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 533 { 534 u16 i = 0; 535 536 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 537 538 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 539 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 540 IXGBE_READ_REG(hw, IXGBE_ERRBC); 541 IXGBE_READ_REG(hw, IXGBE_MSPDC); 542 for (i = 0; i < 8; i++) 543 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 544 545 IXGBE_READ_REG(hw, IXGBE_MLFC); 546 IXGBE_READ_REG(hw, IXGBE_MRFC); 547 IXGBE_READ_REG(hw, IXGBE_RLEC); 548 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 549 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 550 if (hw->mac.type >= ixgbe_mac_82599EB) { 551 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 552 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 553 } else { 554 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 555 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 556 } 557 558 for (i = 0; i < 8; i++) { 559 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 560 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 561 if (hw->mac.type >= ixgbe_mac_82599EB) { 562 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 563 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 564 } else { 565 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 566 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 567 } 568 } 569 if (hw->mac.type >= ixgbe_mac_82599EB) 570 for (i = 0; i < 8; i++) 571 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 572 IXGBE_READ_REG(hw, IXGBE_PRC64); 573 IXGBE_READ_REG(hw, IXGBE_PRC127); 574 IXGBE_READ_REG(hw, IXGBE_PRC255); 575 IXGBE_READ_REG(hw, IXGBE_PRC511); 576 IXGBE_READ_REG(hw, IXGBE_PRC1023); 577 IXGBE_READ_REG(hw, IXGBE_PRC1522); 578 IXGBE_READ_REG(hw, IXGBE_GPRC); 579 IXGBE_READ_REG(hw, IXGBE_BPRC); 580 IXGBE_READ_REG(hw, IXGBE_MPRC); 581 IXGBE_READ_REG(hw, IXGBE_GPTC); 582 IXGBE_READ_REG(hw, IXGBE_GORCL); 583 IXGBE_READ_REG(hw, IXGBE_GORCH); 584 IXGBE_READ_REG(hw, IXGBE_GOTCL); 585 IXGBE_READ_REG(hw, IXGBE_GOTCH); 586 if (hw->mac.type == ixgbe_mac_82598EB) 587 for (i = 0; i < 8; i++) 588 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 589 IXGBE_READ_REG(hw, IXGBE_RUC); 590 IXGBE_READ_REG(hw, IXGBE_RFC); 591 IXGBE_READ_REG(hw, IXGBE_ROC); 592 IXGBE_READ_REG(hw, IXGBE_RJC); 593 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 594 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 595 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 596 IXGBE_READ_REG(hw, IXGBE_TORL); 597 IXGBE_READ_REG(hw, IXGBE_TORH); 598 IXGBE_READ_REG(hw, IXGBE_TPR); 599 IXGBE_READ_REG(hw, IXGBE_TPT); 600 IXGBE_READ_REG(hw, IXGBE_PTC64); 601 IXGBE_READ_REG(hw, IXGBE_PTC127); 602 IXGBE_READ_REG(hw, IXGBE_PTC255); 603 IXGBE_READ_REG(hw, IXGBE_PTC511); 604 IXGBE_READ_REG(hw, IXGBE_PTC1023); 605 IXGBE_READ_REG(hw, IXGBE_PTC1522); 606 IXGBE_READ_REG(hw, IXGBE_MPTC); 607 IXGBE_READ_REG(hw, IXGBE_BPTC); 608 for (i = 0; i < 16; i++) { 609 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 610 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 611 if (hw->mac.type >= ixgbe_mac_82599EB) { 612 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 613 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 614 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 615 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 616 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 617 } else { 618 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 619 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 620 } 621 } 622 623 if (hw->mac.type == ixgbe_mac_X540 || 624 hw->mac.type == ixgbe_mac_X550) { 625 if (hw->phy.id == 0) 626 ixgbe_identify_phy(hw); 627 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 628 IXGBE_MDIO_PCS_DEV_TYPE, &i); 629 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 630 IXGBE_MDIO_PCS_DEV_TYPE, &i); 631 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 632 IXGBE_MDIO_PCS_DEV_TYPE, &i); 633 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 634 IXGBE_MDIO_PCS_DEV_TYPE, &i); 635 } 636 637 return IXGBE_SUCCESS; 638 } 639 640 /** 641 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 642 * @hw: pointer to hardware structure 643 * @pba_num: stores the part number string from the EEPROM 644 * @pba_num_size: part number string buffer length 645 * 646 * Reads the part number string from the EEPROM. 647 **/ 648 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 649 u32 pba_num_size) 650 { 651 s32 ret_val; 652 u16 data; 653 u16 pba_ptr; 654 u16 offset; 655 u16 length; 656 657 DEBUGFUNC("ixgbe_read_pba_string_generic"); 658 659 if (pba_num == NULL) { 660 DEBUGOUT("PBA string buffer was null\n"); 661 return IXGBE_ERR_INVALID_ARGUMENT; 662 } 663 664 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 665 if (ret_val) { 666 DEBUGOUT("NVM Read Error\n"); 667 return ret_val; 668 } 669 670 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 671 if (ret_val) { 672 DEBUGOUT("NVM Read Error\n"); 673 return ret_val; 674 } 675 676 /* 677 * if data is not ptr guard the PBA must be in legacy format which 678 * means pba_ptr is actually our second data word for the PBA number 679 * and we can decode it into an ascii string 680 */ 681 if (data != IXGBE_PBANUM_PTR_GUARD) { 682 DEBUGOUT("NVM PBA number is not stored as string\n"); 683 684 /* we will need 11 characters to store the PBA */ 685 if (pba_num_size < 11) { 686 DEBUGOUT("PBA string buffer too small\n"); 687 return IXGBE_ERR_NO_SPACE; 688 } 689 690 /* extract hex string from data and pba_ptr */ 691 pba_num[0] = (data >> 12) & 0xF; 692 pba_num[1] = (data >> 8) & 0xF; 693 pba_num[2] = (data >> 4) & 0xF; 694 pba_num[3] = data & 0xF; 695 pba_num[4] = (pba_ptr >> 12) & 0xF; 696 pba_num[5] = (pba_ptr >> 8) & 0xF; 697 pba_num[6] = '-'; 698 pba_num[7] = 0; 699 pba_num[8] = (pba_ptr >> 4) & 0xF; 700 pba_num[9] = pba_ptr & 0xF; 701 702 /* put a null character on the end of our string */ 703 pba_num[10] = '\0'; 704 705 /* switch all the data but the '-' to hex char */ 706 for (offset = 0; offset < 10; offset++) { 707 if (pba_num[offset] < 0xA) 708 pba_num[offset] += '0'; 709 else if (pba_num[offset] < 0x10) 710 pba_num[offset] += 'A' - 0xA; 711 } 712 713 return IXGBE_SUCCESS; 714 } 715 716 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 717 if (ret_val) { 718 DEBUGOUT("NVM Read Error\n"); 719 return ret_val; 720 } 721 722 if (length == 0xFFFF || length == 0 || length > hw->eeprom.word_size) { 723 DEBUGOUT("NVM PBA number section invalid length\n"); 724 return IXGBE_ERR_PBA_SECTION; 725 } 726 727 /* check if pba_num buffer is big enough */ 728 if (pba_num_size < (((u32)length * 2) - 1)) { 729 DEBUGOUT("PBA string buffer too small\n"); 730 return IXGBE_ERR_NO_SPACE; 731 } 732 733 /* trim pba length from start of string */ 734 pba_ptr++; 735 length--; 736 737 for (offset = 0; offset < length; offset++) { 738 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 739 if (ret_val) { 740 DEBUGOUT("NVM Read Error\n"); 741 return ret_val; 742 } 743 pba_num[offset * 2] = (u8)(data >> 8); 744 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 745 } 746 pba_num[offset * 2] = '\0'; 747 748 return IXGBE_SUCCESS; 749 } 750 751 /** 752 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 753 * @hw: pointer to hardware structure 754 * @pba_num: stores the part number from the EEPROM 755 * 756 * Reads the part number from the EEPROM. 757 **/ 758 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 759 { 760 s32 ret_val; 761 u16 data; 762 763 DEBUGFUNC("ixgbe_read_pba_num_generic"); 764 765 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 766 if (ret_val) { 767 DEBUGOUT("NVM Read Error\n"); 768 return ret_val; 769 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 770 DEBUGOUT("NVM Not supported\n"); 771 return IXGBE_NOT_IMPLEMENTED; 772 } 773 *pba_num = (u32)data << 16; 774 775 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 776 if (ret_val) { 777 DEBUGOUT("NVM Read Error\n"); 778 return ret_val; 779 } 780 *pba_num |= (u32)data; 781 782 return IXGBE_SUCCESS; 783 } 784 785 /** 786 * ixgbe_read_pba_raw 787 * @hw: pointer to the HW structure 788 * @eeprom_buf: optional pointer to EEPROM image 789 * @eeprom_buf_size: size of EEPROM image in words 790 * @max_pba_block_size: PBA block size limit 791 * @pba: pointer to output PBA structure 792 * 793 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 794 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 795 * 796 **/ 797 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 798 u32 eeprom_buf_size, u16 max_pba_block_size, 799 struct ixgbe_pba *pba) 800 { 801 s32 ret_val; 802 u16 pba_block_size; 803 804 if (pba == NULL) 805 return IXGBE_ERR_PARAM; 806 807 if (eeprom_buf == NULL) { 808 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 809 &pba->word[0]); 810 if (ret_val) 811 return ret_val; 812 } else { 813 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 814 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 815 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 816 } else { 817 return IXGBE_ERR_PARAM; 818 } 819 } 820 821 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 822 if (pba->pba_block == NULL) 823 return IXGBE_ERR_PARAM; 824 825 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 826 eeprom_buf_size, 827 &pba_block_size); 828 if (ret_val) 829 return ret_val; 830 831 if (pba_block_size > max_pba_block_size) 832 return IXGBE_ERR_PARAM; 833 834 if (eeprom_buf == NULL) { 835 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 836 pba_block_size, 837 pba->pba_block); 838 if (ret_val) 839 return ret_val; 840 } else { 841 if (eeprom_buf_size > (u32)(pba->word[1] + 842 pba_block_size)) { 843 memcpy(pba->pba_block, 844 &eeprom_buf[pba->word[1]], 845 pba_block_size * sizeof(u16)); 846 } else { 847 return IXGBE_ERR_PARAM; 848 } 849 } 850 } 851 852 return IXGBE_SUCCESS; 853 } 854 855 /** 856 * ixgbe_write_pba_raw 857 * @hw: pointer to the HW structure 858 * @eeprom_buf: optional pointer to EEPROM image 859 * @eeprom_buf_size: size of EEPROM image in words 860 * @pba: pointer to PBA structure 861 * 862 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 863 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 864 * 865 **/ 866 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 867 u32 eeprom_buf_size, struct ixgbe_pba *pba) 868 { 869 s32 ret_val; 870 871 if (pba == NULL) 872 return IXGBE_ERR_PARAM; 873 874 if (eeprom_buf == NULL) { 875 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 876 &pba->word[0]); 877 if (ret_val) 878 return ret_val; 879 } else { 880 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 881 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 882 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 883 } else { 884 return IXGBE_ERR_PARAM; 885 } 886 } 887 888 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 889 if (pba->pba_block == NULL) 890 return IXGBE_ERR_PARAM; 891 892 if (eeprom_buf == NULL) { 893 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 894 pba->pba_block[0], 895 pba->pba_block); 896 if (ret_val) 897 return ret_val; 898 } else { 899 if (eeprom_buf_size > (u32)(pba->word[1] + 900 pba->pba_block[0])) { 901 memcpy(&eeprom_buf[pba->word[1]], 902 pba->pba_block, 903 pba->pba_block[0] * sizeof(u16)); 904 } else { 905 return IXGBE_ERR_PARAM; 906 } 907 } 908 } 909 910 return IXGBE_SUCCESS; 911 } 912 913 /** 914 * ixgbe_get_pba_block_size 915 * @hw: pointer to the HW structure 916 * @eeprom_buf: optional pointer to EEPROM image 917 * @eeprom_buf_size: size of EEPROM image in words 918 * @pba_data_size: pointer to output variable 919 * 920 * Returns the size of the PBA block in words. Function operates on EEPROM 921 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 922 * EEPROM device. 923 * 924 **/ 925 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 926 u32 eeprom_buf_size, u16 *pba_block_size) 927 { 928 s32 ret_val; 929 u16 pba_word[2]; 930 u16 length; 931 932 DEBUGFUNC("ixgbe_get_pba_block_size"); 933 934 if (eeprom_buf == NULL) { 935 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 936 &pba_word[0]); 937 if (ret_val) 938 return ret_val; 939 } else { 940 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 941 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 942 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 943 } else { 944 return IXGBE_ERR_PARAM; 945 } 946 } 947 948 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 949 if (eeprom_buf == NULL) { 950 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 951 &length); 952 if (ret_val) 953 return ret_val; 954 } else { 955 if (eeprom_buf_size > pba_word[1]) 956 length = eeprom_buf[pba_word[1] + 0]; 957 else 958 return IXGBE_ERR_PARAM; 959 } 960 961 if (length == 0xFFFF || length == 0) 962 return IXGBE_ERR_PBA_SECTION; 963 } else { 964 /* PBA number in legacy format, there is no PBA Block. */ 965 length = 0; 966 } 967 968 if (pba_block_size != NULL) 969 *pba_block_size = length; 970 971 return IXGBE_SUCCESS; 972 } 973 974 /** 975 * ixgbe_get_mac_addr_generic - Generic get MAC address 976 * @hw: pointer to hardware structure 977 * @mac_addr: Adapter MAC address 978 * 979 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 980 * A reset of the adapter must be performed prior to calling this function 981 * in order for the MAC address to have been loaded from the EEPROM into RAR0 982 **/ 983 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 984 { 985 u32 rar_high; 986 u32 rar_low; 987 u16 i; 988 989 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 990 991 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 992 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 993 994 for (i = 0; i < 4; i++) 995 mac_addr[i] = (u8)(rar_low >> (i*8)); 996 997 for (i = 0; i < 2; i++) 998 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 999 1000 return IXGBE_SUCCESS; 1001 } 1002 1003 /** 1004 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 1005 * @hw: pointer to hardware structure 1006 * @link_status: the link status returned by the PCI config space 1007 * 1008 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1009 **/ 1010 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1011 { 1012 struct ixgbe_mac_info *mac = &hw->mac; 1013 1014 if (hw->bus.type == ixgbe_bus_type_unknown) 1015 hw->bus.type = ixgbe_bus_type_pci_express; 1016 1017 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1018 case IXGBE_PCI_LINK_WIDTH_1: 1019 hw->bus.width = ixgbe_bus_width_pcie_x1; 1020 break; 1021 case IXGBE_PCI_LINK_WIDTH_2: 1022 hw->bus.width = ixgbe_bus_width_pcie_x2; 1023 break; 1024 case IXGBE_PCI_LINK_WIDTH_4: 1025 hw->bus.width = ixgbe_bus_width_pcie_x4; 1026 break; 1027 case IXGBE_PCI_LINK_WIDTH_8: 1028 hw->bus.width = ixgbe_bus_width_pcie_x8; 1029 break; 1030 default: 1031 hw->bus.width = ixgbe_bus_width_unknown; 1032 break; 1033 } 1034 1035 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1036 case IXGBE_PCI_LINK_SPEED_2500: 1037 hw->bus.speed = ixgbe_bus_speed_2500; 1038 break; 1039 case IXGBE_PCI_LINK_SPEED_5000: 1040 hw->bus.speed = ixgbe_bus_speed_5000; 1041 break; 1042 case IXGBE_PCI_LINK_SPEED_8000: 1043 hw->bus.speed = ixgbe_bus_speed_8000; 1044 break; 1045 case IXGBE_PCI_LINK_SPEED_16000: 1046 hw->bus.speed = ixgbe_bus_speed_16000; 1047 break; 1048 default: 1049 hw->bus.speed = ixgbe_bus_speed_unknown; 1050 break; 1051 } 1052 1053 mac->ops.set_lan_id(hw); 1054 } 1055 1056 /** 1057 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1058 * @hw: pointer to hardware structure 1059 * 1060 * Gets the PCI bus info (speed, width, type) then calls helper function to 1061 * store this data within the ixgbe_hw structure. 1062 **/ 1063 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1064 { 1065 u16 link_status; 1066 1067 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1068 1069 /* Get the negotiated link width and speed from PCI config space */ 1070 link_status = IXGBE_READ_PCIE_WORD(hw, hw->mac.type == ixgbe_mac_E610 ? 1071 IXGBE_PCI_LINK_STATUS_E610 : 1072 IXGBE_PCI_LINK_STATUS); 1073 1074 ixgbe_set_pci_config_data_generic(hw, link_status); 1075 1076 return IXGBE_SUCCESS; 1077 } 1078 1079 /** 1080 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1081 * @hw: pointer to the HW structure 1082 * 1083 * Determines the LAN function id by reading memory-mapped registers and swaps 1084 * the port value if requested, and set MAC instance for devices that share 1085 * CS4227. 1086 **/ 1087 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1088 { 1089 struct ixgbe_bus_info *bus = &hw->bus; 1090 u32 reg; 1091 u16 ee_ctrl_4; 1092 1093 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1094 1095 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1096 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1097 bus->lan_id = (u8)bus->func; 1098 1099 /* check for a port swap */ 1100 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1101 if (reg & IXGBE_FACTPS_LFS) 1102 bus->func ^= 0x1; 1103 1104 /* Get MAC instance from EEPROM for configuring CS4227 */ 1105 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1106 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1107 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1108 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1109 } 1110 } 1111 1112 /** 1113 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1114 * @hw: pointer to hardware structure 1115 * 1116 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1117 * disables transmit and receive units. The adapter_stopped flag is used by 1118 * the shared code and drivers to determine if the adapter is in a stopped 1119 * state and should not touch the hardware. 1120 **/ 1121 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1122 { 1123 u32 reg_val; 1124 u16 i; 1125 1126 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1127 1128 /* 1129 * Set the adapter_stopped flag so other driver functions stop touching 1130 * the hardware 1131 */ 1132 hw->adapter_stopped = true; 1133 1134 /* Disable the receive unit */ 1135 ixgbe_disable_rx(hw); 1136 1137 /* Clear interrupt mask to stop interrupts from being generated */ 1138 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1139 1140 /* Clear any pending interrupts, flush previous writes */ 1141 IXGBE_READ_REG(hw, IXGBE_EICR); 1142 1143 /* Disable the transmit unit. Each queue must be disabled. */ 1144 for (i = 0; i < hw->mac.max_tx_queues; i++) 1145 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1146 1147 /* Disable the receive unit by stopping each queue */ 1148 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1149 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1150 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1151 reg_val |= IXGBE_RXDCTL_SWFLSH; 1152 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1153 } 1154 1155 /* flush all queues disables */ 1156 IXGBE_WRITE_FLUSH(hw); 1157 msec_delay(2); 1158 1159 /* 1160 * Prevent the PCI-E bus from hanging by disabling PCI-E primary 1161 * access and verify no pending requests 1162 */ 1163 return ixgbe_disable_pcie_primary(hw); 1164 } 1165 1166 /** 1167 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1168 * @hw: pointer to hardware structure 1169 * 1170 * Store the index for the link active LED. This will be used to support 1171 * blinking the LED. 1172 **/ 1173 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1174 { 1175 struct ixgbe_mac_info *mac = &hw->mac; 1176 u32 led_reg, led_mode; 1177 u8 i; 1178 1179 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1180 1181 /* Get LED link active from the LEDCTL register */ 1182 for (i = 0; i < 4; i++) { 1183 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1184 1185 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1186 IXGBE_LED_LINK_ACTIVE) { 1187 mac->led_link_act = i; 1188 return IXGBE_SUCCESS; 1189 } 1190 } 1191 1192 /* 1193 * If LEDCTL register does not have the LED link active set, then use 1194 * known MAC defaults. 1195 */ 1196 switch (hw->mac.type) { 1197 case ixgbe_mac_X550EM_a: 1198 case ixgbe_mac_X550EM_x: 1199 mac->led_link_act = 1; 1200 break; 1201 default: 1202 mac->led_link_act = 2; 1203 } 1204 return IXGBE_SUCCESS; 1205 } 1206 1207 /** 1208 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1209 * @hw: pointer to hardware structure 1210 * @index: led number to turn on 1211 **/ 1212 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1213 { 1214 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1215 1216 DEBUGFUNC("ixgbe_led_on_generic"); 1217 1218 if (index > 3) 1219 return IXGBE_ERR_PARAM; 1220 1221 /* To turn on the LED, set mode to ON. */ 1222 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1223 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1224 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1225 IXGBE_WRITE_FLUSH(hw); 1226 1227 return IXGBE_SUCCESS; 1228 } 1229 1230 /** 1231 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1232 * @hw: pointer to hardware structure 1233 * @index: led number to turn off 1234 **/ 1235 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1236 { 1237 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1238 1239 DEBUGFUNC("ixgbe_led_off_generic"); 1240 1241 if (index > 3) 1242 return IXGBE_ERR_PARAM; 1243 1244 /* To turn off the LED, set mode to OFF. */ 1245 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1246 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1247 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1248 IXGBE_WRITE_FLUSH(hw); 1249 1250 return IXGBE_SUCCESS; 1251 } 1252 1253 /** 1254 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1255 * @hw: pointer to hardware structure 1256 * 1257 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1258 * ixgbe_hw struct in order to set up EEPROM access. 1259 **/ 1260 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1261 { 1262 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1263 u32 eec; 1264 u16 eeprom_size; 1265 1266 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1267 1268 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1269 eeprom->type = ixgbe_eeprom_none; 1270 /* Set default semaphore delay to 10ms which is a well 1271 * tested value */ 1272 eeprom->semaphore_delay = 10; 1273 /* Clear EEPROM page size, it will be initialized as needed */ 1274 eeprom->word_page_size = 0; 1275 1276 /* 1277 * Check for EEPROM present first. 1278 * If not present leave as none 1279 */ 1280 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1281 if (eec & IXGBE_EEC_PRES) { 1282 eeprom->type = ixgbe_eeprom_spi; 1283 1284 /* 1285 * SPI EEPROM is assumed here. This code would need to 1286 * change if a future EEPROM is not SPI. 1287 */ 1288 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1289 IXGBE_EEC_SIZE_SHIFT); 1290 eeprom->word_size = 1 << (eeprom_size + 1291 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1292 } 1293 1294 if (eec & IXGBE_EEC_ADDR_SIZE) 1295 eeprom->address_bits = 16; 1296 else 1297 eeprom->address_bits = 8; 1298 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1299 "%d\n", eeprom->type, eeprom->word_size, 1300 eeprom->address_bits); 1301 } 1302 1303 return IXGBE_SUCCESS; 1304 } 1305 1306 /** 1307 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1308 * @hw: pointer to hardware structure 1309 * @offset: offset within the EEPROM to write 1310 * @words: number of word(s) 1311 * @data: 16 bit word(s) to write to EEPROM 1312 * 1313 * Reads 16 bit word(s) from EEPROM through bit-bang method 1314 **/ 1315 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1316 u16 words, u16 *data) 1317 { 1318 s32 status = IXGBE_SUCCESS; 1319 u16 i, count; 1320 1321 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1322 1323 hw->eeprom.ops.init_params(hw); 1324 1325 if (words == 0) { 1326 status = IXGBE_ERR_INVALID_ARGUMENT; 1327 goto out; 1328 } 1329 1330 if (offset + words > hw->eeprom.word_size) { 1331 status = IXGBE_ERR_EEPROM; 1332 goto out; 1333 } 1334 1335 /* 1336 * The EEPROM page size cannot be queried from the chip. We do lazy 1337 * initialization. It is worth to do that when we write large buffer. 1338 */ 1339 if ((hw->eeprom.word_page_size == 0) && 1340 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1341 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1342 1343 /* 1344 * We cannot hold synchronization semaphores for too long 1345 * to avoid other entity starvation. However it is more efficient 1346 * to read in bursts than synchronizing access for each word. 1347 */ 1348 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1349 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1350 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1351 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1352 count, &data[i]); 1353 1354 if (status != IXGBE_SUCCESS) 1355 break; 1356 } 1357 1358 out: 1359 return status; 1360 } 1361 1362 /** 1363 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1364 * @hw: pointer to hardware structure 1365 * @offset: offset within the EEPROM to be written to 1366 * @words: number of word(s) 1367 * @data: 16 bit word(s) to be written to the EEPROM 1368 * 1369 * If ixgbe_eeprom_update_checksum is not called after this function, the 1370 * EEPROM will most likely contain an invalid checksum. 1371 **/ 1372 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1373 u16 words, u16 *data) 1374 { 1375 s32 status; 1376 u16 word; 1377 u16 page_size; 1378 u16 i; 1379 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1380 1381 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1382 1383 /* Prepare the EEPROM for writing */ 1384 status = ixgbe_acquire_eeprom(hw); 1385 1386 if (status == IXGBE_SUCCESS) { 1387 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1388 ixgbe_release_eeprom(hw); 1389 status = IXGBE_ERR_EEPROM; 1390 } 1391 } 1392 1393 if (status == IXGBE_SUCCESS) { 1394 for (i = 0; i < words; i++) { 1395 ixgbe_standby_eeprom(hw); 1396 1397 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1398 ixgbe_shift_out_eeprom_bits(hw, 1399 IXGBE_EEPROM_WREN_OPCODE_SPI, 1400 IXGBE_EEPROM_OPCODE_BITS); 1401 1402 ixgbe_standby_eeprom(hw); 1403 1404 /* 1405 * Some SPI eeproms use the 8th address bit embedded 1406 * in the opcode 1407 */ 1408 if ((hw->eeprom.address_bits == 8) && 1409 ((offset + i) >= 128)) 1410 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1411 1412 /* Send the Write command (8-bit opcode + addr) */ 1413 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1414 IXGBE_EEPROM_OPCODE_BITS); 1415 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1416 hw->eeprom.address_bits); 1417 1418 page_size = hw->eeprom.word_page_size; 1419 1420 /* Send the data in burst via SPI*/ 1421 do { 1422 word = data[i]; 1423 word = (word >> 8) | (word << 8); 1424 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1425 1426 if (page_size == 0) 1427 break; 1428 1429 /* do not wrap around page */ 1430 if (((offset + i) & (page_size - 1)) == 1431 (page_size - 1)) 1432 break; 1433 } while (++i < words); 1434 1435 ixgbe_standby_eeprom(hw); 1436 msec_delay(10); 1437 } 1438 /* Done with writing - release the EEPROM */ 1439 ixgbe_release_eeprom(hw); 1440 } 1441 1442 return status; 1443 } 1444 1445 /** 1446 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1447 * @hw: pointer to hardware structure 1448 * @offset: offset within the EEPROM to be written to 1449 * @data: 16 bit word to be written to the EEPROM 1450 * 1451 * If ixgbe_eeprom_update_checksum is not called after this function, the 1452 * EEPROM will most likely contain an invalid checksum. 1453 **/ 1454 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1455 { 1456 s32 status; 1457 1458 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1459 1460 hw->eeprom.ops.init_params(hw); 1461 1462 if (offset >= hw->eeprom.word_size) { 1463 status = IXGBE_ERR_EEPROM; 1464 goto out; 1465 } 1466 1467 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1468 1469 out: 1470 return status; 1471 } 1472 1473 /** 1474 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1475 * @hw: pointer to hardware structure 1476 * @offset: offset within the EEPROM to be read 1477 * @data: read 16 bit words(s) from EEPROM 1478 * @words: number of word(s) 1479 * 1480 * Reads 16 bit word(s) from EEPROM through bit-bang method 1481 **/ 1482 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1483 u16 words, u16 *data) 1484 { 1485 s32 status = IXGBE_SUCCESS; 1486 u16 i, count; 1487 1488 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1489 1490 hw->eeprom.ops.init_params(hw); 1491 1492 if (words == 0) { 1493 status = IXGBE_ERR_INVALID_ARGUMENT; 1494 goto out; 1495 } 1496 1497 if (offset + words > hw->eeprom.word_size) { 1498 status = IXGBE_ERR_EEPROM; 1499 goto out; 1500 } 1501 1502 /* 1503 * We cannot hold synchronization semaphores for too long 1504 * to avoid other entity starvation. However it is more efficient 1505 * to read in bursts than synchronizing access for each word. 1506 */ 1507 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1508 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1509 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1510 1511 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1512 count, &data[i]); 1513 1514 if (status != IXGBE_SUCCESS) 1515 break; 1516 } 1517 1518 out: 1519 return status; 1520 } 1521 1522 /** 1523 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1524 * @hw: pointer to hardware structure 1525 * @offset: offset within the EEPROM to be read 1526 * @words: number of word(s) 1527 * @data: read 16 bit word(s) from EEPROM 1528 * 1529 * Reads 16 bit word(s) from EEPROM through bit-bang method 1530 **/ 1531 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1532 u16 words, u16 *data) 1533 { 1534 s32 status; 1535 u16 word_in; 1536 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1537 u16 i; 1538 1539 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1540 1541 /* Prepare the EEPROM for reading */ 1542 status = ixgbe_acquire_eeprom(hw); 1543 1544 if (status == IXGBE_SUCCESS) { 1545 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1546 ixgbe_release_eeprom(hw); 1547 status = IXGBE_ERR_EEPROM; 1548 } 1549 } 1550 1551 if (status == IXGBE_SUCCESS) { 1552 for (i = 0; i < words; i++) { 1553 ixgbe_standby_eeprom(hw); 1554 /* 1555 * Some SPI eeproms use the 8th address bit embedded 1556 * in the opcode 1557 */ 1558 if ((hw->eeprom.address_bits == 8) && 1559 ((offset + i) >= 128)) 1560 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1561 1562 /* Send the READ command (opcode + addr) */ 1563 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1564 IXGBE_EEPROM_OPCODE_BITS); 1565 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1566 hw->eeprom.address_bits); 1567 1568 /* Read the data. */ 1569 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1570 data[i] = (word_in >> 8) | (word_in << 8); 1571 } 1572 1573 /* End this read operation */ 1574 ixgbe_release_eeprom(hw); 1575 } 1576 1577 return status; 1578 } 1579 1580 /** 1581 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1582 * @hw: pointer to hardware structure 1583 * @offset: offset within the EEPROM to be read 1584 * @data: read 16 bit value from EEPROM 1585 * 1586 * Reads 16 bit value from EEPROM through bit-bang method 1587 **/ 1588 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1589 u16 *data) 1590 { 1591 s32 status; 1592 1593 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1594 1595 hw->eeprom.ops.init_params(hw); 1596 1597 if (offset >= hw->eeprom.word_size) { 1598 status = IXGBE_ERR_EEPROM; 1599 goto out; 1600 } 1601 1602 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1603 1604 out: 1605 return status; 1606 } 1607 1608 /** 1609 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1610 * @hw: pointer to hardware structure 1611 * @offset: offset of word in the EEPROM to read 1612 * @words: number of word(s) 1613 * @data: 16 bit word(s) from the EEPROM 1614 * 1615 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1616 **/ 1617 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1618 u16 words, u16 *data) 1619 { 1620 u32 eerd; 1621 s32 status = IXGBE_SUCCESS; 1622 u32 i; 1623 1624 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1625 1626 hw->eeprom.ops.init_params(hw); 1627 1628 if (words == 0) { 1629 status = IXGBE_ERR_INVALID_ARGUMENT; 1630 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1631 goto out; 1632 } 1633 1634 if (offset >= hw->eeprom.word_size) { 1635 status = IXGBE_ERR_EEPROM; 1636 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1637 goto out; 1638 } 1639 1640 for (i = 0; i < words; i++) { 1641 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1642 IXGBE_EEPROM_RW_REG_START; 1643 1644 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1645 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1646 1647 if (status == IXGBE_SUCCESS) { 1648 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1649 IXGBE_EEPROM_RW_REG_DATA); 1650 } else { 1651 DEBUGOUT("Eeprom read timed out\n"); 1652 goto out; 1653 } 1654 } 1655 out: 1656 return status; 1657 } 1658 1659 /** 1660 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1661 * @hw: pointer to hardware structure 1662 * @offset: offset within the EEPROM to be used as a scratch pad 1663 * 1664 * Discover EEPROM page size by writing marching data at given offset. 1665 * This function is called only when we are writing a new large buffer 1666 * at given offset so the data would be overwritten anyway. 1667 **/ 1668 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1669 u16 offset) 1670 { 1671 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1672 s32 status = IXGBE_SUCCESS; 1673 u16 i; 1674 1675 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1676 1677 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1678 data[i] = i; 1679 1680 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1681 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1682 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1683 hw->eeprom.word_page_size = 0; 1684 if (status != IXGBE_SUCCESS) 1685 goto out; 1686 1687 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1688 if (status != IXGBE_SUCCESS) 1689 goto out; 1690 1691 /* 1692 * When writing in burst more than the actual page size 1693 * EEPROM address wraps around current page. 1694 */ 1695 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1696 1697 DEBUGOUT1("Detected EEPROM page size = %d words.", 1698 hw->eeprom.word_page_size); 1699 out: 1700 return status; 1701 } 1702 1703 /** 1704 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1705 * @hw: pointer to hardware structure 1706 * @offset: offset of word in the EEPROM to read 1707 * @data: word read from the EEPROM 1708 * 1709 * Reads a 16 bit word from the EEPROM using the EERD register. 1710 **/ 1711 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1712 { 1713 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1714 } 1715 1716 /** 1717 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1718 * @hw: pointer to hardware structure 1719 * @offset: offset of word in the EEPROM to write 1720 * @words: number of word(s) 1721 * @data: word(s) write to the EEPROM 1722 * 1723 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1724 **/ 1725 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1726 u16 words, u16 *data) 1727 { 1728 u32 eewr; 1729 s32 status = IXGBE_SUCCESS; 1730 u16 i; 1731 1732 DEBUGFUNC("ixgbe_write_eewr_generic"); 1733 1734 hw->eeprom.ops.init_params(hw); 1735 1736 if (words == 0) { 1737 status = IXGBE_ERR_INVALID_ARGUMENT; 1738 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1739 goto out; 1740 } 1741 1742 if (offset >= hw->eeprom.word_size) { 1743 status = IXGBE_ERR_EEPROM; 1744 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1745 goto out; 1746 } 1747 1748 for (i = 0; i < words; i++) { 1749 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1750 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1751 IXGBE_EEPROM_RW_REG_START; 1752 1753 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1754 if (status != IXGBE_SUCCESS) { 1755 DEBUGOUT("Eeprom write EEWR timed out\n"); 1756 goto out; 1757 } 1758 1759 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1760 1761 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1762 if (status != IXGBE_SUCCESS) { 1763 DEBUGOUT("Eeprom write EEWR timed out\n"); 1764 goto out; 1765 } 1766 } 1767 1768 out: 1769 return status; 1770 } 1771 1772 /** 1773 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1774 * @hw: pointer to hardware structure 1775 * @offset: offset of word in the EEPROM to write 1776 * @data: word write to the EEPROM 1777 * 1778 * Write a 16 bit word to the EEPROM using the EEWR register. 1779 **/ 1780 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1781 { 1782 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1783 } 1784 1785 /** 1786 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1787 * @hw: pointer to hardware structure 1788 * @ee_reg: EEPROM flag for polling 1789 * 1790 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1791 * read or write is done respectively. 1792 **/ 1793 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1794 { 1795 u32 i; 1796 u32 reg; 1797 s32 status = IXGBE_ERR_EEPROM; 1798 1799 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1800 1801 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1802 if (ee_reg == IXGBE_NVM_POLL_READ) 1803 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1804 else 1805 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1806 1807 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1808 status = IXGBE_SUCCESS; 1809 break; 1810 } 1811 usec_delay(5); 1812 } 1813 1814 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1815 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1816 "EEPROM read/write done polling timed out"); 1817 1818 return status; 1819 } 1820 1821 /** 1822 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1823 * @hw: pointer to hardware structure 1824 * 1825 * Prepares EEPROM for access using bit-bang method. This function should 1826 * be called before issuing a command to the EEPROM. 1827 **/ 1828 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1829 { 1830 s32 status = IXGBE_SUCCESS; 1831 u32 eec; 1832 u32 i; 1833 1834 DEBUGFUNC("ixgbe_acquire_eeprom"); 1835 1836 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1837 != IXGBE_SUCCESS) 1838 status = IXGBE_ERR_SWFW_SYNC; 1839 1840 if (status == IXGBE_SUCCESS) { 1841 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1842 1843 /* Request EEPROM Access */ 1844 eec |= IXGBE_EEC_REQ; 1845 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1846 1847 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1848 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1849 if (eec & IXGBE_EEC_GNT) 1850 break; 1851 usec_delay(5); 1852 } 1853 1854 /* Release if grant not acquired */ 1855 if (!(eec & IXGBE_EEC_GNT)) { 1856 eec &= ~IXGBE_EEC_REQ; 1857 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1858 DEBUGOUT("Could not acquire EEPROM grant\n"); 1859 1860 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1861 status = IXGBE_ERR_EEPROM; 1862 } 1863 1864 /* Setup EEPROM for Read/Write */ 1865 if (status == IXGBE_SUCCESS) { 1866 /* Clear CS and SK */ 1867 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1868 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1869 IXGBE_WRITE_FLUSH(hw); 1870 usec_delay(1); 1871 } 1872 } 1873 return status; 1874 } 1875 1876 /** 1877 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1878 * @hw: pointer to hardware structure 1879 * 1880 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1881 **/ 1882 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1883 { 1884 s32 status = IXGBE_ERR_EEPROM; 1885 u32 timeout = 2000; 1886 u32 i; 1887 u32 swsm; 1888 1889 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1890 1891 /* Get SMBI software semaphore between device drivers first */ 1892 for (i = 0; i < timeout; i++) { 1893 /* 1894 * If the SMBI bit is 0 when we read it, then the bit will be 1895 * set and we have the semaphore 1896 */ 1897 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1898 if (!(swsm & IXGBE_SWSM_SMBI)) { 1899 status = IXGBE_SUCCESS; 1900 break; 1901 } 1902 usec_delay(50); 1903 } 1904 1905 if (i == timeout) { 1906 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1907 "not granted.\n"); 1908 /* 1909 * this release is particularly important because our attempts 1910 * above to get the semaphore may have succeeded, and if there 1911 * was a timeout, we should unconditionally clear the semaphore 1912 * bits to free the driver to make progress 1913 */ 1914 ixgbe_release_eeprom_semaphore(hw); 1915 1916 usec_delay(50); 1917 /* 1918 * one last try 1919 * If the SMBI bit is 0 when we read it, then the bit will be 1920 * set and we have the semaphore 1921 */ 1922 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1923 if (!(swsm & IXGBE_SWSM_SMBI)) 1924 status = IXGBE_SUCCESS; 1925 } 1926 1927 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1928 if (status == IXGBE_SUCCESS) { 1929 for (i = 0; i < timeout; i++) { 1930 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1931 1932 /* Set the SW EEPROM semaphore bit to request access */ 1933 swsm |= IXGBE_SWSM_SWESMBI; 1934 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1935 1936 /* 1937 * If we set the bit successfully then we got the 1938 * semaphore. 1939 */ 1940 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1941 if (swsm & IXGBE_SWSM_SWESMBI) 1942 break; 1943 1944 usec_delay(50); 1945 } 1946 1947 /* 1948 * Release semaphores and return error if SW EEPROM semaphore 1949 * was not granted because we don't have access to the EEPROM 1950 */ 1951 if (i >= timeout) { 1952 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1953 "SWESMBI Software EEPROM semaphore not granted.\n"); 1954 ixgbe_release_eeprom_semaphore(hw); 1955 status = IXGBE_ERR_EEPROM; 1956 } 1957 } else { 1958 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1959 "Software semaphore SMBI between device drivers " 1960 "not granted.\n"); 1961 } 1962 1963 return status; 1964 } 1965 1966 /** 1967 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1968 * @hw: pointer to hardware structure 1969 * 1970 * This function clears hardware semaphore bits. 1971 **/ 1972 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1973 { 1974 u32 swsm; 1975 1976 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1977 1978 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1979 1980 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1981 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1982 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1983 IXGBE_WRITE_FLUSH(hw); 1984 } 1985 1986 /** 1987 * ixgbe_ready_eeprom - Polls for EEPROM ready 1988 * @hw: pointer to hardware structure 1989 **/ 1990 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1991 { 1992 s32 status = IXGBE_SUCCESS; 1993 u16 i; 1994 u8 spi_stat_reg; 1995 1996 DEBUGFUNC("ixgbe_ready_eeprom"); 1997 1998 /* 1999 * Read "Status Register" repeatedly until the LSB is cleared. The 2000 * EEPROM will signal that the command has been completed by clearing 2001 * bit 0 of the internal status register. If it's not cleared within 2002 * 5 milliseconds, then error out. 2003 */ 2004 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 2005 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 2006 IXGBE_EEPROM_OPCODE_BITS); 2007 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 2008 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 2009 break; 2010 2011 usec_delay(5); 2012 ixgbe_standby_eeprom(hw); 2013 } 2014 2015 /* 2016 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2017 * devices (and only 0-5mSec on 5V devices) 2018 */ 2019 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2020 DEBUGOUT("SPI EEPROM Status error\n"); 2021 status = IXGBE_ERR_EEPROM; 2022 } 2023 2024 return status; 2025 } 2026 2027 /** 2028 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2029 * @hw: pointer to hardware structure 2030 **/ 2031 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2032 { 2033 u32 eec; 2034 2035 DEBUGFUNC("ixgbe_standby_eeprom"); 2036 2037 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2038 2039 /* Toggle CS to flush commands */ 2040 eec |= IXGBE_EEC_CS; 2041 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2042 IXGBE_WRITE_FLUSH(hw); 2043 usec_delay(1); 2044 eec &= ~IXGBE_EEC_CS; 2045 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2046 IXGBE_WRITE_FLUSH(hw); 2047 usec_delay(1); 2048 } 2049 2050 /** 2051 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2052 * @hw: pointer to hardware structure 2053 * @data: data to send to the EEPROM 2054 * @count: number of bits to shift out 2055 **/ 2056 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2057 u16 count) 2058 { 2059 u32 eec; 2060 u32 mask; 2061 u32 i; 2062 2063 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2064 2065 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2066 2067 /* 2068 * Mask is used to shift "count" bits of "data" out to the EEPROM 2069 * one bit at a time. Determine the starting bit based on count 2070 */ 2071 mask = 0x01 << (count - 1); 2072 2073 for (i = 0; i < count; i++) { 2074 /* 2075 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2076 * "1", and then raising and then lowering the clock (the SK 2077 * bit controls the clock input to the EEPROM). A "0" is 2078 * shifted out to the EEPROM by setting "DI" to "0" and then 2079 * raising and then lowering the clock. 2080 */ 2081 if (data & mask) 2082 eec |= IXGBE_EEC_DI; 2083 else 2084 eec &= ~IXGBE_EEC_DI; 2085 2086 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2087 IXGBE_WRITE_FLUSH(hw); 2088 2089 usec_delay(1); 2090 2091 ixgbe_raise_eeprom_clk(hw, &eec); 2092 ixgbe_lower_eeprom_clk(hw, &eec); 2093 2094 /* 2095 * Shift mask to signify next bit of data to shift in to the 2096 * EEPROM 2097 */ 2098 mask = mask >> 1; 2099 } 2100 2101 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2102 eec &= ~IXGBE_EEC_DI; 2103 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2104 IXGBE_WRITE_FLUSH(hw); 2105 } 2106 2107 /** 2108 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2109 * @hw: pointer to hardware structure 2110 * @count: number of bits to shift 2111 **/ 2112 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2113 { 2114 u32 eec; 2115 u32 i; 2116 u16 data = 0; 2117 2118 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2119 2120 /* 2121 * In order to read a register from the EEPROM, we need to shift 2122 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2123 * the clock input to the EEPROM (setting the SK bit), and then reading 2124 * the value of the "DO" bit. During this "shifting in" process the 2125 * "DI" bit should always be clear. 2126 */ 2127 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2128 2129 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2130 2131 for (i = 0; i < count; i++) { 2132 data = data << 1; 2133 ixgbe_raise_eeprom_clk(hw, &eec); 2134 2135 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2136 2137 eec &= ~(IXGBE_EEC_DI); 2138 if (eec & IXGBE_EEC_DO) 2139 data |= 1; 2140 2141 ixgbe_lower_eeprom_clk(hw, &eec); 2142 } 2143 2144 return data; 2145 } 2146 2147 /** 2148 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2149 * @hw: pointer to hardware structure 2150 * @eec: EEC register's current value 2151 **/ 2152 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2153 { 2154 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2155 2156 /* 2157 * Raise the clock input to the EEPROM 2158 * (setting the SK bit), then delay 2159 */ 2160 *eec = *eec | IXGBE_EEC_SK; 2161 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2162 IXGBE_WRITE_FLUSH(hw); 2163 usec_delay(1); 2164 } 2165 2166 /** 2167 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2168 * @hw: pointer to hardware structure 2169 * @eec: EEC's current value 2170 **/ 2171 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2172 { 2173 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2174 2175 /* 2176 * Lower the clock input to the EEPROM (clearing the SK bit), then 2177 * delay 2178 */ 2179 *eec = *eec & ~IXGBE_EEC_SK; 2180 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2181 IXGBE_WRITE_FLUSH(hw); 2182 usec_delay(1); 2183 } 2184 2185 /** 2186 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2187 * @hw: pointer to hardware structure 2188 **/ 2189 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2190 { 2191 u32 eec; 2192 2193 DEBUGFUNC("ixgbe_release_eeprom"); 2194 2195 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2196 2197 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2198 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2199 2200 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2201 IXGBE_WRITE_FLUSH(hw); 2202 2203 usec_delay(1); 2204 2205 /* Stop requesting EEPROM access */ 2206 eec &= ~IXGBE_EEC_REQ; 2207 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2208 2209 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2210 2211 /* Delay before attempt to obtain semaphore again to allow FW access */ 2212 msec_delay(hw->eeprom.semaphore_delay); 2213 } 2214 2215 /** 2216 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2217 * @hw: pointer to hardware structure 2218 * 2219 * Returns a negative error code on error, or the 16-bit checksum 2220 **/ 2221 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2222 { 2223 u16 i; 2224 u32 j; 2225 u32 word_end; 2226 u16 checksum = 0; 2227 u16 length = 0; 2228 u16 pointer = 0; 2229 u16 word = 0; 2230 2231 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2232 2233 /* Include 0x0-0x3F in the checksum */ 2234 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2235 if (hw->eeprom.ops.read(hw, i, &word)) { 2236 DEBUGOUT("EEPROM read failed\n"); 2237 return IXGBE_ERR_EEPROM; 2238 } 2239 checksum += word; 2240 } 2241 2242 /* Include all data from pointers except for the fw pointer */ 2243 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2244 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2245 DEBUGOUT("EEPROM read failed\n"); 2246 return IXGBE_ERR_EEPROM; 2247 } 2248 2249 /* If the pointer seems invalid */ 2250 if (pointer == 0xFFFF || pointer == 0) 2251 continue; 2252 if (pointer >= hw->eeprom.word_size) { 2253 DEBUGOUT("EEPROM pointer outside word range\n"); 2254 return IXGBE_ERR_EEPROM; 2255 } 2256 2257 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2258 DEBUGOUT("EEPROM read failed\n"); 2259 return IXGBE_ERR_EEPROM; 2260 } 2261 2262 if (length == 0xFFFF || length == 0) 2263 continue; 2264 if (length >= hw->eeprom.word_size - pointer) { 2265 DEBUGOUT("EEPROM section outside word range\n"); 2266 return IXGBE_ERR_EEPROM; 2267 } 2268 2269 word_end = (u32)pointer + length; 2270 for (j = (u32)pointer + 1; j <= word_end; j++) { 2271 if (hw->eeprom.ops.read(hw, (u16)j, &word)) { 2272 DEBUGOUT("EEPROM read failed\n"); 2273 return IXGBE_ERR_EEPROM; 2274 } 2275 checksum += word; 2276 } 2277 } 2278 2279 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2280 2281 return (s32)checksum; 2282 } 2283 2284 /** 2285 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2286 * @hw: pointer to hardware structure 2287 * @checksum_val: calculated checksum 2288 * 2289 * Performs checksum calculation and validates the EEPROM checksum. If the 2290 * caller does not need checksum_val, the value can be NULL. 2291 **/ 2292 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2293 u16 *checksum_val) 2294 { 2295 s32 status; 2296 u16 checksum; 2297 u16 read_checksum = 0; 2298 2299 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2300 2301 /* Read the first word from the EEPROM. If this times out or fails, do 2302 * not continue or we could be in for a very long wait while every 2303 * EEPROM read fails 2304 */ 2305 status = hw->eeprom.ops.read(hw, 0, &checksum); 2306 if (status) { 2307 DEBUGOUT("EEPROM read failed\n"); 2308 return status; 2309 } 2310 2311 status = hw->eeprom.ops.calc_checksum(hw); 2312 if (status < 0) 2313 return status; 2314 2315 checksum = (u16)(status & 0xffff); 2316 2317 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2318 if (status) { 2319 DEBUGOUT("EEPROM read failed\n"); 2320 return status; 2321 } 2322 2323 /* Verify read checksum from EEPROM is the same as 2324 * calculated checksum 2325 */ 2326 if (read_checksum != checksum) 2327 status = IXGBE_ERR_EEPROM_CHECKSUM; 2328 2329 /* If the user cares, return the calculated checksum */ 2330 if (checksum_val) 2331 *checksum_val = checksum; 2332 2333 return status; 2334 } 2335 2336 /** 2337 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2338 * @hw: pointer to hardware structure 2339 **/ 2340 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2341 { 2342 s32 status; 2343 u16 checksum; 2344 2345 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2346 2347 /* Read the first word from the EEPROM. If this times out or fails, do 2348 * not continue or we could be in for a very long wait while every 2349 * EEPROM read fails 2350 */ 2351 status = hw->eeprom.ops.read(hw, 0, &checksum); 2352 if (status) { 2353 DEBUGOUT("EEPROM read failed\n"); 2354 return status; 2355 } 2356 2357 status = hw->eeprom.ops.calc_checksum(hw); 2358 if (status < 0) 2359 return status; 2360 2361 checksum = (u16)(status & 0xffff); 2362 2363 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2364 2365 return status; 2366 } 2367 2368 /** 2369 * ixgbe_validate_mac_addr - Validate MAC address 2370 * @mac_addr: pointer to MAC address. 2371 * 2372 * Tests a MAC address to ensure it is a valid Individual Address. 2373 **/ 2374 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2375 { 2376 s32 status = IXGBE_SUCCESS; 2377 2378 DEBUGFUNC("ixgbe_validate_mac_addr"); 2379 2380 /* Make sure it is not a multicast address */ 2381 if (IXGBE_IS_MULTICAST(mac_addr)) { 2382 status = IXGBE_ERR_INVALID_MAC_ADDR; 2383 /* Not a broadcast address */ 2384 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2385 status = IXGBE_ERR_INVALID_MAC_ADDR; 2386 /* Reject the zero address */ 2387 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2388 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2389 status = IXGBE_ERR_INVALID_MAC_ADDR; 2390 } 2391 return status; 2392 } 2393 2394 /** 2395 * ixgbe_set_rar_generic - Set Rx address register 2396 * @hw: pointer to hardware structure 2397 * @index: Receive address register to write 2398 * @addr: Address to put into receive address register 2399 * @vmdq: VMDq "set" or "pool" index 2400 * @enable_addr: set flag that address is active 2401 * 2402 * Puts an ethernet address into a receive address register. 2403 **/ 2404 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2405 u32 enable_addr) 2406 { 2407 u32 rar_low, rar_high; 2408 u32 rar_entries = hw->mac.num_rar_entries; 2409 2410 DEBUGFUNC("ixgbe_set_rar_generic"); 2411 2412 /* Make sure we are using a valid rar index range */ 2413 if (index >= rar_entries) { 2414 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2415 "RAR index %d is out of range.\n", index); 2416 return IXGBE_ERR_INVALID_ARGUMENT; 2417 } 2418 2419 /* setup VMDq pool selection before this RAR gets enabled */ 2420 hw->mac.ops.set_vmdq(hw, index, vmdq); 2421 2422 /* 2423 * HW expects these in little endian so we reverse the byte 2424 * order from network order (big endian) to little endian 2425 */ 2426 rar_low = ((u32)addr[0] | 2427 ((u32)addr[1] << 8) | 2428 ((u32)addr[2] << 16) | 2429 ((u32)addr[3] << 24)); 2430 /* 2431 * Some parts put the VMDq setting in the extra RAH bits, 2432 * so save everything except the lower 16 bits that hold part 2433 * of the address and the address valid bit. 2434 */ 2435 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2436 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2437 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2438 2439 if (enable_addr != 0) 2440 rar_high |= IXGBE_RAH_AV; 2441 2442 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2443 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2444 2445 return IXGBE_SUCCESS; 2446 } 2447 2448 /** 2449 * ixgbe_clear_rar_generic - Remove Rx address register 2450 * @hw: pointer to hardware structure 2451 * @index: Receive address register to write 2452 * 2453 * Clears an ethernet address from a receive address register. 2454 **/ 2455 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2456 { 2457 u32 rar_high; 2458 u32 rar_entries = hw->mac.num_rar_entries; 2459 2460 DEBUGFUNC("ixgbe_clear_rar_generic"); 2461 2462 /* Make sure we are using a valid rar index range */ 2463 if (index >= rar_entries) { 2464 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2465 "RAR index %d is out of range.\n", index); 2466 return IXGBE_ERR_INVALID_ARGUMENT; 2467 } 2468 2469 /* 2470 * Some parts put the VMDq setting in the extra RAH bits, 2471 * so save everything except the lower 16 bits that hold part 2472 * of the address and the address valid bit. 2473 */ 2474 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2475 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2476 2477 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2478 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2479 2480 /* clear VMDq pool/queue selection for this RAR */ 2481 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2482 2483 return IXGBE_SUCCESS; 2484 } 2485 2486 /** 2487 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2488 * @hw: pointer to hardware structure 2489 * 2490 * Places the MAC address in receive address register 0 and clears the rest 2491 * of the receive address registers. Clears the multicast table. Assumes 2492 * the receiver is in reset when the routine is called. 2493 **/ 2494 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2495 { 2496 u32 i; 2497 u32 rar_entries = hw->mac.num_rar_entries; 2498 2499 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2500 2501 /* 2502 * If the current mac address is valid, assume it is a software override 2503 * to the permanent address. 2504 * Otherwise, use the permanent address from the eeprom. 2505 */ 2506 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2507 IXGBE_ERR_INVALID_MAC_ADDR) { 2508 /* Get the MAC address from the RAR0 for later reference */ 2509 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2510 2511 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2512 hw->mac.addr[0], hw->mac.addr[1], 2513 hw->mac.addr[2]); 2514 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2515 hw->mac.addr[4], hw->mac.addr[5]); 2516 } else { 2517 /* Setup the receive address. */ 2518 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2519 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2520 hw->mac.addr[0], hw->mac.addr[1], 2521 hw->mac.addr[2]); 2522 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2523 hw->mac.addr[4], hw->mac.addr[5]); 2524 2525 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2526 } 2527 2528 /* clear VMDq pool/queue selection for RAR 0 */ 2529 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2530 2531 hw->addr_ctrl.overflow_promisc = 0; 2532 2533 hw->addr_ctrl.rar_used_count = 1; 2534 2535 /* Zero out the other receive addresses. */ 2536 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2537 for (i = 1; i < rar_entries; i++) { 2538 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2539 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2540 } 2541 2542 /* Clear the MTA */ 2543 hw->addr_ctrl.mta_in_use = 0; 2544 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2545 2546 DEBUGOUT(" Clearing MTA\n"); 2547 for (i = 0; i < hw->mac.mcft_size; i++) 2548 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2549 2550 ixgbe_init_uta_tables(hw); 2551 2552 return IXGBE_SUCCESS; 2553 } 2554 2555 /** 2556 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2557 * @hw: pointer to hardware structure 2558 * @addr: new address 2559 * @vmdq: VMDq "set" or "pool" index 2560 * 2561 * Adds it to unused receive address register or goes into promiscuous mode. 2562 **/ 2563 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2564 { 2565 u32 rar_entries = hw->mac.num_rar_entries; 2566 u32 rar; 2567 2568 DEBUGFUNC("ixgbe_add_uc_addr"); 2569 2570 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2571 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2572 2573 /* 2574 * Place this address in the RAR if there is room, 2575 * else put the controller into promiscuous mode 2576 */ 2577 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2578 rar = hw->addr_ctrl.rar_used_count; 2579 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2580 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2581 hw->addr_ctrl.rar_used_count++; 2582 } else { 2583 hw->addr_ctrl.overflow_promisc++; 2584 } 2585 2586 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2587 } 2588 2589 /** 2590 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2591 * @hw: pointer to hardware structure 2592 * @addr_list: the list of new addresses 2593 * @addr_count: number of addresses 2594 * @next: iterator function to walk the address list 2595 * 2596 * The given list replaces any existing list. Clears the secondary addrs from 2597 * receive address registers. Uses unused receive address registers for the 2598 * first secondary addresses, and falls back to promiscuous mode as needed. 2599 * 2600 * Drivers using secondary unicast addresses must set user_set_promisc when 2601 * manually putting the device into promiscuous mode. 2602 **/ 2603 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2604 u32 addr_count, ixgbe_mc_addr_itr next) 2605 { 2606 u8 *addr; 2607 u32 i; 2608 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2609 u32 uc_addr_in_use; 2610 u32 fctrl; 2611 u32 vmdq; 2612 2613 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2614 2615 /* 2616 * Clear accounting of old secondary address list, 2617 * don't count RAR[0] 2618 */ 2619 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2620 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2621 hw->addr_ctrl.overflow_promisc = 0; 2622 2623 /* Zero out the other receive addresses */ 2624 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2625 for (i = 0; i < uc_addr_in_use; i++) { 2626 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2627 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2628 } 2629 2630 /* Add the new addresses */ 2631 for (i = 0; i < addr_count; i++) { 2632 DEBUGOUT(" Adding the secondary addresses:\n"); 2633 addr = next(hw, &addr_list, &vmdq); 2634 ixgbe_add_uc_addr(hw, addr, vmdq); 2635 } 2636 2637 if (hw->addr_ctrl.overflow_promisc) { 2638 /* enable promisc if not already in overflow or set by user */ 2639 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2640 DEBUGOUT(" Entering address overflow promisc mode\n"); 2641 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2642 fctrl |= IXGBE_FCTRL_UPE; 2643 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2644 } 2645 } else { 2646 /* only disable if set by overflow, not by user */ 2647 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2648 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2649 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2650 fctrl &= ~IXGBE_FCTRL_UPE; 2651 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2652 } 2653 } 2654 2655 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2656 return IXGBE_SUCCESS; 2657 } 2658 2659 /** 2660 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2661 * @hw: pointer to hardware structure 2662 * @mc_addr: the multicast address 2663 * 2664 * Extracts the 12 bits, from a multicast address, to determine which 2665 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2666 * incoming rx multicast addresses, to determine the bit-vector to check in 2667 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2668 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2669 * to mc_filter_type. 2670 **/ 2671 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2672 { 2673 u32 vector = 0; 2674 2675 DEBUGFUNC("ixgbe_mta_vector"); 2676 2677 switch (hw->mac.mc_filter_type) { 2678 case 0: /* use bits [47:36] of the address */ 2679 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2680 break; 2681 case 1: /* use bits [46:35] of the address */ 2682 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2683 break; 2684 case 2: /* use bits [45:34] of the address */ 2685 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2686 break; 2687 case 3: /* use bits [43:32] of the address */ 2688 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2689 break; 2690 default: /* Invalid mc_filter_type */ 2691 DEBUGOUT("MC filter type param set incorrectly\n"); 2692 ASSERT(0); 2693 break; 2694 } 2695 2696 /* vector can only be 12-bits or boundary will be exceeded */ 2697 vector &= 0xFFF; 2698 return vector; 2699 } 2700 2701 /** 2702 * ixgbe_set_mta - Set bit-vector in multicast table 2703 * @hw: pointer to hardware structure 2704 * @mc_addr: Multicast address 2705 * 2706 * Sets the bit-vector in the multicast table. 2707 **/ 2708 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2709 { 2710 u32 vector; 2711 u32 vector_bit; 2712 u32 vector_reg; 2713 2714 DEBUGFUNC("ixgbe_set_mta"); 2715 2716 hw->addr_ctrl.mta_in_use++; 2717 2718 vector = ixgbe_mta_vector(hw, mc_addr); 2719 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2720 2721 /* 2722 * The MTA is a register array of 128 32-bit registers. It is treated 2723 * like an array of 4096 bits. We want to set bit 2724 * BitArray[vector_value]. So we figure out what register the bit is 2725 * in, read it, OR in the new bit, then write back the new value. The 2726 * register is determined by the upper 7 bits of the vector value and 2727 * the bit within that register are determined by the lower 5 bits of 2728 * the value. 2729 */ 2730 vector_reg = (vector >> 5) & 0x7F; 2731 vector_bit = vector & 0x1F; 2732 hw->mac.mta_shadow[vector_reg] |= 1U << vector_bit; 2733 } 2734 2735 /** 2736 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2737 * @hw: pointer to hardware structure 2738 * @mc_addr_list: the list of new multicast addresses 2739 * @mc_addr_count: number of addresses 2740 * @next: iterator function to walk the multicast address list 2741 * @clear: flag, when set clears the table beforehand 2742 * 2743 * When the clear flag is set, the given list replaces any existing list. 2744 * Hashes the given addresses into the multicast table. 2745 **/ 2746 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2747 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2748 bool clear) 2749 { 2750 u32 i; 2751 u32 vmdq; 2752 2753 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2754 2755 /* 2756 * Set the new number of MC addresses that we are being requested to 2757 * use. 2758 */ 2759 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2760 hw->addr_ctrl.mta_in_use = 0; 2761 2762 /* Clear mta_shadow */ 2763 if (clear) { 2764 DEBUGOUT(" Clearing MTA\n"); 2765 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2766 } 2767 2768 /* Update mta_shadow */ 2769 for (i = 0; i < mc_addr_count; i++) { 2770 DEBUGOUT(" Adding the multicast addresses:\n"); 2771 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2772 } 2773 2774 /* Enable mta */ 2775 for (i = 0; i < hw->mac.mcft_size; i++) 2776 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2777 hw->mac.mta_shadow[i]); 2778 2779 if (hw->addr_ctrl.mta_in_use > 0) 2780 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2781 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2782 2783 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2784 return IXGBE_SUCCESS; 2785 } 2786 2787 /** 2788 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2789 * @hw: pointer to hardware structure 2790 * 2791 * Enables multicast address in RAR and the use of the multicast hash table. 2792 **/ 2793 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2794 { 2795 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2796 2797 DEBUGFUNC("ixgbe_enable_mc_generic"); 2798 2799 if (a->mta_in_use > 0) 2800 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2801 hw->mac.mc_filter_type); 2802 2803 return IXGBE_SUCCESS; 2804 } 2805 2806 /** 2807 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2808 * @hw: pointer to hardware structure 2809 * 2810 * Disables multicast address in RAR and the use of the multicast hash table. 2811 **/ 2812 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2813 { 2814 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2815 2816 DEBUGFUNC("ixgbe_disable_mc_generic"); 2817 2818 if (a->mta_in_use > 0) 2819 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2820 2821 return IXGBE_SUCCESS; 2822 } 2823 2824 /** 2825 * ixgbe_fc_enable_generic - Enable flow control 2826 * @hw: pointer to hardware structure 2827 * 2828 * Enable flow control according to the current settings. 2829 **/ 2830 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2831 { 2832 s32 ret_val = IXGBE_SUCCESS; 2833 u32 mflcn_reg, fccfg_reg; 2834 u32 reg; 2835 u32 fcrtl, fcrth; 2836 int i; 2837 2838 DEBUGFUNC("ixgbe_fc_enable_generic"); 2839 2840 /* Validate the water mark configuration */ 2841 if (!hw->fc.pause_time) { 2842 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2843 goto out; 2844 } 2845 2846 /* Low water mark of zero causes XOFF floods */ 2847 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2848 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2849 hw->fc.high_water[i]) { 2850 if (!hw->fc.low_water[i] || 2851 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2852 DEBUGOUT("Invalid water mark configuration\n"); 2853 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2854 goto out; 2855 } 2856 } 2857 } 2858 2859 /* Negotiate the fc mode to use */ 2860 hw->mac.ops.fc_autoneg(hw); 2861 2862 /* Disable any previous flow control settings */ 2863 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2864 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2865 2866 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2867 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2868 2869 /* 2870 * The possible values of fc.current_mode are: 2871 * 0: Flow control is completely disabled 2872 * 1: Rx flow control is enabled (we can receive pause frames, 2873 * but not send pause frames). 2874 * 2: Tx flow control is enabled (we can send pause frames but 2875 * we do not support receiving pause frames). 2876 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2877 * other: Invalid. 2878 */ 2879 switch (hw->fc.current_mode) { 2880 case ixgbe_fc_none: 2881 /* 2882 * Flow control is disabled by software override or autoneg. 2883 * The code below will actually disable it in the HW. 2884 */ 2885 break; 2886 case ixgbe_fc_rx_pause: 2887 /* 2888 * Rx Flow control is enabled and Tx Flow control is 2889 * disabled by software override. Since there really 2890 * isn't a way to advertise that we are capable of RX 2891 * Pause ONLY, we will advertise that we support both 2892 * symmetric and asymmetric Rx PAUSE. Later, we will 2893 * disable the adapter's ability to send PAUSE frames. 2894 */ 2895 mflcn_reg |= IXGBE_MFLCN_RFCE; 2896 break; 2897 case ixgbe_fc_tx_pause: 2898 /* 2899 * Tx Flow control is enabled, and Rx Flow control is 2900 * disabled by software override. 2901 */ 2902 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2903 break; 2904 case ixgbe_fc_full: 2905 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2906 mflcn_reg |= IXGBE_MFLCN_RFCE; 2907 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2908 break; 2909 default: 2910 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2911 "Flow control param set incorrectly\n"); 2912 ret_val = IXGBE_ERR_CONFIG; 2913 goto out; 2914 break; 2915 } 2916 2917 /* Set 802.3x based flow control settings. */ 2918 mflcn_reg |= IXGBE_MFLCN_DPF; 2919 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2920 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2921 2922 2923 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2924 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2925 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2926 hw->fc.high_water[i]) { 2927 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2928 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2929 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2930 } else { 2931 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2932 /* 2933 * In order to prevent Tx hangs when the internal Tx 2934 * switch is enabled we must set the high water mark 2935 * to the Rx packet buffer size - 24KB. This allows 2936 * the Tx switch to function even under heavy Rx 2937 * workloads. 2938 */ 2939 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2940 } 2941 2942 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2943 } 2944 2945 /* Configure pause time (2 TCs per register) */ 2946 reg = hw->fc.pause_time * 0x00010001U; 2947 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2948 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2949 2950 /* Configure flow control refresh threshold value */ 2951 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2952 2953 out: 2954 return ret_val; 2955 } 2956 2957 /** 2958 * ixgbe_negotiate_fc - Negotiate flow control 2959 * @hw: pointer to hardware structure 2960 * @adv_reg: flow control advertised settings 2961 * @lp_reg: link partner's flow control settings 2962 * @adv_sym: symmetric pause bit in advertisement 2963 * @adv_asm: asymmetric pause bit in advertisement 2964 * @lp_sym: symmetric pause bit in link partner advertisement 2965 * @lp_asm: asymmetric pause bit in link partner advertisement 2966 * 2967 * Find the intersection between advertised settings and link partner's 2968 * advertised settings 2969 **/ 2970 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2971 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2972 { 2973 if ((!(adv_reg)) || (!(lp_reg))) { 2974 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2975 "Local or link partner's advertised flow control " 2976 "settings are NULL. Local: %x, link partner: %x\n", 2977 adv_reg, lp_reg); 2978 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2979 } 2980 2981 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2982 /* 2983 * Now we need to check if the user selected Rx ONLY 2984 * of pause frames. In this case, we had to advertise 2985 * FULL flow control because we could not advertise RX 2986 * ONLY. Hence, we must now check to see if we need to 2987 * turn OFF the TRANSMISSION of PAUSE frames. 2988 */ 2989 if (hw->fc.requested_mode == ixgbe_fc_full) { 2990 hw->fc.current_mode = ixgbe_fc_full; 2991 DEBUGOUT("Flow Control = FULL.\n"); 2992 } else { 2993 hw->fc.current_mode = ixgbe_fc_rx_pause; 2994 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2995 } 2996 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2997 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2998 hw->fc.current_mode = ixgbe_fc_tx_pause; 2999 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 3000 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 3001 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 3002 hw->fc.current_mode = ixgbe_fc_rx_pause; 3003 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 3004 } else { 3005 hw->fc.current_mode = ixgbe_fc_none; 3006 DEBUGOUT("Flow Control = NONE.\n"); 3007 } 3008 return IXGBE_SUCCESS; 3009 } 3010 3011 /** 3012 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 3013 * @hw: pointer to hardware structure 3014 * 3015 * Enable flow control according on 1 gig fiber. 3016 **/ 3017 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 3018 { 3019 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 3020 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3021 3022 /* 3023 * On multispeed fiber at 1g, bail out if 3024 * - link is up but AN did not complete, or if 3025 * - link is up and AN completed but timed out 3026 */ 3027 3028 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3029 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3030 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3031 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3032 goto out; 3033 } 3034 3035 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3036 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3037 3038 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3039 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3040 IXGBE_PCS1GANA_ASM_PAUSE, 3041 IXGBE_PCS1GANA_SYM_PAUSE, 3042 IXGBE_PCS1GANA_ASM_PAUSE); 3043 3044 out: 3045 return ret_val; 3046 } 3047 3048 /** 3049 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3050 * @hw: pointer to hardware structure 3051 * 3052 * Enable flow control according to IEEE clause 37. 3053 **/ 3054 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3055 { 3056 u32 links2, anlp1_reg, autoc_reg, links; 3057 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3058 3059 /* 3060 * On backplane, bail out if 3061 * - backplane autoneg was not completed, or if 3062 * - we are 82599 and link partner is not AN enabled 3063 */ 3064 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3065 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3066 DEBUGOUT("Auto-Negotiation did not complete\n"); 3067 goto out; 3068 } 3069 3070 if (hw->mac.type == ixgbe_mac_82599EB) { 3071 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3072 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3073 DEBUGOUT("Link partner is not AN enabled\n"); 3074 goto out; 3075 } 3076 } 3077 /* 3078 * Read the 10g AN autoc and LP ability registers and resolve 3079 * local flow control settings accordingly 3080 */ 3081 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3082 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3083 3084 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3085 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3086 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3087 3088 out: 3089 return ret_val; 3090 } 3091 3092 /** 3093 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3094 * @hw: pointer to hardware structure 3095 * 3096 * Enable flow control according to IEEE clause 37. 3097 **/ 3098 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3099 { 3100 u16 technology_ability_reg = 0; 3101 u16 lp_technology_ability_reg = 0; 3102 3103 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3104 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3105 &technology_ability_reg); 3106 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3108 &lp_technology_ability_reg); 3109 3110 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3111 (u32)lp_technology_ability_reg, 3112 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3113 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3114 } 3115 3116 /** 3117 * ixgbe_fc_autoneg - Configure flow control 3118 * @hw: pointer to hardware structure 3119 * 3120 * Compares our advertised flow control capabilities to those advertised by 3121 * our link partner, and determines the proper flow control mode to use. 3122 **/ 3123 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3124 { 3125 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3126 ixgbe_link_speed speed; 3127 bool link_up; 3128 3129 DEBUGFUNC("ixgbe_fc_autoneg"); 3130 3131 /* 3132 * AN should have completed when the cable was plugged in. 3133 * Look for reasons to bail out. Bail out if: 3134 * - FC autoneg is disabled, or if 3135 * - link is not up. 3136 */ 3137 if (hw->fc.disable_fc_autoneg) { 3138 /* TODO: This should be just an informative log */ 3139 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 3140 "Flow control autoneg is disabled"); 3141 goto out; 3142 } 3143 3144 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3145 if (!link_up) { 3146 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3147 goto out; 3148 } 3149 3150 switch (hw->phy.media_type) { 3151 /* Autoneg flow control on fiber adapters */ 3152 case ixgbe_media_type_fiber_fixed: 3153 case ixgbe_media_type_fiber_qsfp: 3154 case ixgbe_media_type_fiber: 3155 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3156 ret_val = ixgbe_fc_autoneg_fiber(hw); 3157 break; 3158 3159 /* Autoneg flow control on backplane adapters */ 3160 case ixgbe_media_type_backplane: 3161 ret_val = ixgbe_fc_autoneg_backplane(hw); 3162 break; 3163 3164 /* Autoneg flow control on copper adapters */ 3165 case ixgbe_media_type_copper: 3166 if (ixgbe_device_supports_autoneg_fc(hw)) 3167 ret_val = ixgbe_fc_autoneg_copper(hw); 3168 break; 3169 3170 default: 3171 break; 3172 } 3173 3174 out: 3175 if (ret_val == IXGBE_SUCCESS) { 3176 hw->fc.fc_was_autonegged = true; 3177 } else { 3178 hw->fc.fc_was_autonegged = false; 3179 hw->fc.current_mode = hw->fc.requested_mode; 3180 } 3181 } 3182 3183 /* 3184 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3185 * @hw: pointer to hardware structure 3186 * 3187 * System-wide timeout range is encoded in PCIe Device Control2 register. 3188 * 3189 * Add 10% to specified maximum and return the number of times to poll for 3190 * completion timeout, in units of 100 microsec. Never return less than 3191 * 800 = 80 millisec. 3192 */ 3193 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3194 { 3195 s16 devctl2; 3196 u32 pollcnt; 3197 3198 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3199 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3200 3201 switch (devctl2) { 3202 case IXGBE_PCIDEVCTRL2_65_130ms: 3203 pollcnt = 1300; /* 130 millisec */ 3204 break; 3205 case IXGBE_PCIDEVCTRL2_260_520ms: 3206 pollcnt = 5200; /* 520 millisec */ 3207 break; 3208 case IXGBE_PCIDEVCTRL2_1_2s: 3209 pollcnt = 20000; /* 2 sec */ 3210 break; 3211 case IXGBE_PCIDEVCTRL2_4_8s: 3212 pollcnt = 80000; /* 8 sec */ 3213 break; 3214 case IXGBE_PCIDEVCTRL2_17_34s: 3215 pollcnt = 34000; /* 34 sec */ 3216 break; 3217 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3218 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3219 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3220 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3221 default: 3222 pollcnt = 800; /* 80 millisec minimum */ 3223 break; 3224 } 3225 3226 /* add 10% to spec maximum */ 3227 return (pollcnt * 11) / 10; 3228 } 3229 3230 /** 3231 * ixgbe_disable_pcie_primary - Disable PCI-express primary access 3232 * @hw: pointer to hardware structure 3233 * 3234 * Disables PCI-Express primary access and verifies there are no pending 3235 * requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable 3236 * bit hasn't caused the primary requests to be disabled, else IXGBE_SUCCESS 3237 * is returned signifying primary requests disabled. 3238 **/ 3239 s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) 3240 { 3241 s32 status = IXGBE_SUCCESS; 3242 u32 i, poll; 3243 u16 value; 3244 3245 DEBUGFUNC("ixgbe_disable_pcie_primary"); 3246 3247 /* Always set this bit to ensure any future transactions are blocked */ 3248 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3249 3250 /* Exit if primary requests are blocked */ 3251 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3252 IXGBE_REMOVED(hw->hw_addr)) 3253 goto out; 3254 3255 /* Poll for primary request bit to clear */ 3256 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { 3257 usec_delay(100); 3258 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3259 goto out; 3260 } 3261 3262 /* 3263 * Two consecutive resets are required via CTRL.RST per datasheet 3264 * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine 3265 * of this need. The first reset prevents new primary requests from 3266 * being issued by our device. We then must wait 1usec or more for any 3267 * remaining completions from the PCIe bus to trickle in, and then reset 3268 * again to clear out any effects they may have had on our device. 3269 */ 3270 DEBUGOUT("GIO Primary Disable bit didn't clear - requesting resets\n"); 3271 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3272 3273 if (hw->mac.type >= ixgbe_mac_X550) 3274 goto out; 3275 3276 /* 3277 * Before proceeding, make sure that the PCIe block does not have 3278 * transactions pending. 3279 */ 3280 poll = ixgbe_pcie_timeout_poll(hw); 3281 for (i = 0; i < poll; i++) { 3282 usec_delay(100); 3283 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3284 if (IXGBE_REMOVED(hw->hw_addr)) 3285 goto out; 3286 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3287 goto out; 3288 } 3289 3290 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3291 "PCIe transaction pending bit also did not clear.\n"); 3292 status = IXGBE_ERR_PRIMARY_REQUESTS_PENDING; 3293 3294 out: 3295 return status; 3296 } 3297 3298 /** 3299 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3300 * @hw: pointer to hardware structure 3301 * @mask: Mask to specify which semaphore to acquire 3302 * 3303 * Acquires the SWFW semaphore through the GSSR register for the specified 3304 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3305 **/ 3306 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3307 { 3308 u32 gssr = 0; 3309 u32 swmask = mask; 3310 u32 fwmask = mask << 5; 3311 u32 timeout = 200; 3312 u32 i; 3313 3314 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3315 3316 for (i = 0; i < timeout; i++) { 3317 /* 3318 * SW NVM semaphore bit is used for access to all 3319 * SW_FW_SYNC bits (not just NVM) 3320 */ 3321 if (ixgbe_get_eeprom_semaphore(hw)) 3322 return IXGBE_ERR_SWFW_SYNC; 3323 3324 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3325 if (!(gssr & (fwmask | swmask))) { 3326 gssr |= swmask; 3327 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3328 ixgbe_release_eeprom_semaphore(hw); 3329 return IXGBE_SUCCESS; 3330 } else { 3331 /* Resource is currently in use by FW or SW */ 3332 ixgbe_release_eeprom_semaphore(hw); 3333 msec_delay(5); 3334 } 3335 } 3336 3337 /* If time expired clear the bits holding the lock and retry */ 3338 if (gssr & (fwmask | swmask)) 3339 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3340 3341 msec_delay(5); 3342 return IXGBE_ERR_SWFW_SYNC; 3343 } 3344 3345 /** 3346 * ixgbe_release_swfw_sync - Release SWFW semaphore 3347 * @hw: pointer to hardware structure 3348 * @mask: Mask to specify which semaphore to release 3349 * 3350 * Releases the SWFW semaphore through the GSSR register for the specified 3351 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3352 **/ 3353 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3354 { 3355 u32 gssr; 3356 u32 swmask = mask; 3357 3358 DEBUGFUNC("ixgbe_release_swfw_sync"); 3359 3360 ixgbe_get_eeprom_semaphore(hw); 3361 3362 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3363 gssr &= ~swmask; 3364 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3365 3366 ixgbe_release_eeprom_semaphore(hw); 3367 } 3368 3369 /** 3370 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3371 * @hw: pointer to hardware structure 3372 * 3373 * Stops the receive data path and waits for the HW to internally empty 3374 * the Rx security block 3375 **/ 3376 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3377 { 3378 #define IXGBE_MAX_SECRX_POLL 4000 3379 3380 int i; 3381 int secrxreg; 3382 3383 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3384 3385 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3386 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3387 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3388 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3389 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3390 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3391 break; 3392 else 3393 /* Use interrupt-safe sleep just in case */ 3394 usec_delay(10); 3395 } 3396 3397 /* For informational purposes only */ 3398 if (i >= IXGBE_MAX_SECRX_POLL) 3399 DEBUGOUT("Rx unit being enabled before security " 3400 "path fully disabled. Continuing with init.\n"); 3401 3402 return IXGBE_SUCCESS; 3403 } 3404 3405 /** 3406 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3407 * @hw: pointer to hardware structure 3408 * @locked: bool to indicate whether the SW/FW lock was taken 3409 * @reg_val: Value we read from AUTOC 3410 * 3411 * The default case requires no protection so just to the register read. 3412 */ 3413 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3414 { 3415 *locked = false; 3416 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3417 return IXGBE_SUCCESS; 3418 } 3419 3420 /** 3421 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3422 * @hw: pointer to hardware structure 3423 * @reg_val: value to write to AUTOC 3424 * @locked: bool to indicate whether the SW/FW lock was already taken by 3425 * previous read. 3426 * 3427 * The default case requires no protection so just to the register write. 3428 */ 3429 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3430 { 3431 UNREFERENCED_1PARAMETER(locked); 3432 3433 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3434 return IXGBE_SUCCESS; 3435 } 3436 3437 /** 3438 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3439 * @hw: pointer to hardware structure 3440 * 3441 * Enables the receive data path. 3442 **/ 3443 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3444 { 3445 u32 secrxreg; 3446 3447 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3448 3449 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3450 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3451 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3452 IXGBE_WRITE_FLUSH(hw); 3453 3454 return IXGBE_SUCCESS; 3455 } 3456 3457 /** 3458 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3459 * @hw: pointer to hardware structure 3460 * @regval: register value to write to RXCTRL 3461 * 3462 * Enables the Rx DMA unit 3463 **/ 3464 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3465 { 3466 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3467 3468 if (regval & IXGBE_RXCTRL_RXEN) 3469 ixgbe_enable_rx(hw); 3470 else 3471 ixgbe_disable_rx(hw); 3472 3473 return IXGBE_SUCCESS; 3474 } 3475 3476 /** 3477 * ixgbe_blink_led_start_generic - Blink LED based on index. 3478 * @hw: pointer to hardware structure 3479 * @index: led number to blink 3480 **/ 3481 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3482 { 3483 ixgbe_link_speed speed = 0; 3484 bool link_up = 0; 3485 u32 autoc_reg = 0; 3486 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3487 s32 ret_val = IXGBE_SUCCESS; 3488 bool locked = false; 3489 3490 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3491 3492 if (index > 3) 3493 return IXGBE_ERR_PARAM; 3494 3495 /* 3496 * Link must be up to auto-blink the LEDs; 3497 * Force it if link is down. 3498 */ 3499 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3500 3501 if (!link_up) { 3502 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3503 if (ret_val != IXGBE_SUCCESS) 3504 goto out; 3505 3506 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3507 autoc_reg |= IXGBE_AUTOC_FLU; 3508 3509 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3510 if (ret_val != IXGBE_SUCCESS) 3511 goto out; 3512 3513 IXGBE_WRITE_FLUSH(hw); 3514 msec_delay(10); 3515 } 3516 3517 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3518 led_reg |= IXGBE_LED_BLINK(index); 3519 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3520 IXGBE_WRITE_FLUSH(hw); 3521 3522 out: 3523 return ret_val; 3524 } 3525 3526 /** 3527 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3528 * @hw: pointer to hardware structure 3529 * @index: led number to stop blinking 3530 **/ 3531 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3532 { 3533 u32 autoc_reg = 0; 3534 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3535 s32 ret_val = IXGBE_SUCCESS; 3536 bool locked = false; 3537 3538 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3539 3540 if (index > 3) 3541 return IXGBE_ERR_PARAM; 3542 3543 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3544 if (ret_val != IXGBE_SUCCESS) 3545 goto out; 3546 3547 autoc_reg &= ~IXGBE_AUTOC_FLU; 3548 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3549 3550 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3551 if (ret_val != IXGBE_SUCCESS) 3552 goto out; 3553 3554 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3555 led_reg &= ~IXGBE_LED_BLINK(index); 3556 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3557 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3558 IXGBE_WRITE_FLUSH(hw); 3559 3560 out: 3561 return ret_val; 3562 } 3563 3564 /** 3565 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3566 * @hw: pointer to hardware structure 3567 * @san_mac_offset: SAN MAC address offset 3568 * 3569 * This function will read the EEPROM location for the SAN MAC address 3570 * pointer, and returns the value at that location. This is used in both 3571 * get and set mac_addr routines. 3572 **/ 3573 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3574 u16 *san_mac_offset) 3575 { 3576 s32 ret_val; 3577 3578 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3579 3580 /* 3581 * First read the EEPROM pointer to see if the MAC addresses are 3582 * available. 3583 */ 3584 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3585 san_mac_offset); 3586 if (ret_val) { 3587 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3588 "eeprom at offset %d failed", 3589 IXGBE_SAN_MAC_ADDR_PTR); 3590 } 3591 3592 return ret_val; 3593 } 3594 3595 /** 3596 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3597 * @hw: pointer to hardware structure 3598 * @san_mac_addr: SAN MAC address 3599 * 3600 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3601 * per-port, so set_lan_id() must be called before reading the addresses. 3602 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3603 * upon for non-SFP connections, so we must call it here. 3604 **/ 3605 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3606 { 3607 u16 san_mac_data, san_mac_offset; 3608 u8 i; 3609 s32 ret_val; 3610 3611 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3612 3613 /* 3614 * First read the EEPROM pointer to see if the MAC addresses are 3615 * available. If they're not, no point in calling set_lan_id() here. 3616 */ 3617 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3618 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3619 goto san_mac_addr_out; 3620 3621 /* make sure we know which port we need to program */ 3622 hw->mac.ops.set_lan_id(hw); 3623 /* apply the port offset to the address offset */ 3624 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3625 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3626 for (i = 0; i < 3; i++) { 3627 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3628 &san_mac_data); 3629 if (ret_val) { 3630 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3631 "eeprom read at offset %d failed", 3632 san_mac_offset); 3633 goto san_mac_addr_out; 3634 } 3635 san_mac_addr[i * 2] = (u8)(san_mac_data); 3636 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3637 san_mac_offset++; 3638 } 3639 return IXGBE_SUCCESS; 3640 3641 san_mac_addr_out: 3642 /* 3643 * No addresses available in this EEPROM. It's not an 3644 * error though, so just wipe the local address and return. 3645 */ 3646 for (i = 0; i < 6; i++) 3647 san_mac_addr[i] = 0xFF; 3648 return IXGBE_SUCCESS; 3649 } 3650 3651 /** 3652 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3653 * @hw: pointer to hardware structure 3654 * @san_mac_addr: SAN MAC address 3655 * 3656 * Write a SAN MAC address to the EEPROM. 3657 **/ 3658 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3659 { 3660 s32 ret_val; 3661 u16 san_mac_data, san_mac_offset; 3662 u8 i; 3663 3664 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3665 3666 /* Look for SAN mac address pointer. If not defined, return */ 3667 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3668 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3669 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3670 3671 /* Make sure we know which port we need to write */ 3672 hw->mac.ops.set_lan_id(hw); 3673 /* Apply the port offset to the address offset */ 3674 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3675 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3676 3677 for (i = 0; i < 3; i++) { 3678 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3679 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3680 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3681 san_mac_offset++; 3682 } 3683 3684 return IXGBE_SUCCESS; 3685 } 3686 3687 /** 3688 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3689 * @hw: pointer to hardware structure 3690 * 3691 * Read PCIe configuration space, and get the MSI-X vector count from 3692 * the capabilities table. 3693 **/ 3694 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3695 { 3696 u16 msix_count = 1; 3697 u16 max_msix_count; 3698 u16 pcie_offset; 3699 3700 switch (hw->mac.type) { 3701 case ixgbe_mac_82598EB: 3702 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3703 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3704 break; 3705 case ixgbe_mac_82599EB: 3706 case ixgbe_mac_X540: 3707 case ixgbe_mac_X550: 3708 case ixgbe_mac_X550EM_x: 3709 case ixgbe_mac_X550EM_a: 3710 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3711 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3712 break; 3713 case ixgbe_mac_E610: 3714 pcie_offset = IXGBE_PCIE_MSIX_E610_CAPS; 3715 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3716 break; 3717 default: 3718 return msix_count; 3719 } 3720 3721 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3722 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3723 if (IXGBE_REMOVED(hw->hw_addr)) 3724 msix_count = 0; 3725 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3726 3727 /* MSI-X count is zero-based in HW */ 3728 msix_count++; 3729 3730 if (msix_count > max_msix_count) 3731 msix_count = max_msix_count; 3732 3733 return msix_count; 3734 } 3735 3736 /** 3737 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3738 * @hw: pointer to hardware structure 3739 * @addr: Address to put into receive address register 3740 * @vmdq: VMDq pool to assign 3741 * 3742 * Puts an ethernet address into a receive address register, or 3743 * finds the rar that it is already in; adds to the pool list 3744 **/ 3745 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3746 { 3747 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3748 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3749 u32 rar; 3750 u32 rar_low, rar_high; 3751 u32 addr_low, addr_high; 3752 3753 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3754 3755 /* swap bytes for HW little endian */ 3756 addr_low = addr[0] | (addr[1] << 8) 3757 | (addr[2] << 16) 3758 | (addr[3] << 24); 3759 addr_high = addr[4] | (addr[5] << 8); 3760 3761 /* 3762 * Either find the mac_id in rar or find the first empty space. 3763 * rar_highwater points to just after the highest currently used 3764 * rar in order to shorten the search. It grows when we add a new 3765 * rar to the top. 3766 */ 3767 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3768 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3769 3770 if (((IXGBE_RAH_AV & rar_high) == 0) 3771 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3772 first_empty_rar = rar; 3773 } else if ((rar_high & 0xFFFF) == addr_high) { 3774 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3775 if (rar_low == addr_low) 3776 break; /* found it already in the rars */ 3777 } 3778 } 3779 3780 if (rar < hw->mac.rar_highwater) { 3781 /* already there so just add to the pool bits */ 3782 ixgbe_set_vmdq(hw, rar, vmdq); 3783 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3784 /* stick it into first empty RAR slot we found */ 3785 rar = first_empty_rar; 3786 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3787 } else if (rar == hw->mac.rar_highwater) { 3788 /* add it to the top of the list and inc the highwater mark */ 3789 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3790 hw->mac.rar_highwater++; 3791 } else if (rar >= hw->mac.num_rar_entries) { 3792 return IXGBE_ERR_INVALID_MAC_ADDR; 3793 } 3794 3795 /* 3796 * If we found rar[0], make sure the default pool bit (we use pool 0) 3797 * remains cleared to be sure default pool packets will get delivered 3798 */ 3799 if (rar == 0) 3800 ixgbe_clear_vmdq(hw, rar, 0); 3801 3802 return rar; 3803 } 3804 3805 /** 3806 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3807 * @hw: pointer to hardware struct 3808 * @rar: receive address register index to disassociate 3809 * @vmdq: VMDq pool index to remove from the rar 3810 **/ 3811 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3812 { 3813 u32 mpsar_lo, mpsar_hi; 3814 u32 rar_entries = hw->mac.num_rar_entries; 3815 3816 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3817 3818 /* Make sure we are using a valid rar index range */ 3819 if (rar >= rar_entries) { 3820 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3821 "RAR index %d is out of range.\n", rar); 3822 return IXGBE_ERR_INVALID_ARGUMENT; 3823 } 3824 3825 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3826 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3827 3828 if (IXGBE_REMOVED(hw->hw_addr)) 3829 goto done; 3830 3831 if (!mpsar_lo && !mpsar_hi) 3832 goto done; 3833 3834 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3835 if (mpsar_lo) { 3836 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3837 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3838 } 3839 if (mpsar_hi) { 3840 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3841 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3842 } 3843 } else if (vmdq < 32) { 3844 mpsar_lo &= ~(1U << vmdq); 3845 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3846 } else { 3847 mpsar_hi &= ~(1U << (vmdq - 32)); 3848 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3849 } 3850 3851 /* was that the last pool using this rar? */ 3852 if (mpsar_lo == 0 && mpsar_hi == 0 && 3853 rar != 0 && rar != hw->mac.san_mac_rar_index) 3854 hw->mac.ops.clear_rar(hw, rar); 3855 done: 3856 return IXGBE_SUCCESS; 3857 } 3858 3859 /** 3860 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3861 * @hw: pointer to hardware struct 3862 * @rar: receive address register index to associate with a VMDq index 3863 * @vmdq: VMDq pool index 3864 **/ 3865 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3866 { 3867 u32 mpsar; 3868 u32 rar_entries = hw->mac.num_rar_entries; 3869 3870 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3871 3872 /* Make sure we are using a valid rar index range */ 3873 if (rar >= rar_entries) { 3874 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3875 "RAR index %d is out of range.\n", rar); 3876 return IXGBE_ERR_INVALID_ARGUMENT; 3877 } 3878 3879 if (vmdq < 32) { 3880 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3881 mpsar |= 1U << vmdq; 3882 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3883 } else { 3884 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3885 mpsar |= 1U << (vmdq - 32); 3886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3887 } 3888 return IXGBE_SUCCESS; 3889 } 3890 3891 /** 3892 * ixgbe_set_vmdq_san_mac_generic - Associate default VMDq pool index with 3893 * a rx address 3894 * @hw: pointer to hardware struct 3895 * @vmdq: VMDq pool index 3896 * 3897 * This function should only be involved in the IOV mode. 3898 * In IOV mode, Default pool is next pool after the number of 3899 * VFs advertized and not 0. 3900 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3901 **/ 3902 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3903 { 3904 u32 rar = hw->mac.san_mac_rar_index; 3905 3906 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3907 3908 if (vmdq < 32) { 3909 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1U << vmdq); 3910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3911 } else { 3912 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3913 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1U << (vmdq - 32)); 3914 } 3915 3916 return IXGBE_SUCCESS; 3917 } 3918 3919 /** 3920 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3921 * @hw: pointer to hardware structure 3922 **/ 3923 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3924 { 3925 int i; 3926 3927 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3928 DEBUGOUT(" Clearing UTA\n"); 3929 3930 for (i = 0; i < 128; i++) 3931 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3932 3933 return IXGBE_SUCCESS; 3934 } 3935 3936 /** 3937 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3938 * @hw: pointer to hardware structure 3939 * @vlan: VLAN id to write to VLAN filter 3940 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 3941 * vlanid not found 3942 * 3943 * 3944 * return the VLVF index where this VLAN id should be placed 3945 * 3946 **/ 3947 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3948 { 3949 s32 regindex, first_empty_slot; 3950 u32 bits; 3951 3952 /* short cut the special case */ 3953 if (vlan == 0) 3954 return 0; 3955 3956 /* if vlvf_bypass is set we don't want to use an empty slot, we 3957 * will simply bypass the VLVF if there are no entries present in the 3958 * VLVF that contain our VLAN 3959 */ 3960 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3961 3962 /* add VLAN enable bit for comparison */ 3963 vlan |= IXGBE_VLVF_VIEN; 3964 3965 /* Search for the vlan id in the VLVF entries. Save off the first empty 3966 * slot found along the way. 3967 * 3968 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3969 */ 3970 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3971 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3972 if (bits == vlan) 3973 return regindex; 3974 if (!first_empty_slot && !bits) 3975 first_empty_slot = regindex; 3976 } 3977 3978 /* If we are here then we didn't find the VLAN. Return first empty 3979 * slot we found during our search, else error. 3980 */ 3981 if (!first_empty_slot) 3982 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3983 3984 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3985 } 3986 3987 /** 3988 * ixgbe_set_vfta_generic - Set VLAN filter table 3989 * @hw: pointer to hardware structure 3990 * @vlan: VLAN id to write to VLAN filter 3991 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3992 * @vlan_on: boolean flag to turn on/off VLAN 3993 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3994 * 3995 * Turn on/off specified VLAN in the VLAN filter table. 3996 **/ 3997 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3998 bool vlan_on, bool vlvf_bypass) 3999 { 4000 u32 regidx, vfta_delta, vfta; 4001 s32 ret_val; 4002 4003 DEBUGFUNC("ixgbe_set_vfta_generic"); 4004 4005 if (vlan > 4095 || vind > 63) 4006 return IXGBE_ERR_PARAM; 4007 4008 /* 4009 * this is a 2 part operation - first the VFTA, then the 4010 * VLVF and VLVFB if VT Mode is set 4011 * We don't write the VFTA until we know the VLVF part succeeded. 4012 */ 4013 4014 /* Part 1 4015 * The VFTA is a bitstring made up of 128 32-bit registers 4016 * that enable the particular VLAN id, much like the MTA: 4017 * bits[11-5]: which register 4018 * bits[4-0]: which bit in the register 4019 */ 4020 regidx = vlan / 32; 4021 vfta_delta = 1U << (vlan % 32); 4022 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 4023 4024 /* 4025 * vfta_delta represents the difference between the current value 4026 * of vfta and the value we want in the register. Since the diff 4027 * is an XOR mask we can just update the vfta using an XOR 4028 */ 4029 vfta_delta &= vlan_on ? ~vfta : vfta; 4030 vfta ^= vfta_delta; 4031 4032 /* Part 2 4033 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4034 */ 4035 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4036 vfta, vlvf_bypass); 4037 if (ret_val != IXGBE_SUCCESS) { 4038 if (vlvf_bypass) 4039 goto vfta_update; 4040 return ret_val; 4041 } 4042 4043 vfta_update: 4044 /* Update VFTA now that we are ready for traffic */ 4045 if (vfta_delta) 4046 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4047 4048 return IXGBE_SUCCESS; 4049 } 4050 4051 /** 4052 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4053 * @hw: pointer to hardware structure 4054 * @vlan: VLAN id to write to VLAN filter 4055 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4056 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4057 * @vfta_delta: pointer to the difference between the current value of VFTA 4058 * and the desired value 4059 * @vfta: the desired value of the VFTA 4060 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4061 * 4062 * Turn on/off specified bit in VLVF table. 4063 **/ 4064 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4065 bool vlan_on, u32 *vfta_delta, u32 vfta, 4066 bool vlvf_bypass) 4067 { 4068 u32 bits; 4069 s32 vlvf_index; 4070 4071 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4072 4073 if (vlan > 4095 || vind > 63) 4074 return IXGBE_ERR_PARAM; 4075 4076 /* If VT Mode is set 4077 * Either vlan_on 4078 * make sure the vlan is in VLVF 4079 * set the vind bit in the matching VLVFB 4080 * Or !vlan_on 4081 * clear the pool bit and possibly the vind 4082 */ 4083 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4084 return IXGBE_SUCCESS; 4085 4086 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4087 if (vlvf_index < 0) 4088 return vlvf_index; 4089 4090 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4091 4092 /* set the pool bit */ 4093 bits |= 1U << (vind % 32); 4094 if (vlan_on) 4095 goto vlvf_update; 4096 4097 /* clear the pool bit */ 4098 bits ^= 1U << (vind % 32); 4099 4100 if (!bits && 4101 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4102 /* Clear VFTA first, then disable VLVF. Otherwise 4103 * we run the risk of stray packets leaking into 4104 * the PF via the default pool 4105 */ 4106 if (*vfta_delta) 4107 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4108 4109 /* disable VLVF and clear remaining bit from pool */ 4110 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4111 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4112 4113 return IXGBE_SUCCESS; 4114 } 4115 4116 /* If there are still bits set in the VLVFB registers 4117 * for the VLAN ID indicated we need to see if the 4118 * caller is requesting that we clear the VFTA entry bit. 4119 * If the caller has requested that we clear the VFTA 4120 * entry bit but there are still pools/VFs using this VLAN 4121 * ID entry then ignore the request. We're not worried 4122 * about the case where we're turning the VFTA VLAN ID 4123 * entry bit on, only when requested to turn it off as 4124 * there may be multiple pools and/or VFs using the 4125 * VLAN ID entry. In that case we cannot clear the 4126 * VFTA bit until all pools/VFs using that VLAN ID have also 4127 * been cleared. This will be indicated by "bits" being 4128 * zero. 4129 */ 4130 *vfta_delta = 0; 4131 4132 vlvf_update: 4133 /* record pool change and enable VLAN ID if not already enabled */ 4134 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4135 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4136 4137 return IXGBE_SUCCESS; 4138 } 4139 4140 /** 4141 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4142 * @hw: pointer to hardware structure 4143 * 4144 * Clears the VLAN filter table, and the VMDq index associated with the filter 4145 **/ 4146 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4147 { 4148 u32 offset; 4149 4150 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4151 4152 for (offset = 0; offset < hw->mac.vft_size; offset++) 4153 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4154 4155 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4156 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4157 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4158 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 4159 } 4160 4161 return IXGBE_SUCCESS; 4162 } 4163 4164 /** 4165 * ixgbe_toggle_txdctl_generic - Toggle VF's queues 4166 * @hw: pointer to hardware structure 4167 * @vf_number: VF number 4168 * 4169 * Enable and disable each queue in VF. 4170 */ 4171 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number) 4172 { 4173 u8 queue_count, i; 4174 u32 offset, reg; 4175 4176 if (vf_number > 63) 4177 return IXGBE_ERR_PARAM; 4178 4179 /* 4180 * Determine number of queues by checking 4181 * number of virtual functions 4182 */ 4183 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4184 switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) { 4185 case IXGBE_GCR_EXT_VT_MODE_64: 4186 queue_count = 2; 4187 break; 4188 case IXGBE_GCR_EXT_VT_MODE_32: 4189 queue_count = 4; 4190 break; 4191 case IXGBE_GCR_EXT_VT_MODE_16: 4192 queue_count = 8; 4193 break; 4194 default: 4195 return IXGBE_ERR_CONFIG; 4196 } 4197 4198 /* Toggle queues */ 4199 for (i = 0; i < queue_count; ++i) { 4200 /* Calculate offset of current queue */ 4201 offset = queue_count * vf_number + i; 4202 4203 /* Enable queue */ 4204 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4205 reg |= IXGBE_TXDCTL_ENABLE; 4206 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4207 IXGBE_WRITE_FLUSH(hw); 4208 4209 /* Disable queue */ 4210 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4211 reg &= ~IXGBE_TXDCTL_ENABLE; 4212 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4213 IXGBE_WRITE_FLUSH(hw); 4214 } 4215 4216 return IXGBE_SUCCESS; 4217 } 4218 4219 /** 4220 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4221 * @hw: pointer to hardware structure 4222 * 4223 * Contains the logic to identify if we need to verify link for the 4224 * crosstalk fix 4225 **/ 4226 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4227 { 4228 4229 /* Does FW say we need the fix */ 4230 if (!hw->need_crosstalk_fix) 4231 return false; 4232 4233 /* Only consider SFP+ PHYs i.e. media type fiber */ 4234 switch (hw->mac.ops.get_media_type(hw)) { 4235 case ixgbe_media_type_fiber: 4236 case ixgbe_media_type_fiber_qsfp: 4237 break; 4238 default: 4239 return false; 4240 } 4241 4242 return true; 4243 } 4244 4245 /** 4246 * ixgbe_check_mac_link_generic - Determine link and speed status 4247 * @hw: pointer to hardware structure 4248 * @speed: pointer to link speed 4249 * @link_up: true when link is up 4250 * @link_up_wait_to_complete: bool used to wait for link up or not 4251 * 4252 * Reads the links register to determine if link is up and the current speed 4253 **/ 4254 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4255 bool *link_up, bool link_up_wait_to_complete) 4256 { 4257 u32 links_reg, links_orig; 4258 u32 i; 4259 4260 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4261 4262 /* If Crosstalk fix enabled do the sanity check of making sure 4263 * the SFP+ cage is full. 4264 */ 4265 if (ixgbe_need_crosstalk_fix(hw)) { 4266 u32 sfp_cage_full; 4267 4268 switch (hw->mac.type) { 4269 case ixgbe_mac_82599EB: 4270 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4271 IXGBE_ESDP_SDP2; 4272 break; 4273 case ixgbe_mac_X550EM_x: 4274 case ixgbe_mac_X550EM_a: 4275 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4276 IXGBE_ESDP_SDP0; 4277 break; 4278 default: 4279 /* sanity check - No SFP+ devices here */ 4280 sfp_cage_full = false; 4281 break; 4282 } 4283 4284 if (!sfp_cage_full) { 4285 *link_up = false; 4286 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4287 return IXGBE_SUCCESS; 4288 } 4289 } 4290 4291 /* clear the old state */ 4292 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4293 4294 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4295 4296 if (links_orig != links_reg) { 4297 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4298 links_orig, links_reg); 4299 } 4300 4301 if (link_up_wait_to_complete) { 4302 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4303 if (links_reg & IXGBE_LINKS_UP) { 4304 *link_up = true; 4305 break; 4306 } else { 4307 *link_up = false; 4308 } 4309 msec_delay(100); 4310 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4311 } 4312 } else { 4313 if (links_reg & IXGBE_LINKS_UP) { 4314 if (ixgbe_need_crosstalk_fix(hw)) { 4315 /* Check the link state again after a delay 4316 * to filter out spurious link up 4317 * notifications. 4318 */ 4319 msec_delay(5); 4320 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4321 if (!(links_reg & IXGBE_LINKS_UP)) { 4322 *link_up = false; 4323 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4324 return IXGBE_SUCCESS; 4325 } 4326 4327 } 4328 *link_up = true; 4329 } else { 4330 *link_up = false; 4331 } 4332 } 4333 4334 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4335 case IXGBE_LINKS_SPEED_10G_82599: 4336 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4337 if (hw->mac.type >= ixgbe_mac_X550) { 4338 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4339 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4340 } 4341 break; 4342 case IXGBE_LINKS_SPEED_1G_82599: 4343 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4344 break; 4345 case IXGBE_LINKS_SPEED_100_82599: 4346 *speed = IXGBE_LINK_SPEED_100_FULL; 4347 if (hw->mac.type == ixgbe_mac_X550 || 4348 hw->mac.type == ixgbe_mac_E610) { 4349 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4350 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4351 } 4352 break; 4353 case IXGBE_LINKS_SPEED_10_X550EM_A: 4354 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4355 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4356 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4357 *speed = IXGBE_LINK_SPEED_10_FULL; 4358 break; 4359 default: 4360 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4361 } 4362 4363 return IXGBE_SUCCESS; 4364 } 4365 4366 /** 4367 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4368 * the EEPROM 4369 * @hw: pointer to hardware structure 4370 * @wwnn_prefix: the alternative WWNN prefix 4371 * @wwpn_prefix: the alternative WWPN prefix 4372 * 4373 * This function will read the EEPROM from the alternative SAN MAC address 4374 * block to check the support for the alternative WWNN/WWPN prefix support. 4375 **/ 4376 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4377 u16 *wwpn_prefix) 4378 { 4379 u16 offset, caps; 4380 u16 alt_san_mac_blk_offset; 4381 4382 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4383 4384 /* clear output first */ 4385 *wwnn_prefix = 0xFFFF; 4386 *wwpn_prefix = 0xFFFF; 4387 4388 /* check if alternative SAN MAC is supported */ 4389 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4390 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4391 goto wwn_prefix_err; 4392 4393 if ((alt_san_mac_blk_offset == 0) || 4394 (alt_san_mac_blk_offset == 0xFFFF)) 4395 goto wwn_prefix_out; 4396 4397 /* check capability in alternative san mac address block */ 4398 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4399 if (hw->eeprom.ops.read(hw, offset, &caps)) 4400 goto wwn_prefix_err; 4401 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4402 goto wwn_prefix_out; 4403 4404 /* get the corresponding prefix for WWNN/WWPN */ 4405 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4406 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4407 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4408 "eeprom read at offset %d failed", offset); 4409 } 4410 4411 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4412 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4413 goto wwn_prefix_err; 4414 4415 wwn_prefix_out: 4416 return IXGBE_SUCCESS; 4417 4418 wwn_prefix_err: 4419 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4420 "eeprom read at offset %d failed", offset); 4421 return IXGBE_SUCCESS; 4422 } 4423 4424 /** 4425 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4426 * @hw: pointer to hardware structure 4427 * @bs: the fcoe boot status 4428 * 4429 * This function will read the FCOE boot status from the iSCSI FCOE block 4430 **/ 4431 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4432 { 4433 u16 offset, caps, flags; 4434 s32 status; 4435 4436 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4437 4438 /* clear output first */ 4439 *bs = ixgbe_fcoe_bootstatus_unavailable; 4440 4441 /* check if FCOE IBA block is present */ 4442 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4443 status = hw->eeprom.ops.read(hw, offset, &caps); 4444 if (status != IXGBE_SUCCESS) 4445 goto out; 4446 4447 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4448 goto out; 4449 4450 /* check if iSCSI FCOE block is populated */ 4451 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4452 if (status != IXGBE_SUCCESS) 4453 goto out; 4454 4455 if ((offset == 0) || (offset == 0xFFFF)) 4456 goto out; 4457 4458 /* read fcoe flags in iSCSI FCOE block */ 4459 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4460 status = hw->eeprom.ops.read(hw, offset, &flags); 4461 if (status != IXGBE_SUCCESS) 4462 goto out; 4463 4464 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4465 *bs = ixgbe_fcoe_bootstatus_enabled; 4466 else 4467 *bs = ixgbe_fcoe_bootstatus_disabled; 4468 4469 out: 4470 return status; 4471 } 4472 4473 /** 4474 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4475 * @hw: pointer to hardware structure 4476 * @enable: enable or disable switch for MAC anti-spoofing 4477 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4478 * 4479 **/ 4480 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4481 { 4482 int vf_target_reg = vf >> 3; 4483 int vf_target_shift = vf % 8; 4484 u32 pfvfspoof; 4485 4486 if (hw->mac.type == ixgbe_mac_82598EB) 4487 return; 4488 4489 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4490 if (enable) 4491 pfvfspoof |= (1 << vf_target_shift); 4492 else 4493 pfvfspoof &= ~(1 << vf_target_shift); 4494 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4495 } 4496 4497 /** 4498 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4499 * @hw: pointer to hardware structure 4500 * @enable: enable or disable switch for VLAN anti-spoofing 4501 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4502 * 4503 **/ 4504 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4505 { 4506 int vf_target_reg = vf >> 3; 4507 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4508 u32 pfvfspoof; 4509 4510 if (hw->mac.type == ixgbe_mac_82598EB) 4511 return; 4512 4513 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4514 if (enable) 4515 pfvfspoof |= (1 << vf_target_shift); 4516 else 4517 pfvfspoof &= ~(1 << vf_target_shift); 4518 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4519 } 4520 4521 /** 4522 * ixgbe_get_device_caps_generic - Get additional device capabilities 4523 * @hw: pointer to hardware structure 4524 * @device_caps: the EEPROM word with the extra device capabilities 4525 * 4526 * This function will read the EEPROM location for the device capabilities, 4527 * and return the word through device_caps. 4528 **/ 4529 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4530 { 4531 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4532 4533 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4534 4535 return IXGBE_SUCCESS; 4536 } 4537 4538 /** 4539 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4540 * @hw: pointer to hardware structure 4541 * 4542 **/ 4543 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4544 { 4545 u32 regval; 4546 u32 i; 4547 4548 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4549 4550 /* Enable relaxed ordering */ 4551 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4552 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4553 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4554 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4555 } 4556 4557 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4558 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4559 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4560 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4561 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4562 } 4563 4564 } 4565 4566 /** 4567 * ixgbe_calculate_checksum - Calculate checksum for buffer 4568 * @buffer: pointer to EEPROM 4569 * @length: size of EEPROM to calculate a checksum for 4570 * Calculates the checksum for some buffer on a specified length. The 4571 * checksum calculated is returned. 4572 **/ 4573 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4574 { 4575 u32 i; 4576 u8 sum = 0; 4577 4578 DEBUGFUNC("ixgbe_calculate_checksum"); 4579 4580 if (!buffer) 4581 return 0; 4582 4583 for (i = 0; i < length; i++) 4584 sum += buffer[i]; 4585 4586 return (u8) (0 - sum); 4587 } 4588 4589 /** 4590 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4591 * @hw: pointer to the HW structure 4592 * @buffer: command to write and where the return status will be placed 4593 * @length: length of buffer, must be multiple of 4 bytes 4594 * @timeout: time in ms to wait for command completion 4595 * 4596 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4597 * else returns semaphore error when encountering an error acquiring 4598 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4599 * 4600 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4601 * by the caller. 4602 **/ 4603 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4604 u32 timeout) 4605 { 4606 u32 hicr, i, fwsts; 4607 u16 dword_len; 4608 4609 DEBUGFUNC("ixgbe_hic_unlocked"); 4610 4611 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4612 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4613 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4614 } 4615 4616 /* Set bit 9 of FWSTS clearing FW reset indication */ 4617 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4618 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4619 4620 /* Check that the host interface is enabled. */ 4621 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4622 if (!(hicr & IXGBE_HICR_EN)) { 4623 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4624 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4625 } 4626 4627 /* Calculate length in DWORDs. We must be DWORD aligned */ 4628 if (length % sizeof(u32)) { 4629 DEBUGOUT("Buffer length failure, not aligned to dword"); 4630 return IXGBE_ERR_INVALID_ARGUMENT; 4631 } 4632 4633 dword_len = length >> 2; 4634 4635 /* The device driver writes the relevant command block 4636 * into the ram area. 4637 */ 4638 for (i = 0; i < dword_len; i++) 4639 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4640 i, IXGBE_CPU_TO_LE32(buffer[i])); 4641 4642 /* Setting this bit tells the ARC that a new command is pending. */ 4643 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4644 4645 for (i = 0; i < timeout * 1000; i++) { 4646 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4647 if (!(hicr & IXGBE_HICR_C)) 4648 break; 4649 usec_delay(1); 4650 } 4651 4652 /* For each command except "Apply Update" perform 4653 * status checks in the HICR registry. 4654 */ 4655 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) == 4656 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD) 4657 return IXGBE_SUCCESS; 4658 4659 /* Check command completion */ 4660 if ((timeout && i == timeout * 1000) || 4661 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4662 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4663 "Command has failed with no status valid.\n"); 4664 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4665 } 4666 4667 return IXGBE_SUCCESS; 4668 } 4669 4670 /** 4671 * ixgbe_host_interface_command - Issue command to manageability block 4672 * @hw: pointer to the HW structure 4673 * @buffer: contains the command to write and where the return status will 4674 * be placed 4675 * @length: length of buffer, must be multiple of 4 bytes 4676 * @timeout: time in ms to wait for command completion 4677 * @return_data: read and return data from the buffer (true) or not (false) 4678 * Needed because FW structures are big endian and decoding of 4679 * these fields can be 8 bit or 16 bit based on command. Decoding 4680 * is not easily understood without making a table of commands. 4681 * So we will leave this up to the caller to read back the data 4682 * in these cases. 4683 * 4684 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4685 * else returns semaphore error when encountering an error acquiring 4686 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4687 **/ 4688 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4689 u32 length, u32 timeout, bool return_data) 4690 { 4691 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4692 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4693 u16 buf_len; 4694 s32 status; 4695 u32 bi; 4696 u32 dword_len; 4697 4698 DEBUGFUNC("ixgbe_host_interface_command"); 4699 4700 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4701 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4702 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4703 } 4704 4705 /* Take management host interface semaphore */ 4706 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4707 if (status) 4708 return status; 4709 4710 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4711 if (status) 4712 goto rel_out; 4713 4714 if (!return_data) 4715 goto rel_out; 4716 4717 /* Calculate length in DWORDs */ 4718 dword_len = hdr_size >> 2; 4719 4720 /* first pull in the header so we know the buffer length */ 4721 for (bi = 0; bi < dword_len; bi++) { 4722 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4723 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4724 } 4725 4726 /* 4727 * If there is any thing in data position pull it in 4728 * Read Flash command requires reading buffer length from 4729 * two byes instead of one byte 4730 */ 4731 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD || 4732 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) { 4733 for (; bi < dword_len + 2; bi++) { 4734 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4735 bi); 4736 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4737 } 4738 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4739 & 0xF00) | resp->buf_len; 4740 hdr_size += (2 << 2); 4741 } else { 4742 buf_len = resp->buf_len; 4743 } 4744 if (!buf_len) 4745 goto rel_out; 4746 4747 if (length < buf_len + hdr_size) { 4748 DEBUGOUT("Buffer not large enough for reply message.\n"); 4749 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4750 goto rel_out; 4751 } 4752 4753 /* Calculate length in DWORDs, add 3 for odd lengths */ 4754 dword_len = (buf_len + 3) >> 2; 4755 4756 /* Pull in the rest of the buffer (bi is where we left off) */ 4757 for (; bi <= dword_len; bi++) { 4758 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4759 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4760 } 4761 4762 rel_out: 4763 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4764 4765 return status; 4766 } 4767 4768 /** 4769 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4770 * @hw: pointer to the HW structure 4771 * @maj: driver version major number 4772 * @min: driver version minor number 4773 * @build: driver version build number 4774 * @sub: driver version sub build number 4775 * @len: unused 4776 * @driver_ver: unused 4777 * 4778 * Sends driver version number to firmware through the manageability 4779 * block. On success return IXGBE_SUCCESS 4780 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4781 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4782 **/ 4783 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4784 u8 build, u8 sub, u16 len, 4785 const char *driver_ver) 4786 { 4787 struct ixgbe_hic_drv_info fw_cmd; 4788 int i; 4789 s32 ret_val = IXGBE_SUCCESS; 4790 4791 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4792 UNREFERENCED_2PARAMETER(len, driver_ver); 4793 4794 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4795 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4796 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4797 fw_cmd.port_num = (u8)hw->bus.func; 4798 fw_cmd.ver_maj = maj; 4799 fw_cmd.ver_min = min; 4800 fw_cmd.ver_build = build; 4801 fw_cmd.ver_sub = sub; 4802 fw_cmd.hdr.checksum = 0; 4803 fw_cmd.pad = 0; 4804 fw_cmd.pad2 = 0; 4805 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4806 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4807 4808 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4809 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4810 sizeof(fw_cmd), 4811 IXGBE_HI_COMMAND_TIMEOUT, 4812 true); 4813 if (ret_val != IXGBE_SUCCESS) 4814 continue; 4815 4816 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4817 FW_CEM_RESP_STATUS_SUCCESS) 4818 ret_val = IXGBE_SUCCESS; 4819 else 4820 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4821 4822 break; 4823 } 4824 4825 return ret_val; 4826 } 4827 4828 /** 4829 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4830 * @hw: pointer to hardware structure 4831 * @num_pb: number of packet buffers to allocate 4832 * @headroom: reserve n KB of headroom 4833 * @strategy: packet buffer allocation strategy 4834 **/ 4835 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4836 int strategy) 4837 { 4838 u32 pbsize = hw->mac.rx_pb_size; 4839 int i = 0; 4840 u32 rxpktsize, txpktsize, txpbthresh; 4841 4842 /* Reserve headroom */ 4843 pbsize -= headroom; 4844 4845 if (!num_pb) 4846 num_pb = 1; 4847 4848 /* Divide remaining packet buffer space amongst the number of packet 4849 * buffers requested using supplied strategy. 4850 */ 4851 switch (strategy) { 4852 case PBA_STRATEGY_WEIGHTED: 4853 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4854 * buffer with 5/8 of the packet buffer space. 4855 */ 4856 rxpktsize = (pbsize * 5) / (num_pb * 4); 4857 pbsize -= rxpktsize * (num_pb / 2); 4858 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4859 for (; i < (num_pb / 2); i++) 4860 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4861 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4862 for (; i < num_pb; i++) 4863 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4864 break; 4865 case PBA_STRATEGY_EQUAL: 4866 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4867 for (; i < num_pb; i++) 4868 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4869 break; 4870 default: 4871 break; 4872 } 4873 4874 /* Only support an equally distributed Tx packet buffer strategy. */ 4875 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4876 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4877 for (i = 0; i < num_pb; i++) { 4878 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4879 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4880 } 4881 4882 /* Clear unused TCs, if any, to zero buffer size*/ 4883 for (; i < IXGBE_MAX_PB; i++) { 4884 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4885 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4886 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4887 } 4888 } 4889 4890 /** 4891 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4892 * @hw: pointer to the hardware structure 4893 * 4894 * The 82599 and x540 MACs can experience issues if TX work is still pending 4895 * when a reset occurs. This function prevents this by flushing the PCIe 4896 * buffers on the system. 4897 **/ 4898 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4899 { 4900 u32 gcr_ext, hlreg0, i, poll; 4901 u16 value; 4902 4903 /* 4904 * If double reset is not requested then all transactions should 4905 * already be clear and as such there is no work to do 4906 */ 4907 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4908 return; 4909 4910 /* 4911 * Set loopback enable to prevent any transmits from being sent 4912 * should the link come up. This assumes that the RXCTRL.RXEN bit 4913 * has already been cleared. 4914 */ 4915 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4916 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4917 4918 /* Wait for a last completion before clearing buffers */ 4919 IXGBE_WRITE_FLUSH(hw); 4920 msec_delay(3); 4921 4922 /* 4923 * Before proceeding, make sure that the PCIe block does not have 4924 * transactions pending. 4925 */ 4926 poll = ixgbe_pcie_timeout_poll(hw); 4927 for (i = 0; i < poll; i++) { 4928 usec_delay(100); 4929 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4930 if (IXGBE_REMOVED(hw->hw_addr)) 4931 goto out; 4932 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4933 goto out; 4934 } 4935 4936 out: 4937 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4938 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4939 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4940 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4941 4942 /* Flush all writes and allow 20usec for all transactions to clear */ 4943 IXGBE_WRITE_FLUSH(hw); 4944 usec_delay(20); 4945 4946 /* restore previous register values */ 4947 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4948 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4949 } 4950 4951 static const u8 ixgbe_emc_temp_data[4] = { 4952 IXGBE_EMC_INTERNAL_DATA, 4953 IXGBE_EMC_DIODE1_DATA, 4954 IXGBE_EMC_DIODE2_DATA, 4955 IXGBE_EMC_DIODE3_DATA 4956 }; 4957 static const u8 ixgbe_emc_therm_limit[4] = { 4958 IXGBE_EMC_INTERNAL_THERM_LIMIT, 4959 IXGBE_EMC_DIODE1_THERM_LIMIT, 4960 IXGBE_EMC_DIODE2_THERM_LIMIT, 4961 IXGBE_EMC_DIODE3_THERM_LIMIT 4962 }; 4963 4964 /** 4965 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data 4966 * @hw: pointer to hardware structure 4967 * 4968 * Returns the thermal sensor data structure 4969 **/ 4970 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 4971 { 4972 s32 status = IXGBE_SUCCESS; 4973 u16 ets_offset; 4974 u16 ets_cfg; 4975 u16 ets_sensor; 4976 u8 num_sensors; 4977 u8 sensor_index; 4978 u8 sensor_location; 4979 u8 i; 4980 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 4981 4982 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic"); 4983 4984 /* Only support thermal sensors attached to 82599 physical port 0 */ 4985 if ((hw->mac.type != ixgbe_mac_82599EB) || 4986 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) { 4987 status = IXGBE_NOT_IMPLEMENTED; 4988 goto out; 4989 } 4990 4991 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset); 4992 if (status) 4993 goto out; 4994 4995 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) { 4996 status = IXGBE_NOT_IMPLEMENTED; 4997 goto out; 4998 } 4999 5000 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg); 5001 if (status) 5002 goto out; 5003 5004 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 5005 != IXGBE_ETS_TYPE_EMC) { 5006 status = IXGBE_NOT_IMPLEMENTED; 5007 goto out; 5008 } 5009 5010 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 5011 if (num_sensors > IXGBE_MAX_SENSORS) 5012 num_sensors = IXGBE_MAX_SENSORS; 5013 5014 for (i = 0; i < num_sensors; i++) { 5015 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 5016 &ets_sensor); 5017 if (status) 5018 goto out; 5019 5020 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 5021 IXGBE_ETS_DATA_INDEX_SHIFT); 5022 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 5023 IXGBE_ETS_DATA_LOC_SHIFT); 5024 5025 if (sensor_location != 0) { 5026 status = hw->phy.ops.read_i2c_byte(hw, 5027 ixgbe_emc_temp_data[sensor_index], 5028 IXGBE_I2C_THERMAL_SENSOR_ADDR, 5029 &data->sensor[i].temp); 5030 if (status) 5031 goto out; 5032 } 5033 } 5034 out: 5035 return status; 5036 } 5037 5038 /** 5039 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 5040 * @hw: pointer to hardware structure 5041 * 5042 * Inits the thermal sensor thresholds according to the NVM map 5043 * and save off the threshold and location values into mac.thermal_sensor_data 5044 **/ 5045 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 5046 { 5047 s32 status = IXGBE_SUCCESS; 5048 u16 offset; 5049 u16 ets_offset; 5050 u16 ets_cfg; 5051 u16 ets_sensor; 5052 u8 low_thresh_delta; 5053 u8 num_sensors; 5054 u8 sensor_index; 5055 u8 sensor_location; 5056 u8 therm_limit; 5057 u8 i; 5058 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 5059 5060 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic"); 5061 5062 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 5063 5064 /* Only support thermal sensors attached to 82599 physical port 0 */ 5065 if ((hw->mac.type != ixgbe_mac_82599EB) || 5066 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 5067 return IXGBE_NOT_IMPLEMENTED; 5068 5069 offset = IXGBE_ETS_CFG; 5070 if (hw->eeprom.ops.read(hw, offset, &ets_offset)) 5071 goto eeprom_err; 5072 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 5073 return IXGBE_NOT_IMPLEMENTED; 5074 5075 offset = ets_offset; 5076 if (hw->eeprom.ops.read(hw, offset, &ets_cfg)) 5077 goto eeprom_err; 5078 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 5079 != IXGBE_ETS_TYPE_EMC) 5080 return IXGBE_NOT_IMPLEMENTED; 5081 5082 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 5083 IXGBE_ETS_LTHRES_DELTA_SHIFT); 5084 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 5085 5086 for (i = 0; i < num_sensors; i++) { 5087 offset = ets_offset + 1 + i; 5088 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) { 5089 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 5090 "eeprom read at offset %d failed", 5091 offset); 5092 continue; 5093 } 5094 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 5095 IXGBE_ETS_DATA_INDEX_SHIFT); 5096 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 5097 IXGBE_ETS_DATA_LOC_SHIFT); 5098 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 5099 5100 hw->phy.ops.write_i2c_byte(hw, 5101 ixgbe_emc_therm_limit[sensor_index], 5102 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 5103 5104 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) { 5105 data->sensor[i].location = sensor_location; 5106 data->sensor[i].caution_thresh = therm_limit; 5107 data->sensor[i].max_op_thresh = therm_limit - 5108 low_thresh_delta; 5109 } 5110 } 5111 return status; 5112 5113 eeprom_err: 5114 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 5115 "eeprom read at offset %d failed", offset); 5116 return IXGBE_NOT_IMPLEMENTED; 5117 } 5118 5119 /** 5120 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 5121 * 5122 * @hw: pointer to hardware structure 5123 * @cmd: Command we send to the FW 5124 * @status: The reply from the FW 5125 * 5126 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 5127 **/ 5128 #define IXGBE_BYPASS_BB_WAIT 1 5129 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 5130 { 5131 int i; 5132 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 5133 u32 esdp; 5134 5135 if (!status) 5136 return IXGBE_ERR_PARAM; 5137 5138 *status = 0; 5139 5140 /* SDP vary by MAC type */ 5141 switch (hw->mac.type) { 5142 case ixgbe_mac_82599EB: 5143 sck = IXGBE_ESDP_SDP7; 5144 sdi = IXGBE_ESDP_SDP0; 5145 sdo = IXGBE_ESDP_SDP6; 5146 dir_sck = IXGBE_ESDP_SDP7_DIR; 5147 dir_sdi = IXGBE_ESDP_SDP0_DIR; 5148 dir_sdo = IXGBE_ESDP_SDP6_DIR; 5149 break; 5150 case ixgbe_mac_X540: 5151 sck = IXGBE_ESDP_SDP2; 5152 sdi = IXGBE_ESDP_SDP0; 5153 sdo = IXGBE_ESDP_SDP1; 5154 dir_sck = IXGBE_ESDP_SDP2_DIR; 5155 dir_sdi = IXGBE_ESDP_SDP0_DIR; 5156 dir_sdo = IXGBE_ESDP_SDP1_DIR; 5157 break; 5158 default: 5159 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 5160 } 5161 5162 /* Set SDP pins direction */ 5163 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5164 esdp |= dir_sck; /* SCK as output */ 5165 esdp |= dir_sdi; /* SDI as output */ 5166 esdp &= ~dir_sdo; /* SDO as input */ 5167 esdp |= sck; 5168 esdp |= sdi; 5169 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5170 IXGBE_WRITE_FLUSH(hw); 5171 msec_delay(IXGBE_BYPASS_BB_WAIT); 5172 5173 /* Generate start condition */ 5174 esdp &= ~sdi; 5175 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5176 IXGBE_WRITE_FLUSH(hw); 5177 msec_delay(IXGBE_BYPASS_BB_WAIT); 5178 5179 esdp &= ~sck; 5180 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5181 IXGBE_WRITE_FLUSH(hw); 5182 msec_delay(IXGBE_BYPASS_BB_WAIT); 5183 5184 /* Clock out the new control word and clock in the status */ 5185 for (i = 0; i < 32; i++) { 5186 if ((cmd >> (31 - i)) & 0x01) { 5187 esdp |= sdi; 5188 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5189 } else { 5190 esdp &= ~sdi; 5191 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5192 } 5193 IXGBE_WRITE_FLUSH(hw); 5194 msec_delay(IXGBE_BYPASS_BB_WAIT); 5195 5196 esdp |= sck; 5197 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5198 IXGBE_WRITE_FLUSH(hw); 5199 msec_delay(IXGBE_BYPASS_BB_WAIT); 5200 5201 esdp &= ~sck; 5202 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5203 IXGBE_WRITE_FLUSH(hw); 5204 msec_delay(IXGBE_BYPASS_BB_WAIT); 5205 5206 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5207 if (esdp & sdo) 5208 *status = (*status << 1) | 0x01; 5209 else 5210 *status = (*status << 1) | 0x00; 5211 msec_delay(IXGBE_BYPASS_BB_WAIT); 5212 } 5213 5214 /* stop condition */ 5215 esdp |= sck; 5216 esdp &= ~sdi; 5217 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5218 IXGBE_WRITE_FLUSH(hw); 5219 msec_delay(IXGBE_BYPASS_BB_WAIT); 5220 5221 esdp |= sdi; 5222 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5223 IXGBE_WRITE_FLUSH(hw); 5224 5225 /* set the page bits to match the cmd that the status it belongs to */ 5226 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 5227 5228 return IXGBE_SUCCESS; 5229 } 5230 5231 /** 5232 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 5233 * @in_reg: The register cmd for the bit-bang read. 5234 * @out_reg: The register returned from a bit-bang read. 5235 * 5236 * If we send a write we can't be sure it took until we can read back 5237 * that same register. It can be a problem as some of the fields may 5238 * for valid reasons change inbetween the time wrote the register and 5239 * we read it again to verify. So this function check everything we 5240 * can check and then assumes it worked. 5241 **/ 5242 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 5243 { 5244 u32 mask; 5245 5246 /* Page must match for all control pages */ 5247 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 5248 return false; 5249 5250 switch (in_reg & BYPASS_PAGE_M) { 5251 case BYPASS_PAGE_CTL0: 5252 /* All the following can't change since the last write 5253 * - All the event actions 5254 * - The timeout value 5255 */ 5256 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 5257 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 5258 BYPASS_WDTIMEOUT_M | 5259 BYPASS_WDT_VALUE_M; 5260 if ((out_reg & mask) != (in_reg & mask)) 5261 return false; 5262 5263 /* 0x0 is never a valid value for bypass status */ 5264 if (!(out_reg & BYPASS_STATUS_OFF_M)) 5265 return false; 5266 break; 5267 case BYPASS_PAGE_CTL1: 5268 /* All the following can't change since the last write 5269 * - time valid bit 5270 * - time we last sent 5271 */ 5272 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 5273 if ((out_reg & mask) != (in_reg & mask)) 5274 return false; 5275 break; 5276 case BYPASS_PAGE_CTL2: 5277 /* All we can check in this page is control number 5278 * which is already done above. 5279 */ 5280 break; 5281 } 5282 5283 /* We are as sure as we can be return true */ 5284 return true; 5285 } 5286 5287 /** 5288 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 5289 * 5290 * @hw: pointer to hardware structure 5291 * @ctrl: The control word we are setting. 5292 * @event: The event we are setting in the FW. This also happens to 5293 * be the mask for the event we are setting (handy) 5294 * @action: The action we set the event to in the FW. This is in a 5295 * bit field that happens to be what we want to put in 5296 * the event spot (also handy) 5297 **/ 5298 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5299 u32 action) 5300 { 5301 u32 by_ctl = 0; 5302 u32 cmd, verify; 5303 u32 count = 0; 5304 5305 /* Get current values */ 5306 cmd = ctrl; /* just reading only need control number */ 5307 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5308 return IXGBE_ERR_INVALID_ARGUMENT; 5309 5310 /* Set to new action */ 5311 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5312 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5313 return IXGBE_ERR_INVALID_ARGUMENT; 5314 5315 /* Page 0 force a FW eeprom write which is slow so verify */ 5316 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5317 verify = BYPASS_PAGE_CTL0; 5318 do { 5319 if (count++ > 5) 5320 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5321 5322 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5323 return IXGBE_ERR_INVALID_ARGUMENT; 5324 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5325 } else { 5326 /* We have give the FW time for the write to stick */ 5327 msec_delay(100); 5328 } 5329 5330 return IXGBE_SUCCESS; 5331 } 5332 5333 /** 5334 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5335 * 5336 * @hw: pointer to hardware structure 5337 * @addr: The bypass eeprom address to read. 5338 * @value: The 8b of data at the address above. 5339 **/ 5340 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5341 { 5342 u32 cmd; 5343 u32 status; 5344 5345 5346 /* send the request */ 5347 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5348 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5349 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5350 return IXGBE_ERR_INVALID_ARGUMENT; 5351 5352 /* We have give the FW time for the write to stick */ 5353 msec_delay(100); 5354 5355 /* now read the results */ 5356 cmd &= ~BYPASS_WE; 5357 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5358 return IXGBE_ERR_INVALID_ARGUMENT; 5359 5360 *value = status & BYPASS_CTL2_DATA_M; 5361 5362 return IXGBE_SUCCESS; 5363 } 5364 5365 /** 5366 * ixgbe_get_orom_version - Return option ROM from EEPROM 5367 * 5368 * @hw: pointer to hardware structure 5369 * @nvm_ver: pointer to output structure 5370 * 5371 * if valid option ROM version, nvm_ver->or_valid set to true 5372 * else nvm_ver->or_valid is false. 5373 **/ 5374 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5375 struct ixgbe_nvm_version *nvm_ver) 5376 { 5377 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5378 5379 nvm_ver->or_valid = false; 5380 /* Option Rom may or may not be present. Start with pointer */ 5381 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5382 5383 /* make sure offset is valid */ 5384 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5385 return; 5386 5387 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5388 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5389 5390 /* option rom exists and is valid */ 5391 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5392 eeprom_cfg_blkl == NVM_VER_INVALID || 5393 eeprom_cfg_blkh == NVM_VER_INVALID) 5394 return; 5395 5396 nvm_ver->or_valid = true; 5397 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5398 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5399 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5400 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5401 } 5402 5403 /** 5404 * ixgbe_get_oem_prod_version - Return OEM Product version 5405 * 5406 * @hw: pointer to hardware structure 5407 * @nvm_ver: pointer to output structure 5408 * 5409 * if valid OEM product version, nvm_ver->oem_valid set to true 5410 * else nvm_ver->oem_valid is false. 5411 **/ 5412 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5413 struct ixgbe_nvm_version *nvm_ver) 5414 { 5415 u16 rel_num, prod_ver, mod_len, cap, offset; 5416 5417 nvm_ver->oem_valid = false; 5418 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5419 5420 /* Return if offset to OEM Product Version block is invalid */ 5421 if (offset == 0x0 || offset == NVM_INVALID_PTR) 5422 return; 5423 5424 /* Read product version block */ 5425 hw->eeprom.ops.read(hw, offset, &mod_len); 5426 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5427 5428 /* Return if OEM product version block is invalid */ 5429 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5430 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5431 return; 5432 5433 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5434 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5435 5436 /* Return if version is invalid */ 5437 if ((rel_num | prod_ver) == 0x0 || 5438 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5439 return; 5440 5441 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5442 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5443 nvm_ver->oem_release = rel_num; 5444 nvm_ver->oem_valid = true; 5445 } 5446 5447 /** 5448 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5449 * 5450 * @hw: pointer to hardware structure 5451 * @nvm_ver: pointer to output structure 5452 * 5453 * word read errors will return 0xFFFF 5454 **/ 5455 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5456 { 5457 u16 etk_id_l, etk_id_h; 5458 5459 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5460 etk_id_l = NVM_VER_INVALID; 5461 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5462 etk_id_h = NVM_VER_INVALID; 5463 5464 /* The word order for the version format is determined by high order 5465 * word bit 15. 5466 */ 5467 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5468 nvm_ver->etk_id = (u32)etk_id_h; 5469 nvm_ver->etk_id |= (u32)etk_id_l << NVM_ETK_SHIFT; 5470 } else { 5471 nvm_ver->etk_id = (u32)etk_id_l; 5472 nvm_ver->etk_id |= (u32)etk_id_h << NVM_ETK_SHIFT; 5473 } 5474 } 5475 5476 /** 5477 * ixgbe_get_nvm_version - Return version of NVM and its components 5478 * 5479 * @hw: pointer to hardware structure 5480 * @nvm_ver: pointer to output structure 5481 * 5482 * irrelevant component fields will return 0, read errors will return 0xff 5483 **/ 5484 void ixgbe_get_nvm_version(struct ixgbe_hw *hw, 5485 struct ixgbe_nvm_version *nvm_ver) 5486 { 5487 u16 word, phy_ver; 5488 5489 DEBUGFUNC("ixgbe_get_nvm_version"); 5490 5491 memset(nvm_ver, 0, sizeof(struct ixgbe_nvm_version)); 5492 5493 /* eeprom version is mac-type specific */ 5494 switch (hw->mac.type) { 5495 case ixgbe_mac_82598EB: 5496 /* version of eeprom section */ 5497 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_82598, &word)) 5498 word = NVM_VER_INVALID; 5499 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5500 >> NVM_EEP_MAJ_SHIFT); 5501 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) 5502 >> NVM_EEP_MIN_SHIFT); 5503 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); 5504 break; 5505 case ixgbe_mac_X540: 5506 /* version of eeprom section */ 5507 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) 5508 word = NVM_VER_INVALID; 5509 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5510 >> NVM_EEP_MAJ_SHIFT); 5511 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) 5512 >> NVM_EEP_MIN_SHIFT); 5513 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); 5514 break; 5515 5516 case ixgbe_mac_X550: 5517 case ixgbe_mac_X550EM_x: 5518 case ixgbe_mac_X550EM_a: 5519 case ixgbe_mac_E610: 5520 /* version of eeprom section */ 5521 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) 5522 word = NVM_VER_INVALID; 5523 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5524 >> NVM_EEP_MAJ_SHIFT); 5525 nvm_ver->nvm_minor = (word & NVM_EEP_X550_MINOR_MASK); 5526 5527 break; 5528 default: 5529 break; 5530 } 5531 5532 /* phy version is mac-type specific */ 5533 switch (hw->mac.type) { 5534 case ixgbe_mac_X540: 5535 case ixgbe_mac_X550: 5536 case ixgbe_mac_X550EM_x: 5537 case ixgbe_mac_X550EM_a: 5538 case ixgbe_mac_E610: 5539 /* intel phy firmware version */ 5540 if (ixgbe_read_eeprom(hw, NVM_EEP_PHY_OFF_X540, &word)) 5541 word = NVM_VER_INVALID; 5542 nvm_ver->phy_fw_maj = ((word & NVM_PHY_MAJOR_MASK) 5543 >> NVM_PHY_MAJ_SHIFT); 5544 nvm_ver->phy_fw_min = ((word & NVM_PHY_MINOR_MASK) 5545 >> NVM_PHY_MIN_SHIFT); 5546 nvm_ver->phy_fw_id = (word & NVM_PHY_ID_MASK); 5547 break; 5548 default: 5549 break; 5550 } 5551 5552 ixgbe_get_etk_id(hw, nvm_ver); 5553 5554 /* devstarter image */ 5555 if (ixgbe_read_eeprom(hw, NVM_DS_OFFSET, &word)) 5556 word = NVM_VER_INVALID; 5557 nvm_ver->devstart_major = ((word & NVM_DS_MAJOR_MASK) >> NVM_DS_SHIFT); 5558 nvm_ver->devstart_minor = (word & NVM_DS_MINOR_MASK); 5559 5560 /* OEM customization word */ 5561 if (ixgbe_read_eeprom(hw, NVM_OEM_OFFSET, &nvm_ver->oem_specific)) 5562 nvm_ver->oem_specific = NVM_VER_INVALID; 5563 5564 /* vendor (not intel) phy firmware version */ 5565 if (ixgbe_get_phy_firmware_version(hw, &phy_ver)) 5566 phy_ver = NVM_VER_INVALID; 5567 nvm_ver->phy_vend_maj = ((phy_ver & NVM_PHYVEND_MAJOR_MASK) 5568 >> NVM_PHYVEND_SHIFT); 5569 nvm_ver->phy_vend_min = (phy_ver & NVM_PHYVEND_MINOR_MASK); 5570 5571 /* Option Rom may or may not be present. Start with pointer */ 5572 ixgbe_get_orom_version(hw, nvm_ver); 5573 return; 5574 } 5575 5576 /** 5577 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5578 * @hw: pointer to hardware structure 5579 * @map: pointer to u8 arr for returning map 5580 * 5581 * Read the rtrup2tc HW register and resolve its content into map 5582 **/ 5583 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5584 { 5585 u32 reg, i; 5586 5587 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5588 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5589 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5590 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5591 return; 5592 } 5593 5594 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5595 { 5596 u32 pfdtxgswc; 5597 u32 rxctrl; 5598 5599 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5600 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5601 if (hw->mac.type != ixgbe_mac_82598EB) { 5602 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5603 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5604 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5605 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5606 hw->mac.set_lben = true; 5607 } else { 5608 hw->mac.set_lben = false; 5609 } 5610 } 5611 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5612 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5613 } 5614 } 5615 5616 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5617 { 5618 u32 pfdtxgswc; 5619 u32 rxctrl; 5620 5621 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5622 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5623 5624 if (hw->mac.type != ixgbe_mac_82598EB) { 5625 if (hw->mac.set_lben) { 5626 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5627 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5628 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5629 hw->mac.set_lben = false; 5630 } 5631 } 5632 } 5633 5634 /** 5635 * ixgbe_mng_present - returns true when management capability is present 5636 * @hw: pointer to hardware structure 5637 */ 5638 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5639 { 5640 u32 fwsm; 5641 5642 if (hw->mac.type < ixgbe_mac_82599EB) 5643 return false; 5644 5645 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5646 5647 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5648 } 5649 5650 /** 5651 * ixgbe_mng_enabled - Is the manageability engine enabled? 5652 * @hw: pointer to hardware structure 5653 * 5654 * Returns true if the manageability engine is enabled. 5655 **/ 5656 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5657 { 5658 u32 fwsm, manc, factps; 5659 5660 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5661 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5662 return false; 5663 5664 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5665 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5666 return false; 5667 5668 if (hw->mac.type <= ixgbe_mac_X540) { 5669 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5670 if (factps & IXGBE_FACTPS_MNGCG) 5671 return false; 5672 } 5673 5674 return true; 5675 } 5676 5677 /** 5678 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5679 * @hw: pointer to hardware structure 5680 * @speed: new link speed 5681 * @autoneg_wait_to_complete: true when waiting for completion is needed 5682 * 5683 * Set the link speed in the MAC and/or PHY register and restarts link. 5684 **/ 5685 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5686 ixgbe_link_speed speed, 5687 bool autoneg_wait_to_complete) 5688 { 5689 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5690 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5691 s32 status = IXGBE_SUCCESS; 5692 u32 speedcnt = 0; 5693 u32 i = 0; 5694 bool autoneg, link_up = false; 5695 5696 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5697 5698 /* Mask off requested but non-supported speeds */ 5699 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5700 if (status != IXGBE_SUCCESS) 5701 return status; 5702 5703 speed &= link_speed; 5704 5705 /* Try each speed one by one, highest priority first. We do this in 5706 * software because 10Gb fiber doesn't support speed autonegotiation. 5707 */ 5708 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5709 speedcnt++; 5710 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5711 5712 /* Set the module link speed */ 5713 switch (hw->phy.media_type) { 5714 case ixgbe_media_type_fiber_fixed: 5715 case ixgbe_media_type_fiber: 5716 ixgbe_set_rate_select_speed(hw, 5717 IXGBE_LINK_SPEED_10GB_FULL); 5718 break; 5719 case ixgbe_media_type_fiber_qsfp: 5720 /* QSFP module automatically detects MAC link speed */ 5721 break; 5722 default: 5723 DEBUGOUT("Unexpected media type.\n"); 5724 break; 5725 } 5726 5727 /* Allow module to change analog characteristics (1G->10G) */ 5728 msec_delay(40); 5729 5730 status = ixgbe_setup_mac_link(hw, 5731 IXGBE_LINK_SPEED_10GB_FULL, 5732 autoneg_wait_to_complete); 5733 if (status != IXGBE_SUCCESS) 5734 return status; 5735 5736 /* Flap the Tx laser if it has not already been done */ 5737 ixgbe_flap_tx_laser(hw); 5738 5739 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5740 * Section 73.10.2, we may have to wait up to 1000ms if KR is 5741 * attempted. 82599 uses the same timing for 10g SFI. 5742 */ 5743 for (i = 0; i < 10; i++) { 5744 /* Wait for the link partner to also set speed */ 5745 msec_delay(100); 5746 5747 /* If we have link, just jump out */ 5748 status = ixgbe_check_link(hw, &link_speed, 5749 &link_up, false); 5750 if (status != IXGBE_SUCCESS) 5751 return status; 5752 5753 if (link_up) 5754 goto out; 5755 } 5756 } 5757 5758 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5759 speedcnt++; 5760 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5761 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5762 5763 /* Set the module link speed */ 5764 switch (hw->phy.media_type) { 5765 case ixgbe_media_type_fiber_fixed: 5766 case ixgbe_media_type_fiber: 5767 ixgbe_set_rate_select_speed(hw, 5768 IXGBE_LINK_SPEED_1GB_FULL); 5769 break; 5770 case ixgbe_media_type_fiber_qsfp: 5771 /* QSFP module automatically detects link speed */ 5772 break; 5773 default: 5774 DEBUGOUT("Unexpected media type.\n"); 5775 break; 5776 } 5777 5778 /* Allow module to change analog characteristics (10G->1G) */ 5779 msec_delay(40); 5780 5781 status = ixgbe_setup_mac_link(hw, 5782 IXGBE_LINK_SPEED_1GB_FULL, 5783 autoneg_wait_to_complete); 5784 if (status != IXGBE_SUCCESS) 5785 return status; 5786 5787 /* Flap the Tx laser if it has not already been done */ 5788 ixgbe_flap_tx_laser(hw); 5789 5790 /* Wait for the link partner to also set speed */ 5791 msec_delay(100); 5792 5793 /* If we have link, just jump out */ 5794 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 5795 if (status != IXGBE_SUCCESS) 5796 return status; 5797 5798 if (link_up) 5799 goto out; 5800 } 5801 5802 /* We didn't get link. Configure back to the highest speed we tried, 5803 * (if there was more than one). We call ourselves back with just the 5804 * single highest speed that the user requested. 5805 */ 5806 if (speedcnt > 1) 5807 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5808 highest_link_speed, 5809 autoneg_wait_to_complete); 5810 5811 out: 5812 /* Set autoneg_advertised value based on input link speed */ 5813 hw->phy.autoneg_advertised = 0; 5814 5815 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5816 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5817 5818 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5819 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5820 5821 return status; 5822 } 5823 5824 /** 5825 * ixgbe_set_soft_rate_select_speed - Set module link speed 5826 * @hw: pointer to hardware structure 5827 * @speed: link speed to set 5828 * 5829 * Set module link speed via the soft rate select. 5830 */ 5831 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5832 ixgbe_link_speed speed) 5833 { 5834 s32 status; 5835 u8 rs, eeprom_data; 5836 5837 switch (speed) { 5838 case IXGBE_LINK_SPEED_10GB_FULL: 5839 /* one bit mask same as setting on */ 5840 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5841 break; 5842 case IXGBE_LINK_SPEED_1GB_FULL: 5843 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5844 break; 5845 default: 5846 DEBUGOUT("Invalid fixed module speed\n"); 5847 return; 5848 } 5849 5850 /* Set RS0 */ 5851 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5852 IXGBE_I2C_EEPROM_DEV_ADDR2, 5853 &eeprom_data); 5854 if (status) { 5855 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5856 goto out; 5857 } 5858 5859 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5860 5861 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5862 IXGBE_I2C_EEPROM_DEV_ADDR2, 5863 eeprom_data); 5864 if (status) { 5865 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5866 goto out; 5867 } 5868 5869 /* Set RS1 */ 5870 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5871 IXGBE_I2C_EEPROM_DEV_ADDR2, 5872 &eeprom_data); 5873 if (status) { 5874 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5875 goto out; 5876 } 5877 5878 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5879 5880 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5881 IXGBE_I2C_EEPROM_DEV_ADDR2, 5882 eeprom_data); 5883 if (status) { 5884 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5885 goto out; 5886 } 5887 out: 5888 return; 5889 } 5890