1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 #include "ixgbe_dcb.h" 38 #include "ixgbe_dcb_82599.h" 39 #include "ixgbe_api.h" 40 41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 47 u16 count); 48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 52 53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 55 u16 *san_mac_offset); 56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 57 u16 words, u16 *data); 58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 59 u16 words, u16 *data); 60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 61 u16 offset); 62 63 /** 64 * ixgbe_init_ops_generic - Inits function ptrs 65 * @hw: pointer to the hardware structure 66 * 67 * Initialize the function pointers. 68 **/ 69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 70 { 71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 72 struct ixgbe_mac_info *mac = &hw->mac; 73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 74 75 DEBUGFUNC("ixgbe_init_ops_generic"); 76 77 /* EEPROM */ 78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 80 if (eec & IXGBE_EEC_PRES) { 81 eeprom->ops.read = ixgbe_read_eerd_generic; 82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 83 } else { 84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 85 eeprom->ops.read_buffer = 86 ixgbe_read_eeprom_buffer_bit_bang_generic; 87 } 88 eeprom->ops.write = ixgbe_write_eeprom_generic; 89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 90 eeprom->ops.validate_checksum = 91 ixgbe_validate_eeprom_checksum_generic; 92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 94 95 /* MAC */ 96 mac->ops.init_hw = ixgbe_init_hw_generic; 97 mac->ops.reset_hw = NULL; 98 mac->ops.start_hw = ixgbe_start_hw_generic; 99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 100 mac->ops.get_media_type = NULL; 101 mac->ops.get_supported_physical_layer = NULL; 102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 109 mac->ops.prot_autoc_read = prot_autoc_read_generic; 110 mac->ops.prot_autoc_write = prot_autoc_write_generic; 111 112 /* LEDs */ 113 mac->ops.led_on = ixgbe_led_on_generic; 114 mac->ops.led_off = ixgbe_led_off_generic; 115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 117 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 118 119 /* RAR, Multicast, VLAN */ 120 mac->ops.set_rar = ixgbe_set_rar_generic; 121 mac->ops.clear_rar = ixgbe_clear_rar_generic; 122 mac->ops.insert_mac_addr = NULL; 123 mac->ops.set_vmdq = NULL; 124 mac->ops.clear_vmdq = NULL; 125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 128 mac->ops.enable_mc = ixgbe_enable_mc_generic; 129 mac->ops.disable_mc = ixgbe_disable_mc_generic; 130 mac->ops.clear_vfta = NULL; 131 mac->ops.set_vfta = NULL; 132 mac->ops.set_vlvf = NULL; 133 mac->ops.init_uta_tables = NULL; 134 mac->ops.enable_rx = ixgbe_enable_rx_generic; 135 mac->ops.disable_rx = ixgbe_disable_rx_generic; 136 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic; 137 138 /* Flow Control */ 139 mac->ops.fc_enable = ixgbe_fc_enable_generic; 140 mac->ops.setup_fc = ixgbe_setup_fc_generic; 141 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 142 143 /* Link */ 144 mac->ops.get_link_capabilities = NULL; 145 mac->ops.setup_link = NULL; 146 mac->ops.check_link = NULL; 147 mac->ops.dmac_config = NULL; 148 mac->ops.dmac_update_tcs = NULL; 149 mac->ops.dmac_config_tcs = NULL; 150 151 return IXGBE_SUCCESS; 152 } 153 154 /** 155 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 156 * of flow control 157 * @hw: pointer to hardware structure 158 * 159 * This function returns true if the device supports flow control 160 * autonegotiation, and false if it does not. 161 * 162 **/ 163 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 164 { 165 bool supported = false; 166 ixgbe_link_speed speed; 167 bool link_up; 168 169 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 170 171 switch (hw->phy.media_type) { 172 case ixgbe_media_type_fiber_fixed: 173 case ixgbe_media_type_fiber_qsfp: 174 case ixgbe_media_type_fiber: 175 /* flow control autoneg block list */ 176 switch (hw->device_id) { 177 case IXGBE_DEV_ID_X550EM_A_SFP: 178 case IXGBE_DEV_ID_X550EM_A_SFP_N: 179 case IXGBE_DEV_ID_X550EM_A_QSFP: 180 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 181 case IXGBE_DEV_ID_E610_SFP: 182 supported = false; 183 break; 184 default: 185 hw->mac.ops.check_link(hw, &speed, &link_up, false); 186 /* if link is down, assume supported */ 187 if (link_up) 188 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 189 true : false; 190 else 191 supported = true; 192 } 193 194 break; 195 case ixgbe_media_type_backplane: 196 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 197 supported = false; 198 else 199 supported = true; 200 break; 201 case ixgbe_media_type_copper: 202 /* only some copper devices support flow control autoneg */ 203 switch (hw->device_id) { 204 case IXGBE_DEV_ID_82599_T3_LOM: 205 case IXGBE_DEV_ID_X540T: 206 case IXGBE_DEV_ID_X540T1: 207 case IXGBE_DEV_ID_X540_BYPASS: 208 case IXGBE_DEV_ID_X550T: 209 case IXGBE_DEV_ID_X550T1: 210 case IXGBE_DEV_ID_X550EM_X_10G_T: 211 case IXGBE_DEV_ID_X550EM_A_10G_T: 212 case IXGBE_DEV_ID_X550EM_A_1G_T: 213 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 214 case IXGBE_DEV_ID_E610_10G_T: 215 case IXGBE_DEV_ID_E610_2_5G_T: 216 supported = true; 217 break; 218 default: 219 supported = false; 220 } 221 default: 222 break; 223 } 224 225 if (!supported) 226 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 227 "Device %x does not support flow control autoneg", 228 hw->device_id); 229 230 return supported; 231 } 232 233 /** 234 * ixgbe_setup_fc_generic - Set up flow control 235 * @hw: pointer to hardware structure 236 * 237 * Called at init time to set up flow control. 238 **/ 239 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 240 { 241 s32 ret_val = IXGBE_SUCCESS; 242 u32 reg = 0, reg_bp = 0; 243 u16 reg_cu = 0; 244 bool locked = false; 245 246 DEBUGFUNC("ixgbe_setup_fc_generic"); 247 248 /* Validate the requested mode */ 249 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 250 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 251 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 252 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 253 goto out; 254 } 255 256 /* 257 * 10gig parts do not have a word in the EEPROM to determine the 258 * default flow control setting, so we explicitly set it to full. 259 */ 260 if (hw->fc.requested_mode == ixgbe_fc_default) 261 hw->fc.requested_mode = ixgbe_fc_full; 262 263 /* 264 * Set up the 1G and 10G flow control advertisement registers so the 265 * HW will be able to do fc autoneg once the cable is plugged in. If 266 * we link at 10G, the 1G advertisement is harmless and vice versa. 267 */ 268 switch (hw->phy.media_type) { 269 case ixgbe_media_type_backplane: 270 /* some MAC's need RMW protection on AUTOC */ 271 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 272 if (ret_val != IXGBE_SUCCESS) 273 goto out; 274 275 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 276 break; 277 case ixgbe_media_type_fiber_fixed: 278 case ixgbe_media_type_fiber_qsfp: 279 case ixgbe_media_type_fiber: 280 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 281 282 break; 283 case ixgbe_media_type_copper: 284 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 285 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 286 break; 287 default: 288 break; 289 } 290 291 /* 292 * The possible values of fc.requested_mode are: 293 * 0: Flow control is completely disabled 294 * 1: Rx flow control is enabled (we can receive pause frames, 295 * but not send pause frames). 296 * 2: Tx flow control is enabled (we can send pause frames but 297 * we do not support receiving pause frames). 298 * 3: Both Rx and Tx flow control (symmetric) are enabled. 299 * other: Invalid. 300 */ 301 switch (hw->fc.requested_mode) { 302 case ixgbe_fc_none: 303 /* Flow control completely disabled by software override. */ 304 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 305 if (hw->phy.media_type == ixgbe_media_type_backplane) 306 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 307 IXGBE_AUTOC_ASM_PAUSE); 308 else if (hw->phy.media_type == ixgbe_media_type_copper) 309 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 310 break; 311 case ixgbe_fc_tx_pause: 312 /* 313 * Tx Flow control is enabled, and Rx Flow control is 314 * disabled by software override. 315 */ 316 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 317 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 318 if (hw->phy.media_type == ixgbe_media_type_backplane) { 319 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 320 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 321 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 322 reg_cu |= IXGBE_TAF_ASM_PAUSE; 323 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 324 } 325 break; 326 case ixgbe_fc_rx_pause: 327 /* 328 * Rx Flow control is enabled and Tx Flow control is 329 * disabled by software override. Since there really 330 * isn't a way to advertise that we are capable of RX 331 * Pause ONLY, we will advertise that we support both 332 * symmetric and asymmetric Rx PAUSE, as such we fall 333 * through to the fc_full statement. Later, we will 334 * disable the adapter's ability to send PAUSE frames. 335 */ 336 case ixgbe_fc_full: 337 /* Flow control (both Rx and Tx) is enabled by SW override. */ 338 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 339 if (hw->phy.media_type == ixgbe_media_type_backplane) 340 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 341 IXGBE_AUTOC_ASM_PAUSE; 342 else if (hw->phy.media_type == ixgbe_media_type_copper) 343 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 344 break; 345 default: 346 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 347 "Flow control param set incorrectly\n"); 348 ret_val = IXGBE_ERR_CONFIG; 349 goto out; 350 break; 351 } 352 353 if (hw->mac.type < ixgbe_mac_X540) { 354 /* 355 * Enable auto-negotiation between the MAC & PHY; 356 * the MAC will advertise clause 37 flow control. 357 */ 358 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 359 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 360 361 /* Disable AN timeout */ 362 if (hw->fc.strict_ieee) 363 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 364 365 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 366 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 367 } 368 369 /* 370 * AUTOC restart handles negotiation of 1G and 10G on backplane 371 * and copper. There is no need to set the PCS1GCTL register. 372 * 373 */ 374 if (hw->phy.media_type == ixgbe_media_type_backplane) { 375 reg_bp |= IXGBE_AUTOC_AN_RESTART; 376 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 377 if (ret_val) 378 goto out; 379 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 380 (ixgbe_device_supports_autoneg_fc(hw))) { 381 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 382 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 383 } 384 385 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 386 out: 387 return ret_val; 388 } 389 390 /** 391 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 392 * @hw: pointer to hardware structure 393 * 394 * Starts the hardware by filling the bus info structure and media type, clears 395 * all on chip counters, initializes receive address registers, multicast 396 * table, VLAN filter table, calls routine to set up link and flow control 397 * settings, and leaves transmit and receive units disabled and uninitialized 398 **/ 399 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 400 { 401 s32 ret_val; 402 u32 ctrl_ext; 403 u16 device_caps; 404 405 DEBUGFUNC("ixgbe_start_hw_generic"); 406 407 /* Set the media type */ 408 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 409 410 /* PHY ops initialization must be done in reset_hw() */ 411 412 /* Clear the VLAN filter table */ 413 hw->mac.ops.clear_vfta(hw); 414 415 /* Clear statistics registers */ 416 hw->mac.ops.clear_hw_cntrs(hw); 417 418 /* Set No Snoop Disable */ 419 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 420 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 421 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 422 IXGBE_WRITE_FLUSH(hw); 423 424 /* Setup flow control */ 425 ret_val = ixgbe_setup_fc(hw); 426 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 427 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 428 return ret_val; 429 } 430 431 /* Cache bit indicating need for crosstalk fix */ 432 switch (hw->mac.type) { 433 case ixgbe_mac_82599EB: 434 case ixgbe_mac_X550EM_x: 435 case ixgbe_mac_X550EM_a: 436 hw->mac.ops.get_device_caps(hw, &device_caps); 437 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 438 hw->need_crosstalk_fix = false; 439 else 440 hw->need_crosstalk_fix = true; 441 break; 442 default: 443 hw->need_crosstalk_fix = false; 444 break; 445 } 446 447 /* Clear adapter stopped flag */ 448 hw->adapter_stopped = false; 449 450 return IXGBE_SUCCESS; 451 } 452 453 /** 454 * ixgbe_start_hw_gen2 - Init sequence for common device family 455 * @hw: pointer to hw structure 456 * 457 * Performs the init sequence common to the second generation 458 * of 10 GbE devices. 459 * Devices in the second generation: 460 * 82599 461 * X540 462 **/ 463 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 464 { 465 u32 i; 466 u32 regval; 467 468 /* Clear the rate limiters */ 469 for (i = 0; i < hw->mac.max_tx_queues; i++) { 470 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 471 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 472 } 473 IXGBE_WRITE_FLUSH(hw); 474 475 /* Disable relaxed ordering */ 476 for (i = 0; i < hw->mac.max_tx_queues; i++) { 477 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 478 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 479 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 480 } 481 482 for (i = 0; i < hw->mac.max_rx_queues; i++) { 483 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 484 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 485 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 486 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 487 } 488 } 489 490 /** 491 * ixgbe_init_hw_generic - Generic hardware initialization 492 * @hw: pointer to hardware structure 493 * 494 * Initialize the hardware by resetting the hardware, filling the bus info 495 * structure and media type, clears all on chip counters, initializes receive 496 * address registers, multicast table, VLAN filter table, calls routine to set 497 * up link and flow control settings, and leaves transmit and receive units 498 * disabled and uninitialized 499 **/ 500 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 501 { 502 s32 status; 503 504 DEBUGFUNC("ixgbe_init_hw_generic"); 505 506 /* Reset the hardware */ 507 status = hw->mac.ops.reset_hw(hw); 508 509 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 510 /* Start the HW */ 511 status = hw->mac.ops.start_hw(hw); 512 } 513 514 /* Initialize the LED link active for LED blink support */ 515 if (hw->mac.ops.init_led_link_act) 516 hw->mac.ops.init_led_link_act(hw); 517 518 if (status != IXGBE_SUCCESS) 519 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 520 521 return status; 522 } 523 524 /** 525 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 526 * @hw: pointer to hardware structure 527 * 528 * Clears all hardware statistics counters by reading them from the hardware 529 * Statistics counters are clear on read. 530 **/ 531 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 532 { 533 u16 i = 0; 534 535 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 536 537 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 538 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 539 IXGBE_READ_REG(hw, IXGBE_ERRBC); 540 IXGBE_READ_REG(hw, IXGBE_MSPDC); 541 for (i = 0; i < 8; i++) 542 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 543 544 IXGBE_READ_REG(hw, IXGBE_MLFC); 545 IXGBE_READ_REG(hw, IXGBE_MRFC); 546 IXGBE_READ_REG(hw, IXGBE_RLEC); 547 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 548 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 549 if (hw->mac.type >= ixgbe_mac_82599EB) { 550 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 551 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 552 } else { 553 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 554 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 555 } 556 557 for (i = 0; i < 8; i++) { 558 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 559 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 560 if (hw->mac.type >= ixgbe_mac_82599EB) { 561 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 562 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 563 } else { 564 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 565 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 566 } 567 } 568 if (hw->mac.type >= ixgbe_mac_82599EB) 569 for (i = 0; i < 8; i++) 570 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 571 IXGBE_READ_REG(hw, IXGBE_PRC64); 572 IXGBE_READ_REG(hw, IXGBE_PRC127); 573 IXGBE_READ_REG(hw, IXGBE_PRC255); 574 IXGBE_READ_REG(hw, IXGBE_PRC511); 575 IXGBE_READ_REG(hw, IXGBE_PRC1023); 576 IXGBE_READ_REG(hw, IXGBE_PRC1522); 577 IXGBE_READ_REG(hw, IXGBE_GPRC); 578 IXGBE_READ_REG(hw, IXGBE_BPRC); 579 IXGBE_READ_REG(hw, IXGBE_MPRC); 580 IXGBE_READ_REG(hw, IXGBE_GPTC); 581 IXGBE_READ_REG(hw, IXGBE_GORCL); 582 IXGBE_READ_REG(hw, IXGBE_GORCH); 583 IXGBE_READ_REG(hw, IXGBE_GOTCL); 584 IXGBE_READ_REG(hw, IXGBE_GOTCH); 585 if (hw->mac.type == ixgbe_mac_82598EB) 586 for (i = 0; i < 8; i++) 587 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 588 IXGBE_READ_REG(hw, IXGBE_RUC); 589 IXGBE_READ_REG(hw, IXGBE_RFC); 590 IXGBE_READ_REG(hw, IXGBE_ROC); 591 IXGBE_READ_REG(hw, IXGBE_RJC); 592 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 593 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 594 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 595 IXGBE_READ_REG(hw, IXGBE_TORL); 596 IXGBE_READ_REG(hw, IXGBE_TORH); 597 IXGBE_READ_REG(hw, IXGBE_TPR); 598 IXGBE_READ_REG(hw, IXGBE_TPT); 599 IXGBE_READ_REG(hw, IXGBE_PTC64); 600 IXGBE_READ_REG(hw, IXGBE_PTC127); 601 IXGBE_READ_REG(hw, IXGBE_PTC255); 602 IXGBE_READ_REG(hw, IXGBE_PTC511); 603 IXGBE_READ_REG(hw, IXGBE_PTC1023); 604 IXGBE_READ_REG(hw, IXGBE_PTC1522); 605 IXGBE_READ_REG(hw, IXGBE_MPTC); 606 IXGBE_READ_REG(hw, IXGBE_BPTC); 607 for (i = 0; i < 16; i++) { 608 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 609 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 610 if (hw->mac.type >= ixgbe_mac_82599EB) { 611 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 612 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 613 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 614 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 615 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 616 } else { 617 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 618 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 619 } 620 } 621 622 if (hw->mac.type == ixgbe_mac_X540 || 623 hw->mac.type == ixgbe_mac_X550) { 624 if (hw->phy.id == 0) 625 ixgbe_identify_phy(hw); 626 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 627 IXGBE_MDIO_PCS_DEV_TYPE, &i); 628 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 629 IXGBE_MDIO_PCS_DEV_TYPE, &i); 630 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 631 IXGBE_MDIO_PCS_DEV_TYPE, &i); 632 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 633 IXGBE_MDIO_PCS_DEV_TYPE, &i); 634 } 635 636 return IXGBE_SUCCESS; 637 } 638 639 /** 640 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 641 * @hw: pointer to hardware structure 642 * @pba_num: stores the part number string from the EEPROM 643 * @pba_num_size: part number string buffer length 644 * 645 * Reads the part number string from the EEPROM. 646 **/ 647 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 648 u32 pba_num_size) 649 { 650 s32 ret_val; 651 u16 data; 652 u16 pba_ptr; 653 u16 offset; 654 u16 length; 655 656 DEBUGFUNC("ixgbe_read_pba_string_generic"); 657 658 if (pba_num == NULL) { 659 DEBUGOUT("PBA string buffer was null\n"); 660 return IXGBE_ERR_INVALID_ARGUMENT; 661 } 662 663 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 664 if (ret_val) { 665 DEBUGOUT("NVM Read Error\n"); 666 return ret_val; 667 } 668 669 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 670 if (ret_val) { 671 DEBUGOUT("NVM Read Error\n"); 672 return ret_val; 673 } 674 675 /* 676 * if data is not ptr guard the PBA must be in legacy format which 677 * means pba_ptr is actually our second data word for the PBA number 678 * and we can decode it into an ascii string 679 */ 680 if (data != IXGBE_PBANUM_PTR_GUARD) { 681 DEBUGOUT("NVM PBA number is not stored as string\n"); 682 683 /* we will need 11 characters to store the PBA */ 684 if (pba_num_size < 11) { 685 DEBUGOUT("PBA string buffer too small\n"); 686 return IXGBE_ERR_NO_SPACE; 687 } 688 689 /* extract hex string from data and pba_ptr */ 690 pba_num[0] = (data >> 12) & 0xF; 691 pba_num[1] = (data >> 8) & 0xF; 692 pba_num[2] = (data >> 4) & 0xF; 693 pba_num[3] = data & 0xF; 694 pba_num[4] = (pba_ptr >> 12) & 0xF; 695 pba_num[5] = (pba_ptr >> 8) & 0xF; 696 pba_num[6] = '-'; 697 pba_num[7] = 0; 698 pba_num[8] = (pba_ptr >> 4) & 0xF; 699 pba_num[9] = pba_ptr & 0xF; 700 701 /* put a null character on the end of our string */ 702 pba_num[10] = '\0'; 703 704 /* switch all the data but the '-' to hex char */ 705 for (offset = 0; offset < 10; offset++) { 706 if (pba_num[offset] < 0xA) 707 pba_num[offset] += '0'; 708 else if (pba_num[offset] < 0x10) 709 pba_num[offset] += 'A' - 0xA; 710 } 711 712 return IXGBE_SUCCESS; 713 } 714 715 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 716 if (ret_val) { 717 DEBUGOUT("NVM Read Error\n"); 718 return ret_val; 719 } 720 721 if (length == 0xFFFF || length == 0 || length > hw->eeprom.word_size) { 722 DEBUGOUT("NVM PBA number section invalid length\n"); 723 return IXGBE_ERR_PBA_SECTION; 724 } 725 726 /* check if pba_num buffer is big enough */ 727 if (pba_num_size < (((u32)length * 2) - 1)) { 728 DEBUGOUT("PBA string buffer too small\n"); 729 return IXGBE_ERR_NO_SPACE; 730 } 731 732 /* trim pba length from start of string */ 733 pba_ptr++; 734 length--; 735 736 for (offset = 0; offset < length; offset++) { 737 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 738 if (ret_val) { 739 DEBUGOUT("NVM Read Error\n"); 740 return ret_val; 741 } 742 pba_num[offset * 2] = (u8)(data >> 8); 743 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 744 } 745 pba_num[offset * 2] = '\0'; 746 747 return IXGBE_SUCCESS; 748 } 749 750 /** 751 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 752 * @hw: pointer to hardware structure 753 * @pba_num: stores the part number from the EEPROM 754 * 755 * Reads the part number from the EEPROM. 756 **/ 757 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 758 { 759 s32 ret_val; 760 u16 data; 761 762 DEBUGFUNC("ixgbe_read_pba_num_generic"); 763 764 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 765 if (ret_val) { 766 DEBUGOUT("NVM Read Error\n"); 767 return ret_val; 768 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 769 DEBUGOUT("NVM Not supported\n"); 770 return IXGBE_NOT_IMPLEMENTED; 771 } 772 *pba_num = (u32)(data << 16); 773 774 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 775 if (ret_val) { 776 DEBUGOUT("NVM Read Error\n"); 777 return ret_val; 778 } 779 *pba_num |= (u32)data; 780 781 return IXGBE_SUCCESS; 782 } 783 784 /** 785 * ixgbe_read_pba_raw 786 * @hw: pointer to the HW structure 787 * @eeprom_buf: optional pointer to EEPROM image 788 * @eeprom_buf_size: size of EEPROM image in words 789 * @max_pba_block_size: PBA block size limit 790 * @pba: pointer to output PBA structure 791 * 792 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 793 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 794 * 795 **/ 796 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 797 u32 eeprom_buf_size, u16 max_pba_block_size, 798 struct ixgbe_pba *pba) 799 { 800 s32 ret_val; 801 u16 pba_block_size; 802 803 if (pba == NULL) 804 return IXGBE_ERR_PARAM; 805 806 if (eeprom_buf == NULL) { 807 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 808 &pba->word[0]); 809 if (ret_val) 810 return ret_val; 811 } else { 812 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 813 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 814 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 815 } else { 816 return IXGBE_ERR_PARAM; 817 } 818 } 819 820 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 821 if (pba->pba_block == NULL) 822 return IXGBE_ERR_PARAM; 823 824 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 825 eeprom_buf_size, 826 &pba_block_size); 827 if (ret_val) 828 return ret_val; 829 830 if (pba_block_size > max_pba_block_size) 831 return IXGBE_ERR_PARAM; 832 833 if (eeprom_buf == NULL) { 834 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 835 pba_block_size, 836 pba->pba_block); 837 if (ret_val) 838 return ret_val; 839 } else { 840 if (eeprom_buf_size > (u32)(pba->word[1] + 841 pba_block_size)) { 842 memcpy(pba->pba_block, 843 &eeprom_buf[pba->word[1]], 844 pba_block_size * sizeof(u16)); 845 } else { 846 return IXGBE_ERR_PARAM; 847 } 848 } 849 } 850 851 return IXGBE_SUCCESS; 852 } 853 854 /** 855 * ixgbe_write_pba_raw 856 * @hw: pointer to the HW structure 857 * @eeprom_buf: optional pointer to EEPROM image 858 * @eeprom_buf_size: size of EEPROM image in words 859 * @pba: pointer to PBA structure 860 * 861 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 862 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 863 * 864 **/ 865 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 866 u32 eeprom_buf_size, struct ixgbe_pba *pba) 867 { 868 s32 ret_val; 869 870 if (pba == NULL) 871 return IXGBE_ERR_PARAM; 872 873 if (eeprom_buf == NULL) { 874 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 875 &pba->word[0]); 876 if (ret_val) 877 return ret_val; 878 } else { 879 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 880 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 881 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 882 } else { 883 return IXGBE_ERR_PARAM; 884 } 885 } 886 887 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 888 if (pba->pba_block == NULL) 889 return IXGBE_ERR_PARAM; 890 891 if (eeprom_buf == NULL) { 892 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 893 pba->pba_block[0], 894 pba->pba_block); 895 if (ret_val) 896 return ret_val; 897 } else { 898 if (eeprom_buf_size > (u32)(pba->word[1] + 899 pba->pba_block[0])) { 900 memcpy(&eeprom_buf[pba->word[1]], 901 pba->pba_block, 902 pba->pba_block[0] * sizeof(u16)); 903 } else { 904 return IXGBE_ERR_PARAM; 905 } 906 } 907 } 908 909 return IXGBE_SUCCESS; 910 } 911 912 /** 913 * ixgbe_get_pba_block_size 914 * @hw: pointer to the HW structure 915 * @eeprom_buf: optional pointer to EEPROM image 916 * @eeprom_buf_size: size of EEPROM image in words 917 * @pba_data_size: pointer to output variable 918 * 919 * Returns the size of the PBA block in words. Function operates on EEPROM 920 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 921 * EEPROM device. 922 * 923 **/ 924 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 925 u32 eeprom_buf_size, u16 *pba_block_size) 926 { 927 s32 ret_val; 928 u16 pba_word[2]; 929 u16 length; 930 931 DEBUGFUNC("ixgbe_get_pba_block_size"); 932 933 if (eeprom_buf == NULL) { 934 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 935 &pba_word[0]); 936 if (ret_val) 937 return ret_val; 938 } else { 939 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 940 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 941 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 942 } else { 943 return IXGBE_ERR_PARAM; 944 } 945 } 946 947 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 948 if (eeprom_buf == NULL) { 949 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 950 &length); 951 if (ret_val) 952 return ret_val; 953 } else { 954 if (eeprom_buf_size > pba_word[1]) 955 length = eeprom_buf[pba_word[1] + 0]; 956 else 957 return IXGBE_ERR_PARAM; 958 } 959 960 if (length == 0xFFFF || length == 0) 961 return IXGBE_ERR_PBA_SECTION; 962 } else { 963 /* PBA number in legacy format, there is no PBA Block. */ 964 length = 0; 965 } 966 967 if (pba_block_size != NULL) 968 *pba_block_size = length; 969 970 return IXGBE_SUCCESS; 971 } 972 973 /** 974 * ixgbe_get_mac_addr_generic - Generic get MAC address 975 * @hw: pointer to hardware structure 976 * @mac_addr: Adapter MAC address 977 * 978 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 979 * A reset of the adapter must be performed prior to calling this function 980 * in order for the MAC address to have been loaded from the EEPROM into RAR0 981 **/ 982 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 983 { 984 u32 rar_high; 985 u32 rar_low; 986 u16 i; 987 988 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 989 990 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 991 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 992 993 for (i = 0; i < 4; i++) 994 mac_addr[i] = (u8)(rar_low >> (i*8)); 995 996 for (i = 0; i < 2; i++) 997 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 998 999 return IXGBE_SUCCESS; 1000 } 1001 1002 /** 1003 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 1004 * @hw: pointer to hardware structure 1005 * @link_status: the link status returned by the PCI config space 1006 * 1007 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1008 **/ 1009 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1010 { 1011 struct ixgbe_mac_info *mac = &hw->mac; 1012 1013 if (hw->bus.type == ixgbe_bus_type_unknown) 1014 hw->bus.type = ixgbe_bus_type_pci_express; 1015 1016 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1017 case IXGBE_PCI_LINK_WIDTH_1: 1018 hw->bus.width = ixgbe_bus_width_pcie_x1; 1019 break; 1020 case IXGBE_PCI_LINK_WIDTH_2: 1021 hw->bus.width = ixgbe_bus_width_pcie_x2; 1022 break; 1023 case IXGBE_PCI_LINK_WIDTH_4: 1024 hw->bus.width = ixgbe_bus_width_pcie_x4; 1025 break; 1026 case IXGBE_PCI_LINK_WIDTH_8: 1027 hw->bus.width = ixgbe_bus_width_pcie_x8; 1028 break; 1029 default: 1030 hw->bus.width = ixgbe_bus_width_unknown; 1031 break; 1032 } 1033 1034 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1035 case IXGBE_PCI_LINK_SPEED_2500: 1036 hw->bus.speed = ixgbe_bus_speed_2500; 1037 break; 1038 case IXGBE_PCI_LINK_SPEED_5000: 1039 hw->bus.speed = ixgbe_bus_speed_5000; 1040 break; 1041 case IXGBE_PCI_LINK_SPEED_8000: 1042 hw->bus.speed = ixgbe_bus_speed_8000; 1043 break; 1044 case IXGBE_PCI_LINK_SPEED_16000: 1045 hw->bus.speed = ixgbe_bus_speed_16000; 1046 break; 1047 default: 1048 hw->bus.speed = ixgbe_bus_speed_unknown; 1049 break; 1050 } 1051 1052 mac->ops.set_lan_id(hw); 1053 } 1054 1055 /** 1056 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1057 * @hw: pointer to hardware structure 1058 * 1059 * Gets the PCI bus info (speed, width, type) then calls helper function to 1060 * store this data within the ixgbe_hw structure. 1061 **/ 1062 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1063 { 1064 u16 link_status; 1065 1066 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1067 1068 /* Get the negotiated link width and speed from PCI config space */ 1069 link_status = IXGBE_READ_PCIE_WORD(hw, hw->mac.type == ixgbe_mac_E610 ? 1070 IXGBE_PCI_LINK_STATUS_E610 : 1071 IXGBE_PCI_LINK_STATUS); 1072 1073 ixgbe_set_pci_config_data_generic(hw, link_status); 1074 1075 return IXGBE_SUCCESS; 1076 } 1077 1078 /** 1079 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1080 * @hw: pointer to the HW structure 1081 * 1082 * Determines the LAN function id by reading memory-mapped registers and swaps 1083 * the port value if requested, and set MAC instance for devices that share 1084 * CS4227. 1085 **/ 1086 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1087 { 1088 struct ixgbe_bus_info *bus = &hw->bus; 1089 u32 reg; 1090 u16 ee_ctrl_4; 1091 1092 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1093 1094 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1095 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1096 bus->lan_id = (u8)bus->func; 1097 1098 /* check for a port swap */ 1099 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1100 if (reg & IXGBE_FACTPS_LFS) 1101 bus->func ^= 0x1; 1102 1103 /* Get MAC instance from EEPROM for configuring CS4227 */ 1104 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1105 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1106 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1107 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1108 } 1109 } 1110 1111 /** 1112 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1113 * @hw: pointer to hardware structure 1114 * 1115 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1116 * disables transmit and receive units. The adapter_stopped flag is used by 1117 * the shared code and drivers to determine if the adapter is in a stopped 1118 * state and should not touch the hardware. 1119 **/ 1120 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1121 { 1122 u32 reg_val; 1123 u16 i; 1124 1125 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1126 1127 /* 1128 * Set the adapter_stopped flag so other driver functions stop touching 1129 * the hardware 1130 */ 1131 hw->adapter_stopped = true; 1132 1133 /* Disable the receive unit */ 1134 ixgbe_disable_rx(hw); 1135 1136 /* Clear interrupt mask to stop interrupts from being generated */ 1137 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1138 1139 /* Clear any pending interrupts, flush previous writes */ 1140 IXGBE_READ_REG(hw, IXGBE_EICR); 1141 1142 /* Disable the transmit unit. Each queue must be disabled. */ 1143 for (i = 0; i < hw->mac.max_tx_queues; i++) 1144 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1145 1146 /* Disable the receive unit by stopping each queue */ 1147 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1148 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1149 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1150 reg_val |= IXGBE_RXDCTL_SWFLSH; 1151 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1152 } 1153 1154 /* flush all queues disables */ 1155 IXGBE_WRITE_FLUSH(hw); 1156 msec_delay(2); 1157 1158 /* 1159 * Prevent the PCI-E bus from hanging by disabling PCI-E primary 1160 * access and verify no pending requests 1161 */ 1162 return ixgbe_disable_pcie_primary(hw); 1163 } 1164 1165 /** 1166 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1167 * @hw: pointer to hardware structure 1168 * 1169 * Store the index for the link active LED. This will be used to support 1170 * blinking the LED. 1171 **/ 1172 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1173 { 1174 struct ixgbe_mac_info *mac = &hw->mac; 1175 u32 led_reg, led_mode; 1176 u8 i; 1177 1178 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1179 1180 /* Get LED link active from the LEDCTL register */ 1181 for (i = 0; i < 4; i++) { 1182 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1183 1184 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1185 IXGBE_LED_LINK_ACTIVE) { 1186 mac->led_link_act = i; 1187 return IXGBE_SUCCESS; 1188 } 1189 } 1190 1191 /* 1192 * If LEDCTL register does not have the LED link active set, then use 1193 * known MAC defaults. 1194 */ 1195 switch (hw->mac.type) { 1196 case ixgbe_mac_X550EM_a: 1197 case ixgbe_mac_X550EM_x: 1198 mac->led_link_act = 1; 1199 break; 1200 default: 1201 mac->led_link_act = 2; 1202 } 1203 return IXGBE_SUCCESS; 1204 } 1205 1206 /** 1207 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1208 * @hw: pointer to hardware structure 1209 * @index: led number to turn on 1210 **/ 1211 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1212 { 1213 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1214 1215 DEBUGFUNC("ixgbe_led_on_generic"); 1216 1217 if (index > 3) 1218 return IXGBE_ERR_PARAM; 1219 1220 /* To turn on the LED, set mode to ON. */ 1221 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1222 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1223 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1224 IXGBE_WRITE_FLUSH(hw); 1225 1226 return IXGBE_SUCCESS; 1227 } 1228 1229 /** 1230 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1231 * @hw: pointer to hardware structure 1232 * @index: led number to turn off 1233 **/ 1234 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1235 { 1236 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1237 1238 DEBUGFUNC("ixgbe_led_off_generic"); 1239 1240 if (index > 3) 1241 return IXGBE_ERR_PARAM; 1242 1243 /* To turn off the LED, set mode to OFF. */ 1244 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1245 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1246 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1247 IXGBE_WRITE_FLUSH(hw); 1248 1249 return IXGBE_SUCCESS; 1250 } 1251 1252 /** 1253 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1254 * @hw: pointer to hardware structure 1255 * 1256 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1257 * ixgbe_hw struct in order to set up EEPROM access. 1258 **/ 1259 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1260 { 1261 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1262 u32 eec; 1263 u16 eeprom_size; 1264 1265 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1266 1267 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1268 eeprom->type = ixgbe_eeprom_none; 1269 /* Set default semaphore delay to 10ms which is a well 1270 * tested value */ 1271 eeprom->semaphore_delay = 10; 1272 /* Clear EEPROM page size, it will be initialized as needed */ 1273 eeprom->word_page_size = 0; 1274 1275 /* 1276 * Check for EEPROM present first. 1277 * If not present leave as none 1278 */ 1279 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1280 if (eec & IXGBE_EEC_PRES) { 1281 eeprom->type = ixgbe_eeprom_spi; 1282 1283 /* 1284 * SPI EEPROM is assumed here. This code would need to 1285 * change if a future EEPROM is not SPI. 1286 */ 1287 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1288 IXGBE_EEC_SIZE_SHIFT); 1289 eeprom->word_size = 1 << (eeprom_size + 1290 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1291 } 1292 1293 if (eec & IXGBE_EEC_ADDR_SIZE) 1294 eeprom->address_bits = 16; 1295 else 1296 eeprom->address_bits = 8; 1297 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1298 "%d\n", eeprom->type, eeprom->word_size, 1299 eeprom->address_bits); 1300 } 1301 1302 return IXGBE_SUCCESS; 1303 } 1304 1305 /** 1306 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1307 * @hw: pointer to hardware structure 1308 * @offset: offset within the EEPROM to write 1309 * @words: number of word(s) 1310 * @data: 16 bit word(s) to write to EEPROM 1311 * 1312 * Reads 16 bit word(s) from EEPROM through bit-bang method 1313 **/ 1314 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1315 u16 words, u16 *data) 1316 { 1317 s32 status = IXGBE_SUCCESS; 1318 u16 i, count; 1319 1320 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1321 1322 hw->eeprom.ops.init_params(hw); 1323 1324 if (words == 0) { 1325 status = IXGBE_ERR_INVALID_ARGUMENT; 1326 goto out; 1327 } 1328 1329 if (offset + words > hw->eeprom.word_size) { 1330 status = IXGBE_ERR_EEPROM; 1331 goto out; 1332 } 1333 1334 /* 1335 * The EEPROM page size cannot be queried from the chip. We do lazy 1336 * initialization. It is worth to do that when we write large buffer. 1337 */ 1338 if ((hw->eeprom.word_page_size == 0) && 1339 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1340 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1341 1342 /* 1343 * We cannot hold synchronization semaphores for too long 1344 * to avoid other entity starvation. However it is more efficient 1345 * to read in bursts than synchronizing access for each word. 1346 */ 1347 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1348 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1349 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1350 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1351 count, &data[i]); 1352 1353 if (status != IXGBE_SUCCESS) 1354 break; 1355 } 1356 1357 out: 1358 return status; 1359 } 1360 1361 /** 1362 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1363 * @hw: pointer to hardware structure 1364 * @offset: offset within the EEPROM to be written to 1365 * @words: number of word(s) 1366 * @data: 16 bit word(s) to be written to the EEPROM 1367 * 1368 * If ixgbe_eeprom_update_checksum is not called after this function, the 1369 * EEPROM will most likely contain an invalid checksum. 1370 **/ 1371 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1372 u16 words, u16 *data) 1373 { 1374 s32 status; 1375 u16 word; 1376 u16 page_size; 1377 u16 i; 1378 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1379 1380 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1381 1382 /* Prepare the EEPROM for writing */ 1383 status = ixgbe_acquire_eeprom(hw); 1384 1385 if (status == IXGBE_SUCCESS) { 1386 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1387 ixgbe_release_eeprom(hw); 1388 status = IXGBE_ERR_EEPROM; 1389 } 1390 } 1391 1392 if (status == IXGBE_SUCCESS) { 1393 for (i = 0; i < words; i++) { 1394 ixgbe_standby_eeprom(hw); 1395 1396 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1397 ixgbe_shift_out_eeprom_bits(hw, 1398 IXGBE_EEPROM_WREN_OPCODE_SPI, 1399 IXGBE_EEPROM_OPCODE_BITS); 1400 1401 ixgbe_standby_eeprom(hw); 1402 1403 /* 1404 * Some SPI eeproms use the 8th address bit embedded 1405 * in the opcode 1406 */ 1407 if ((hw->eeprom.address_bits == 8) && 1408 ((offset + i) >= 128)) 1409 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1410 1411 /* Send the Write command (8-bit opcode + addr) */ 1412 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1413 IXGBE_EEPROM_OPCODE_BITS); 1414 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1415 hw->eeprom.address_bits); 1416 1417 page_size = hw->eeprom.word_page_size; 1418 1419 /* Send the data in burst via SPI*/ 1420 do { 1421 word = data[i]; 1422 word = (word >> 8) | (word << 8); 1423 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1424 1425 if (page_size == 0) 1426 break; 1427 1428 /* do not wrap around page */ 1429 if (((offset + i) & (page_size - 1)) == 1430 (page_size - 1)) 1431 break; 1432 } while (++i < words); 1433 1434 ixgbe_standby_eeprom(hw); 1435 msec_delay(10); 1436 } 1437 /* Done with writing - release the EEPROM */ 1438 ixgbe_release_eeprom(hw); 1439 } 1440 1441 return status; 1442 } 1443 1444 /** 1445 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1446 * @hw: pointer to hardware structure 1447 * @offset: offset within the EEPROM to be written to 1448 * @data: 16 bit word to be written to the EEPROM 1449 * 1450 * If ixgbe_eeprom_update_checksum is not called after this function, the 1451 * EEPROM will most likely contain an invalid checksum. 1452 **/ 1453 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1454 { 1455 s32 status; 1456 1457 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1458 1459 hw->eeprom.ops.init_params(hw); 1460 1461 if (offset >= hw->eeprom.word_size) { 1462 status = IXGBE_ERR_EEPROM; 1463 goto out; 1464 } 1465 1466 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1467 1468 out: 1469 return status; 1470 } 1471 1472 /** 1473 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1474 * @hw: pointer to hardware structure 1475 * @offset: offset within the EEPROM to be read 1476 * @data: read 16 bit words(s) from EEPROM 1477 * @words: number of word(s) 1478 * 1479 * Reads 16 bit word(s) from EEPROM through bit-bang method 1480 **/ 1481 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1482 u16 words, u16 *data) 1483 { 1484 s32 status = IXGBE_SUCCESS; 1485 u16 i, count; 1486 1487 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1488 1489 hw->eeprom.ops.init_params(hw); 1490 1491 if (words == 0) { 1492 status = IXGBE_ERR_INVALID_ARGUMENT; 1493 goto out; 1494 } 1495 1496 if (offset + words > hw->eeprom.word_size) { 1497 status = IXGBE_ERR_EEPROM; 1498 goto out; 1499 } 1500 1501 /* 1502 * We cannot hold synchronization semaphores for too long 1503 * to avoid other entity starvation. However it is more efficient 1504 * to read in bursts than synchronizing access for each word. 1505 */ 1506 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1507 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1508 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1509 1510 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1511 count, &data[i]); 1512 1513 if (status != IXGBE_SUCCESS) 1514 break; 1515 } 1516 1517 out: 1518 return status; 1519 } 1520 1521 /** 1522 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1523 * @hw: pointer to hardware structure 1524 * @offset: offset within the EEPROM to be read 1525 * @words: number of word(s) 1526 * @data: read 16 bit word(s) from EEPROM 1527 * 1528 * Reads 16 bit word(s) from EEPROM through bit-bang method 1529 **/ 1530 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1531 u16 words, u16 *data) 1532 { 1533 s32 status; 1534 u16 word_in; 1535 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1536 u16 i; 1537 1538 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1539 1540 /* Prepare the EEPROM for reading */ 1541 status = ixgbe_acquire_eeprom(hw); 1542 1543 if (status == IXGBE_SUCCESS) { 1544 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1545 ixgbe_release_eeprom(hw); 1546 status = IXGBE_ERR_EEPROM; 1547 } 1548 } 1549 1550 if (status == IXGBE_SUCCESS) { 1551 for (i = 0; i < words; i++) { 1552 ixgbe_standby_eeprom(hw); 1553 /* 1554 * Some SPI eeproms use the 8th address bit embedded 1555 * in the opcode 1556 */ 1557 if ((hw->eeprom.address_bits == 8) && 1558 ((offset + i) >= 128)) 1559 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1560 1561 /* Send the READ command (opcode + addr) */ 1562 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1563 IXGBE_EEPROM_OPCODE_BITS); 1564 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1565 hw->eeprom.address_bits); 1566 1567 /* Read the data. */ 1568 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1569 data[i] = (word_in >> 8) | (word_in << 8); 1570 } 1571 1572 /* End this read operation */ 1573 ixgbe_release_eeprom(hw); 1574 } 1575 1576 return status; 1577 } 1578 1579 /** 1580 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1581 * @hw: pointer to hardware structure 1582 * @offset: offset within the EEPROM to be read 1583 * @data: read 16 bit value from EEPROM 1584 * 1585 * Reads 16 bit value from EEPROM through bit-bang method 1586 **/ 1587 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1588 u16 *data) 1589 { 1590 s32 status; 1591 1592 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1593 1594 hw->eeprom.ops.init_params(hw); 1595 1596 if (offset >= hw->eeprom.word_size) { 1597 status = IXGBE_ERR_EEPROM; 1598 goto out; 1599 } 1600 1601 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1602 1603 out: 1604 return status; 1605 } 1606 1607 /** 1608 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1609 * @hw: pointer to hardware structure 1610 * @offset: offset of word in the EEPROM to read 1611 * @words: number of word(s) 1612 * @data: 16 bit word(s) from the EEPROM 1613 * 1614 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1615 **/ 1616 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1617 u16 words, u16 *data) 1618 { 1619 u32 eerd; 1620 s32 status = IXGBE_SUCCESS; 1621 u32 i; 1622 1623 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1624 1625 hw->eeprom.ops.init_params(hw); 1626 1627 if (words == 0) { 1628 status = IXGBE_ERR_INVALID_ARGUMENT; 1629 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1630 goto out; 1631 } 1632 1633 if (offset >= hw->eeprom.word_size) { 1634 status = IXGBE_ERR_EEPROM; 1635 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1636 goto out; 1637 } 1638 1639 for (i = 0; i < words; i++) { 1640 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1641 IXGBE_EEPROM_RW_REG_START; 1642 1643 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1644 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1645 1646 if (status == IXGBE_SUCCESS) { 1647 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1648 IXGBE_EEPROM_RW_REG_DATA); 1649 } else { 1650 DEBUGOUT("Eeprom read timed out\n"); 1651 goto out; 1652 } 1653 } 1654 out: 1655 return status; 1656 } 1657 1658 /** 1659 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1660 * @hw: pointer to hardware structure 1661 * @offset: offset within the EEPROM to be used as a scratch pad 1662 * 1663 * Discover EEPROM page size by writing marching data at given offset. 1664 * This function is called only when we are writing a new large buffer 1665 * at given offset so the data would be overwritten anyway. 1666 **/ 1667 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1668 u16 offset) 1669 { 1670 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1671 s32 status = IXGBE_SUCCESS; 1672 u16 i; 1673 1674 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1675 1676 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1677 data[i] = i; 1678 1679 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1680 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1681 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1682 hw->eeprom.word_page_size = 0; 1683 if (status != IXGBE_SUCCESS) 1684 goto out; 1685 1686 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1687 if (status != IXGBE_SUCCESS) 1688 goto out; 1689 1690 /* 1691 * When writing in burst more than the actual page size 1692 * EEPROM address wraps around current page. 1693 */ 1694 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1695 1696 DEBUGOUT1("Detected EEPROM page size = %d words.", 1697 hw->eeprom.word_page_size); 1698 out: 1699 return status; 1700 } 1701 1702 /** 1703 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1704 * @hw: pointer to hardware structure 1705 * @offset: offset of word in the EEPROM to read 1706 * @data: word read from the EEPROM 1707 * 1708 * Reads a 16 bit word from the EEPROM using the EERD register. 1709 **/ 1710 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1711 { 1712 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1713 } 1714 1715 /** 1716 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1717 * @hw: pointer to hardware structure 1718 * @offset: offset of word in the EEPROM to write 1719 * @words: number of word(s) 1720 * @data: word(s) write to the EEPROM 1721 * 1722 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1723 **/ 1724 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1725 u16 words, u16 *data) 1726 { 1727 u32 eewr; 1728 s32 status = IXGBE_SUCCESS; 1729 u16 i; 1730 1731 DEBUGFUNC("ixgbe_write_eewr_generic"); 1732 1733 hw->eeprom.ops.init_params(hw); 1734 1735 if (words == 0) { 1736 status = IXGBE_ERR_INVALID_ARGUMENT; 1737 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1738 goto out; 1739 } 1740 1741 if (offset >= hw->eeprom.word_size) { 1742 status = IXGBE_ERR_EEPROM; 1743 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1744 goto out; 1745 } 1746 1747 for (i = 0; i < words; i++) { 1748 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1749 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1750 IXGBE_EEPROM_RW_REG_START; 1751 1752 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1753 if (status != IXGBE_SUCCESS) { 1754 DEBUGOUT("Eeprom write EEWR timed out\n"); 1755 goto out; 1756 } 1757 1758 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1759 1760 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1761 if (status != IXGBE_SUCCESS) { 1762 DEBUGOUT("Eeprom write EEWR timed out\n"); 1763 goto out; 1764 } 1765 } 1766 1767 out: 1768 return status; 1769 } 1770 1771 /** 1772 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1773 * @hw: pointer to hardware structure 1774 * @offset: offset of word in the EEPROM to write 1775 * @data: word write to the EEPROM 1776 * 1777 * Write a 16 bit word to the EEPROM using the EEWR register. 1778 **/ 1779 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1780 { 1781 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1782 } 1783 1784 /** 1785 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1786 * @hw: pointer to hardware structure 1787 * @ee_reg: EEPROM flag for polling 1788 * 1789 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1790 * read or write is done respectively. 1791 **/ 1792 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1793 { 1794 u32 i; 1795 u32 reg; 1796 s32 status = IXGBE_ERR_EEPROM; 1797 1798 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1799 1800 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1801 if (ee_reg == IXGBE_NVM_POLL_READ) 1802 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1803 else 1804 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1805 1806 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1807 status = IXGBE_SUCCESS; 1808 break; 1809 } 1810 usec_delay(5); 1811 } 1812 1813 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1814 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1815 "EEPROM read/write done polling timed out"); 1816 1817 return status; 1818 } 1819 1820 /** 1821 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1822 * @hw: pointer to hardware structure 1823 * 1824 * Prepares EEPROM for access using bit-bang method. This function should 1825 * be called before issuing a command to the EEPROM. 1826 **/ 1827 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1828 { 1829 s32 status = IXGBE_SUCCESS; 1830 u32 eec; 1831 u32 i; 1832 1833 DEBUGFUNC("ixgbe_acquire_eeprom"); 1834 1835 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1836 != IXGBE_SUCCESS) 1837 status = IXGBE_ERR_SWFW_SYNC; 1838 1839 if (status == IXGBE_SUCCESS) { 1840 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1841 1842 /* Request EEPROM Access */ 1843 eec |= IXGBE_EEC_REQ; 1844 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1845 1846 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1847 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1848 if (eec & IXGBE_EEC_GNT) 1849 break; 1850 usec_delay(5); 1851 } 1852 1853 /* Release if grant not acquired */ 1854 if (!(eec & IXGBE_EEC_GNT)) { 1855 eec &= ~IXGBE_EEC_REQ; 1856 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1857 DEBUGOUT("Could not acquire EEPROM grant\n"); 1858 1859 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1860 status = IXGBE_ERR_EEPROM; 1861 } 1862 1863 /* Setup EEPROM for Read/Write */ 1864 if (status == IXGBE_SUCCESS) { 1865 /* Clear CS and SK */ 1866 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1867 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1868 IXGBE_WRITE_FLUSH(hw); 1869 usec_delay(1); 1870 } 1871 } 1872 return status; 1873 } 1874 1875 /** 1876 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1877 * @hw: pointer to hardware structure 1878 * 1879 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1880 **/ 1881 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1882 { 1883 s32 status = IXGBE_ERR_EEPROM; 1884 u32 timeout = 2000; 1885 u32 i; 1886 u32 swsm; 1887 1888 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1889 1890 /* Get SMBI software semaphore between device drivers first */ 1891 for (i = 0; i < timeout; i++) { 1892 /* 1893 * If the SMBI bit is 0 when we read it, then the bit will be 1894 * set and we have the semaphore 1895 */ 1896 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1897 if (!(swsm & IXGBE_SWSM_SMBI)) { 1898 status = IXGBE_SUCCESS; 1899 break; 1900 } 1901 usec_delay(50); 1902 } 1903 1904 if (i == timeout) { 1905 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1906 "not granted.\n"); 1907 /* 1908 * this release is particularly important because our attempts 1909 * above to get the semaphore may have succeeded, and if there 1910 * was a timeout, we should unconditionally clear the semaphore 1911 * bits to free the driver to make progress 1912 */ 1913 ixgbe_release_eeprom_semaphore(hw); 1914 1915 usec_delay(50); 1916 /* 1917 * one last try 1918 * If the SMBI bit is 0 when we read it, then the bit will be 1919 * set and we have the semaphore 1920 */ 1921 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1922 if (!(swsm & IXGBE_SWSM_SMBI)) 1923 status = IXGBE_SUCCESS; 1924 } 1925 1926 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1927 if (status == IXGBE_SUCCESS) { 1928 for (i = 0; i < timeout; i++) { 1929 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1930 1931 /* Set the SW EEPROM semaphore bit to request access */ 1932 swsm |= IXGBE_SWSM_SWESMBI; 1933 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1934 1935 /* 1936 * If we set the bit successfully then we got the 1937 * semaphore. 1938 */ 1939 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1940 if (swsm & IXGBE_SWSM_SWESMBI) 1941 break; 1942 1943 usec_delay(50); 1944 } 1945 1946 /* 1947 * Release semaphores and return error if SW EEPROM semaphore 1948 * was not granted because we don't have access to the EEPROM 1949 */ 1950 if (i >= timeout) { 1951 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1952 "SWESMBI Software EEPROM semaphore not granted.\n"); 1953 ixgbe_release_eeprom_semaphore(hw); 1954 status = IXGBE_ERR_EEPROM; 1955 } 1956 } else { 1957 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1958 "Software semaphore SMBI between device drivers " 1959 "not granted.\n"); 1960 } 1961 1962 return status; 1963 } 1964 1965 /** 1966 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1967 * @hw: pointer to hardware structure 1968 * 1969 * This function clears hardware semaphore bits. 1970 **/ 1971 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1972 { 1973 u32 swsm; 1974 1975 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1976 1977 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1978 1979 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1980 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1981 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1982 IXGBE_WRITE_FLUSH(hw); 1983 } 1984 1985 /** 1986 * ixgbe_ready_eeprom - Polls for EEPROM ready 1987 * @hw: pointer to hardware structure 1988 **/ 1989 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1990 { 1991 s32 status = IXGBE_SUCCESS; 1992 u16 i; 1993 u8 spi_stat_reg; 1994 1995 DEBUGFUNC("ixgbe_ready_eeprom"); 1996 1997 /* 1998 * Read "Status Register" repeatedly until the LSB is cleared. The 1999 * EEPROM will signal that the command has been completed by clearing 2000 * bit 0 of the internal status register. If it's not cleared within 2001 * 5 milliseconds, then error out. 2002 */ 2003 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 2004 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 2005 IXGBE_EEPROM_OPCODE_BITS); 2006 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 2007 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 2008 break; 2009 2010 usec_delay(5); 2011 ixgbe_standby_eeprom(hw); 2012 } 2013 2014 /* 2015 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2016 * devices (and only 0-5mSec on 5V devices) 2017 */ 2018 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2019 DEBUGOUT("SPI EEPROM Status error\n"); 2020 status = IXGBE_ERR_EEPROM; 2021 } 2022 2023 return status; 2024 } 2025 2026 /** 2027 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2028 * @hw: pointer to hardware structure 2029 **/ 2030 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2031 { 2032 u32 eec; 2033 2034 DEBUGFUNC("ixgbe_standby_eeprom"); 2035 2036 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2037 2038 /* Toggle CS to flush commands */ 2039 eec |= IXGBE_EEC_CS; 2040 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2041 IXGBE_WRITE_FLUSH(hw); 2042 usec_delay(1); 2043 eec &= ~IXGBE_EEC_CS; 2044 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2045 IXGBE_WRITE_FLUSH(hw); 2046 usec_delay(1); 2047 } 2048 2049 /** 2050 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2051 * @hw: pointer to hardware structure 2052 * @data: data to send to the EEPROM 2053 * @count: number of bits to shift out 2054 **/ 2055 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2056 u16 count) 2057 { 2058 u32 eec; 2059 u32 mask; 2060 u32 i; 2061 2062 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2063 2064 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2065 2066 /* 2067 * Mask is used to shift "count" bits of "data" out to the EEPROM 2068 * one bit at a time. Determine the starting bit based on count 2069 */ 2070 mask = 0x01 << (count - 1); 2071 2072 for (i = 0; i < count; i++) { 2073 /* 2074 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2075 * "1", and then raising and then lowering the clock (the SK 2076 * bit controls the clock input to the EEPROM). A "0" is 2077 * shifted out to the EEPROM by setting "DI" to "0" and then 2078 * raising and then lowering the clock. 2079 */ 2080 if (data & mask) 2081 eec |= IXGBE_EEC_DI; 2082 else 2083 eec &= ~IXGBE_EEC_DI; 2084 2085 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2086 IXGBE_WRITE_FLUSH(hw); 2087 2088 usec_delay(1); 2089 2090 ixgbe_raise_eeprom_clk(hw, &eec); 2091 ixgbe_lower_eeprom_clk(hw, &eec); 2092 2093 /* 2094 * Shift mask to signify next bit of data to shift in to the 2095 * EEPROM 2096 */ 2097 mask = mask >> 1; 2098 } 2099 2100 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2101 eec &= ~IXGBE_EEC_DI; 2102 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2103 IXGBE_WRITE_FLUSH(hw); 2104 } 2105 2106 /** 2107 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2108 * @hw: pointer to hardware structure 2109 * @count: number of bits to shift 2110 **/ 2111 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2112 { 2113 u32 eec; 2114 u32 i; 2115 u16 data = 0; 2116 2117 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2118 2119 /* 2120 * In order to read a register from the EEPROM, we need to shift 2121 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2122 * the clock input to the EEPROM (setting the SK bit), and then reading 2123 * the value of the "DO" bit. During this "shifting in" process the 2124 * "DI" bit should always be clear. 2125 */ 2126 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2127 2128 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2129 2130 for (i = 0; i < count; i++) { 2131 data = data << 1; 2132 ixgbe_raise_eeprom_clk(hw, &eec); 2133 2134 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2135 2136 eec &= ~(IXGBE_EEC_DI); 2137 if (eec & IXGBE_EEC_DO) 2138 data |= 1; 2139 2140 ixgbe_lower_eeprom_clk(hw, &eec); 2141 } 2142 2143 return data; 2144 } 2145 2146 /** 2147 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2148 * @hw: pointer to hardware structure 2149 * @eec: EEC register's current value 2150 **/ 2151 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2152 { 2153 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2154 2155 /* 2156 * Raise the clock input to the EEPROM 2157 * (setting the SK bit), then delay 2158 */ 2159 *eec = *eec | IXGBE_EEC_SK; 2160 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2161 IXGBE_WRITE_FLUSH(hw); 2162 usec_delay(1); 2163 } 2164 2165 /** 2166 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2167 * @hw: pointer to hardware structure 2168 * @eec: EEC's current value 2169 **/ 2170 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2171 { 2172 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2173 2174 /* 2175 * Lower the clock input to the EEPROM (clearing the SK bit), then 2176 * delay 2177 */ 2178 *eec = *eec & ~IXGBE_EEC_SK; 2179 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2180 IXGBE_WRITE_FLUSH(hw); 2181 usec_delay(1); 2182 } 2183 2184 /** 2185 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2186 * @hw: pointer to hardware structure 2187 **/ 2188 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2189 { 2190 u32 eec; 2191 2192 DEBUGFUNC("ixgbe_release_eeprom"); 2193 2194 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2195 2196 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2197 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2198 2199 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2200 IXGBE_WRITE_FLUSH(hw); 2201 2202 usec_delay(1); 2203 2204 /* Stop requesting EEPROM access */ 2205 eec &= ~IXGBE_EEC_REQ; 2206 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2207 2208 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2209 2210 /* Delay before attempt to obtain semaphore again to allow FW access */ 2211 msec_delay(hw->eeprom.semaphore_delay); 2212 } 2213 2214 /** 2215 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2216 * @hw: pointer to hardware structure 2217 * 2218 * Returns a negative error code on error, or the 16-bit checksum 2219 **/ 2220 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2221 { 2222 u16 i; 2223 u16 j; 2224 u16 checksum = 0; 2225 u16 length = 0; 2226 u16 pointer = 0; 2227 u16 word = 0; 2228 2229 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2230 2231 /* Include 0x0-0x3F in the checksum */ 2232 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2233 if (hw->eeprom.ops.read(hw, i, &word)) { 2234 DEBUGOUT("EEPROM read failed\n"); 2235 return IXGBE_ERR_EEPROM; 2236 } 2237 checksum += word; 2238 } 2239 2240 /* Include all data from pointers except for the fw pointer */ 2241 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2242 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2243 DEBUGOUT("EEPROM read failed\n"); 2244 return IXGBE_ERR_EEPROM; 2245 } 2246 2247 /* If the pointer seems invalid */ 2248 if (pointer == 0xFFFF || pointer == 0) 2249 continue; 2250 2251 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2252 DEBUGOUT("EEPROM read failed\n"); 2253 return IXGBE_ERR_EEPROM; 2254 } 2255 2256 if (length == 0xFFFF || length == 0) 2257 continue; 2258 2259 for (j = pointer + 1; j <= pointer + length; j++) { 2260 if (hw->eeprom.ops.read(hw, j, &word)) { 2261 DEBUGOUT("EEPROM read failed\n"); 2262 return IXGBE_ERR_EEPROM; 2263 } 2264 checksum += word; 2265 } 2266 } 2267 2268 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2269 2270 return (s32)checksum; 2271 } 2272 2273 /** 2274 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2275 * @hw: pointer to hardware structure 2276 * @checksum_val: calculated checksum 2277 * 2278 * Performs checksum calculation and validates the EEPROM checksum. If the 2279 * caller does not need checksum_val, the value can be NULL. 2280 **/ 2281 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2282 u16 *checksum_val) 2283 { 2284 s32 status; 2285 u16 checksum; 2286 u16 read_checksum = 0; 2287 2288 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2289 2290 /* Read the first word from the EEPROM. If this times out or fails, do 2291 * not continue or we could be in for a very long wait while every 2292 * EEPROM read fails 2293 */ 2294 status = hw->eeprom.ops.read(hw, 0, &checksum); 2295 if (status) { 2296 DEBUGOUT("EEPROM read failed\n"); 2297 return status; 2298 } 2299 2300 status = hw->eeprom.ops.calc_checksum(hw); 2301 if (status < 0) 2302 return status; 2303 2304 checksum = (u16)(status & 0xffff); 2305 2306 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2307 if (status) { 2308 DEBUGOUT("EEPROM read failed\n"); 2309 return status; 2310 } 2311 2312 /* Verify read checksum from EEPROM is the same as 2313 * calculated checksum 2314 */ 2315 if (read_checksum != checksum) 2316 status = IXGBE_ERR_EEPROM_CHECKSUM; 2317 2318 /* If the user cares, return the calculated checksum */ 2319 if (checksum_val) 2320 *checksum_val = checksum; 2321 2322 return status; 2323 } 2324 2325 /** 2326 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2327 * @hw: pointer to hardware structure 2328 **/ 2329 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2330 { 2331 s32 status; 2332 u16 checksum; 2333 2334 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2335 2336 /* Read the first word from the EEPROM. If this times out or fails, do 2337 * not continue or we could be in for a very long wait while every 2338 * EEPROM read fails 2339 */ 2340 status = hw->eeprom.ops.read(hw, 0, &checksum); 2341 if (status) { 2342 DEBUGOUT("EEPROM read failed\n"); 2343 return status; 2344 } 2345 2346 status = hw->eeprom.ops.calc_checksum(hw); 2347 if (status < 0) 2348 return status; 2349 2350 checksum = (u16)(status & 0xffff); 2351 2352 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2353 2354 return status; 2355 } 2356 2357 /** 2358 * ixgbe_validate_mac_addr - Validate MAC address 2359 * @mac_addr: pointer to MAC address. 2360 * 2361 * Tests a MAC address to ensure it is a valid Individual Address. 2362 **/ 2363 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2364 { 2365 s32 status = IXGBE_SUCCESS; 2366 2367 DEBUGFUNC("ixgbe_validate_mac_addr"); 2368 2369 /* Make sure it is not a multicast address */ 2370 if (IXGBE_IS_MULTICAST(mac_addr)) { 2371 status = IXGBE_ERR_INVALID_MAC_ADDR; 2372 /* Not a broadcast address */ 2373 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2374 status = IXGBE_ERR_INVALID_MAC_ADDR; 2375 /* Reject the zero address */ 2376 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2377 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2378 status = IXGBE_ERR_INVALID_MAC_ADDR; 2379 } 2380 return status; 2381 } 2382 2383 /** 2384 * ixgbe_set_rar_generic - Set Rx address register 2385 * @hw: pointer to hardware structure 2386 * @index: Receive address register to write 2387 * @addr: Address to put into receive address register 2388 * @vmdq: VMDq "set" or "pool" index 2389 * @enable_addr: set flag that address is active 2390 * 2391 * Puts an ethernet address into a receive address register. 2392 **/ 2393 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2394 u32 enable_addr) 2395 { 2396 u32 rar_low, rar_high; 2397 u32 rar_entries = hw->mac.num_rar_entries; 2398 2399 DEBUGFUNC("ixgbe_set_rar_generic"); 2400 2401 /* Make sure we are using a valid rar index range */ 2402 if (index >= rar_entries) { 2403 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2404 "RAR index %d is out of range.\n", index); 2405 return IXGBE_ERR_INVALID_ARGUMENT; 2406 } 2407 2408 /* setup VMDq pool selection before this RAR gets enabled */ 2409 hw->mac.ops.set_vmdq(hw, index, vmdq); 2410 2411 /* 2412 * HW expects these in little endian so we reverse the byte 2413 * order from network order (big endian) to little endian 2414 */ 2415 rar_low = ((u32)addr[0] | 2416 ((u32)addr[1] << 8) | 2417 ((u32)addr[2] << 16) | 2418 ((u32)addr[3] << 24)); 2419 /* 2420 * Some parts put the VMDq setting in the extra RAH bits, 2421 * so save everything except the lower 16 bits that hold part 2422 * of the address and the address valid bit. 2423 */ 2424 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2425 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2426 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2427 2428 if (enable_addr != 0) 2429 rar_high |= IXGBE_RAH_AV; 2430 2431 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2432 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2433 2434 return IXGBE_SUCCESS; 2435 } 2436 2437 /** 2438 * ixgbe_clear_rar_generic - Remove Rx address register 2439 * @hw: pointer to hardware structure 2440 * @index: Receive address register to write 2441 * 2442 * Clears an ethernet address from a receive address register. 2443 **/ 2444 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2445 { 2446 u32 rar_high; 2447 u32 rar_entries = hw->mac.num_rar_entries; 2448 2449 DEBUGFUNC("ixgbe_clear_rar_generic"); 2450 2451 /* Make sure we are using a valid rar index range */ 2452 if (index >= rar_entries) { 2453 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2454 "RAR index %d is out of range.\n", index); 2455 return IXGBE_ERR_INVALID_ARGUMENT; 2456 } 2457 2458 /* 2459 * Some parts put the VMDq setting in the extra RAH bits, 2460 * so save everything except the lower 16 bits that hold part 2461 * of the address and the address valid bit. 2462 */ 2463 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2464 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2465 2466 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2467 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2468 2469 /* clear VMDq pool/queue selection for this RAR */ 2470 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2471 2472 return IXGBE_SUCCESS; 2473 } 2474 2475 /** 2476 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2477 * @hw: pointer to hardware structure 2478 * 2479 * Places the MAC address in receive address register 0 and clears the rest 2480 * of the receive address registers. Clears the multicast table. Assumes 2481 * the receiver is in reset when the routine is called. 2482 **/ 2483 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2484 { 2485 u32 i; 2486 u32 rar_entries = hw->mac.num_rar_entries; 2487 2488 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2489 2490 /* 2491 * If the current mac address is valid, assume it is a software override 2492 * to the permanent address. 2493 * Otherwise, use the permanent address from the eeprom. 2494 */ 2495 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2496 IXGBE_ERR_INVALID_MAC_ADDR) { 2497 /* Get the MAC address from the RAR0 for later reference */ 2498 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2499 2500 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2501 hw->mac.addr[0], hw->mac.addr[1], 2502 hw->mac.addr[2]); 2503 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2504 hw->mac.addr[4], hw->mac.addr[5]); 2505 } else { 2506 /* Setup the receive address. */ 2507 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2508 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2509 hw->mac.addr[0], hw->mac.addr[1], 2510 hw->mac.addr[2]); 2511 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2512 hw->mac.addr[4], hw->mac.addr[5]); 2513 2514 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2515 } 2516 2517 /* clear VMDq pool/queue selection for RAR 0 */ 2518 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2519 2520 hw->addr_ctrl.overflow_promisc = 0; 2521 2522 hw->addr_ctrl.rar_used_count = 1; 2523 2524 /* Zero out the other receive addresses. */ 2525 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2526 for (i = 1; i < rar_entries; i++) { 2527 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2528 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2529 } 2530 2531 /* Clear the MTA */ 2532 hw->addr_ctrl.mta_in_use = 0; 2533 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2534 2535 DEBUGOUT(" Clearing MTA\n"); 2536 for (i = 0; i < hw->mac.mcft_size; i++) 2537 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2538 2539 ixgbe_init_uta_tables(hw); 2540 2541 return IXGBE_SUCCESS; 2542 } 2543 2544 /** 2545 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2546 * @hw: pointer to hardware structure 2547 * @addr: new address 2548 * @vmdq: VMDq "set" or "pool" index 2549 * 2550 * Adds it to unused receive address register or goes into promiscuous mode. 2551 **/ 2552 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2553 { 2554 u32 rar_entries = hw->mac.num_rar_entries; 2555 u32 rar; 2556 2557 DEBUGFUNC("ixgbe_add_uc_addr"); 2558 2559 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2560 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2561 2562 /* 2563 * Place this address in the RAR if there is room, 2564 * else put the controller into promiscuous mode 2565 */ 2566 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2567 rar = hw->addr_ctrl.rar_used_count; 2568 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2569 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2570 hw->addr_ctrl.rar_used_count++; 2571 } else { 2572 hw->addr_ctrl.overflow_promisc++; 2573 } 2574 2575 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2576 } 2577 2578 /** 2579 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2580 * @hw: pointer to hardware structure 2581 * @addr_list: the list of new addresses 2582 * @addr_count: number of addresses 2583 * @next: iterator function to walk the address list 2584 * 2585 * The given list replaces any existing list. Clears the secondary addrs from 2586 * receive address registers. Uses unused receive address registers for the 2587 * first secondary addresses, and falls back to promiscuous mode as needed. 2588 * 2589 * Drivers using secondary unicast addresses must set user_set_promisc when 2590 * manually putting the device into promiscuous mode. 2591 **/ 2592 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2593 u32 addr_count, ixgbe_mc_addr_itr next) 2594 { 2595 u8 *addr; 2596 u32 i; 2597 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2598 u32 uc_addr_in_use; 2599 u32 fctrl; 2600 u32 vmdq; 2601 2602 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2603 2604 /* 2605 * Clear accounting of old secondary address list, 2606 * don't count RAR[0] 2607 */ 2608 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2609 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2610 hw->addr_ctrl.overflow_promisc = 0; 2611 2612 /* Zero out the other receive addresses */ 2613 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2614 for (i = 0; i < uc_addr_in_use; i++) { 2615 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2616 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2617 } 2618 2619 /* Add the new addresses */ 2620 for (i = 0; i < addr_count; i++) { 2621 DEBUGOUT(" Adding the secondary addresses:\n"); 2622 addr = next(hw, &addr_list, &vmdq); 2623 ixgbe_add_uc_addr(hw, addr, vmdq); 2624 } 2625 2626 if (hw->addr_ctrl.overflow_promisc) { 2627 /* enable promisc if not already in overflow or set by user */ 2628 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2629 DEBUGOUT(" Entering address overflow promisc mode\n"); 2630 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2631 fctrl |= IXGBE_FCTRL_UPE; 2632 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2633 } 2634 } else { 2635 /* only disable if set by overflow, not by user */ 2636 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2637 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2638 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2639 fctrl &= ~IXGBE_FCTRL_UPE; 2640 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2641 } 2642 } 2643 2644 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2645 return IXGBE_SUCCESS; 2646 } 2647 2648 /** 2649 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2650 * @hw: pointer to hardware structure 2651 * @mc_addr: the multicast address 2652 * 2653 * Extracts the 12 bits, from a multicast address, to determine which 2654 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2655 * incoming rx multicast addresses, to determine the bit-vector to check in 2656 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2657 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2658 * to mc_filter_type. 2659 **/ 2660 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2661 { 2662 u32 vector = 0; 2663 2664 DEBUGFUNC("ixgbe_mta_vector"); 2665 2666 switch (hw->mac.mc_filter_type) { 2667 case 0: /* use bits [47:36] of the address */ 2668 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2669 break; 2670 case 1: /* use bits [46:35] of the address */ 2671 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2672 break; 2673 case 2: /* use bits [45:34] of the address */ 2674 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2675 break; 2676 case 3: /* use bits [43:32] of the address */ 2677 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2678 break; 2679 default: /* Invalid mc_filter_type */ 2680 DEBUGOUT("MC filter type param set incorrectly\n"); 2681 ASSERT(0); 2682 break; 2683 } 2684 2685 /* vector can only be 12-bits or boundary will be exceeded */ 2686 vector &= 0xFFF; 2687 return vector; 2688 } 2689 2690 /** 2691 * ixgbe_set_mta - Set bit-vector in multicast table 2692 * @hw: pointer to hardware structure 2693 * @mc_addr: Multicast address 2694 * 2695 * Sets the bit-vector in the multicast table. 2696 **/ 2697 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2698 { 2699 u32 vector; 2700 u32 vector_bit; 2701 u32 vector_reg; 2702 2703 DEBUGFUNC("ixgbe_set_mta"); 2704 2705 hw->addr_ctrl.mta_in_use++; 2706 2707 vector = ixgbe_mta_vector(hw, mc_addr); 2708 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2709 2710 /* 2711 * The MTA is a register array of 128 32-bit registers. It is treated 2712 * like an array of 4096 bits. We want to set bit 2713 * BitArray[vector_value]. So we figure out what register the bit is 2714 * in, read it, OR in the new bit, then write back the new value. The 2715 * register is determined by the upper 7 bits of the vector value and 2716 * the bit within that register are determined by the lower 5 bits of 2717 * the value. 2718 */ 2719 vector_reg = (vector >> 5) & 0x7F; 2720 vector_bit = vector & 0x1F; 2721 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2722 } 2723 2724 /** 2725 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2726 * @hw: pointer to hardware structure 2727 * @mc_addr_list: the list of new multicast addresses 2728 * @mc_addr_count: number of addresses 2729 * @next: iterator function to walk the multicast address list 2730 * @clear: flag, when set clears the table beforehand 2731 * 2732 * When the clear flag is set, the given list replaces any existing list. 2733 * Hashes the given addresses into the multicast table. 2734 **/ 2735 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2736 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2737 bool clear) 2738 { 2739 u32 i; 2740 u32 vmdq; 2741 2742 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2743 2744 /* 2745 * Set the new number of MC addresses that we are being requested to 2746 * use. 2747 */ 2748 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2749 hw->addr_ctrl.mta_in_use = 0; 2750 2751 /* Clear mta_shadow */ 2752 if (clear) { 2753 DEBUGOUT(" Clearing MTA\n"); 2754 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2755 } 2756 2757 /* Update mta_shadow */ 2758 for (i = 0; i < mc_addr_count; i++) { 2759 DEBUGOUT(" Adding the multicast addresses:\n"); 2760 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2761 } 2762 2763 /* Enable mta */ 2764 for (i = 0; i < hw->mac.mcft_size; i++) 2765 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2766 hw->mac.mta_shadow[i]); 2767 2768 if (hw->addr_ctrl.mta_in_use > 0) 2769 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2770 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2771 2772 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2773 return IXGBE_SUCCESS; 2774 } 2775 2776 /** 2777 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2778 * @hw: pointer to hardware structure 2779 * 2780 * Enables multicast address in RAR and the use of the multicast hash table. 2781 **/ 2782 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2783 { 2784 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2785 2786 DEBUGFUNC("ixgbe_enable_mc_generic"); 2787 2788 if (a->mta_in_use > 0) 2789 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2790 hw->mac.mc_filter_type); 2791 2792 return IXGBE_SUCCESS; 2793 } 2794 2795 /** 2796 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2797 * @hw: pointer to hardware structure 2798 * 2799 * Disables multicast address in RAR and the use of the multicast hash table. 2800 **/ 2801 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2802 { 2803 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2804 2805 DEBUGFUNC("ixgbe_disable_mc_generic"); 2806 2807 if (a->mta_in_use > 0) 2808 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2809 2810 return IXGBE_SUCCESS; 2811 } 2812 2813 /** 2814 * ixgbe_fc_enable_generic - Enable flow control 2815 * @hw: pointer to hardware structure 2816 * 2817 * Enable flow control according to the current settings. 2818 **/ 2819 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2820 { 2821 s32 ret_val = IXGBE_SUCCESS; 2822 u32 mflcn_reg, fccfg_reg; 2823 u32 reg; 2824 u32 fcrtl, fcrth; 2825 int i; 2826 2827 DEBUGFUNC("ixgbe_fc_enable_generic"); 2828 2829 /* Validate the water mark configuration */ 2830 if (!hw->fc.pause_time) { 2831 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2832 goto out; 2833 } 2834 2835 /* Low water mark of zero causes XOFF floods */ 2836 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2837 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2838 hw->fc.high_water[i]) { 2839 if (!hw->fc.low_water[i] || 2840 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2841 DEBUGOUT("Invalid water mark configuration\n"); 2842 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2843 goto out; 2844 } 2845 } 2846 } 2847 2848 /* Negotiate the fc mode to use */ 2849 hw->mac.ops.fc_autoneg(hw); 2850 2851 /* Disable any previous flow control settings */ 2852 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2853 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2854 2855 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2856 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2857 2858 /* 2859 * The possible values of fc.current_mode are: 2860 * 0: Flow control is completely disabled 2861 * 1: Rx flow control is enabled (we can receive pause frames, 2862 * but not send pause frames). 2863 * 2: Tx flow control is enabled (we can send pause frames but 2864 * we do not support receiving pause frames). 2865 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2866 * other: Invalid. 2867 */ 2868 switch (hw->fc.current_mode) { 2869 case ixgbe_fc_none: 2870 /* 2871 * Flow control is disabled by software override or autoneg. 2872 * The code below will actually disable it in the HW. 2873 */ 2874 break; 2875 case ixgbe_fc_rx_pause: 2876 /* 2877 * Rx Flow control is enabled and Tx Flow control is 2878 * disabled by software override. Since there really 2879 * isn't a way to advertise that we are capable of RX 2880 * Pause ONLY, we will advertise that we support both 2881 * symmetric and asymmetric Rx PAUSE. Later, we will 2882 * disable the adapter's ability to send PAUSE frames. 2883 */ 2884 mflcn_reg |= IXGBE_MFLCN_RFCE; 2885 break; 2886 case ixgbe_fc_tx_pause: 2887 /* 2888 * Tx Flow control is enabled, and Rx Flow control is 2889 * disabled by software override. 2890 */ 2891 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2892 break; 2893 case ixgbe_fc_full: 2894 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2895 mflcn_reg |= IXGBE_MFLCN_RFCE; 2896 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2897 break; 2898 default: 2899 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2900 "Flow control param set incorrectly\n"); 2901 ret_val = IXGBE_ERR_CONFIG; 2902 goto out; 2903 break; 2904 } 2905 2906 /* Set 802.3x based flow control settings. */ 2907 mflcn_reg |= IXGBE_MFLCN_DPF; 2908 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2909 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2910 2911 2912 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2913 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2914 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2915 hw->fc.high_water[i]) { 2916 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2917 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2918 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2919 } else { 2920 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2921 /* 2922 * In order to prevent Tx hangs when the internal Tx 2923 * switch is enabled we must set the high water mark 2924 * to the Rx packet buffer size - 24KB. This allows 2925 * the Tx switch to function even under heavy Rx 2926 * workloads. 2927 */ 2928 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2929 } 2930 2931 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2932 } 2933 2934 /* Configure pause time (2 TCs per register) */ 2935 reg = hw->fc.pause_time * 0x00010001; 2936 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2937 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2938 2939 /* Configure flow control refresh threshold value */ 2940 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2941 2942 out: 2943 return ret_val; 2944 } 2945 2946 /** 2947 * ixgbe_negotiate_fc - Negotiate flow control 2948 * @hw: pointer to hardware structure 2949 * @adv_reg: flow control advertised settings 2950 * @lp_reg: link partner's flow control settings 2951 * @adv_sym: symmetric pause bit in advertisement 2952 * @adv_asm: asymmetric pause bit in advertisement 2953 * @lp_sym: symmetric pause bit in link partner advertisement 2954 * @lp_asm: asymmetric pause bit in link partner advertisement 2955 * 2956 * Find the intersection between advertised settings and link partner's 2957 * advertised settings 2958 **/ 2959 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2960 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2961 { 2962 if ((!(adv_reg)) || (!(lp_reg))) { 2963 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2964 "Local or link partner's advertised flow control " 2965 "settings are NULL. Local: %x, link partner: %x\n", 2966 adv_reg, lp_reg); 2967 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2968 } 2969 2970 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2971 /* 2972 * Now we need to check if the user selected Rx ONLY 2973 * of pause frames. In this case, we had to advertise 2974 * FULL flow control because we could not advertise RX 2975 * ONLY. Hence, we must now check to see if we need to 2976 * turn OFF the TRANSMISSION of PAUSE frames. 2977 */ 2978 if (hw->fc.requested_mode == ixgbe_fc_full) { 2979 hw->fc.current_mode = ixgbe_fc_full; 2980 DEBUGOUT("Flow Control = FULL.\n"); 2981 } else { 2982 hw->fc.current_mode = ixgbe_fc_rx_pause; 2983 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2984 } 2985 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2986 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2987 hw->fc.current_mode = ixgbe_fc_tx_pause; 2988 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2989 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2990 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2991 hw->fc.current_mode = ixgbe_fc_rx_pause; 2992 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2993 } else { 2994 hw->fc.current_mode = ixgbe_fc_none; 2995 DEBUGOUT("Flow Control = NONE.\n"); 2996 } 2997 return IXGBE_SUCCESS; 2998 } 2999 3000 /** 3001 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 3002 * @hw: pointer to hardware structure 3003 * 3004 * Enable flow control according on 1 gig fiber. 3005 **/ 3006 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 3007 { 3008 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 3009 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3010 3011 /* 3012 * On multispeed fiber at 1g, bail out if 3013 * - link is up but AN did not complete, or if 3014 * - link is up and AN completed but timed out 3015 */ 3016 3017 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3018 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3019 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3020 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3021 goto out; 3022 } 3023 3024 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3025 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3026 3027 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3028 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3029 IXGBE_PCS1GANA_ASM_PAUSE, 3030 IXGBE_PCS1GANA_SYM_PAUSE, 3031 IXGBE_PCS1GANA_ASM_PAUSE); 3032 3033 out: 3034 return ret_val; 3035 } 3036 3037 /** 3038 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3039 * @hw: pointer to hardware structure 3040 * 3041 * Enable flow control according to IEEE clause 37. 3042 **/ 3043 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3044 { 3045 u32 links2, anlp1_reg, autoc_reg, links; 3046 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3047 3048 /* 3049 * On backplane, bail out if 3050 * - backplane autoneg was not completed, or if 3051 * - we are 82599 and link partner is not AN enabled 3052 */ 3053 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3054 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3055 DEBUGOUT("Auto-Negotiation did not complete\n"); 3056 goto out; 3057 } 3058 3059 if (hw->mac.type == ixgbe_mac_82599EB) { 3060 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3061 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3062 DEBUGOUT("Link partner is not AN enabled\n"); 3063 goto out; 3064 } 3065 } 3066 /* 3067 * Read the 10g AN autoc and LP ability registers and resolve 3068 * local flow control settings accordingly 3069 */ 3070 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3071 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3072 3073 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3074 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3075 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3076 3077 out: 3078 return ret_val; 3079 } 3080 3081 /** 3082 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3083 * @hw: pointer to hardware structure 3084 * 3085 * Enable flow control according to IEEE clause 37. 3086 **/ 3087 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3088 { 3089 u16 technology_ability_reg = 0; 3090 u16 lp_technology_ability_reg = 0; 3091 3092 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3093 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3094 &technology_ability_reg); 3095 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3096 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3097 &lp_technology_ability_reg); 3098 3099 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3100 (u32)lp_technology_ability_reg, 3101 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3102 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3103 } 3104 3105 /** 3106 * ixgbe_fc_autoneg - Configure flow control 3107 * @hw: pointer to hardware structure 3108 * 3109 * Compares our advertised flow control capabilities to those advertised by 3110 * our link partner, and determines the proper flow control mode to use. 3111 **/ 3112 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3113 { 3114 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3115 ixgbe_link_speed speed; 3116 bool link_up; 3117 3118 DEBUGFUNC("ixgbe_fc_autoneg"); 3119 3120 /* 3121 * AN should have completed when the cable was plugged in. 3122 * Look for reasons to bail out. Bail out if: 3123 * - FC autoneg is disabled, or if 3124 * - link is not up. 3125 */ 3126 if (hw->fc.disable_fc_autoneg) { 3127 /* TODO: This should be just an informative log */ 3128 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 3129 "Flow control autoneg is disabled"); 3130 goto out; 3131 } 3132 3133 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3134 if (!link_up) { 3135 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3136 goto out; 3137 } 3138 3139 switch (hw->phy.media_type) { 3140 /* Autoneg flow control on fiber adapters */ 3141 case ixgbe_media_type_fiber_fixed: 3142 case ixgbe_media_type_fiber_qsfp: 3143 case ixgbe_media_type_fiber: 3144 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3145 ret_val = ixgbe_fc_autoneg_fiber(hw); 3146 break; 3147 3148 /* Autoneg flow control on backplane adapters */ 3149 case ixgbe_media_type_backplane: 3150 ret_val = ixgbe_fc_autoneg_backplane(hw); 3151 break; 3152 3153 /* Autoneg flow control on copper adapters */ 3154 case ixgbe_media_type_copper: 3155 if (ixgbe_device_supports_autoneg_fc(hw)) 3156 ret_val = ixgbe_fc_autoneg_copper(hw); 3157 break; 3158 3159 default: 3160 break; 3161 } 3162 3163 out: 3164 if (ret_val == IXGBE_SUCCESS) { 3165 hw->fc.fc_was_autonegged = true; 3166 } else { 3167 hw->fc.fc_was_autonegged = false; 3168 hw->fc.current_mode = hw->fc.requested_mode; 3169 } 3170 } 3171 3172 /* 3173 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3174 * @hw: pointer to hardware structure 3175 * 3176 * System-wide timeout range is encoded in PCIe Device Control2 register. 3177 * 3178 * Add 10% to specified maximum and return the number of times to poll for 3179 * completion timeout, in units of 100 microsec. Never return less than 3180 * 800 = 80 millisec. 3181 */ 3182 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3183 { 3184 s16 devctl2; 3185 u32 pollcnt; 3186 3187 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3188 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3189 3190 switch (devctl2) { 3191 case IXGBE_PCIDEVCTRL2_65_130ms: 3192 pollcnt = 1300; /* 130 millisec */ 3193 break; 3194 case IXGBE_PCIDEVCTRL2_260_520ms: 3195 pollcnt = 5200; /* 520 millisec */ 3196 break; 3197 case IXGBE_PCIDEVCTRL2_1_2s: 3198 pollcnt = 20000; /* 2 sec */ 3199 break; 3200 case IXGBE_PCIDEVCTRL2_4_8s: 3201 pollcnt = 80000; /* 8 sec */ 3202 break; 3203 case IXGBE_PCIDEVCTRL2_17_34s: 3204 pollcnt = 34000; /* 34 sec */ 3205 break; 3206 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3207 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3208 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3209 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3210 default: 3211 pollcnt = 800; /* 80 millisec minimum */ 3212 break; 3213 } 3214 3215 /* add 10% to spec maximum */ 3216 return (pollcnt * 11) / 10; 3217 } 3218 3219 /** 3220 * ixgbe_disable_pcie_primary - Disable PCI-express primary access 3221 * @hw: pointer to hardware structure 3222 * 3223 * Disables PCI-Express primary access and verifies there are no pending 3224 * requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable 3225 * bit hasn't caused the primary requests to be disabled, else IXGBE_SUCCESS 3226 * is returned signifying primary requests disabled. 3227 **/ 3228 s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) 3229 { 3230 s32 status = IXGBE_SUCCESS; 3231 u32 i, poll; 3232 u16 value; 3233 3234 DEBUGFUNC("ixgbe_disable_pcie_primary"); 3235 3236 /* Always set this bit to ensure any future transactions are blocked */ 3237 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3238 3239 /* Exit if primary requests are blocked */ 3240 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3241 IXGBE_REMOVED(hw->hw_addr)) 3242 goto out; 3243 3244 /* Poll for primary request bit to clear */ 3245 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { 3246 usec_delay(100); 3247 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3248 goto out; 3249 } 3250 3251 /* 3252 * Two consecutive resets are required via CTRL.RST per datasheet 3253 * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine 3254 * of this need. The first reset prevents new primary requests from 3255 * being issued by our device. We then must wait 1usec or more for any 3256 * remaining completions from the PCIe bus to trickle in, and then reset 3257 * again to clear out any effects they may have had on our device. 3258 */ 3259 DEBUGOUT("GIO Primary Disable bit didn't clear - requesting resets\n"); 3260 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3261 3262 if (hw->mac.type >= ixgbe_mac_X550) 3263 goto out; 3264 3265 /* 3266 * Before proceeding, make sure that the PCIe block does not have 3267 * transactions pending. 3268 */ 3269 poll = ixgbe_pcie_timeout_poll(hw); 3270 for (i = 0; i < poll; i++) { 3271 usec_delay(100); 3272 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3273 if (IXGBE_REMOVED(hw->hw_addr)) 3274 goto out; 3275 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3276 goto out; 3277 } 3278 3279 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3280 "PCIe transaction pending bit also did not clear.\n"); 3281 status = IXGBE_ERR_PRIMARY_REQUESTS_PENDING; 3282 3283 out: 3284 return status; 3285 } 3286 3287 /** 3288 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3289 * @hw: pointer to hardware structure 3290 * @mask: Mask to specify which semaphore to acquire 3291 * 3292 * Acquires the SWFW semaphore through the GSSR register for the specified 3293 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3294 **/ 3295 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3296 { 3297 u32 gssr = 0; 3298 u32 swmask = mask; 3299 u32 fwmask = mask << 5; 3300 u32 timeout = 200; 3301 u32 i; 3302 3303 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3304 3305 for (i = 0; i < timeout; i++) { 3306 /* 3307 * SW NVM semaphore bit is used for access to all 3308 * SW_FW_SYNC bits (not just NVM) 3309 */ 3310 if (ixgbe_get_eeprom_semaphore(hw)) 3311 return IXGBE_ERR_SWFW_SYNC; 3312 3313 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3314 if (!(gssr & (fwmask | swmask))) { 3315 gssr |= swmask; 3316 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3317 ixgbe_release_eeprom_semaphore(hw); 3318 return IXGBE_SUCCESS; 3319 } else { 3320 /* Resource is currently in use by FW or SW */ 3321 ixgbe_release_eeprom_semaphore(hw); 3322 msec_delay(5); 3323 } 3324 } 3325 3326 /* If time expired clear the bits holding the lock and retry */ 3327 if (gssr & (fwmask | swmask)) 3328 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3329 3330 msec_delay(5); 3331 return IXGBE_ERR_SWFW_SYNC; 3332 } 3333 3334 /** 3335 * ixgbe_release_swfw_sync - Release SWFW semaphore 3336 * @hw: pointer to hardware structure 3337 * @mask: Mask to specify which semaphore to release 3338 * 3339 * Releases the SWFW semaphore through the GSSR register for the specified 3340 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3341 **/ 3342 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3343 { 3344 u32 gssr; 3345 u32 swmask = mask; 3346 3347 DEBUGFUNC("ixgbe_release_swfw_sync"); 3348 3349 ixgbe_get_eeprom_semaphore(hw); 3350 3351 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3352 gssr &= ~swmask; 3353 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3354 3355 ixgbe_release_eeprom_semaphore(hw); 3356 } 3357 3358 /** 3359 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3360 * @hw: pointer to hardware structure 3361 * 3362 * Stops the receive data path and waits for the HW to internally empty 3363 * the Rx security block 3364 **/ 3365 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3366 { 3367 #define IXGBE_MAX_SECRX_POLL 4000 3368 3369 int i; 3370 int secrxreg; 3371 3372 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3373 3374 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3375 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3376 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3377 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3378 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3379 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3380 break; 3381 else 3382 /* Use interrupt-safe sleep just in case */ 3383 usec_delay(10); 3384 } 3385 3386 /* For informational purposes only */ 3387 if (i >= IXGBE_MAX_SECRX_POLL) 3388 DEBUGOUT("Rx unit being enabled before security " 3389 "path fully disabled. Continuing with init.\n"); 3390 3391 return IXGBE_SUCCESS; 3392 } 3393 3394 /** 3395 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3396 * @hw: pointer to hardware structure 3397 * @locked: bool to indicate whether the SW/FW lock was taken 3398 * @reg_val: Value we read from AUTOC 3399 * 3400 * The default case requires no protection so just to the register read. 3401 */ 3402 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3403 { 3404 *locked = false; 3405 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3406 return IXGBE_SUCCESS; 3407 } 3408 3409 /** 3410 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3411 * @hw: pointer to hardware structure 3412 * @reg_val: value to write to AUTOC 3413 * @locked: bool to indicate whether the SW/FW lock was already taken by 3414 * previous read. 3415 * 3416 * The default case requires no protection so just to the register write. 3417 */ 3418 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3419 { 3420 UNREFERENCED_1PARAMETER(locked); 3421 3422 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3423 return IXGBE_SUCCESS; 3424 } 3425 3426 /** 3427 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3428 * @hw: pointer to hardware structure 3429 * 3430 * Enables the receive data path. 3431 **/ 3432 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3433 { 3434 u32 secrxreg; 3435 3436 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3437 3438 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3439 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3440 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3441 IXGBE_WRITE_FLUSH(hw); 3442 3443 return IXGBE_SUCCESS; 3444 } 3445 3446 /** 3447 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3448 * @hw: pointer to hardware structure 3449 * @regval: register value to write to RXCTRL 3450 * 3451 * Enables the Rx DMA unit 3452 **/ 3453 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3454 { 3455 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3456 3457 if (regval & IXGBE_RXCTRL_RXEN) 3458 ixgbe_enable_rx(hw); 3459 else 3460 ixgbe_disable_rx(hw); 3461 3462 return IXGBE_SUCCESS; 3463 } 3464 3465 /** 3466 * ixgbe_blink_led_start_generic - Blink LED based on index. 3467 * @hw: pointer to hardware structure 3468 * @index: led number to blink 3469 **/ 3470 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3471 { 3472 ixgbe_link_speed speed = 0; 3473 bool link_up = 0; 3474 u32 autoc_reg = 0; 3475 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3476 s32 ret_val = IXGBE_SUCCESS; 3477 bool locked = false; 3478 3479 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3480 3481 if (index > 3) 3482 return IXGBE_ERR_PARAM; 3483 3484 /* 3485 * Link must be up to auto-blink the LEDs; 3486 * Force it if link is down. 3487 */ 3488 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3489 3490 if (!link_up) { 3491 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3492 if (ret_val != IXGBE_SUCCESS) 3493 goto out; 3494 3495 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3496 autoc_reg |= IXGBE_AUTOC_FLU; 3497 3498 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3499 if (ret_val != IXGBE_SUCCESS) 3500 goto out; 3501 3502 IXGBE_WRITE_FLUSH(hw); 3503 msec_delay(10); 3504 } 3505 3506 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3507 led_reg |= IXGBE_LED_BLINK(index); 3508 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3509 IXGBE_WRITE_FLUSH(hw); 3510 3511 out: 3512 return ret_val; 3513 } 3514 3515 /** 3516 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3517 * @hw: pointer to hardware structure 3518 * @index: led number to stop blinking 3519 **/ 3520 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3521 { 3522 u32 autoc_reg = 0; 3523 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3524 s32 ret_val = IXGBE_SUCCESS; 3525 bool locked = false; 3526 3527 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3528 3529 if (index > 3) 3530 return IXGBE_ERR_PARAM; 3531 3532 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3533 if (ret_val != IXGBE_SUCCESS) 3534 goto out; 3535 3536 autoc_reg &= ~IXGBE_AUTOC_FLU; 3537 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3538 3539 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3540 if (ret_val != IXGBE_SUCCESS) 3541 goto out; 3542 3543 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3544 led_reg &= ~IXGBE_LED_BLINK(index); 3545 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3546 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3547 IXGBE_WRITE_FLUSH(hw); 3548 3549 out: 3550 return ret_val; 3551 } 3552 3553 /** 3554 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3555 * @hw: pointer to hardware structure 3556 * @san_mac_offset: SAN MAC address offset 3557 * 3558 * This function will read the EEPROM location for the SAN MAC address 3559 * pointer, and returns the value at that location. This is used in both 3560 * get and set mac_addr routines. 3561 **/ 3562 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3563 u16 *san_mac_offset) 3564 { 3565 s32 ret_val; 3566 3567 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3568 3569 /* 3570 * First read the EEPROM pointer to see if the MAC addresses are 3571 * available. 3572 */ 3573 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3574 san_mac_offset); 3575 if (ret_val) { 3576 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3577 "eeprom at offset %d failed", 3578 IXGBE_SAN_MAC_ADDR_PTR); 3579 } 3580 3581 return ret_val; 3582 } 3583 3584 /** 3585 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3586 * @hw: pointer to hardware structure 3587 * @san_mac_addr: SAN MAC address 3588 * 3589 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3590 * per-port, so set_lan_id() must be called before reading the addresses. 3591 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3592 * upon for non-SFP connections, so we must call it here. 3593 **/ 3594 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3595 { 3596 u16 san_mac_data, san_mac_offset; 3597 u8 i; 3598 s32 ret_val; 3599 3600 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3601 3602 /* 3603 * First read the EEPROM pointer to see if the MAC addresses are 3604 * available. If they're not, no point in calling set_lan_id() here. 3605 */ 3606 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3607 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3608 goto san_mac_addr_out; 3609 3610 /* make sure we know which port we need to program */ 3611 hw->mac.ops.set_lan_id(hw); 3612 /* apply the port offset to the address offset */ 3613 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3614 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3615 for (i = 0; i < 3; i++) { 3616 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3617 &san_mac_data); 3618 if (ret_val) { 3619 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3620 "eeprom read at offset %d failed", 3621 san_mac_offset); 3622 goto san_mac_addr_out; 3623 } 3624 san_mac_addr[i * 2] = (u8)(san_mac_data); 3625 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3626 san_mac_offset++; 3627 } 3628 return IXGBE_SUCCESS; 3629 3630 san_mac_addr_out: 3631 /* 3632 * No addresses available in this EEPROM. It's not an 3633 * error though, so just wipe the local address and return. 3634 */ 3635 for (i = 0; i < 6; i++) 3636 san_mac_addr[i] = 0xFF; 3637 return IXGBE_SUCCESS; 3638 } 3639 3640 /** 3641 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3642 * @hw: pointer to hardware structure 3643 * @san_mac_addr: SAN MAC address 3644 * 3645 * Write a SAN MAC address to the EEPROM. 3646 **/ 3647 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3648 { 3649 s32 ret_val; 3650 u16 san_mac_data, san_mac_offset; 3651 u8 i; 3652 3653 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3654 3655 /* Look for SAN mac address pointer. If not defined, return */ 3656 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3657 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3658 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3659 3660 /* Make sure we know which port we need to write */ 3661 hw->mac.ops.set_lan_id(hw); 3662 /* Apply the port offset to the address offset */ 3663 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3664 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3665 3666 for (i = 0; i < 3; i++) { 3667 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3668 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3669 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3670 san_mac_offset++; 3671 } 3672 3673 return IXGBE_SUCCESS; 3674 } 3675 3676 /** 3677 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3678 * @hw: pointer to hardware structure 3679 * 3680 * Read PCIe configuration space, and get the MSI-X vector count from 3681 * the capabilities table. 3682 **/ 3683 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3684 { 3685 u16 msix_count = 1; 3686 u16 max_msix_count; 3687 u16 pcie_offset; 3688 3689 switch (hw->mac.type) { 3690 case ixgbe_mac_82598EB: 3691 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3692 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3693 break; 3694 case ixgbe_mac_82599EB: 3695 case ixgbe_mac_X540: 3696 case ixgbe_mac_X550: 3697 case ixgbe_mac_X550EM_x: 3698 case ixgbe_mac_X550EM_a: 3699 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3700 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3701 break; 3702 case ixgbe_mac_E610: 3703 pcie_offset = IXGBE_PCIE_MSIX_E610_CAPS; 3704 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3705 break; 3706 default: 3707 return msix_count; 3708 } 3709 3710 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3711 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3712 if (IXGBE_REMOVED(hw->hw_addr)) 3713 msix_count = 0; 3714 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3715 3716 /* MSI-X count is zero-based in HW */ 3717 msix_count++; 3718 3719 if (msix_count > max_msix_count) 3720 msix_count = max_msix_count; 3721 3722 return msix_count; 3723 } 3724 3725 /** 3726 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3727 * @hw: pointer to hardware structure 3728 * @addr: Address to put into receive address register 3729 * @vmdq: VMDq pool to assign 3730 * 3731 * Puts an ethernet address into a receive address register, or 3732 * finds the rar that it is already in; adds to the pool list 3733 **/ 3734 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3735 { 3736 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3737 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3738 u32 rar; 3739 u32 rar_low, rar_high; 3740 u32 addr_low, addr_high; 3741 3742 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3743 3744 /* swap bytes for HW little endian */ 3745 addr_low = addr[0] | (addr[1] << 8) 3746 | (addr[2] << 16) 3747 | (addr[3] << 24); 3748 addr_high = addr[4] | (addr[5] << 8); 3749 3750 /* 3751 * Either find the mac_id in rar or find the first empty space. 3752 * rar_highwater points to just after the highest currently used 3753 * rar in order to shorten the search. It grows when we add a new 3754 * rar to the top. 3755 */ 3756 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3757 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3758 3759 if (((IXGBE_RAH_AV & rar_high) == 0) 3760 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3761 first_empty_rar = rar; 3762 } else if ((rar_high & 0xFFFF) == addr_high) { 3763 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3764 if (rar_low == addr_low) 3765 break; /* found it already in the rars */ 3766 } 3767 } 3768 3769 if (rar < hw->mac.rar_highwater) { 3770 /* already there so just add to the pool bits */ 3771 ixgbe_set_vmdq(hw, rar, vmdq); 3772 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3773 /* stick it into first empty RAR slot we found */ 3774 rar = first_empty_rar; 3775 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3776 } else if (rar == hw->mac.rar_highwater) { 3777 /* add it to the top of the list and inc the highwater mark */ 3778 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3779 hw->mac.rar_highwater++; 3780 } else if (rar >= hw->mac.num_rar_entries) { 3781 return IXGBE_ERR_INVALID_MAC_ADDR; 3782 } 3783 3784 /* 3785 * If we found rar[0], make sure the default pool bit (we use pool 0) 3786 * remains cleared to be sure default pool packets will get delivered 3787 */ 3788 if (rar == 0) 3789 ixgbe_clear_vmdq(hw, rar, 0); 3790 3791 return rar; 3792 } 3793 3794 /** 3795 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3796 * @hw: pointer to hardware struct 3797 * @rar: receive address register index to disassociate 3798 * @vmdq: VMDq pool index to remove from the rar 3799 **/ 3800 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3801 { 3802 u32 mpsar_lo, mpsar_hi; 3803 u32 rar_entries = hw->mac.num_rar_entries; 3804 3805 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3806 3807 /* Make sure we are using a valid rar index range */ 3808 if (rar >= rar_entries) { 3809 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3810 "RAR index %d is out of range.\n", rar); 3811 return IXGBE_ERR_INVALID_ARGUMENT; 3812 } 3813 3814 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3815 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3816 3817 if (IXGBE_REMOVED(hw->hw_addr)) 3818 goto done; 3819 3820 if (!mpsar_lo && !mpsar_hi) 3821 goto done; 3822 3823 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3824 if (mpsar_lo) { 3825 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3826 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3827 } 3828 if (mpsar_hi) { 3829 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3830 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3831 } 3832 } else if (vmdq < 32) { 3833 mpsar_lo &= ~(1 << vmdq); 3834 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3835 } else { 3836 mpsar_hi &= ~(1 << (vmdq - 32)); 3837 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3838 } 3839 3840 /* was that the last pool using this rar? */ 3841 if (mpsar_lo == 0 && mpsar_hi == 0 && 3842 rar != 0 && rar != hw->mac.san_mac_rar_index) 3843 hw->mac.ops.clear_rar(hw, rar); 3844 done: 3845 return IXGBE_SUCCESS; 3846 } 3847 3848 /** 3849 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3850 * @hw: pointer to hardware struct 3851 * @rar: receive address register index to associate with a VMDq index 3852 * @vmdq: VMDq pool index 3853 **/ 3854 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3855 { 3856 u32 mpsar; 3857 u32 rar_entries = hw->mac.num_rar_entries; 3858 3859 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3860 3861 /* Make sure we are using a valid rar index range */ 3862 if (rar >= rar_entries) { 3863 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3864 "RAR index %d is out of range.\n", rar); 3865 return IXGBE_ERR_INVALID_ARGUMENT; 3866 } 3867 3868 if (vmdq < 32) { 3869 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3870 mpsar |= 1 << vmdq; 3871 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3872 } else { 3873 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3874 mpsar |= 1 << (vmdq - 32); 3875 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3876 } 3877 return IXGBE_SUCCESS; 3878 } 3879 3880 /** 3881 * ixgbe_set_vmdq_san_mac_generic - Associate default VMDq pool index with 3882 * a rx address 3883 * @hw: pointer to hardware struct 3884 * @vmdq: VMDq pool index 3885 * 3886 * This function should only be involved in the IOV mode. 3887 * In IOV mode, Default pool is next pool after the number of 3888 * VFs advertized and not 0. 3889 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3890 **/ 3891 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3892 { 3893 u32 rar = hw->mac.san_mac_rar_index; 3894 3895 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3896 3897 if (vmdq < 32) { 3898 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3899 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3900 } else { 3901 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3902 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3903 } 3904 3905 return IXGBE_SUCCESS; 3906 } 3907 3908 /** 3909 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3910 * @hw: pointer to hardware structure 3911 **/ 3912 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3913 { 3914 int i; 3915 3916 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3917 DEBUGOUT(" Clearing UTA\n"); 3918 3919 for (i = 0; i < 128; i++) 3920 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3921 3922 return IXGBE_SUCCESS; 3923 } 3924 3925 /** 3926 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3927 * @hw: pointer to hardware structure 3928 * @vlan: VLAN id to write to VLAN filter 3929 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 3930 * vlanid not found 3931 * 3932 * 3933 * return the VLVF index where this VLAN id should be placed 3934 * 3935 **/ 3936 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3937 { 3938 s32 regindex, first_empty_slot; 3939 u32 bits; 3940 3941 /* short cut the special case */ 3942 if (vlan == 0) 3943 return 0; 3944 3945 /* if vlvf_bypass is set we don't want to use an empty slot, we 3946 * will simply bypass the VLVF if there are no entries present in the 3947 * VLVF that contain our VLAN 3948 */ 3949 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3950 3951 /* add VLAN enable bit for comparison */ 3952 vlan |= IXGBE_VLVF_VIEN; 3953 3954 /* Search for the vlan id in the VLVF entries. Save off the first empty 3955 * slot found along the way. 3956 * 3957 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3958 */ 3959 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3960 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3961 if (bits == vlan) 3962 return regindex; 3963 if (!first_empty_slot && !bits) 3964 first_empty_slot = regindex; 3965 } 3966 3967 /* If we are here then we didn't find the VLAN. Return first empty 3968 * slot we found during our search, else error. 3969 */ 3970 if (!first_empty_slot) 3971 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3972 3973 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3974 } 3975 3976 /** 3977 * ixgbe_set_vfta_generic - Set VLAN filter table 3978 * @hw: pointer to hardware structure 3979 * @vlan: VLAN id to write to VLAN filter 3980 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3981 * @vlan_on: boolean flag to turn on/off VLAN 3982 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3983 * 3984 * Turn on/off specified VLAN in the VLAN filter table. 3985 **/ 3986 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3987 bool vlan_on, bool vlvf_bypass) 3988 { 3989 u32 regidx, vfta_delta, vfta; 3990 s32 ret_val; 3991 3992 DEBUGFUNC("ixgbe_set_vfta_generic"); 3993 3994 if (vlan > 4095 || vind > 63) 3995 return IXGBE_ERR_PARAM; 3996 3997 /* 3998 * this is a 2 part operation - first the VFTA, then the 3999 * VLVF and VLVFB if VT Mode is set 4000 * We don't write the VFTA until we know the VLVF part succeeded. 4001 */ 4002 4003 /* Part 1 4004 * The VFTA is a bitstring made up of 128 32-bit registers 4005 * that enable the particular VLAN id, much like the MTA: 4006 * bits[11-5]: which register 4007 * bits[4-0]: which bit in the register 4008 */ 4009 regidx = vlan / 32; 4010 vfta_delta = 1 << (vlan % 32); 4011 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 4012 4013 /* 4014 * vfta_delta represents the difference between the current value 4015 * of vfta and the value we want in the register. Since the diff 4016 * is an XOR mask we can just update the vfta using an XOR 4017 */ 4018 vfta_delta &= vlan_on ? ~vfta : vfta; 4019 vfta ^= vfta_delta; 4020 4021 /* Part 2 4022 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4023 */ 4024 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4025 vfta, vlvf_bypass); 4026 if (ret_val != IXGBE_SUCCESS) { 4027 if (vlvf_bypass) 4028 goto vfta_update; 4029 return ret_val; 4030 } 4031 4032 vfta_update: 4033 /* Update VFTA now that we are ready for traffic */ 4034 if (vfta_delta) 4035 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4036 4037 return IXGBE_SUCCESS; 4038 } 4039 4040 /** 4041 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4042 * @hw: pointer to hardware structure 4043 * @vlan: VLAN id to write to VLAN filter 4044 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4045 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4046 * @vfta_delta: pointer to the difference between the current value of VFTA 4047 * and the desired value 4048 * @vfta: the desired value of the VFTA 4049 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4050 * 4051 * Turn on/off specified bit in VLVF table. 4052 **/ 4053 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4054 bool vlan_on, u32 *vfta_delta, u32 vfta, 4055 bool vlvf_bypass) 4056 { 4057 u32 bits; 4058 s32 vlvf_index; 4059 4060 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4061 4062 if (vlan > 4095 || vind > 63) 4063 return IXGBE_ERR_PARAM; 4064 4065 /* If VT Mode is set 4066 * Either vlan_on 4067 * make sure the vlan is in VLVF 4068 * set the vind bit in the matching VLVFB 4069 * Or !vlan_on 4070 * clear the pool bit and possibly the vind 4071 */ 4072 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4073 return IXGBE_SUCCESS; 4074 4075 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4076 if (vlvf_index < 0) 4077 return vlvf_index; 4078 4079 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4080 4081 /* set the pool bit */ 4082 bits |= 1 << (vind % 32); 4083 if (vlan_on) 4084 goto vlvf_update; 4085 4086 /* clear the pool bit */ 4087 bits ^= 1 << (vind % 32); 4088 4089 if (!bits && 4090 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4091 /* Clear VFTA first, then disable VLVF. Otherwise 4092 * we run the risk of stray packets leaking into 4093 * the PF via the default pool 4094 */ 4095 if (*vfta_delta) 4096 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4097 4098 /* disable VLVF and clear remaining bit from pool */ 4099 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4100 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4101 4102 return IXGBE_SUCCESS; 4103 } 4104 4105 /* If there are still bits set in the VLVFB registers 4106 * for the VLAN ID indicated we need to see if the 4107 * caller is requesting that we clear the VFTA entry bit. 4108 * If the caller has requested that we clear the VFTA 4109 * entry bit but there are still pools/VFs using this VLAN 4110 * ID entry then ignore the request. We're not worried 4111 * about the case where we're turning the VFTA VLAN ID 4112 * entry bit on, only when requested to turn it off as 4113 * there may be multiple pools and/or VFs using the 4114 * VLAN ID entry. In that case we cannot clear the 4115 * VFTA bit until all pools/VFs using that VLAN ID have also 4116 * been cleared. This will be indicated by "bits" being 4117 * zero. 4118 */ 4119 *vfta_delta = 0; 4120 4121 vlvf_update: 4122 /* record pool change and enable VLAN ID if not already enabled */ 4123 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4124 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4125 4126 return IXGBE_SUCCESS; 4127 } 4128 4129 /** 4130 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4131 * @hw: pointer to hardware structure 4132 * 4133 * Clears the VLAN filter table, and the VMDq index associated with the filter 4134 **/ 4135 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4136 { 4137 u32 offset; 4138 4139 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4140 4141 for (offset = 0; offset < hw->mac.vft_size; offset++) 4142 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4143 4144 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4145 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4146 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4147 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 4148 } 4149 4150 return IXGBE_SUCCESS; 4151 } 4152 4153 /** 4154 * ixgbe_toggle_txdctl_generic - Toggle VF's queues 4155 * @hw: pointer to hardware structure 4156 * @vf_number: VF index 4157 * 4158 * Enable and disable each queue in VF. 4159 */ 4160 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number) 4161 { 4162 u8 queue_count, i; 4163 u32 offset, reg; 4164 4165 if (vf_number > 63) 4166 return IXGBE_ERR_PARAM; 4167 4168 /* 4169 * Determine number of queues by checking 4170 * number of virtual functions 4171 */ 4172 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4173 switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) { 4174 case IXGBE_GCR_EXT_VT_MODE_64: 4175 queue_count = 2; 4176 break; 4177 case IXGBE_GCR_EXT_VT_MODE_32: 4178 queue_count = 4; 4179 break; 4180 case IXGBE_GCR_EXT_VT_MODE_16: 4181 queue_count = 8; 4182 break; 4183 default: 4184 return IXGBE_ERR_CONFIG; 4185 } 4186 4187 /* Toggle queues */ 4188 for (i = 0; i < queue_count; ++i) { 4189 /* Calculate offset of current queue */ 4190 offset = queue_count * vf_number + i; 4191 4192 /* Enable queue */ 4193 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4194 reg |= IXGBE_TXDCTL_ENABLE; 4195 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4196 IXGBE_WRITE_FLUSH(hw); 4197 4198 /* Disable queue */ 4199 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4200 reg &= ~IXGBE_TXDCTL_ENABLE; 4201 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4202 IXGBE_WRITE_FLUSH(hw); 4203 } 4204 4205 return IXGBE_SUCCESS; 4206 } 4207 4208 /** 4209 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4210 * @hw: pointer to hardware structure 4211 * 4212 * Contains the logic to identify if we need to verify link for the 4213 * crosstalk fix 4214 **/ 4215 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4216 { 4217 4218 /* Does FW say we need the fix */ 4219 if (!hw->need_crosstalk_fix) 4220 return false; 4221 4222 /* Only consider SFP+ PHYs i.e. media type fiber */ 4223 switch (hw->mac.ops.get_media_type(hw)) { 4224 case ixgbe_media_type_fiber: 4225 case ixgbe_media_type_fiber_qsfp: 4226 break; 4227 default: 4228 return false; 4229 } 4230 4231 return true; 4232 } 4233 4234 /** 4235 * ixgbe_check_mac_link_generic - Determine link and speed status 4236 * @hw: pointer to hardware structure 4237 * @speed: pointer to link speed 4238 * @link_up: true when link is up 4239 * @link_up_wait_to_complete: bool used to wait for link up or not 4240 * 4241 * Reads the links register to determine if link is up and the current speed 4242 **/ 4243 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4244 bool *link_up, bool link_up_wait_to_complete) 4245 { 4246 u32 links_reg, links_orig; 4247 u32 i; 4248 4249 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4250 4251 /* If Crosstalk fix enabled do the sanity check of making sure 4252 * the SFP+ cage is full. 4253 */ 4254 if (ixgbe_need_crosstalk_fix(hw)) { 4255 u32 sfp_cage_full; 4256 4257 switch (hw->mac.type) { 4258 case ixgbe_mac_82599EB: 4259 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4260 IXGBE_ESDP_SDP2; 4261 break; 4262 case ixgbe_mac_X550EM_x: 4263 case ixgbe_mac_X550EM_a: 4264 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4265 IXGBE_ESDP_SDP0; 4266 break; 4267 default: 4268 /* sanity check - No SFP+ devices here */ 4269 sfp_cage_full = false; 4270 break; 4271 } 4272 4273 if (!sfp_cage_full) { 4274 *link_up = false; 4275 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4276 return IXGBE_SUCCESS; 4277 } 4278 } 4279 4280 /* clear the old state */ 4281 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4282 4283 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4284 4285 if (links_orig != links_reg) { 4286 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4287 links_orig, links_reg); 4288 } 4289 4290 if (link_up_wait_to_complete) { 4291 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4292 if (links_reg & IXGBE_LINKS_UP) { 4293 *link_up = true; 4294 break; 4295 } else { 4296 *link_up = false; 4297 } 4298 msec_delay(100); 4299 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4300 } 4301 } else { 4302 if (links_reg & IXGBE_LINKS_UP) { 4303 if (ixgbe_need_crosstalk_fix(hw)) { 4304 /* Check the link state again after a delay 4305 * to filter out spurious link up 4306 * notifications. 4307 */ 4308 msec_delay(5); 4309 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4310 if (!(links_reg & IXGBE_LINKS_UP)) { 4311 *link_up = false; 4312 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4313 return IXGBE_SUCCESS; 4314 } 4315 4316 } 4317 *link_up = true; 4318 } else { 4319 *link_up = false; 4320 } 4321 } 4322 4323 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4324 case IXGBE_LINKS_SPEED_10G_82599: 4325 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4326 if (hw->mac.type >= ixgbe_mac_X550) { 4327 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4328 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4329 } 4330 break; 4331 case IXGBE_LINKS_SPEED_1G_82599: 4332 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4333 break; 4334 case IXGBE_LINKS_SPEED_100_82599: 4335 *speed = IXGBE_LINK_SPEED_100_FULL; 4336 if (hw->mac.type == ixgbe_mac_X550 || 4337 hw->mac.type == ixgbe_mac_E610) { 4338 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4339 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4340 } 4341 break; 4342 case IXGBE_LINKS_SPEED_10_X550EM_A: 4343 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4344 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4345 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4346 *speed = IXGBE_LINK_SPEED_10_FULL; 4347 break; 4348 default: 4349 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4350 } 4351 4352 return IXGBE_SUCCESS; 4353 } 4354 4355 /** 4356 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4357 * the EEPROM 4358 * @hw: pointer to hardware structure 4359 * @wwnn_prefix: the alternative WWNN prefix 4360 * @wwpn_prefix: the alternative WWPN prefix 4361 * 4362 * This function will read the EEPROM from the alternative SAN MAC address 4363 * block to check the support for the alternative WWNN/WWPN prefix support. 4364 **/ 4365 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4366 u16 *wwpn_prefix) 4367 { 4368 u16 offset, caps; 4369 u16 alt_san_mac_blk_offset; 4370 4371 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4372 4373 /* clear output first */ 4374 *wwnn_prefix = 0xFFFF; 4375 *wwpn_prefix = 0xFFFF; 4376 4377 /* check if alternative SAN MAC is supported */ 4378 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4379 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4380 goto wwn_prefix_err; 4381 4382 if ((alt_san_mac_blk_offset == 0) || 4383 (alt_san_mac_blk_offset == 0xFFFF)) 4384 goto wwn_prefix_out; 4385 4386 /* check capability in alternative san mac address block */ 4387 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4388 if (hw->eeprom.ops.read(hw, offset, &caps)) 4389 goto wwn_prefix_err; 4390 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4391 goto wwn_prefix_out; 4392 4393 /* get the corresponding prefix for WWNN/WWPN */ 4394 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4395 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4396 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4397 "eeprom read at offset %d failed", offset); 4398 } 4399 4400 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4401 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4402 goto wwn_prefix_err; 4403 4404 wwn_prefix_out: 4405 return IXGBE_SUCCESS; 4406 4407 wwn_prefix_err: 4408 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4409 "eeprom read at offset %d failed", offset); 4410 return IXGBE_SUCCESS; 4411 } 4412 4413 /** 4414 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4415 * @hw: pointer to hardware structure 4416 * @bs: the fcoe boot status 4417 * 4418 * This function will read the FCOE boot status from the iSCSI FCOE block 4419 **/ 4420 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4421 { 4422 u16 offset, caps, flags; 4423 s32 status; 4424 4425 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4426 4427 /* clear output first */ 4428 *bs = ixgbe_fcoe_bootstatus_unavailable; 4429 4430 /* check if FCOE IBA block is present */ 4431 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4432 status = hw->eeprom.ops.read(hw, offset, &caps); 4433 if (status != IXGBE_SUCCESS) 4434 goto out; 4435 4436 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4437 goto out; 4438 4439 /* check if iSCSI FCOE block is populated */ 4440 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4441 if (status != IXGBE_SUCCESS) 4442 goto out; 4443 4444 if ((offset == 0) || (offset == 0xFFFF)) 4445 goto out; 4446 4447 /* read fcoe flags in iSCSI FCOE block */ 4448 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4449 status = hw->eeprom.ops.read(hw, offset, &flags); 4450 if (status != IXGBE_SUCCESS) 4451 goto out; 4452 4453 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4454 *bs = ixgbe_fcoe_bootstatus_enabled; 4455 else 4456 *bs = ixgbe_fcoe_bootstatus_disabled; 4457 4458 out: 4459 return status; 4460 } 4461 4462 /** 4463 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4464 * @hw: pointer to hardware structure 4465 * @enable: enable or disable switch for MAC anti-spoofing 4466 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4467 * 4468 **/ 4469 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4470 { 4471 int vf_target_reg = vf >> 3; 4472 int vf_target_shift = vf % 8; 4473 u32 pfvfspoof; 4474 4475 if (hw->mac.type == ixgbe_mac_82598EB) 4476 return; 4477 4478 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4479 if (enable) 4480 pfvfspoof |= (1 << vf_target_shift); 4481 else 4482 pfvfspoof &= ~(1 << vf_target_shift); 4483 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4484 } 4485 4486 /** 4487 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4488 * @hw: pointer to hardware structure 4489 * @enable: enable or disable switch for VLAN anti-spoofing 4490 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4491 * 4492 **/ 4493 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4494 { 4495 int vf_target_reg = vf >> 3; 4496 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4497 u32 pfvfspoof; 4498 4499 if (hw->mac.type == ixgbe_mac_82598EB) 4500 return; 4501 4502 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4503 if (enable) 4504 pfvfspoof |= (1 << vf_target_shift); 4505 else 4506 pfvfspoof &= ~(1 << vf_target_shift); 4507 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4508 } 4509 4510 /** 4511 * ixgbe_get_device_caps_generic - Get additional device capabilities 4512 * @hw: pointer to hardware structure 4513 * @device_caps: the EEPROM word with the extra device capabilities 4514 * 4515 * This function will read the EEPROM location for the device capabilities, 4516 * and return the word through device_caps. 4517 **/ 4518 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4519 { 4520 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4521 4522 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4523 4524 return IXGBE_SUCCESS; 4525 } 4526 4527 /** 4528 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4529 * @hw: pointer to hardware structure 4530 * 4531 **/ 4532 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4533 { 4534 u32 regval; 4535 u32 i; 4536 4537 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4538 4539 /* Enable relaxed ordering */ 4540 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4541 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4542 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4543 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4544 } 4545 4546 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4547 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4548 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4549 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4550 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4551 } 4552 4553 } 4554 4555 /** 4556 * ixgbe_calculate_checksum - Calculate checksum for buffer 4557 * @buffer: pointer to EEPROM 4558 * @length: size of EEPROM to calculate a checksum for 4559 * Calculates the checksum for some buffer on a specified length. The 4560 * checksum calculated is returned. 4561 **/ 4562 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4563 { 4564 u32 i; 4565 u8 sum = 0; 4566 4567 DEBUGFUNC("ixgbe_calculate_checksum"); 4568 4569 if (!buffer) 4570 return 0; 4571 4572 for (i = 0; i < length; i++) 4573 sum += buffer[i]; 4574 4575 return (u8) (0 - sum); 4576 } 4577 4578 /** 4579 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4580 * @hw: pointer to the HW structure 4581 * @buffer: command to write and where the return status will be placed 4582 * @length: length of buffer, must be multiple of 4 bytes 4583 * @timeout: time in ms to wait for command completion 4584 * 4585 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4586 * else returns semaphore error when encountering an error acquiring 4587 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4588 * 4589 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4590 * by the caller. 4591 **/ 4592 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4593 u32 timeout) 4594 { 4595 u32 hicr, i, fwsts; 4596 u16 dword_len; 4597 4598 DEBUGFUNC("ixgbe_hic_unlocked"); 4599 4600 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4601 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4602 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4603 } 4604 4605 /* Set bit 9 of FWSTS clearing FW reset indication */ 4606 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4607 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4608 4609 /* Check that the host interface is enabled. */ 4610 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4611 if (!(hicr & IXGBE_HICR_EN)) { 4612 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4613 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4614 } 4615 4616 /* Calculate length in DWORDs. We must be DWORD aligned */ 4617 if (length % sizeof(u32)) { 4618 DEBUGOUT("Buffer length failure, not aligned to dword"); 4619 return IXGBE_ERR_INVALID_ARGUMENT; 4620 } 4621 4622 dword_len = length >> 2; 4623 4624 /* The device driver writes the relevant command block 4625 * into the ram area. 4626 */ 4627 for (i = 0; i < dword_len; i++) 4628 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4629 i, IXGBE_CPU_TO_LE32(buffer[i])); 4630 4631 /* Setting this bit tells the ARC that a new command is pending. */ 4632 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4633 4634 for (i = 0; i < timeout; i++) { 4635 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4636 if (!(hicr & IXGBE_HICR_C)) 4637 break; 4638 msec_delay(1); 4639 } 4640 4641 /* For each command except "Apply Update" perform 4642 * status checks in the HICR registry. 4643 */ 4644 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) == 4645 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD) 4646 return IXGBE_SUCCESS; 4647 4648 /* Check command completion */ 4649 if ((timeout && i == timeout) || 4650 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4651 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4652 "Command has failed with no status valid.\n"); 4653 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4654 } 4655 4656 return IXGBE_SUCCESS; 4657 } 4658 4659 /** 4660 * ixgbe_host_interface_command - Issue command to manageability block 4661 * @hw: pointer to the HW structure 4662 * @buffer: contains the command to write and where the return status will 4663 * be placed 4664 * @length: length of buffer, must be multiple of 4 bytes 4665 * @timeout: time in ms to wait for command completion 4666 * @return_data: read and return data from the buffer (true) or not (false) 4667 * Needed because FW structures are big endian and decoding of 4668 * these fields can be 8 bit or 16 bit based on command. Decoding 4669 * is not easily understood without making a table of commands. 4670 * So we will leave this up to the caller to read back the data 4671 * in these cases. 4672 * 4673 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4674 * else returns semaphore error when encountering an error acquiring 4675 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4676 **/ 4677 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4678 u32 length, u32 timeout, bool return_data) 4679 { 4680 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4681 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4682 u16 buf_len; 4683 s32 status; 4684 u32 bi; 4685 u32 dword_len; 4686 4687 DEBUGFUNC("ixgbe_host_interface_command"); 4688 4689 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4690 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4691 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4692 } 4693 4694 /* Take management host interface semaphore */ 4695 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4696 if (status) 4697 return status; 4698 4699 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4700 if (status) 4701 goto rel_out; 4702 4703 if (!return_data) 4704 goto rel_out; 4705 4706 /* Calculate length in DWORDs */ 4707 dword_len = hdr_size >> 2; 4708 4709 /* first pull in the header so we know the buffer length */ 4710 for (bi = 0; bi < dword_len; bi++) { 4711 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4712 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4713 } 4714 4715 /* 4716 * If there is any thing in data position pull it in 4717 * Read Flash command requires reading buffer length from 4718 * two byes instead of one byte 4719 */ 4720 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD || 4721 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) { 4722 for (; bi < dword_len + 2; bi++) { 4723 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4724 bi); 4725 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4726 } 4727 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4728 & 0xF00) | resp->buf_len; 4729 hdr_size += (2 << 2); 4730 } else { 4731 buf_len = resp->buf_len; 4732 } 4733 if (!buf_len) 4734 goto rel_out; 4735 4736 if (length < buf_len + hdr_size) { 4737 DEBUGOUT("Buffer not large enough for reply message.\n"); 4738 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4739 goto rel_out; 4740 } 4741 4742 /* Calculate length in DWORDs, add 3 for odd lengths */ 4743 dword_len = (buf_len + 3) >> 2; 4744 4745 /* Pull in the rest of the buffer (bi is where we left off) */ 4746 for (; bi <= dword_len; bi++) { 4747 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4748 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4749 } 4750 4751 rel_out: 4752 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4753 4754 return status; 4755 } 4756 4757 /** 4758 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4759 * @hw: pointer to the HW structure 4760 * @maj: driver version major number 4761 * @min: driver version minor number 4762 * @build: driver version build number 4763 * @sub: driver version sub build number 4764 * @len: unused 4765 * @driver_ver: unused 4766 * 4767 * Sends driver version number to firmware through the manageability 4768 * block. On success return IXGBE_SUCCESS 4769 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4770 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4771 **/ 4772 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4773 u8 build, u8 sub, u16 len, 4774 const char *driver_ver) 4775 { 4776 struct ixgbe_hic_drv_info fw_cmd; 4777 int i; 4778 s32 ret_val = IXGBE_SUCCESS; 4779 4780 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4781 UNREFERENCED_2PARAMETER(len, driver_ver); 4782 4783 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4784 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4785 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4786 fw_cmd.port_num = (u8)hw->bus.func; 4787 fw_cmd.ver_maj = maj; 4788 fw_cmd.ver_min = min; 4789 fw_cmd.ver_build = build; 4790 fw_cmd.ver_sub = sub; 4791 fw_cmd.hdr.checksum = 0; 4792 fw_cmd.pad = 0; 4793 fw_cmd.pad2 = 0; 4794 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4795 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4796 4797 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4798 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4799 sizeof(fw_cmd), 4800 IXGBE_HI_COMMAND_TIMEOUT, 4801 true); 4802 if (ret_val != IXGBE_SUCCESS) 4803 continue; 4804 4805 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4806 FW_CEM_RESP_STATUS_SUCCESS) 4807 ret_val = IXGBE_SUCCESS; 4808 else 4809 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4810 4811 break; 4812 } 4813 4814 return ret_val; 4815 } 4816 4817 /** 4818 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4819 * @hw: pointer to hardware structure 4820 * @num_pb: number of packet buffers to allocate 4821 * @headroom: reserve n KB of headroom 4822 * @strategy: packet buffer allocation strategy 4823 **/ 4824 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4825 int strategy) 4826 { 4827 u32 pbsize = hw->mac.rx_pb_size; 4828 int i = 0; 4829 u32 rxpktsize, txpktsize, txpbthresh; 4830 4831 /* Reserve headroom */ 4832 pbsize -= headroom; 4833 4834 if (!num_pb) 4835 num_pb = 1; 4836 4837 /* Divide remaining packet buffer space amongst the number of packet 4838 * buffers requested using supplied strategy. 4839 */ 4840 switch (strategy) { 4841 case PBA_STRATEGY_WEIGHTED: 4842 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4843 * buffer with 5/8 of the packet buffer space. 4844 */ 4845 rxpktsize = (pbsize * 5) / (num_pb * 4); 4846 pbsize -= rxpktsize * (num_pb / 2); 4847 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4848 for (; i < (num_pb / 2); i++) 4849 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4850 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4851 for (; i < num_pb; i++) 4852 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4853 break; 4854 case PBA_STRATEGY_EQUAL: 4855 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4856 for (; i < num_pb; i++) 4857 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4858 break; 4859 default: 4860 break; 4861 } 4862 4863 /* Only support an equally distributed Tx packet buffer strategy. */ 4864 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4865 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4866 for (i = 0; i < num_pb; i++) { 4867 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4868 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4869 } 4870 4871 /* Clear unused TCs, if any, to zero buffer size*/ 4872 for (; i < IXGBE_MAX_PB; i++) { 4873 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4874 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4875 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4876 } 4877 } 4878 4879 /** 4880 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4881 * @hw: pointer to the hardware structure 4882 * 4883 * The 82599 and x540 MACs can experience issues if TX work is still pending 4884 * when a reset occurs. This function prevents this by flushing the PCIe 4885 * buffers on the system. 4886 **/ 4887 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4888 { 4889 u32 gcr_ext, hlreg0, i, poll; 4890 u16 value; 4891 4892 /* 4893 * If double reset is not requested then all transactions should 4894 * already be clear and as such there is no work to do 4895 */ 4896 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4897 return; 4898 4899 /* 4900 * Set loopback enable to prevent any transmits from being sent 4901 * should the link come up. This assumes that the RXCTRL.RXEN bit 4902 * has already been cleared. 4903 */ 4904 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4905 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4906 4907 /* Wait for a last completion before clearing buffers */ 4908 IXGBE_WRITE_FLUSH(hw); 4909 msec_delay(3); 4910 4911 /* 4912 * Before proceeding, make sure that the PCIe block does not have 4913 * transactions pending. 4914 */ 4915 poll = ixgbe_pcie_timeout_poll(hw); 4916 for (i = 0; i < poll; i++) { 4917 usec_delay(100); 4918 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4919 if (IXGBE_REMOVED(hw->hw_addr)) 4920 goto out; 4921 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4922 goto out; 4923 } 4924 4925 out: 4926 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4927 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4928 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4929 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4930 4931 /* Flush all writes and allow 20usec for all transactions to clear */ 4932 IXGBE_WRITE_FLUSH(hw); 4933 usec_delay(20); 4934 4935 /* restore previous register values */ 4936 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4937 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4938 } 4939 4940 static const u8 ixgbe_emc_temp_data[4] = { 4941 IXGBE_EMC_INTERNAL_DATA, 4942 IXGBE_EMC_DIODE1_DATA, 4943 IXGBE_EMC_DIODE2_DATA, 4944 IXGBE_EMC_DIODE3_DATA 4945 }; 4946 static const u8 ixgbe_emc_therm_limit[4] = { 4947 IXGBE_EMC_INTERNAL_THERM_LIMIT, 4948 IXGBE_EMC_DIODE1_THERM_LIMIT, 4949 IXGBE_EMC_DIODE2_THERM_LIMIT, 4950 IXGBE_EMC_DIODE3_THERM_LIMIT 4951 }; 4952 4953 /** 4954 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data 4955 * @hw: pointer to hardware structure 4956 * 4957 * Returns the thermal sensor data structure 4958 **/ 4959 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 4960 { 4961 s32 status = IXGBE_SUCCESS; 4962 u16 ets_offset; 4963 u16 ets_cfg; 4964 u16 ets_sensor; 4965 u8 num_sensors; 4966 u8 sensor_index; 4967 u8 sensor_location; 4968 u8 i; 4969 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 4970 4971 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic"); 4972 4973 /* Only support thermal sensors attached to 82599 physical port 0 */ 4974 if ((hw->mac.type != ixgbe_mac_82599EB) || 4975 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) { 4976 status = IXGBE_NOT_IMPLEMENTED; 4977 goto out; 4978 } 4979 4980 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset); 4981 if (status) 4982 goto out; 4983 4984 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) { 4985 status = IXGBE_NOT_IMPLEMENTED; 4986 goto out; 4987 } 4988 4989 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg); 4990 if (status) 4991 goto out; 4992 4993 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 4994 != IXGBE_ETS_TYPE_EMC) { 4995 status = IXGBE_NOT_IMPLEMENTED; 4996 goto out; 4997 } 4998 4999 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 5000 if (num_sensors > IXGBE_MAX_SENSORS) 5001 num_sensors = IXGBE_MAX_SENSORS; 5002 5003 for (i = 0; i < num_sensors; i++) { 5004 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 5005 &ets_sensor); 5006 if (status) 5007 goto out; 5008 5009 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 5010 IXGBE_ETS_DATA_INDEX_SHIFT); 5011 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 5012 IXGBE_ETS_DATA_LOC_SHIFT); 5013 5014 if (sensor_location != 0) { 5015 status = hw->phy.ops.read_i2c_byte(hw, 5016 ixgbe_emc_temp_data[sensor_index], 5017 IXGBE_I2C_THERMAL_SENSOR_ADDR, 5018 &data->sensor[i].temp); 5019 if (status) 5020 goto out; 5021 } 5022 } 5023 out: 5024 return status; 5025 } 5026 5027 /** 5028 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 5029 * @hw: pointer to hardware structure 5030 * 5031 * Inits the thermal sensor thresholds according to the NVM map 5032 * and save off the threshold and location values into mac.thermal_sensor_data 5033 **/ 5034 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 5035 { 5036 s32 status = IXGBE_SUCCESS; 5037 u16 offset; 5038 u16 ets_offset; 5039 u16 ets_cfg; 5040 u16 ets_sensor; 5041 u8 low_thresh_delta; 5042 u8 num_sensors; 5043 u8 sensor_index; 5044 u8 sensor_location; 5045 u8 therm_limit; 5046 u8 i; 5047 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 5048 5049 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic"); 5050 5051 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 5052 5053 /* Only support thermal sensors attached to 82599 physical port 0 */ 5054 if ((hw->mac.type != ixgbe_mac_82599EB) || 5055 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 5056 return IXGBE_NOT_IMPLEMENTED; 5057 5058 offset = IXGBE_ETS_CFG; 5059 if (hw->eeprom.ops.read(hw, offset, &ets_offset)) 5060 goto eeprom_err; 5061 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 5062 return IXGBE_NOT_IMPLEMENTED; 5063 5064 offset = ets_offset; 5065 if (hw->eeprom.ops.read(hw, offset, &ets_cfg)) 5066 goto eeprom_err; 5067 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 5068 != IXGBE_ETS_TYPE_EMC) 5069 return IXGBE_NOT_IMPLEMENTED; 5070 5071 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 5072 IXGBE_ETS_LTHRES_DELTA_SHIFT); 5073 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 5074 5075 for (i = 0; i < num_sensors; i++) { 5076 offset = ets_offset + 1 + i; 5077 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) { 5078 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 5079 "eeprom read at offset %d failed", 5080 offset); 5081 continue; 5082 } 5083 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 5084 IXGBE_ETS_DATA_INDEX_SHIFT); 5085 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 5086 IXGBE_ETS_DATA_LOC_SHIFT); 5087 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 5088 5089 hw->phy.ops.write_i2c_byte(hw, 5090 ixgbe_emc_therm_limit[sensor_index], 5091 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 5092 5093 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) { 5094 data->sensor[i].location = sensor_location; 5095 data->sensor[i].caution_thresh = therm_limit; 5096 data->sensor[i].max_op_thresh = therm_limit - 5097 low_thresh_delta; 5098 } 5099 } 5100 return status; 5101 5102 eeprom_err: 5103 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 5104 "eeprom read at offset %d failed", offset); 5105 return IXGBE_NOT_IMPLEMENTED; 5106 } 5107 5108 /** 5109 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 5110 * 5111 * @hw: pointer to hardware structure 5112 * @cmd: Command we send to the FW 5113 * @status: The reply from the FW 5114 * 5115 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 5116 **/ 5117 #define IXGBE_BYPASS_BB_WAIT 1 5118 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 5119 { 5120 int i; 5121 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 5122 u32 esdp; 5123 5124 if (!status) 5125 return IXGBE_ERR_PARAM; 5126 5127 *status = 0; 5128 5129 /* SDP vary by MAC type */ 5130 switch (hw->mac.type) { 5131 case ixgbe_mac_82599EB: 5132 sck = IXGBE_ESDP_SDP7; 5133 sdi = IXGBE_ESDP_SDP0; 5134 sdo = IXGBE_ESDP_SDP6; 5135 dir_sck = IXGBE_ESDP_SDP7_DIR; 5136 dir_sdi = IXGBE_ESDP_SDP0_DIR; 5137 dir_sdo = IXGBE_ESDP_SDP6_DIR; 5138 break; 5139 case ixgbe_mac_X540: 5140 sck = IXGBE_ESDP_SDP2; 5141 sdi = IXGBE_ESDP_SDP0; 5142 sdo = IXGBE_ESDP_SDP1; 5143 dir_sck = IXGBE_ESDP_SDP2_DIR; 5144 dir_sdi = IXGBE_ESDP_SDP0_DIR; 5145 dir_sdo = IXGBE_ESDP_SDP1_DIR; 5146 break; 5147 default: 5148 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 5149 } 5150 5151 /* Set SDP pins direction */ 5152 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5153 esdp |= dir_sck; /* SCK as output */ 5154 esdp |= dir_sdi; /* SDI as output */ 5155 esdp &= ~dir_sdo; /* SDO as input */ 5156 esdp |= sck; 5157 esdp |= sdi; 5158 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5159 IXGBE_WRITE_FLUSH(hw); 5160 msec_delay(IXGBE_BYPASS_BB_WAIT); 5161 5162 /* Generate start condition */ 5163 esdp &= ~sdi; 5164 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5165 IXGBE_WRITE_FLUSH(hw); 5166 msec_delay(IXGBE_BYPASS_BB_WAIT); 5167 5168 esdp &= ~sck; 5169 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5170 IXGBE_WRITE_FLUSH(hw); 5171 msec_delay(IXGBE_BYPASS_BB_WAIT); 5172 5173 /* Clock out the new control word and clock in the status */ 5174 for (i = 0; i < 32; i++) { 5175 if ((cmd >> (31 - i)) & 0x01) { 5176 esdp |= sdi; 5177 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5178 } else { 5179 esdp &= ~sdi; 5180 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5181 } 5182 IXGBE_WRITE_FLUSH(hw); 5183 msec_delay(IXGBE_BYPASS_BB_WAIT); 5184 5185 esdp |= sck; 5186 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5187 IXGBE_WRITE_FLUSH(hw); 5188 msec_delay(IXGBE_BYPASS_BB_WAIT); 5189 5190 esdp &= ~sck; 5191 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5192 IXGBE_WRITE_FLUSH(hw); 5193 msec_delay(IXGBE_BYPASS_BB_WAIT); 5194 5195 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5196 if (esdp & sdo) 5197 *status = (*status << 1) | 0x01; 5198 else 5199 *status = (*status << 1) | 0x00; 5200 msec_delay(IXGBE_BYPASS_BB_WAIT); 5201 } 5202 5203 /* stop condition */ 5204 esdp |= sck; 5205 esdp &= ~sdi; 5206 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5207 IXGBE_WRITE_FLUSH(hw); 5208 msec_delay(IXGBE_BYPASS_BB_WAIT); 5209 5210 esdp |= sdi; 5211 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5212 IXGBE_WRITE_FLUSH(hw); 5213 5214 /* set the page bits to match the cmd that the status it belongs to */ 5215 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 5216 5217 return IXGBE_SUCCESS; 5218 } 5219 5220 /** 5221 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 5222 * @in_reg: The register cmd for the bit-bang read. 5223 * @out_reg: The register returned from a bit-bang read. 5224 * 5225 * If we send a write we can't be sure it took until we can read back 5226 * that same register. It can be a problem as some of the fields may 5227 * for valid reasons change inbetween the time wrote the register and 5228 * we read it again to verify. So this function check everything we 5229 * can check and then assumes it worked. 5230 **/ 5231 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 5232 { 5233 u32 mask; 5234 5235 /* Page must match for all control pages */ 5236 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 5237 return false; 5238 5239 switch (in_reg & BYPASS_PAGE_M) { 5240 case BYPASS_PAGE_CTL0: 5241 /* All the following can't change since the last write 5242 * - All the event actions 5243 * - The timeout value 5244 */ 5245 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 5246 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 5247 BYPASS_WDTIMEOUT_M | 5248 BYPASS_WDT_VALUE_M; 5249 if ((out_reg & mask) != (in_reg & mask)) 5250 return false; 5251 5252 /* 0x0 is never a valid value for bypass status */ 5253 if (!(out_reg & BYPASS_STATUS_OFF_M)) 5254 return false; 5255 break; 5256 case BYPASS_PAGE_CTL1: 5257 /* All the following can't change since the last write 5258 * - time valid bit 5259 * - time we last sent 5260 */ 5261 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 5262 if ((out_reg & mask) != (in_reg & mask)) 5263 return false; 5264 break; 5265 case BYPASS_PAGE_CTL2: 5266 /* All we can check in this page is control number 5267 * which is already done above. 5268 */ 5269 break; 5270 } 5271 5272 /* We are as sure as we can be return true */ 5273 return true; 5274 } 5275 5276 /** 5277 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 5278 * 5279 * @hw: pointer to hardware structure 5280 * @ctrl: The control word we are setting. 5281 * @event: The event we are setting in the FW. This also happens to 5282 * be the mask for the event we are setting (handy) 5283 * @action: The action we set the event to in the FW. This is in a 5284 * bit field that happens to be what we want to put in 5285 * the event spot (also handy) 5286 **/ 5287 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5288 u32 action) 5289 { 5290 u32 by_ctl = 0; 5291 u32 cmd, verify; 5292 u32 count = 0; 5293 5294 /* Get current values */ 5295 cmd = ctrl; /* just reading only need control number */ 5296 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5297 return IXGBE_ERR_INVALID_ARGUMENT; 5298 5299 /* Set to new action */ 5300 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5301 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5302 return IXGBE_ERR_INVALID_ARGUMENT; 5303 5304 /* Page 0 force a FW eeprom write which is slow so verify */ 5305 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5306 verify = BYPASS_PAGE_CTL0; 5307 do { 5308 if (count++ > 5) 5309 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5310 5311 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5312 return IXGBE_ERR_INVALID_ARGUMENT; 5313 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5314 } else { 5315 /* We have give the FW time for the write to stick */ 5316 msec_delay(100); 5317 } 5318 5319 return IXGBE_SUCCESS; 5320 } 5321 5322 /** 5323 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5324 * 5325 * @hw: pointer to hardware structure 5326 * @addr: The bypass eeprom address to read. 5327 * @value: The 8b of data at the address above. 5328 **/ 5329 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5330 { 5331 u32 cmd; 5332 u32 status; 5333 5334 5335 /* send the request */ 5336 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5337 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5338 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5339 return IXGBE_ERR_INVALID_ARGUMENT; 5340 5341 /* We have give the FW time for the write to stick */ 5342 msec_delay(100); 5343 5344 /* now read the results */ 5345 cmd &= ~BYPASS_WE; 5346 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5347 return IXGBE_ERR_INVALID_ARGUMENT; 5348 5349 *value = status & BYPASS_CTL2_DATA_M; 5350 5351 return IXGBE_SUCCESS; 5352 } 5353 5354 /** 5355 * ixgbe_get_orom_version - Return option ROM from EEPROM 5356 * 5357 * @hw: pointer to hardware structure 5358 * @nvm_ver: pointer to output structure 5359 * 5360 * if valid option ROM version, nvm_ver->or_valid set to true 5361 * else nvm_ver->or_valid is false. 5362 **/ 5363 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5364 struct ixgbe_nvm_version *nvm_ver) 5365 { 5366 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5367 5368 nvm_ver->or_valid = false; 5369 /* Option Rom may or may not be present. Start with pointer */ 5370 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5371 5372 /* make sure offset is valid */ 5373 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5374 return; 5375 5376 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5377 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5378 5379 /* option rom exists and is valid */ 5380 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5381 eeprom_cfg_blkl == NVM_VER_INVALID || 5382 eeprom_cfg_blkh == NVM_VER_INVALID) 5383 return; 5384 5385 nvm_ver->or_valid = true; 5386 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5387 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5388 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5389 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5390 } 5391 5392 /** 5393 * ixgbe_get_oem_prod_version - Return OEM Product version 5394 * 5395 * @hw: pointer to hardware structure 5396 * @nvm_ver: pointer to output structure 5397 * 5398 * if valid OEM product version, nvm_ver->oem_valid set to true 5399 * else nvm_ver->oem_valid is false. 5400 **/ 5401 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5402 struct ixgbe_nvm_version *nvm_ver) 5403 { 5404 u16 rel_num, prod_ver, mod_len, cap, offset; 5405 5406 nvm_ver->oem_valid = false; 5407 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5408 5409 /* Return if offset to OEM Product Version block is invalid */ 5410 if (offset == 0x0 || offset == NVM_INVALID_PTR) 5411 return; 5412 5413 /* Read product version block */ 5414 hw->eeprom.ops.read(hw, offset, &mod_len); 5415 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5416 5417 /* Return if OEM product version block is invalid */ 5418 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5419 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5420 return; 5421 5422 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5423 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5424 5425 /* Return if version is invalid */ 5426 if ((rel_num | prod_ver) == 0x0 || 5427 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5428 return; 5429 5430 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5431 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5432 nvm_ver->oem_release = rel_num; 5433 nvm_ver->oem_valid = true; 5434 } 5435 5436 /** 5437 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5438 * 5439 * @hw: pointer to hardware structure 5440 * @nvm_ver: pointer to output structure 5441 * 5442 * word read errors will return 0xFFFF 5443 **/ 5444 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5445 { 5446 u16 etk_id_l, etk_id_h; 5447 5448 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5449 etk_id_l = NVM_VER_INVALID; 5450 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5451 etk_id_h = NVM_VER_INVALID; 5452 5453 /* The word order for the version format is determined by high order 5454 * word bit 15. 5455 */ 5456 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5457 nvm_ver->etk_id = etk_id_h; 5458 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 5459 } else { 5460 nvm_ver->etk_id = etk_id_l; 5461 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 5462 } 5463 } 5464 5465 /** 5466 * ixgbe_get_nvm_version - Return version of NVM and its components 5467 * 5468 * @hw: pointer to hardware structure 5469 * @nvm_ver: pointer to output structure 5470 * 5471 * irrelevant component fields will return 0, read errors will return 0xff 5472 **/ 5473 void ixgbe_get_nvm_version(struct ixgbe_hw *hw, 5474 struct ixgbe_nvm_version *nvm_ver) 5475 { 5476 u16 word, phy_ver; 5477 5478 DEBUGFUNC("ixgbe_get_nvm_version"); 5479 5480 memset(nvm_ver, 0, sizeof(struct ixgbe_nvm_version)); 5481 5482 /* eeprom version is mac-type specific */ 5483 switch (hw->mac.type) { 5484 case ixgbe_mac_82598EB: 5485 /* version of eeprom section */ 5486 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_82598, &word)) 5487 word = NVM_VER_INVALID; 5488 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5489 >> NVM_EEP_MAJ_SHIFT); 5490 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) 5491 >> NVM_EEP_MIN_SHIFT); 5492 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); 5493 break; 5494 case ixgbe_mac_X540: 5495 /* version of eeprom section */ 5496 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) 5497 word = NVM_VER_INVALID; 5498 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5499 >> NVM_EEP_MAJ_SHIFT); 5500 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) 5501 >> NVM_EEP_MIN_SHIFT); 5502 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); 5503 break; 5504 5505 case ixgbe_mac_X550: 5506 case ixgbe_mac_X550EM_x: 5507 case ixgbe_mac_X550EM_a: 5508 case ixgbe_mac_E610: 5509 /* version of eeprom section */ 5510 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) 5511 word = NVM_VER_INVALID; 5512 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) 5513 >> NVM_EEP_MAJ_SHIFT); 5514 nvm_ver->nvm_minor = (word & NVM_EEP_X550_MINOR_MASK); 5515 5516 break; 5517 default: 5518 break; 5519 } 5520 5521 /* phy version is mac-type specific */ 5522 switch (hw->mac.type) { 5523 case ixgbe_mac_X540: 5524 case ixgbe_mac_X550: 5525 case ixgbe_mac_X550EM_x: 5526 case ixgbe_mac_X550EM_a: 5527 case ixgbe_mac_E610: 5528 /* intel phy firmware version */ 5529 if (ixgbe_read_eeprom(hw, NVM_EEP_PHY_OFF_X540, &word)) 5530 word = NVM_VER_INVALID; 5531 nvm_ver->phy_fw_maj = ((word & NVM_PHY_MAJOR_MASK) 5532 >> NVM_PHY_MAJ_SHIFT); 5533 nvm_ver->phy_fw_min = ((word & NVM_PHY_MINOR_MASK) 5534 >> NVM_PHY_MIN_SHIFT); 5535 nvm_ver->phy_fw_id = (word & NVM_PHY_ID_MASK); 5536 break; 5537 default: 5538 break; 5539 } 5540 5541 ixgbe_get_etk_id(hw, nvm_ver); 5542 5543 /* devstarter image */ 5544 if (ixgbe_read_eeprom(hw, NVM_DS_OFFSET, &word)) 5545 word = NVM_VER_INVALID; 5546 nvm_ver->devstart_major = ((word & NVM_DS_MAJOR_MASK) >> NVM_DS_SHIFT); 5547 nvm_ver->devstart_minor = (word & NVM_DS_MINOR_MASK); 5548 5549 /* OEM customization word */ 5550 if (ixgbe_read_eeprom(hw, NVM_OEM_OFFSET, &nvm_ver->oem_specific)) 5551 nvm_ver->oem_specific = NVM_VER_INVALID; 5552 5553 /* vendor (not intel) phy firmware version */ 5554 if (ixgbe_get_phy_firmware_version(hw, &phy_ver)) 5555 phy_ver = NVM_VER_INVALID; 5556 nvm_ver->phy_vend_maj = ((phy_ver & NVM_PHYVEND_MAJOR_MASK) 5557 >> NVM_PHYVEND_SHIFT); 5558 nvm_ver->phy_vend_min = (phy_ver & NVM_PHYVEND_MINOR_MASK); 5559 5560 /* Option Rom may or may not be present. Start with pointer */ 5561 ixgbe_get_orom_version(hw, nvm_ver); 5562 return; 5563 } 5564 5565 /** 5566 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5567 * @hw: pointer to hardware structure 5568 * @map: pointer to u8 arr for returning map 5569 * 5570 * Read the rtrup2tc HW register and resolve its content into map 5571 **/ 5572 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5573 { 5574 u32 reg, i; 5575 5576 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5577 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5578 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5579 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5580 return; 5581 } 5582 5583 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5584 { 5585 u32 pfdtxgswc; 5586 u32 rxctrl; 5587 5588 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5589 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5590 if (hw->mac.type != ixgbe_mac_82598EB) { 5591 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5592 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5593 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5594 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5595 hw->mac.set_lben = true; 5596 } else { 5597 hw->mac.set_lben = false; 5598 } 5599 } 5600 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5601 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5602 } 5603 } 5604 5605 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5606 { 5607 u32 pfdtxgswc; 5608 u32 rxctrl; 5609 5610 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5611 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5612 5613 if (hw->mac.type != ixgbe_mac_82598EB) { 5614 if (hw->mac.set_lben) { 5615 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5616 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5617 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5618 hw->mac.set_lben = false; 5619 } 5620 } 5621 } 5622 5623 /** 5624 * ixgbe_mng_present - returns true when management capability is present 5625 * @hw: pointer to hardware structure 5626 */ 5627 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5628 { 5629 u32 fwsm; 5630 5631 if (hw->mac.type < ixgbe_mac_82599EB) 5632 return false; 5633 5634 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5635 5636 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5637 } 5638 5639 /** 5640 * ixgbe_mng_enabled - Is the manageability engine enabled? 5641 * @hw: pointer to hardware structure 5642 * 5643 * Returns true if the manageability engine is enabled. 5644 **/ 5645 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5646 { 5647 u32 fwsm, manc, factps; 5648 5649 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5650 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5651 return false; 5652 5653 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5654 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5655 return false; 5656 5657 if (hw->mac.type <= ixgbe_mac_X540) { 5658 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5659 if (factps & IXGBE_FACTPS_MNGCG) 5660 return false; 5661 } 5662 5663 return true; 5664 } 5665 5666 /** 5667 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5668 * @hw: pointer to hardware structure 5669 * @speed: new link speed 5670 * @autoneg_wait_to_complete: true when waiting for completion is needed 5671 * 5672 * Set the link speed in the MAC and/or PHY register and restarts link. 5673 **/ 5674 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5675 ixgbe_link_speed speed, 5676 bool autoneg_wait_to_complete) 5677 { 5678 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5679 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5680 s32 status = IXGBE_SUCCESS; 5681 u32 speedcnt = 0; 5682 u32 i = 0; 5683 bool autoneg, link_up = false; 5684 5685 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5686 5687 /* Mask off requested but non-supported speeds */ 5688 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5689 if (status != IXGBE_SUCCESS) 5690 return status; 5691 5692 speed &= link_speed; 5693 5694 /* Try each speed one by one, highest priority first. We do this in 5695 * software because 10Gb fiber doesn't support speed autonegotiation. 5696 */ 5697 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5698 speedcnt++; 5699 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5700 5701 /* Set the module link speed */ 5702 switch (hw->phy.media_type) { 5703 case ixgbe_media_type_fiber_fixed: 5704 case ixgbe_media_type_fiber: 5705 ixgbe_set_rate_select_speed(hw, 5706 IXGBE_LINK_SPEED_10GB_FULL); 5707 break; 5708 case ixgbe_media_type_fiber_qsfp: 5709 /* QSFP module automatically detects MAC link speed */ 5710 break; 5711 default: 5712 DEBUGOUT("Unexpected media type.\n"); 5713 break; 5714 } 5715 5716 /* Allow module to change analog characteristics (1G->10G) */ 5717 msec_delay(40); 5718 5719 status = ixgbe_setup_mac_link(hw, 5720 IXGBE_LINK_SPEED_10GB_FULL, 5721 autoneg_wait_to_complete); 5722 if (status != IXGBE_SUCCESS) 5723 return status; 5724 5725 /* Flap the Tx laser if it has not already been done */ 5726 ixgbe_flap_tx_laser(hw); 5727 5728 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5729 * Section 73.10.2, we may have to wait up to 1000ms if KR is 5730 * attempted. 82599 uses the same timing for 10g SFI. 5731 */ 5732 for (i = 0; i < 10; i++) { 5733 /* Wait for the link partner to also set speed */ 5734 msec_delay(100); 5735 5736 /* If we have link, just jump out */ 5737 status = ixgbe_check_link(hw, &link_speed, 5738 &link_up, false); 5739 if (status != IXGBE_SUCCESS) 5740 return status; 5741 5742 if (link_up) 5743 goto out; 5744 } 5745 } 5746 5747 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5748 speedcnt++; 5749 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5750 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5751 5752 /* Set the module link speed */ 5753 switch (hw->phy.media_type) { 5754 case ixgbe_media_type_fiber_fixed: 5755 case ixgbe_media_type_fiber: 5756 ixgbe_set_rate_select_speed(hw, 5757 IXGBE_LINK_SPEED_1GB_FULL); 5758 break; 5759 case ixgbe_media_type_fiber_qsfp: 5760 /* QSFP module automatically detects link speed */ 5761 break; 5762 default: 5763 DEBUGOUT("Unexpected media type.\n"); 5764 break; 5765 } 5766 5767 /* Allow module to change analog characteristics (10G->1G) */ 5768 msec_delay(40); 5769 5770 status = ixgbe_setup_mac_link(hw, 5771 IXGBE_LINK_SPEED_1GB_FULL, 5772 autoneg_wait_to_complete); 5773 if (status != IXGBE_SUCCESS) 5774 return status; 5775 5776 /* Flap the Tx laser if it has not already been done */ 5777 ixgbe_flap_tx_laser(hw); 5778 5779 /* Wait for the link partner to also set speed */ 5780 msec_delay(100); 5781 5782 /* If we have link, just jump out */ 5783 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 5784 if (status != IXGBE_SUCCESS) 5785 return status; 5786 5787 if (link_up) 5788 goto out; 5789 } 5790 5791 /* We didn't get link. Configure back to the highest speed we tried, 5792 * (if there was more than one). We call ourselves back with just the 5793 * single highest speed that the user requested. 5794 */ 5795 if (speedcnt > 1) 5796 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5797 highest_link_speed, 5798 autoneg_wait_to_complete); 5799 5800 out: 5801 /* Set autoneg_advertised value based on input link speed */ 5802 hw->phy.autoneg_advertised = 0; 5803 5804 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5805 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5806 5807 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5808 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5809 5810 return status; 5811 } 5812 5813 /** 5814 * ixgbe_set_soft_rate_select_speed - Set module link speed 5815 * @hw: pointer to hardware structure 5816 * @speed: link speed to set 5817 * 5818 * Set module link speed via the soft rate select. 5819 */ 5820 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5821 ixgbe_link_speed speed) 5822 { 5823 s32 status; 5824 u8 rs, eeprom_data; 5825 5826 switch (speed) { 5827 case IXGBE_LINK_SPEED_10GB_FULL: 5828 /* one bit mask same as setting on */ 5829 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5830 break; 5831 case IXGBE_LINK_SPEED_1GB_FULL: 5832 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5833 break; 5834 default: 5835 DEBUGOUT("Invalid fixed module speed\n"); 5836 return; 5837 } 5838 5839 /* Set RS0 */ 5840 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5841 IXGBE_I2C_EEPROM_DEV_ADDR2, 5842 &eeprom_data); 5843 if (status) { 5844 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5845 goto out; 5846 } 5847 5848 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5849 5850 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5851 IXGBE_I2C_EEPROM_DEV_ADDR2, 5852 eeprom_data); 5853 if (status) { 5854 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5855 goto out; 5856 } 5857 5858 /* Set RS1 */ 5859 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5860 IXGBE_I2C_EEPROM_DEV_ADDR2, 5861 &eeprom_data); 5862 if (status) { 5863 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5864 goto out; 5865 } 5866 5867 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5868 5869 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5870 IXGBE_I2C_EEPROM_DEV_ADDR2, 5871 eeprom_data); 5872 if (status) { 5873 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5874 goto out; 5875 } 5876 out: 5877 return; 5878 } 5879