1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2017, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 #include "ixgbe_dcb.h" 39 #include "ixgbe_dcb_82599.h" 40 #include "ixgbe_api.h" 41 42 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 43 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 44 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 45 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 46 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 47 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 48 u16 count); 49 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 50 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 52 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 53 54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 55 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 56 u16 *san_mac_offset); 57 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 58 u16 words, u16 *data); 59 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 62 u16 offset); 63 64 /** 65 * ixgbe_init_ops_generic - Inits function ptrs 66 * @hw: pointer to the hardware structure 67 * 68 * Initialize the function pointers. 69 **/ 70 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 71 { 72 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 73 struct ixgbe_mac_info *mac = &hw->mac; 74 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 75 76 DEBUGFUNC("ixgbe_init_ops_generic"); 77 78 /* EEPROM */ 79 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 80 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 81 if (eec & IXGBE_EEC_PRES) { 82 eeprom->ops.read = ixgbe_read_eerd_generic; 83 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 84 } else { 85 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 86 eeprom->ops.read_buffer = 87 ixgbe_read_eeprom_buffer_bit_bang_generic; 88 } 89 eeprom->ops.write = ixgbe_write_eeprom_generic; 90 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 91 eeprom->ops.validate_checksum = 92 ixgbe_validate_eeprom_checksum_generic; 93 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 94 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 95 96 /* MAC */ 97 mac->ops.init_hw = ixgbe_init_hw_generic; 98 mac->ops.reset_hw = NULL; 99 mac->ops.start_hw = ixgbe_start_hw_generic; 100 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 101 mac->ops.get_media_type = NULL; 102 mac->ops.get_supported_physical_layer = NULL; 103 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 104 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 105 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 106 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 107 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 108 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 109 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 110 mac->ops.prot_autoc_read = prot_autoc_read_generic; 111 mac->ops.prot_autoc_write = prot_autoc_write_generic; 112 113 /* LEDs */ 114 mac->ops.led_on = ixgbe_led_on_generic; 115 mac->ops.led_off = ixgbe_led_off_generic; 116 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 117 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 118 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 119 120 /* RAR, Multicast, VLAN */ 121 mac->ops.set_rar = ixgbe_set_rar_generic; 122 mac->ops.clear_rar = ixgbe_clear_rar_generic; 123 mac->ops.insert_mac_addr = NULL; 124 mac->ops.set_vmdq = NULL; 125 mac->ops.clear_vmdq = NULL; 126 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 127 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 128 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 129 mac->ops.enable_mc = ixgbe_enable_mc_generic; 130 mac->ops.disable_mc = ixgbe_disable_mc_generic; 131 mac->ops.clear_vfta = NULL; 132 mac->ops.set_vfta = NULL; 133 mac->ops.set_vlvf = NULL; 134 mac->ops.init_uta_tables = NULL; 135 mac->ops.enable_rx = ixgbe_enable_rx_generic; 136 mac->ops.disable_rx = ixgbe_disable_rx_generic; 137 138 /* Flow Control */ 139 mac->ops.fc_enable = ixgbe_fc_enable_generic; 140 mac->ops.setup_fc = ixgbe_setup_fc_generic; 141 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 142 143 /* Link */ 144 mac->ops.get_link_capabilities = NULL; 145 mac->ops.setup_link = NULL; 146 mac->ops.check_link = NULL; 147 mac->ops.dmac_config = NULL; 148 mac->ops.dmac_update_tcs = NULL; 149 mac->ops.dmac_config_tcs = NULL; 150 151 return IXGBE_SUCCESS; 152 } 153 154 /** 155 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 156 * of flow control 157 * @hw: pointer to hardware structure 158 * 159 * This function returns TRUE if the device supports flow control 160 * autonegotiation, and FALSE if it does not. 161 * 162 **/ 163 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 164 { 165 bool supported = FALSE; 166 ixgbe_link_speed speed; 167 bool link_up; 168 169 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 170 171 switch (hw->phy.media_type) { 172 case ixgbe_media_type_fiber_fixed: 173 case ixgbe_media_type_fiber_qsfp: 174 case ixgbe_media_type_fiber: 175 /* flow control autoneg black list */ 176 switch (hw->device_id) { 177 case IXGBE_DEV_ID_X550EM_A_SFP: 178 case IXGBE_DEV_ID_X550EM_A_SFP_N: 179 case IXGBE_DEV_ID_X550EM_A_QSFP: 180 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 181 supported = FALSE; 182 break; 183 default: 184 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 185 /* if link is down, assume supported */ 186 if (link_up) 187 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 188 TRUE : FALSE; 189 else 190 supported = TRUE; 191 } 192 193 break; 194 case ixgbe_media_type_backplane: 195 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 196 supported = FALSE; 197 else 198 supported = TRUE; 199 break; 200 case ixgbe_media_type_copper: 201 /* only some copper devices support flow control autoneg */ 202 switch (hw->device_id) { 203 case IXGBE_DEV_ID_82599_T3_LOM: 204 case IXGBE_DEV_ID_X540T: 205 case IXGBE_DEV_ID_X540T1: 206 case IXGBE_DEV_ID_X540_BYPASS: 207 case IXGBE_DEV_ID_X550T: 208 case IXGBE_DEV_ID_X550T1: 209 case IXGBE_DEV_ID_X550EM_X_10G_T: 210 case IXGBE_DEV_ID_X550EM_A_10G_T: 211 case IXGBE_DEV_ID_X550EM_A_1G_T: 212 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 213 supported = TRUE; 214 break; 215 default: 216 supported = FALSE; 217 } 218 default: 219 break; 220 } 221 222 if (!supported) 223 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 224 "Device %x does not support flow control autoneg", 225 hw->device_id); 226 227 return supported; 228 } 229 230 /** 231 * ixgbe_setup_fc_generic - Set up flow control 232 * @hw: pointer to hardware structure 233 * 234 * Called at init time to set up flow control. 235 **/ 236 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 237 { 238 s32 ret_val = IXGBE_SUCCESS; 239 u32 reg = 0, reg_bp = 0; 240 u16 reg_cu = 0; 241 bool locked = FALSE; 242 243 DEBUGFUNC("ixgbe_setup_fc_generic"); 244 245 /* Validate the requested mode */ 246 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 247 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 248 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 249 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 250 goto out; 251 } 252 253 /* 254 * 10gig parts do not have a word in the EEPROM to determine the 255 * default flow control setting, so we explicitly set it to full. 256 */ 257 if (hw->fc.requested_mode == ixgbe_fc_default) 258 hw->fc.requested_mode = ixgbe_fc_full; 259 260 /* 261 * Set up the 1G and 10G flow control advertisement registers so the 262 * HW will be able to do fc autoneg once the cable is plugged in. If 263 * we link at 10G, the 1G advertisement is harmless and vice versa. 264 */ 265 switch (hw->phy.media_type) { 266 case ixgbe_media_type_backplane: 267 /* some MAC's need RMW protection on AUTOC */ 268 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 269 if (ret_val != IXGBE_SUCCESS) 270 goto out; 271 272 /* fall through - only backplane uses autoc */ 273 case ixgbe_media_type_fiber_fixed: 274 case ixgbe_media_type_fiber_qsfp: 275 case ixgbe_media_type_fiber: 276 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 277 278 break; 279 case ixgbe_media_type_copper: 280 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 281 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 282 break; 283 default: 284 break; 285 } 286 287 /* 288 * The possible values of fc.requested_mode are: 289 * 0: Flow control is completely disabled 290 * 1: Rx flow control is enabled (we can receive pause frames, 291 * but not send pause frames). 292 * 2: Tx flow control is enabled (we can send pause frames but 293 * we do not support receiving pause frames). 294 * 3: Both Rx and Tx flow control (symmetric) are enabled. 295 * other: Invalid. 296 */ 297 switch (hw->fc.requested_mode) { 298 case ixgbe_fc_none: 299 /* Flow control completely disabled by software override. */ 300 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 301 if (hw->phy.media_type == ixgbe_media_type_backplane) 302 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 303 IXGBE_AUTOC_ASM_PAUSE); 304 else if (hw->phy.media_type == ixgbe_media_type_copper) 305 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 306 break; 307 case ixgbe_fc_tx_pause: 308 /* 309 * Tx Flow control is enabled, and Rx Flow control is 310 * disabled by software override. 311 */ 312 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 313 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 314 if (hw->phy.media_type == ixgbe_media_type_backplane) { 315 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 316 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 317 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 318 reg_cu |= IXGBE_TAF_ASM_PAUSE; 319 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 320 } 321 break; 322 case ixgbe_fc_rx_pause: 323 /* 324 * Rx Flow control is enabled and Tx Flow control is 325 * disabled by software override. Since there really 326 * isn't a way to advertise that we are capable of RX 327 * Pause ONLY, we will advertise that we support both 328 * symmetric and asymmetric Rx PAUSE, as such we fall 329 * through to the fc_full statement. Later, we will 330 * disable the adapter's ability to send PAUSE frames. 331 */ 332 case ixgbe_fc_full: 333 /* Flow control (both Rx and Tx) is enabled by SW override. */ 334 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 335 if (hw->phy.media_type == ixgbe_media_type_backplane) 336 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 337 IXGBE_AUTOC_ASM_PAUSE; 338 else if (hw->phy.media_type == ixgbe_media_type_copper) 339 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 340 break; 341 default: 342 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 343 "Flow control param set incorrectly\n"); 344 ret_val = IXGBE_ERR_CONFIG; 345 goto out; 346 break; 347 } 348 349 if (hw->mac.type < ixgbe_mac_X540) { 350 /* 351 * Enable auto-negotiation between the MAC & PHY; 352 * the MAC will advertise clause 37 flow control. 353 */ 354 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 355 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 356 357 /* Disable AN timeout */ 358 if (hw->fc.strict_ieee) 359 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 360 361 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 362 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 363 } 364 365 /* 366 * AUTOC restart handles negotiation of 1G and 10G on backplane 367 * and copper. There is no need to set the PCS1GCTL register. 368 * 369 */ 370 if (hw->phy.media_type == ixgbe_media_type_backplane) { 371 reg_bp |= IXGBE_AUTOC_AN_RESTART; 372 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 373 if (ret_val) 374 goto out; 375 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 376 (ixgbe_device_supports_autoneg_fc(hw))) { 377 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 378 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 379 } 380 381 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 382 out: 383 return ret_val; 384 } 385 386 /** 387 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 388 * @hw: pointer to hardware structure 389 * 390 * Starts the hardware by filling the bus info structure and media type, clears 391 * all on chip counters, initializes receive address registers, multicast 392 * table, VLAN filter table, calls routine to set up link and flow control 393 * settings, and leaves transmit and receive units disabled and uninitialized 394 **/ 395 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 396 { 397 s32 ret_val; 398 u32 ctrl_ext; 399 u16 device_caps; 400 401 DEBUGFUNC("ixgbe_start_hw_generic"); 402 403 /* Set the media type */ 404 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 405 406 /* PHY ops initialization must be done in reset_hw() */ 407 408 /* Clear the VLAN filter table */ 409 hw->mac.ops.clear_vfta(hw); 410 411 /* Clear statistics registers */ 412 hw->mac.ops.clear_hw_cntrs(hw); 413 414 /* Set No Snoop Disable */ 415 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 416 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 417 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 418 IXGBE_WRITE_FLUSH(hw); 419 420 /* Setup flow control */ 421 ret_val = ixgbe_setup_fc(hw); 422 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 423 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 424 return ret_val; 425 } 426 427 /* Cache bit indicating need for crosstalk fix */ 428 switch (hw->mac.type) { 429 case ixgbe_mac_82599EB: 430 case ixgbe_mac_X550EM_x: 431 case ixgbe_mac_X550EM_a: 432 hw->mac.ops.get_device_caps(hw, &device_caps); 433 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 434 hw->need_crosstalk_fix = FALSE; 435 else 436 hw->need_crosstalk_fix = TRUE; 437 break; 438 default: 439 hw->need_crosstalk_fix = FALSE; 440 break; 441 } 442 443 /* Clear adapter stopped flag */ 444 hw->adapter_stopped = FALSE; 445 446 return IXGBE_SUCCESS; 447 } 448 449 /** 450 * ixgbe_start_hw_gen2 - Init sequence for common device family 451 * @hw: pointer to hw structure 452 * 453 * Performs the init sequence common to the second generation 454 * of 10 GbE devices. 455 * Devices in the second generation: 456 * 82599 457 * X540 458 **/ 459 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 460 { 461 u32 i; 462 u32 regval; 463 464 /* Clear the rate limiters */ 465 for (i = 0; i < hw->mac.max_tx_queues; i++) { 466 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 467 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 468 } 469 IXGBE_WRITE_FLUSH(hw); 470 471 /* Disable relaxed ordering */ 472 for (i = 0; i < hw->mac.max_tx_queues; i++) { 473 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 474 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 475 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 476 } 477 478 for (i = 0; i < hw->mac.max_rx_queues; i++) { 479 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 480 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 481 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 482 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 483 } 484 485 return IXGBE_SUCCESS; 486 } 487 488 /** 489 * ixgbe_init_hw_generic - Generic hardware initialization 490 * @hw: pointer to hardware structure 491 * 492 * Initialize the hardware by resetting the hardware, filling the bus info 493 * structure and media type, clears all on chip counters, initializes receive 494 * address registers, multicast table, VLAN filter table, calls routine to set 495 * up link and flow control settings, and leaves transmit and receive units 496 * disabled and uninitialized 497 **/ 498 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 499 { 500 s32 status; 501 502 DEBUGFUNC("ixgbe_init_hw_generic"); 503 504 /* Reset the hardware */ 505 status = hw->mac.ops.reset_hw(hw); 506 507 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 508 /* Start the HW */ 509 status = hw->mac.ops.start_hw(hw); 510 } 511 512 /* Initialize the LED link active for LED blink support */ 513 if (hw->mac.ops.init_led_link_act) 514 hw->mac.ops.init_led_link_act(hw); 515 516 if (status != IXGBE_SUCCESS) 517 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 518 519 return status; 520 } 521 522 /** 523 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 524 * @hw: pointer to hardware structure 525 * 526 * Clears all hardware statistics counters by reading them from the hardware 527 * Statistics counters are clear on read. 528 **/ 529 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 530 { 531 u16 i = 0; 532 533 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 534 535 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 536 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 537 IXGBE_READ_REG(hw, IXGBE_ERRBC); 538 IXGBE_READ_REG(hw, IXGBE_MSPDC); 539 for (i = 0; i < 8; i++) 540 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 541 542 IXGBE_READ_REG(hw, IXGBE_MLFC); 543 IXGBE_READ_REG(hw, IXGBE_MRFC); 544 IXGBE_READ_REG(hw, IXGBE_RLEC); 545 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 546 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 547 if (hw->mac.type >= ixgbe_mac_82599EB) { 548 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 549 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 550 } else { 551 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 552 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 553 } 554 555 for (i = 0; i < 8; i++) { 556 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 557 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 558 if (hw->mac.type >= ixgbe_mac_82599EB) { 559 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 560 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 561 } else { 562 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 563 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 564 } 565 } 566 if (hw->mac.type >= ixgbe_mac_82599EB) 567 for (i = 0; i < 8; i++) 568 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 569 IXGBE_READ_REG(hw, IXGBE_PRC64); 570 IXGBE_READ_REG(hw, IXGBE_PRC127); 571 IXGBE_READ_REG(hw, IXGBE_PRC255); 572 IXGBE_READ_REG(hw, IXGBE_PRC511); 573 IXGBE_READ_REG(hw, IXGBE_PRC1023); 574 IXGBE_READ_REG(hw, IXGBE_PRC1522); 575 IXGBE_READ_REG(hw, IXGBE_GPRC); 576 IXGBE_READ_REG(hw, IXGBE_BPRC); 577 IXGBE_READ_REG(hw, IXGBE_MPRC); 578 IXGBE_READ_REG(hw, IXGBE_GPTC); 579 IXGBE_READ_REG(hw, IXGBE_GORCL); 580 IXGBE_READ_REG(hw, IXGBE_GORCH); 581 IXGBE_READ_REG(hw, IXGBE_GOTCL); 582 IXGBE_READ_REG(hw, IXGBE_GOTCH); 583 if (hw->mac.type == ixgbe_mac_82598EB) 584 for (i = 0; i < 8; i++) 585 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 586 IXGBE_READ_REG(hw, IXGBE_RUC); 587 IXGBE_READ_REG(hw, IXGBE_RFC); 588 IXGBE_READ_REG(hw, IXGBE_ROC); 589 IXGBE_READ_REG(hw, IXGBE_RJC); 590 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 591 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 592 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 593 IXGBE_READ_REG(hw, IXGBE_TORL); 594 IXGBE_READ_REG(hw, IXGBE_TORH); 595 IXGBE_READ_REG(hw, IXGBE_TPR); 596 IXGBE_READ_REG(hw, IXGBE_TPT); 597 IXGBE_READ_REG(hw, IXGBE_PTC64); 598 IXGBE_READ_REG(hw, IXGBE_PTC127); 599 IXGBE_READ_REG(hw, IXGBE_PTC255); 600 IXGBE_READ_REG(hw, IXGBE_PTC511); 601 IXGBE_READ_REG(hw, IXGBE_PTC1023); 602 IXGBE_READ_REG(hw, IXGBE_PTC1522); 603 IXGBE_READ_REG(hw, IXGBE_MPTC); 604 IXGBE_READ_REG(hw, IXGBE_BPTC); 605 for (i = 0; i < 16; i++) { 606 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 607 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 608 if (hw->mac.type >= ixgbe_mac_82599EB) { 609 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 610 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 611 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 612 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 613 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 614 } else { 615 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 616 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 617 } 618 } 619 620 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 621 if (hw->phy.id == 0) 622 ixgbe_identify_phy(hw); 623 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 624 IXGBE_MDIO_PCS_DEV_TYPE, &i); 625 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 626 IXGBE_MDIO_PCS_DEV_TYPE, &i); 627 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 628 IXGBE_MDIO_PCS_DEV_TYPE, &i); 629 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 630 IXGBE_MDIO_PCS_DEV_TYPE, &i); 631 } 632 633 return IXGBE_SUCCESS; 634 } 635 636 /** 637 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 638 * @hw: pointer to hardware structure 639 * @pba_num: stores the part number string from the EEPROM 640 * @pba_num_size: part number string buffer length 641 * 642 * Reads the part number string from the EEPROM. 643 **/ 644 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 645 u32 pba_num_size) 646 { 647 s32 ret_val; 648 u16 data; 649 u16 pba_ptr; 650 u16 offset; 651 u16 length; 652 653 DEBUGFUNC("ixgbe_read_pba_string_generic"); 654 655 if (pba_num == NULL) { 656 DEBUGOUT("PBA string buffer was null\n"); 657 return IXGBE_ERR_INVALID_ARGUMENT; 658 } 659 660 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 661 if (ret_val) { 662 DEBUGOUT("NVM Read Error\n"); 663 return ret_val; 664 } 665 666 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 667 if (ret_val) { 668 DEBUGOUT("NVM Read Error\n"); 669 return ret_val; 670 } 671 672 /* 673 * if data is not ptr guard the PBA must be in legacy format which 674 * means pba_ptr is actually our second data word for the PBA number 675 * and we can decode it into an ascii string 676 */ 677 if (data != IXGBE_PBANUM_PTR_GUARD) { 678 DEBUGOUT("NVM PBA number is not stored as string\n"); 679 680 /* we will need 11 characters to store the PBA */ 681 if (pba_num_size < 11) { 682 DEBUGOUT("PBA string buffer too small\n"); 683 return IXGBE_ERR_NO_SPACE; 684 } 685 686 /* extract hex string from data and pba_ptr */ 687 pba_num[0] = (data >> 12) & 0xF; 688 pba_num[1] = (data >> 8) & 0xF; 689 pba_num[2] = (data >> 4) & 0xF; 690 pba_num[3] = data & 0xF; 691 pba_num[4] = (pba_ptr >> 12) & 0xF; 692 pba_num[5] = (pba_ptr >> 8) & 0xF; 693 pba_num[6] = '-'; 694 pba_num[7] = 0; 695 pba_num[8] = (pba_ptr >> 4) & 0xF; 696 pba_num[9] = pba_ptr & 0xF; 697 698 /* put a null character on the end of our string */ 699 pba_num[10] = '\0'; 700 701 /* switch all the data but the '-' to hex char */ 702 for (offset = 0; offset < 10; offset++) { 703 if (pba_num[offset] < 0xA) 704 pba_num[offset] += '0'; 705 else if (pba_num[offset] < 0x10) 706 pba_num[offset] += 'A' - 0xA; 707 } 708 709 return IXGBE_SUCCESS; 710 } 711 712 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 713 if (ret_val) { 714 DEBUGOUT("NVM Read Error\n"); 715 return ret_val; 716 } 717 718 if (length == 0xFFFF || length == 0) { 719 DEBUGOUT("NVM PBA number section invalid length\n"); 720 return IXGBE_ERR_PBA_SECTION; 721 } 722 723 /* check if pba_num buffer is big enough */ 724 if (pba_num_size < (((u32)length * 2) - 1)) { 725 DEBUGOUT("PBA string buffer too small\n"); 726 return IXGBE_ERR_NO_SPACE; 727 } 728 729 /* trim pba length from start of string */ 730 pba_ptr++; 731 length--; 732 733 for (offset = 0; offset < length; offset++) { 734 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 735 if (ret_val) { 736 DEBUGOUT("NVM Read Error\n"); 737 return ret_val; 738 } 739 pba_num[offset * 2] = (u8)(data >> 8); 740 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 741 } 742 pba_num[offset * 2] = '\0'; 743 744 return IXGBE_SUCCESS; 745 } 746 747 /** 748 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 749 * @hw: pointer to hardware structure 750 * @pba_num: stores the part number from the EEPROM 751 * 752 * Reads the part number from the EEPROM. 753 **/ 754 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 755 { 756 s32 ret_val; 757 u16 data; 758 759 DEBUGFUNC("ixgbe_read_pba_num_generic"); 760 761 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 762 if (ret_val) { 763 DEBUGOUT("NVM Read Error\n"); 764 return ret_val; 765 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 766 DEBUGOUT("NVM Not supported\n"); 767 return IXGBE_NOT_IMPLEMENTED; 768 } 769 *pba_num = (u32)(data << 16); 770 771 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 772 if (ret_val) { 773 DEBUGOUT("NVM Read Error\n"); 774 return ret_val; 775 } 776 *pba_num |= data; 777 778 return IXGBE_SUCCESS; 779 } 780 781 /** 782 * ixgbe_read_pba_raw 783 * @hw: pointer to the HW structure 784 * @eeprom_buf: optional pointer to EEPROM image 785 * @eeprom_buf_size: size of EEPROM image in words 786 * @max_pba_block_size: PBA block size limit 787 * @pba: pointer to output PBA structure 788 * 789 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 790 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 791 * 792 **/ 793 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 794 u32 eeprom_buf_size, u16 max_pba_block_size, 795 struct ixgbe_pba *pba) 796 { 797 s32 ret_val; 798 u16 pba_block_size; 799 800 if (pba == NULL) 801 return IXGBE_ERR_PARAM; 802 803 if (eeprom_buf == NULL) { 804 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 805 &pba->word[0]); 806 if (ret_val) 807 return ret_val; 808 } else { 809 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 810 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 811 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 812 } else { 813 return IXGBE_ERR_PARAM; 814 } 815 } 816 817 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 818 if (pba->pba_block == NULL) 819 return IXGBE_ERR_PARAM; 820 821 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 822 eeprom_buf_size, 823 &pba_block_size); 824 if (ret_val) 825 return ret_val; 826 827 if (pba_block_size > max_pba_block_size) 828 return IXGBE_ERR_PARAM; 829 830 if (eeprom_buf == NULL) { 831 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 832 pba_block_size, 833 pba->pba_block); 834 if (ret_val) 835 return ret_val; 836 } else { 837 if (eeprom_buf_size > (u32)(pba->word[1] + 838 pba_block_size)) { 839 memcpy(pba->pba_block, 840 &eeprom_buf[pba->word[1]], 841 pba_block_size * sizeof(u16)); 842 } else { 843 return IXGBE_ERR_PARAM; 844 } 845 } 846 } 847 848 return IXGBE_SUCCESS; 849 } 850 851 /** 852 * ixgbe_write_pba_raw 853 * @hw: pointer to the HW structure 854 * @eeprom_buf: optional pointer to EEPROM image 855 * @eeprom_buf_size: size of EEPROM image in words 856 * @pba: pointer to PBA structure 857 * 858 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 859 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 860 * 861 **/ 862 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 863 u32 eeprom_buf_size, struct ixgbe_pba *pba) 864 { 865 s32 ret_val; 866 867 if (pba == NULL) 868 return IXGBE_ERR_PARAM; 869 870 if (eeprom_buf == NULL) { 871 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 872 &pba->word[0]); 873 if (ret_val) 874 return ret_val; 875 } else { 876 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 877 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 878 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 879 } else { 880 return IXGBE_ERR_PARAM; 881 } 882 } 883 884 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 885 if (pba->pba_block == NULL) 886 return IXGBE_ERR_PARAM; 887 888 if (eeprom_buf == NULL) { 889 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 890 pba->pba_block[0], 891 pba->pba_block); 892 if (ret_val) 893 return ret_val; 894 } else { 895 if (eeprom_buf_size > (u32)(pba->word[1] + 896 pba->pba_block[0])) { 897 memcpy(&eeprom_buf[pba->word[1]], 898 pba->pba_block, 899 pba->pba_block[0] * sizeof(u16)); 900 } else { 901 return IXGBE_ERR_PARAM; 902 } 903 } 904 } 905 906 return IXGBE_SUCCESS; 907 } 908 909 /** 910 * ixgbe_get_pba_block_size 911 * @hw: pointer to the HW structure 912 * @eeprom_buf: optional pointer to EEPROM image 913 * @eeprom_buf_size: size of EEPROM image in words 914 * @pba_data_size: pointer to output variable 915 * 916 * Returns the size of the PBA block in words. Function operates on EEPROM 917 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 918 * EEPROM device. 919 * 920 **/ 921 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 922 u32 eeprom_buf_size, u16 *pba_block_size) 923 { 924 s32 ret_val; 925 u16 pba_word[2]; 926 u16 length; 927 928 DEBUGFUNC("ixgbe_get_pba_block_size"); 929 930 if (eeprom_buf == NULL) { 931 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 932 &pba_word[0]); 933 if (ret_val) 934 return ret_val; 935 } else { 936 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 937 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 938 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 939 } else { 940 return IXGBE_ERR_PARAM; 941 } 942 } 943 944 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 945 if (eeprom_buf == NULL) { 946 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 947 &length); 948 if (ret_val) 949 return ret_val; 950 } else { 951 if (eeprom_buf_size > pba_word[1]) 952 length = eeprom_buf[pba_word[1] + 0]; 953 else 954 return IXGBE_ERR_PARAM; 955 } 956 957 if (length == 0xFFFF || length == 0) 958 return IXGBE_ERR_PBA_SECTION; 959 } else { 960 /* PBA number in legacy format, there is no PBA Block. */ 961 length = 0; 962 } 963 964 if (pba_block_size != NULL) 965 *pba_block_size = length; 966 967 return IXGBE_SUCCESS; 968 } 969 970 /** 971 * ixgbe_get_mac_addr_generic - Generic get MAC address 972 * @hw: pointer to hardware structure 973 * @mac_addr: Adapter MAC address 974 * 975 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 976 * A reset of the adapter must be performed prior to calling this function 977 * in order for the MAC address to have been loaded from the EEPROM into RAR0 978 **/ 979 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 980 { 981 u32 rar_high; 982 u32 rar_low; 983 u16 i; 984 985 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 986 987 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 988 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 989 990 for (i = 0; i < 4; i++) 991 mac_addr[i] = (u8)(rar_low >> (i*8)); 992 993 for (i = 0; i < 2; i++) 994 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 995 996 return IXGBE_SUCCESS; 997 } 998 999 /** 1000 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 1001 * @hw: pointer to hardware structure 1002 * @link_status: the link status returned by the PCI config space 1003 * 1004 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1005 **/ 1006 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1007 { 1008 struct ixgbe_mac_info *mac = &hw->mac; 1009 1010 if (hw->bus.type == ixgbe_bus_type_unknown) 1011 hw->bus.type = ixgbe_bus_type_pci_express; 1012 1013 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1014 case IXGBE_PCI_LINK_WIDTH_1: 1015 hw->bus.width = ixgbe_bus_width_pcie_x1; 1016 break; 1017 case IXGBE_PCI_LINK_WIDTH_2: 1018 hw->bus.width = ixgbe_bus_width_pcie_x2; 1019 break; 1020 case IXGBE_PCI_LINK_WIDTH_4: 1021 hw->bus.width = ixgbe_bus_width_pcie_x4; 1022 break; 1023 case IXGBE_PCI_LINK_WIDTH_8: 1024 hw->bus.width = ixgbe_bus_width_pcie_x8; 1025 break; 1026 default: 1027 hw->bus.width = ixgbe_bus_width_unknown; 1028 break; 1029 } 1030 1031 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1032 case IXGBE_PCI_LINK_SPEED_2500: 1033 hw->bus.speed = ixgbe_bus_speed_2500; 1034 break; 1035 case IXGBE_PCI_LINK_SPEED_5000: 1036 hw->bus.speed = ixgbe_bus_speed_5000; 1037 break; 1038 case IXGBE_PCI_LINK_SPEED_8000: 1039 hw->bus.speed = ixgbe_bus_speed_8000; 1040 break; 1041 default: 1042 hw->bus.speed = ixgbe_bus_speed_unknown; 1043 break; 1044 } 1045 1046 mac->ops.set_lan_id(hw); 1047 } 1048 1049 /** 1050 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1051 * @hw: pointer to hardware structure 1052 * 1053 * Gets the PCI bus info (speed, width, type) then calls helper function to 1054 * store this data within the ixgbe_hw structure. 1055 **/ 1056 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1057 { 1058 u16 link_status; 1059 1060 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1061 1062 /* Get the negotiated link width and speed from PCI config space */ 1063 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1064 1065 ixgbe_set_pci_config_data_generic(hw, link_status); 1066 1067 return IXGBE_SUCCESS; 1068 } 1069 1070 /** 1071 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1072 * @hw: pointer to the HW structure 1073 * 1074 * Determines the LAN function id by reading memory-mapped registers and swaps 1075 * the port value if requested, and set MAC instance for devices that share 1076 * CS4227. 1077 **/ 1078 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1079 { 1080 struct ixgbe_bus_info *bus = &hw->bus; 1081 u32 reg; 1082 u16 ee_ctrl_4; 1083 1084 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1085 1086 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1087 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1088 bus->lan_id = (u8)bus->func; 1089 1090 /* check for a port swap */ 1091 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1092 if (reg & IXGBE_FACTPS_LFS) 1093 bus->func ^= 0x1; 1094 1095 /* Get MAC instance from EEPROM for configuring CS4227 */ 1096 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1097 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1098 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1099 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1100 } 1101 } 1102 1103 /** 1104 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1105 * @hw: pointer to hardware structure 1106 * 1107 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1108 * disables transmit and receive units. The adapter_stopped flag is used by 1109 * the shared code and drivers to determine if the adapter is in a stopped 1110 * state and should not touch the hardware. 1111 **/ 1112 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1113 { 1114 u32 reg_val; 1115 u16 i; 1116 1117 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1118 1119 /* 1120 * Set the adapter_stopped flag so other driver functions stop touching 1121 * the hardware 1122 */ 1123 hw->adapter_stopped = TRUE; 1124 1125 /* Disable the receive unit */ 1126 ixgbe_disable_rx(hw); 1127 1128 /* Clear interrupt mask to stop interrupts from being generated */ 1129 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1130 1131 /* Clear any pending interrupts, flush previous writes */ 1132 IXGBE_READ_REG(hw, IXGBE_EICR); 1133 1134 /* Disable the transmit unit. Each queue must be disabled. */ 1135 for (i = 0; i < hw->mac.max_tx_queues; i++) 1136 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1137 1138 /* Disable the receive unit by stopping each queue */ 1139 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1140 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1141 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1142 reg_val |= IXGBE_RXDCTL_SWFLSH; 1143 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1144 } 1145 1146 /* flush all queues disables */ 1147 IXGBE_WRITE_FLUSH(hw); 1148 msec_delay(2); 1149 1150 /* 1151 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1152 * access and verify no pending requests 1153 */ 1154 return ixgbe_disable_pcie_master(hw); 1155 } 1156 1157 /** 1158 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1159 * @hw: pointer to hardware structure 1160 * 1161 * Store the index for the link active LED. This will be used to support 1162 * blinking the LED. 1163 **/ 1164 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1165 { 1166 struct ixgbe_mac_info *mac = &hw->mac; 1167 u32 led_reg, led_mode; 1168 u8 i; 1169 1170 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1171 1172 /* Get LED link active from the LEDCTL register */ 1173 for (i = 0; i < 4; i++) { 1174 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1175 1176 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1177 IXGBE_LED_LINK_ACTIVE) { 1178 mac->led_link_act = i; 1179 return IXGBE_SUCCESS; 1180 } 1181 } 1182 1183 /* 1184 * If LEDCTL register does not have the LED link active set, then use 1185 * known MAC defaults. 1186 */ 1187 switch (hw->mac.type) { 1188 case ixgbe_mac_X550EM_a: 1189 case ixgbe_mac_X550EM_x: 1190 mac->led_link_act = 1; 1191 break; 1192 default: 1193 mac->led_link_act = 2; 1194 } 1195 return IXGBE_SUCCESS; 1196 } 1197 1198 /** 1199 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1200 * @hw: pointer to hardware structure 1201 * @index: led number to turn on 1202 **/ 1203 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1204 { 1205 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1206 1207 DEBUGFUNC("ixgbe_led_on_generic"); 1208 1209 if (index > 3) 1210 return IXGBE_ERR_PARAM; 1211 1212 /* To turn on the LED, set mode to ON. */ 1213 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1214 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1215 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1216 IXGBE_WRITE_FLUSH(hw); 1217 1218 return IXGBE_SUCCESS; 1219 } 1220 1221 /** 1222 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1223 * @hw: pointer to hardware structure 1224 * @index: led number to turn off 1225 **/ 1226 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1227 { 1228 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1229 1230 DEBUGFUNC("ixgbe_led_off_generic"); 1231 1232 if (index > 3) 1233 return IXGBE_ERR_PARAM; 1234 1235 /* To turn off the LED, set mode to OFF. */ 1236 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1237 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1238 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1239 IXGBE_WRITE_FLUSH(hw); 1240 1241 return IXGBE_SUCCESS; 1242 } 1243 1244 /** 1245 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1246 * @hw: pointer to hardware structure 1247 * 1248 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1249 * ixgbe_hw struct in order to set up EEPROM access. 1250 **/ 1251 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1252 { 1253 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1254 u32 eec; 1255 u16 eeprom_size; 1256 1257 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1258 1259 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1260 eeprom->type = ixgbe_eeprom_none; 1261 /* Set default semaphore delay to 10ms which is a well 1262 * tested value */ 1263 eeprom->semaphore_delay = 10; 1264 /* Clear EEPROM page size, it will be initialized as needed */ 1265 eeprom->word_page_size = 0; 1266 1267 /* 1268 * Check for EEPROM present first. 1269 * If not present leave as none 1270 */ 1271 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1272 if (eec & IXGBE_EEC_PRES) { 1273 eeprom->type = ixgbe_eeprom_spi; 1274 1275 /* 1276 * SPI EEPROM is assumed here. This code would need to 1277 * change if a future EEPROM is not SPI. 1278 */ 1279 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1280 IXGBE_EEC_SIZE_SHIFT); 1281 eeprom->word_size = 1 << (eeprom_size + 1282 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1283 } 1284 1285 if (eec & IXGBE_EEC_ADDR_SIZE) 1286 eeprom->address_bits = 16; 1287 else 1288 eeprom->address_bits = 8; 1289 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1290 "%d\n", eeprom->type, eeprom->word_size, 1291 eeprom->address_bits); 1292 } 1293 1294 return IXGBE_SUCCESS; 1295 } 1296 1297 /** 1298 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1299 * @hw: pointer to hardware structure 1300 * @offset: offset within the EEPROM to write 1301 * @words: number of word(s) 1302 * @data: 16 bit word(s) to write to EEPROM 1303 * 1304 * Reads 16 bit word(s) from EEPROM through bit-bang method 1305 **/ 1306 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1307 u16 words, u16 *data) 1308 { 1309 s32 status = IXGBE_SUCCESS; 1310 u16 i, count; 1311 1312 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1313 1314 hw->eeprom.ops.init_params(hw); 1315 1316 if (words == 0) { 1317 status = IXGBE_ERR_INVALID_ARGUMENT; 1318 goto out; 1319 } 1320 1321 if (offset + words > hw->eeprom.word_size) { 1322 status = IXGBE_ERR_EEPROM; 1323 goto out; 1324 } 1325 1326 /* 1327 * The EEPROM page size cannot be queried from the chip. We do lazy 1328 * initialization. It is worth to do that when we write large buffer. 1329 */ 1330 if ((hw->eeprom.word_page_size == 0) && 1331 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1332 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1333 1334 /* 1335 * We cannot hold synchronization semaphores for too long 1336 * to avoid other entity starvation. However it is more efficient 1337 * to read in bursts than synchronizing access for each word. 1338 */ 1339 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1340 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1341 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1342 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1343 count, &data[i]); 1344 1345 if (status != IXGBE_SUCCESS) 1346 break; 1347 } 1348 1349 out: 1350 return status; 1351 } 1352 1353 /** 1354 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1355 * @hw: pointer to hardware structure 1356 * @offset: offset within the EEPROM to be written to 1357 * @words: number of word(s) 1358 * @data: 16 bit word(s) to be written to the EEPROM 1359 * 1360 * If ixgbe_eeprom_update_checksum is not called after this function, the 1361 * EEPROM will most likely contain an invalid checksum. 1362 **/ 1363 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1364 u16 words, u16 *data) 1365 { 1366 s32 status; 1367 u16 word; 1368 u16 page_size; 1369 u16 i; 1370 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1371 1372 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1373 1374 /* Prepare the EEPROM for writing */ 1375 status = ixgbe_acquire_eeprom(hw); 1376 1377 if (status == IXGBE_SUCCESS) { 1378 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1379 ixgbe_release_eeprom(hw); 1380 status = IXGBE_ERR_EEPROM; 1381 } 1382 } 1383 1384 if (status == IXGBE_SUCCESS) { 1385 for (i = 0; i < words; i++) { 1386 ixgbe_standby_eeprom(hw); 1387 1388 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1389 ixgbe_shift_out_eeprom_bits(hw, 1390 IXGBE_EEPROM_WREN_OPCODE_SPI, 1391 IXGBE_EEPROM_OPCODE_BITS); 1392 1393 ixgbe_standby_eeprom(hw); 1394 1395 /* 1396 * Some SPI eeproms use the 8th address bit embedded 1397 * in the opcode 1398 */ 1399 if ((hw->eeprom.address_bits == 8) && 1400 ((offset + i) >= 128)) 1401 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1402 1403 /* Send the Write command (8-bit opcode + addr) */ 1404 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1405 IXGBE_EEPROM_OPCODE_BITS); 1406 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1407 hw->eeprom.address_bits); 1408 1409 page_size = hw->eeprom.word_page_size; 1410 1411 /* Send the data in burst via SPI*/ 1412 do { 1413 word = data[i]; 1414 word = (word >> 8) | (word << 8); 1415 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1416 1417 if (page_size == 0) 1418 break; 1419 1420 /* do not wrap around page */ 1421 if (((offset + i) & (page_size - 1)) == 1422 (page_size - 1)) 1423 break; 1424 } while (++i < words); 1425 1426 ixgbe_standby_eeprom(hw); 1427 msec_delay(10); 1428 } 1429 /* Done with writing - release the EEPROM */ 1430 ixgbe_release_eeprom(hw); 1431 } 1432 1433 return status; 1434 } 1435 1436 /** 1437 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1438 * @hw: pointer to hardware structure 1439 * @offset: offset within the EEPROM to be written to 1440 * @data: 16 bit word to be written to the EEPROM 1441 * 1442 * If ixgbe_eeprom_update_checksum is not called after this function, the 1443 * EEPROM will most likely contain an invalid checksum. 1444 **/ 1445 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1446 { 1447 s32 status; 1448 1449 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1450 1451 hw->eeprom.ops.init_params(hw); 1452 1453 if (offset >= hw->eeprom.word_size) { 1454 status = IXGBE_ERR_EEPROM; 1455 goto out; 1456 } 1457 1458 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1459 1460 out: 1461 return status; 1462 } 1463 1464 /** 1465 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1466 * @hw: pointer to hardware structure 1467 * @offset: offset within the EEPROM to be read 1468 * @data: read 16 bit words(s) from EEPROM 1469 * @words: number of word(s) 1470 * 1471 * Reads 16 bit word(s) from EEPROM through bit-bang method 1472 **/ 1473 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1474 u16 words, u16 *data) 1475 { 1476 s32 status = IXGBE_SUCCESS; 1477 u16 i, count; 1478 1479 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1480 1481 hw->eeprom.ops.init_params(hw); 1482 1483 if (words == 0) { 1484 status = IXGBE_ERR_INVALID_ARGUMENT; 1485 goto out; 1486 } 1487 1488 if (offset + words > hw->eeprom.word_size) { 1489 status = IXGBE_ERR_EEPROM; 1490 goto out; 1491 } 1492 1493 /* 1494 * We cannot hold synchronization semaphores for too long 1495 * to avoid other entity starvation. However it is more efficient 1496 * to read in bursts than synchronizing access for each word. 1497 */ 1498 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1499 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1500 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1501 1502 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1503 count, &data[i]); 1504 1505 if (status != IXGBE_SUCCESS) 1506 break; 1507 } 1508 1509 out: 1510 return status; 1511 } 1512 1513 /** 1514 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1515 * @hw: pointer to hardware structure 1516 * @offset: offset within the EEPROM to be read 1517 * @words: number of word(s) 1518 * @data: read 16 bit word(s) from EEPROM 1519 * 1520 * Reads 16 bit word(s) from EEPROM through bit-bang method 1521 **/ 1522 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1523 u16 words, u16 *data) 1524 { 1525 s32 status; 1526 u16 word_in; 1527 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1528 u16 i; 1529 1530 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1531 1532 /* Prepare the EEPROM for reading */ 1533 status = ixgbe_acquire_eeprom(hw); 1534 1535 if (status == IXGBE_SUCCESS) { 1536 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1537 ixgbe_release_eeprom(hw); 1538 status = IXGBE_ERR_EEPROM; 1539 } 1540 } 1541 1542 if (status == IXGBE_SUCCESS) { 1543 for (i = 0; i < words; i++) { 1544 ixgbe_standby_eeprom(hw); 1545 /* 1546 * Some SPI eeproms use the 8th address bit embedded 1547 * in the opcode 1548 */ 1549 if ((hw->eeprom.address_bits == 8) && 1550 ((offset + i) >= 128)) 1551 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1552 1553 /* Send the READ command (opcode + addr) */ 1554 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1555 IXGBE_EEPROM_OPCODE_BITS); 1556 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1557 hw->eeprom.address_bits); 1558 1559 /* Read the data. */ 1560 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1561 data[i] = (word_in >> 8) | (word_in << 8); 1562 } 1563 1564 /* End this read operation */ 1565 ixgbe_release_eeprom(hw); 1566 } 1567 1568 return status; 1569 } 1570 1571 /** 1572 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1573 * @hw: pointer to hardware structure 1574 * @offset: offset within the EEPROM to be read 1575 * @data: read 16 bit value from EEPROM 1576 * 1577 * Reads 16 bit value from EEPROM through bit-bang method 1578 **/ 1579 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1580 u16 *data) 1581 { 1582 s32 status; 1583 1584 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1585 1586 hw->eeprom.ops.init_params(hw); 1587 1588 if (offset >= hw->eeprom.word_size) { 1589 status = IXGBE_ERR_EEPROM; 1590 goto out; 1591 } 1592 1593 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1594 1595 out: 1596 return status; 1597 } 1598 1599 /** 1600 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1601 * @hw: pointer to hardware structure 1602 * @offset: offset of word in the EEPROM to read 1603 * @words: number of word(s) 1604 * @data: 16 bit word(s) from the EEPROM 1605 * 1606 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1607 **/ 1608 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1609 u16 words, u16 *data) 1610 { 1611 u32 eerd; 1612 s32 status = IXGBE_SUCCESS; 1613 u32 i; 1614 1615 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1616 1617 hw->eeprom.ops.init_params(hw); 1618 1619 if (words == 0) { 1620 status = IXGBE_ERR_INVALID_ARGUMENT; 1621 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1622 goto out; 1623 } 1624 1625 if (offset >= hw->eeprom.word_size) { 1626 status = IXGBE_ERR_EEPROM; 1627 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1628 goto out; 1629 } 1630 1631 for (i = 0; i < words; i++) { 1632 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1633 IXGBE_EEPROM_RW_REG_START; 1634 1635 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1636 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1637 1638 if (status == IXGBE_SUCCESS) { 1639 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1640 IXGBE_EEPROM_RW_REG_DATA); 1641 } else { 1642 DEBUGOUT("Eeprom read timed out\n"); 1643 goto out; 1644 } 1645 } 1646 out: 1647 return status; 1648 } 1649 1650 /** 1651 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1652 * @hw: pointer to hardware structure 1653 * @offset: offset within the EEPROM to be used as a scratch pad 1654 * 1655 * Discover EEPROM page size by writing marching data at given offset. 1656 * This function is called only when we are writing a new large buffer 1657 * at given offset so the data would be overwritten anyway. 1658 **/ 1659 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1660 u16 offset) 1661 { 1662 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1663 s32 status = IXGBE_SUCCESS; 1664 u16 i; 1665 1666 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1667 1668 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1669 data[i] = i; 1670 1671 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1672 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1673 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1674 hw->eeprom.word_page_size = 0; 1675 if (status != IXGBE_SUCCESS) 1676 goto out; 1677 1678 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1679 if (status != IXGBE_SUCCESS) 1680 goto out; 1681 1682 /* 1683 * When writing in burst more than the actual page size 1684 * EEPROM address wraps around current page. 1685 */ 1686 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1687 1688 DEBUGOUT1("Detected EEPROM page size = %d words.", 1689 hw->eeprom.word_page_size); 1690 out: 1691 return status; 1692 } 1693 1694 /** 1695 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1696 * @hw: pointer to hardware structure 1697 * @offset: offset of word in the EEPROM to read 1698 * @data: word read from the EEPROM 1699 * 1700 * Reads a 16 bit word from the EEPROM using the EERD register. 1701 **/ 1702 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1703 { 1704 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1705 } 1706 1707 /** 1708 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1709 * @hw: pointer to hardware structure 1710 * @offset: offset of word in the EEPROM to write 1711 * @words: number of word(s) 1712 * @data: word(s) write to the EEPROM 1713 * 1714 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1715 **/ 1716 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1717 u16 words, u16 *data) 1718 { 1719 u32 eewr; 1720 s32 status = IXGBE_SUCCESS; 1721 u16 i; 1722 1723 DEBUGFUNC("ixgbe_write_eewr_generic"); 1724 1725 hw->eeprom.ops.init_params(hw); 1726 1727 if (words == 0) { 1728 status = IXGBE_ERR_INVALID_ARGUMENT; 1729 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1730 goto out; 1731 } 1732 1733 if (offset >= hw->eeprom.word_size) { 1734 status = IXGBE_ERR_EEPROM; 1735 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1736 goto out; 1737 } 1738 1739 for (i = 0; i < words; i++) { 1740 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1741 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1742 IXGBE_EEPROM_RW_REG_START; 1743 1744 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1745 if (status != IXGBE_SUCCESS) { 1746 DEBUGOUT("Eeprom write EEWR timed out\n"); 1747 goto out; 1748 } 1749 1750 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1751 1752 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1753 if (status != IXGBE_SUCCESS) { 1754 DEBUGOUT("Eeprom write EEWR timed out\n"); 1755 goto out; 1756 } 1757 } 1758 1759 out: 1760 return status; 1761 } 1762 1763 /** 1764 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1765 * @hw: pointer to hardware structure 1766 * @offset: offset of word in the EEPROM to write 1767 * @data: word write to the EEPROM 1768 * 1769 * Write a 16 bit word to the EEPROM using the EEWR register. 1770 **/ 1771 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1772 { 1773 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1774 } 1775 1776 /** 1777 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1778 * @hw: pointer to hardware structure 1779 * @ee_reg: EEPROM flag for polling 1780 * 1781 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1782 * read or write is done respectively. 1783 **/ 1784 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1785 { 1786 u32 i; 1787 u32 reg; 1788 s32 status = IXGBE_ERR_EEPROM; 1789 1790 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1791 1792 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1793 if (ee_reg == IXGBE_NVM_POLL_READ) 1794 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1795 else 1796 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1797 1798 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1799 status = IXGBE_SUCCESS; 1800 break; 1801 } 1802 usec_delay(5); 1803 } 1804 1805 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1806 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1807 "EEPROM read/write done polling timed out"); 1808 1809 return status; 1810 } 1811 1812 /** 1813 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1814 * @hw: pointer to hardware structure 1815 * 1816 * Prepares EEPROM for access using bit-bang method. This function should 1817 * be called before issuing a command to the EEPROM. 1818 **/ 1819 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1820 { 1821 s32 status = IXGBE_SUCCESS; 1822 u32 eec; 1823 u32 i; 1824 1825 DEBUGFUNC("ixgbe_acquire_eeprom"); 1826 1827 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1828 != IXGBE_SUCCESS) 1829 status = IXGBE_ERR_SWFW_SYNC; 1830 1831 if (status == IXGBE_SUCCESS) { 1832 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1833 1834 /* Request EEPROM Access */ 1835 eec |= IXGBE_EEC_REQ; 1836 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1837 1838 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1839 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1840 if (eec & IXGBE_EEC_GNT) 1841 break; 1842 usec_delay(5); 1843 } 1844 1845 /* Release if grant not acquired */ 1846 if (!(eec & IXGBE_EEC_GNT)) { 1847 eec &= ~IXGBE_EEC_REQ; 1848 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1849 DEBUGOUT("Could not acquire EEPROM grant\n"); 1850 1851 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1852 status = IXGBE_ERR_EEPROM; 1853 } 1854 1855 /* Setup EEPROM for Read/Write */ 1856 if (status == IXGBE_SUCCESS) { 1857 /* Clear CS and SK */ 1858 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1859 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1860 IXGBE_WRITE_FLUSH(hw); 1861 usec_delay(1); 1862 } 1863 } 1864 return status; 1865 } 1866 1867 /** 1868 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1869 * @hw: pointer to hardware structure 1870 * 1871 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1872 **/ 1873 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1874 { 1875 s32 status = IXGBE_ERR_EEPROM; 1876 u32 timeout = 2000; 1877 u32 i; 1878 u32 swsm; 1879 1880 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1881 1882 1883 /* Get SMBI software semaphore between device drivers first */ 1884 for (i = 0; i < timeout; i++) { 1885 /* 1886 * If the SMBI bit is 0 when we read it, then the bit will be 1887 * set and we have the semaphore 1888 */ 1889 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1890 if (!(swsm & IXGBE_SWSM_SMBI)) { 1891 status = IXGBE_SUCCESS; 1892 break; 1893 } 1894 usec_delay(50); 1895 } 1896 1897 if (i == timeout) { 1898 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1899 "not granted.\n"); 1900 /* 1901 * this release is particularly important because our attempts 1902 * above to get the semaphore may have succeeded, and if there 1903 * was a timeout, we should unconditionally clear the semaphore 1904 * bits to free the driver to make progress 1905 */ 1906 ixgbe_release_eeprom_semaphore(hw); 1907 1908 usec_delay(50); 1909 /* 1910 * one last try 1911 * If the SMBI bit is 0 when we read it, then the bit will be 1912 * set and we have the semaphore 1913 */ 1914 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1915 if (!(swsm & IXGBE_SWSM_SMBI)) 1916 status = IXGBE_SUCCESS; 1917 } 1918 1919 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1920 if (status == IXGBE_SUCCESS) { 1921 for (i = 0; i < timeout; i++) { 1922 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1923 1924 /* Set the SW EEPROM semaphore bit to request access */ 1925 swsm |= IXGBE_SWSM_SWESMBI; 1926 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1927 1928 /* 1929 * If we set the bit successfully then we got the 1930 * semaphore. 1931 */ 1932 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1933 if (swsm & IXGBE_SWSM_SWESMBI) 1934 break; 1935 1936 usec_delay(50); 1937 } 1938 1939 /* 1940 * Release semaphores and return error if SW EEPROM semaphore 1941 * was not granted because we don't have access to the EEPROM 1942 */ 1943 if (i >= timeout) { 1944 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1945 "SWESMBI Software EEPROM semaphore not granted.\n"); 1946 ixgbe_release_eeprom_semaphore(hw); 1947 status = IXGBE_ERR_EEPROM; 1948 } 1949 } else { 1950 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1951 "Software semaphore SMBI between device drivers " 1952 "not granted.\n"); 1953 } 1954 1955 return status; 1956 } 1957 1958 /** 1959 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1960 * @hw: pointer to hardware structure 1961 * 1962 * This function clears hardware semaphore bits. 1963 **/ 1964 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1965 { 1966 u32 swsm; 1967 1968 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1969 1970 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1971 1972 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1973 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1974 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1975 IXGBE_WRITE_FLUSH(hw); 1976 } 1977 1978 /** 1979 * ixgbe_ready_eeprom - Polls for EEPROM ready 1980 * @hw: pointer to hardware structure 1981 **/ 1982 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1983 { 1984 s32 status = IXGBE_SUCCESS; 1985 u16 i; 1986 u8 spi_stat_reg; 1987 1988 DEBUGFUNC("ixgbe_ready_eeprom"); 1989 1990 /* 1991 * Read "Status Register" repeatedly until the LSB is cleared. The 1992 * EEPROM will signal that the command has been completed by clearing 1993 * bit 0 of the internal status register. If it's not cleared within 1994 * 5 milliseconds, then error out. 1995 */ 1996 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1997 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1998 IXGBE_EEPROM_OPCODE_BITS); 1999 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 2000 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 2001 break; 2002 2003 usec_delay(5); 2004 ixgbe_standby_eeprom(hw); 2005 } 2006 2007 /* 2008 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2009 * devices (and only 0-5mSec on 5V devices) 2010 */ 2011 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2012 DEBUGOUT("SPI EEPROM Status error\n"); 2013 status = IXGBE_ERR_EEPROM; 2014 } 2015 2016 return status; 2017 } 2018 2019 /** 2020 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2021 * @hw: pointer to hardware structure 2022 **/ 2023 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2024 { 2025 u32 eec; 2026 2027 DEBUGFUNC("ixgbe_standby_eeprom"); 2028 2029 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2030 2031 /* Toggle CS to flush commands */ 2032 eec |= IXGBE_EEC_CS; 2033 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2034 IXGBE_WRITE_FLUSH(hw); 2035 usec_delay(1); 2036 eec &= ~IXGBE_EEC_CS; 2037 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2038 IXGBE_WRITE_FLUSH(hw); 2039 usec_delay(1); 2040 } 2041 2042 /** 2043 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2044 * @hw: pointer to hardware structure 2045 * @data: data to send to the EEPROM 2046 * @count: number of bits to shift out 2047 **/ 2048 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2049 u16 count) 2050 { 2051 u32 eec; 2052 u32 mask; 2053 u32 i; 2054 2055 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2056 2057 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2058 2059 /* 2060 * Mask is used to shift "count" bits of "data" out to the EEPROM 2061 * one bit at a time. Determine the starting bit based on count 2062 */ 2063 mask = 0x01 << (count - 1); 2064 2065 for (i = 0; i < count; i++) { 2066 /* 2067 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2068 * "1", and then raising and then lowering the clock (the SK 2069 * bit controls the clock input to the EEPROM). A "0" is 2070 * shifted out to the EEPROM by setting "DI" to "0" and then 2071 * raising and then lowering the clock. 2072 */ 2073 if (data & mask) 2074 eec |= IXGBE_EEC_DI; 2075 else 2076 eec &= ~IXGBE_EEC_DI; 2077 2078 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2079 IXGBE_WRITE_FLUSH(hw); 2080 2081 usec_delay(1); 2082 2083 ixgbe_raise_eeprom_clk(hw, &eec); 2084 ixgbe_lower_eeprom_clk(hw, &eec); 2085 2086 /* 2087 * Shift mask to signify next bit of data to shift in to the 2088 * EEPROM 2089 */ 2090 mask = mask >> 1; 2091 } 2092 2093 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2094 eec &= ~IXGBE_EEC_DI; 2095 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2096 IXGBE_WRITE_FLUSH(hw); 2097 } 2098 2099 /** 2100 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2101 * @hw: pointer to hardware structure 2102 * @count: number of bits to shift 2103 **/ 2104 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2105 { 2106 u32 eec; 2107 u32 i; 2108 u16 data = 0; 2109 2110 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2111 2112 /* 2113 * In order to read a register from the EEPROM, we need to shift 2114 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2115 * the clock input to the EEPROM (setting the SK bit), and then reading 2116 * the value of the "DO" bit. During this "shifting in" process the 2117 * "DI" bit should always be clear. 2118 */ 2119 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2120 2121 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2122 2123 for (i = 0; i < count; i++) { 2124 data = data << 1; 2125 ixgbe_raise_eeprom_clk(hw, &eec); 2126 2127 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2128 2129 eec &= ~(IXGBE_EEC_DI); 2130 if (eec & IXGBE_EEC_DO) 2131 data |= 1; 2132 2133 ixgbe_lower_eeprom_clk(hw, &eec); 2134 } 2135 2136 return data; 2137 } 2138 2139 /** 2140 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2141 * @hw: pointer to hardware structure 2142 * @eec: EEC register's current value 2143 **/ 2144 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2145 { 2146 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2147 2148 /* 2149 * Raise the clock input to the EEPROM 2150 * (setting the SK bit), then delay 2151 */ 2152 *eec = *eec | IXGBE_EEC_SK; 2153 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2154 IXGBE_WRITE_FLUSH(hw); 2155 usec_delay(1); 2156 } 2157 2158 /** 2159 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2160 * @hw: pointer to hardware structure 2161 * @eec: EEC's current value 2162 **/ 2163 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2164 { 2165 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2166 2167 /* 2168 * Lower the clock input to the EEPROM (clearing the SK bit), then 2169 * delay 2170 */ 2171 *eec = *eec & ~IXGBE_EEC_SK; 2172 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2173 IXGBE_WRITE_FLUSH(hw); 2174 usec_delay(1); 2175 } 2176 2177 /** 2178 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2179 * @hw: pointer to hardware structure 2180 **/ 2181 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2182 { 2183 u32 eec; 2184 2185 DEBUGFUNC("ixgbe_release_eeprom"); 2186 2187 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2188 2189 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2190 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2191 2192 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2193 IXGBE_WRITE_FLUSH(hw); 2194 2195 usec_delay(1); 2196 2197 /* Stop requesting EEPROM access */ 2198 eec &= ~IXGBE_EEC_REQ; 2199 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2200 2201 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2202 2203 /* Delay before attempt to obtain semaphore again to allow FW access */ 2204 msec_delay(hw->eeprom.semaphore_delay); 2205 } 2206 2207 /** 2208 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2209 * @hw: pointer to hardware structure 2210 * 2211 * Returns a negative error code on error, or the 16-bit checksum 2212 **/ 2213 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2214 { 2215 u16 i; 2216 u16 j; 2217 u16 checksum = 0; 2218 u16 length = 0; 2219 u16 pointer = 0; 2220 u16 word = 0; 2221 2222 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2223 2224 /* Include 0x0-0x3F in the checksum */ 2225 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2226 if (hw->eeprom.ops.read(hw, i, &word)) { 2227 DEBUGOUT("EEPROM read failed\n"); 2228 return IXGBE_ERR_EEPROM; 2229 } 2230 checksum += word; 2231 } 2232 2233 /* Include all data from pointers except for the fw pointer */ 2234 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2235 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2236 DEBUGOUT("EEPROM read failed\n"); 2237 return IXGBE_ERR_EEPROM; 2238 } 2239 2240 /* If the pointer seems invalid */ 2241 if (pointer == 0xFFFF || pointer == 0) 2242 continue; 2243 2244 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2245 DEBUGOUT("EEPROM read failed\n"); 2246 return IXGBE_ERR_EEPROM; 2247 } 2248 2249 if (length == 0xFFFF || length == 0) 2250 continue; 2251 2252 for (j = pointer + 1; j <= pointer + length; j++) { 2253 if (hw->eeprom.ops.read(hw, j, &word)) { 2254 DEBUGOUT("EEPROM read failed\n"); 2255 return IXGBE_ERR_EEPROM; 2256 } 2257 checksum += word; 2258 } 2259 } 2260 2261 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2262 2263 return (s32)checksum; 2264 } 2265 2266 /** 2267 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2268 * @hw: pointer to hardware structure 2269 * @checksum_val: calculated checksum 2270 * 2271 * Performs checksum calculation and validates the EEPROM checksum. If the 2272 * caller does not need checksum_val, the value can be NULL. 2273 **/ 2274 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2275 u16 *checksum_val) 2276 { 2277 s32 status; 2278 u16 checksum; 2279 u16 read_checksum = 0; 2280 2281 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2282 2283 /* Read the first word from the EEPROM. If this times out or fails, do 2284 * not continue or we could be in for a very long wait while every 2285 * EEPROM read fails 2286 */ 2287 status = hw->eeprom.ops.read(hw, 0, &checksum); 2288 if (status) { 2289 DEBUGOUT("EEPROM read failed\n"); 2290 return status; 2291 } 2292 2293 status = hw->eeprom.ops.calc_checksum(hw); 2294 if (status < 0) 2295 return status; 2296 2297 checksum = (u16)(status & 0xffff); 2298 2299 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2300 if (status) { 2301 DEBUGOUT("EEPROM read failed\n"); 2302 return status; 2303 } 2304 2305 /* Verify read checksum from EEPROM is the same as 2306 * calculated checksum 2307 */ 2308 if (read_checksum != checksum) 2309 status = IXGBE_ERR_EEPROM_CHECKSUM; 2310 2311 /* If the user cares, return the calculated checksum */ 2312 if (checksum_val) 2313 *checksum_val = checksum; 2314 2315 return status; 2316 } 2317 2318 /** 2319 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2320 * @hw: pointer to hardware structure 2321 **/ 2322 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2323 { 2324 s32 status; 2325 u16 checksum; 2326 2327 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2328 2329 /* Read the first word from the EEPROM. If this times out or fails, do 2330 * not continue or we could be in for a very long wait while every 2331 * EEPROM read fails 2332 */ 2333 status = hw->eeprom.ops.read(hw, 0, &checksum); 2334 if (status) { 2335 DEBUGOUT("EEPROM read failed\n"); 2336 return status; 2337 } 2338 2339 status = hw->eeprom.ops.calc_checksum(hw); 2340 if (status < 0) 2341 return status; 2342 2343 checksum = (u16)(status & 0xffff); 2344 2345 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2346 2347 return status; 2348 } 2349 2350 /** 2351 * ixgbe_validate_mac_addr - Validate MAC address 2352 * @mac_addr: pointer to MAC address. 2353 * 2354 * Tests a MAC address to ensure it is a valid Individual Address. 2355 **/ 2356 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2357 { 2358 s32 status = IXGBE_SUCCESS; 2359 2360 DEBUGFUNC("ixgbe_validate_mac_addr"); 2361 2362 /* Make sure it is not a multicast address */ 2363 if (IXGBE_IS_MULTICAST(mac_addr)) { 2364 status = IXGBE_ERR_INVALID_MAC_ADDR; 2365 /* Not a broadcast address */ 2366 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2367 status = IXGBE_ERR_INVALID_MAC_ADDR; 2368 /* Reject the zero address */ 2369 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2370 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2371 status = IXGBE_ERR_INVALID_MAC_ADDR; 2372 } 2373 return status; 2374 } 2375 2376 /** 2377 * ixgbe_set_rar_generic - Set Rx address register 2378 * @hw: pointer to hardware structure 2379 * @index: Receive address register to write 2380 * @addr: Address to put into receive address register 2381 * @vmdq: VMDq "set" or "pool" index 2382 * @enable_addr: set flag that address is active 2383 * 2384 * Puts an ethernet address into a receive address register. 2385 **/ 2386 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2387 u32 enable_addr) 2388 { 2389 u32 rar_low, rar_high; 2390 u32 rar_entries = hw->mac.num_rar_entries; 2391 2392 DEBUGFUNC("ixgbe_set_rar_generic"); 2393 2394 /* Make sure we are using a valid rar index range */ 2395 if (index >= rar_entries) { 2396 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2397 "RAR index %d is out of range.\n", index); 2398 return IXGBE_ERR_INVALID_ARGUMENT; 2399 } 2400 2401 /* setup VMDq pool selection before this RAR gets enabled */ 2402 hw->mac.ops.set_vmdq(hw, index, vmdq); 2403 2404 /* 2405 * HW expects these in little endian so we reverse the byte 2406 * order from network order (big endian) to little endian 2407 */ 2408 rar_low = ((u32)addr[0] | 2409 ((u32)addr[1] << 8) | 2410 ((u32)addr[2] << 16) | 2411 ((u32)addr[3] << 24)); 2412 /* 2413 * Some parts put the VMDq setting in the extra RAH bits, 2414 * so save everything except the lower 16 bits that hold part 2415 * of the address and the address valid bit. 2416 */ 2417 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2418 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2419 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2420 2421 if (enable_addr != 0) 2422 rar_high |= IXGBE_RAH_AV; 2423 2424 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2425 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2426 2427 return IXGBE_SUCCESS; 2428 } 2429 2430 /** 2431 * ixgbe_clear_rar_generic - Remove Rx address register 2432 * @hw: pointer to hardware structure 2433 * @index: Receive address register to write 2434 * 2435 * Clears an ethernet address from a receive address register. 2436 **/ 2437 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2438 { 2439 u32 rar_high; 2440 u32 rar_entries = hw->mac.num_rar_entries; 2441 2442 DEBUGFUNC("ixgbe_clear_rar_generic"); 2443 2444 /* Make sure we are using a valid rar index range */ 2445 if (index >= rar_entries) { 2446 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2447 "RAR index %d is out of range.\n", index); 2448 return IXGBE_ERR_INVALID_ARGUMENT; 2449 } 2450 2451 /* 2452 * Some parts put the VMDq setting in the extra RAH bits, 2453 * so save everything except the lower 16 bits that hold part 2454 * of the address and the address valid bit. 2455 */ 2456 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2457 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2458 2459 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2460 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2461 2462 /* clear VMDq pool/queue selection for this RAR */ 2463 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2464 2465 return IXGBE_SUCCESS; 2466 } 2467 2468 /** 2469 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2470 * @hw: pointer to hardware structure 2471 * 2472 * Places the MAC address in receive address register 0 and clears the rest 2473 * of the receive address registers. Clears the multicast table. Assumes 2474 * the receiver is in reset when the routine is called. 2475 **/ 2476 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2477 { 2478 u32 i; 2479 u32 rar_entries = hw->mac.num_rar_entries; 2480 2481 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2482 2483 /* 2484 * If the current mac address is valid, assume it is a software override 2485 * to the permanent address. 2486 * Otherwise, use the permanent address from the eeprom. 2487 */ 2488 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2489 IXGBE_ERR_INVALID_MAC_ADDR) { 2490 /* Get the MAC address from the RAR0 for later reference */ 2491 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2492 2493 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2494 hw->mac.addr[0], hw->mac.addr[1], 2495 hw->mac.addr[2]); 2496 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2497 hw->mac.addr[4], hw->mac.addr[5]); 2498 } else { 2499 /* Setup the receive address. */ 2500 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2501 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2502 hw->mac.addr[0], hw->mac.addr[1], 2503 hw->mac.addr[2]); 2504 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2505 hw->mac.addr[4], hw->mac.addr[5]); 2506 2507 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2508 } 2509 2510 /* clear VMDq pool/queue selection for RAR 0 */ 2511 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2512 2513 hw->addr_ctrl.overflow_promisc = 0; 2514 2515 hw->addr_ctrl.rar_used_count = 1; 2516 2517 /* Zero out the other receive addresses. */ 2518 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2519 for (i = 1; i < rar_entries; i++) { 2520 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2521 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2522 } 2523 2524 /* Clear the MTA */ 2525 hw->addr_ctrl.mta_in_use = 0; 2526 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2527 2528 DEBUGOUT(" Clearing MTA\n"); 2529 for (i = 0; i < hw->mac.mcft_size; i++) 2530 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2531 2532 ixgbe_init_uta_tables(hw); 2533 2534 return IXGBE_SUCCESS; 2535 } 2536 2537 /** 2538 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2539 * @hw: pointer to hardware structure 2540 * @addr: new address 2541 * @vmdq: VMDq "set" or "pool" index 2542 * 2543 * Adds it to unused receive address register or goes into promiscuous mode. 2544 **/ 2545 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2546 { 2547 u32 rar_entries = hw->mac.num_rar_entries; 2548 u32 rar; 2549 2550 DEBUGFUNC("ixgbe_add_uc_addr"); 2551 2552 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2553 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2554 2555 /* 2556 * Place this address in the RAR if there is room, 2557 * else put the controller into promiscuous mode 2558 */ 2559 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2560 rar = hw->addr_ctrl.rar_used_count; 2561 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2562 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2563 hw->addr_ctrl.rar_used_count++; 2564 } else { 2565 hw->addr_ctrl.overflow_promisc++; 2566 } 2567 2568 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2569 } 2570 2571 /** 2572 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2573 * @hw: pointer to hardware structure 2574 * @addr_list: the list of new addresses 2575 * @addr_count: number of addresses 2576 * @next: iterator function to walk the address list 2577 * 2578 * The given list replaces any existing list. Clears the secondary addrs from 2579 * receive address registers. Uses unused receive address registers for the 2580 * first secondary addresses, and falls back to promiscuous mode as needed. 2581 * 2582 * Drivers using secondary unicast addresses must set user_set_promisc when 2583 * manually putting the device into promiscuous mode. 2584 **/ 2585 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2586 u32 addr_count, ixgbe_mc_addr_itr next) 2587 { 2588 u8 *addr; 2589 u32 i; 2590 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2591 u32 uc_addr_in_use; 2592 u32 fctrl; 2593 u32 vmdq; 2594 2595 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2596 2597 /* 2598 * Clear accounting of old secondary address list, 2599 * don't count RAR[0] 2600 */ 2601 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2602 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2603 hw->addr_ctrl.overflow_promisc = 0; 2604 2605 /* Zero out the other receive addresses */ 2606 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2607 for (i = 0; i < uc_addr_in_use; i++) { 2608 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2609 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2610 } 2611 2612 /* Add the new addresses */ 2613 for (i = 0; i < addr_count; i++) { 2614 DEBUGOUT(" Adding the secondary addresses:\n"); 2615 addr = next(hw, &addr_list, &vmdq); 2616 ixgbe_add_uc_addr(hw, addr, vmdq); 2617 } 2618 2619 if (hw->addr_ctrl.overflow_promisc) { 2620 /* enable promisc if not already in overflow or set by user */ 2621 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2622 DEBUGOUT(" Entering address overflow promisc mode\n"); 2623 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2624 fctrl |= IXGBE_FCTRL_UPE; 2625 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2626 } 2627 } else { 2628 /* only disable if set by overflow, not by user */ 2629 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2630 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2631 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2632 fctrl &= ~IXGBE_FCTRL_UPE; 2633 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2634 } 2635 } 2636 2637 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2638 return IXGBE_SUCCESS; 2639 } 2640 2641 /** 2642 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2643 * @hw: pointer to hardware structure 2644 * @mc_addr: the multicast address 2645 * 2646 * Extracts the 12 bits, from a multicast address, to determine which 2647 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2648 * incoming rx multicast addresses, to determine the bit-vector to check in 2649 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2650 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2651 * to mc_filter_type. 2652 **/ 2653 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2654 { 2655 u32 vector = 0; 2656 2657 DEBUGFUNC("ixgbe_mta_vector"); 2658 2659 switch (hw->mac.mc_filter_type) { 2660 case 0: /* use bits [47:36] of the address */ 2661 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2662 break; 2663 case 1: /* use bits [46:35] of the address */ 2664 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2665 break; 2666 case 2: /* use bits [45:34] of the address */ 2667 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2668 break; 2669 case 3: /* use bits [43:32] of the address */ 2670 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2671 break; 2672 default: /* Invalid mc_filter_type */ 2673 DEBUGOUT("MC filter type param set incorrectly\n"); 2674 ASSERT(0); 2675 break; 2676 } 2677 2678 /* vector can only be 12-bits or boundary will be exceeded */ 2679 vector &= 0xFFF; 2680 return vector; 2681 } 2682 2683 /** 2684 * ixgbe_set_mta - Set bit-vector in multicast table 2685 * @hw: pointer to hardware structure 2686 * @mc_addr: Multicast address 2687 * 2688 * Sets the bit-vector in the multicast table. 2689 **/ 2690 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2691 { 2692 u32 vector; 2693 u32 vector_bit; 2694 u32 vector_reg; 2695 2696 DEBUGFUNC("ixgbe_set_mta"); 2697 2698 hw->addr_ctrl.mta_in_use++; 2699 2700 vector = ixgbe_mta_vector(hw, mc_addr); 2701 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2702 2703 /* 2704 * The MTA is a register array of 128 32-bit registers. It is treated 2705 * like an array of 4096 bits. We want to set bit 2706 * BitArray[vector_value]. So we figure out what register the bit is 2707 * in, read it, OR in the new bit, then write back the new value. The 2708 * register is determined by the upper 7 bits of the vector value and 2709 * the bit within that register are determined by the lower 5 bits of 2710 * the value. 2711 */ 2712 vector_reg = (vector >> 5) & 0x7F; 2713 vector_bit = vector & 0x1F; 2714 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2715 } 2716 2717 /** 2718 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2719 * @hw: pointer to hardware structure 2720 * @mc_addr_list: the list of new multicast addresses 2721 * @mc_addr_count: number of addresses 2722 * @next: iterator function to walk the multicast address list 2723 * @clear: flag, when set clears the table beforehand 2724 * 2725 * When the clear flag is set, the given list replaces any existing list. 2726 * Hashes the given addresses into the multicast table. 2727 **/ 2728 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2729 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2730 bool clear) 2731 { 2732 u32 i; 2733 u32 vmdq; 2734 2735 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2736 2737 /* 2738 * Set the new number of MC addresses that we are being requested to 2739 * use. 2740 */ 2741 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2742 hw->addr_ctrl.mta_in_use = 0; 2743 2744 /* Clear mta_shadow */ 2745 if (clear) { 2746 DEBUGOUT(" Clearing MTA\n"); 2747 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2748 } 2749 2750 /* Update mta_shadow */ 2751 for (i = 0; i < mc_addr_count; i++) { 2752 DEBUGOUT(" Adding the multicast addresses:\n"); 2753 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2754 } 2755 2756 /* Enable mta */ 2757 for (i = 0; i < hw->mac.mcft_size; i++) 2758 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2759 hw->mac.mta_shadow[i]); 2760 2761 if (hw->addr_ctrl.mta_in_use > 0) 2762 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2763 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2764 2765 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2766 return IXGBE_SUCCESS; 2767 } 2768 2769 /** 2770 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2771 * @hw: pointer to hardware structure 2772 * 2773 * Enables multicast address in RAR and the use of the multicast hash table. 2774 **/ 2775 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2776 { 2777 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2778 2779 DEBUGFUNC("ixgbe_enable_mc_generic"); 2780 2781 if (a->mta_in_use > 0) 2782 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2783 hw->mac.mc_filter_type); 2784 2785 return IXGBE_SUCCESS; 2786 } 2787 2788 /** 2789 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2790 * @hw: pointer to hardware structure 2791 * 2792 * Disables multicast address in RAR and the use of the multicast hash table. 2793 **/ 2794 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2795 { 2796 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2797 2798 DEBUGFUNC("ixgbe_disable_mc_generic"); 2799 2800 if (a->mta_in_use > 0) 2801 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2802 2803 return IXGBE_SUCCESS; 2804 } 2805 2806 /** 2807 * ixgbe_fc_enable_generic - Enable flow control 2808 * @hw: pointer to hardware structure 2809 * 2810 * Enable flow control according to the current settings. 2811 **/ 2812 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2813 { 2814 s32 ret_val = IXGBE_SUCCESS; 2815 u32 mflcn_reg, fccfg_reg; 2816 u32 reg; 2817 u32 fcrtl, fcrth; 2818 int i; 2819 2820 DEBUGFUNC("ixgbe_fc_enable_generic"); 2821 2822 /* Validate the water mark configuration */ 2823 if (!hw->fc.pause_time) { 2824 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2825 goto out; 2826 } 2827 2828 /* Low water mark of zero causes XOFF floods */ 2829 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2830 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2831 hw->fc.high_water[i]) { 2832 if (!hw->fc.low_water[i] || 2833 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2834 DEBUGOUT("Invalid water mark configuration\n"); 2835 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2836 goto out; 2837 } 2838 } 2839 } 2840 2841 /* Negotiate the fc mode to use */ 2842 hw->mac.ops.fc_autoneg(hw); 2843 2844 /* Disable any previous flow control settings */ 2845 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2846 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2847 2848 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2849 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2850 2851 /* 2852 * The possible values of fc.current_mode are: 2853 * 0: Flow control is completely disabled 2854 * 1: Rx flow control is enabled (we can receive pause frames, 2855 * but not send pause frames). 2856 * 2: Tx flow control is enabled (we can send pause frames but 2857 * we do not support receiving pause frames). 2858 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2859 * other: Invalid. 2860 */ 2861 switch (hw->fc.current_mode) { 2862 case ixgbe_fc_none: 2863 /* 2864 * Flow control is disabled by software override or autoneg. 2865 * The code below will actually disable it in the HW. 2866 */ 2867 break; 2868 case ixgbe_fc_rx_pause: 2869 /* 2870 * Rx Flow control is enabled and Tx Flow control is 2871 * disabled by software override. Since there really 2872 * isn't a way to advertise that we are capable of RX 2873 * Pause ONLY, we will advertise that we support both 2874 * symmetric and asymmetric Rx PAUSE. Later, we will 2875 * disable the adapter's ability to send PAUSE frames. 2876 */ 2877 mflcn_reg |= IXGBE_MFLCN_RFCE; 2878 break; 2879 case ixgbe_fc_tx_pause: 2880 /* 2881 * Tx Flow control is enabled, and Rx Flow control is 2882 * disabled by software override. 2883 */ 2884 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2885 break; 2886 case ixgbe_fc_full: 2887 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2888 mflcn_reg |= IXGBE_MFLCN_RFCE; 2889 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2890 break; 2891 default: 2892 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2893 "Flow control param set incorrectly\n"); 2894 ret_val = IXGBE_ERR_CONFIG; 2895 goto out; 2896 break; 2897 } 2898 2899 /* Set 802.3x based flow control settings. */ 2900 mflcn_reg |= IXGBE_MFLCN_DPF; 2901 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2902 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2903 2904 2905 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2906 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2907 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2908 hw->fc.high_water[i]) { 2909 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2910 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2911 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2912 } else { 2913 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2914 /* 2915 * In order to prevent Tx hangs when the internal Tx 2916 * switch is enabled we must set the high water mark 2917 * to the Rx packet buffer size - 24KB. This allows 2918 * the Tx switch to function even under heavy Rx 2919 * workloads. 2920 */ 2921 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2922 } 2923 2924 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2925 } 2926 2927 /* Configure pause time (2 TCs per register) */ 2928 reg = hw->fc.pause_time * 0x00010001; 2929 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2930 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2931 2932 /* Configure flow control refresh threshold value */ 2933 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2934 2935 out: 2936 return ret_val; 2937 } 2938 2939 /** 2940 * ixgbe_negotiate_fc - Negotiate flow control 2941 * @hw: pointer to hardware structure 2942 * @adv_reg: flow control advertised settings 2943 * @lp_reg: link partner's flow control settings 2944 * @adv_sym: symmetric pause bit in advertisement 2945 * @adv_asm: asymmetric pause bit in advertisement 2946 * @lp_sym: symmetric pause bit in link partner advertisement 2947 * @lp_asm: asymmetric pause bit in link partner advertisement 2948 * 2949 * Find the intersection between advertised settings and link partner's 2950 * advertised settings 2951 **/ 2952 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2953 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2954 { 2955 if ((!(adv_reg)) || (!(lp_reg))) { 2956 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2957 "Local or link partner's advertised flow control " 2958 "settings are NULL. Local: %x, link partner: %x\n", 2959 adv_reg, lp_reg); 2960 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2961 } 2962 2963 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2964 /* 2965 * Now we need to check if the user selected Rx ONLY 2966 * of pause frames. In this case, we had to advertise 2967 * FULL flow control because we could not advertise RX 2968 * ONLY. Hence, we must now check to see if we need to 2969 * turn OFF the TRANSMISSION of PAUSE frames. 2970 */ 2971 if (hw->fc.requested_mode == ixgbe_fc_full) { 2972 hw->fc.current_mode = ixgbe_fc_full; 2973 DEBUGOUT("Flow Control = FULL.\n"); 2974 } else { 2975 hw->fc.current_mode = ixgbe_fc_rx_pause; 2976 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2977 } 2978 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2979 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2980 hw->fc.current_mode = ixgbe_fc_tx_pause; 2981 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2982 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2983 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2984 hw->fc.current_mode = ixgbe_fc_rx_pause; 2985 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2986 } else { 2987 hw->fc.current_mode = ixgbe_fc_none; 2988 DEBUGOUT("Flow Control = NONE.\n"); 2989 } 2990 return IXGBE_SUCCESS; 2991 } 2992 2993 /** 2994 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2995 * @hw: pointer to hardware structure 2996 * 2997 * Enable flow control according on 1 gig fiber. 2998 **/ 2999 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 3000 { 3001 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 3002 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3003 3004 /* 3005 * On multispeed fiber at 1g, bail out if 3006 * - link is up but AN did not complete, or if 3007 * - link is up and AN completed but timed out 3008 */ 3009 3010 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3011 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3012 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3013 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3014 goto out; 3015 } 3016 3017 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3018 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3019 3020 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3021 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3022 IXGBE_PCS1GANA_ASM_PAUSE, 3023 IXGBE_PCS1GANA_SYM_PAUSE, 3024 IXGBE_PCS1GANA_ASM_PAUSE); 3025 3026 out: 3027 return ret_val; 3028 } 3029 3030 /** 3031 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3032 * @hw: pointer to hardware structure 3033 * 3034 * Enable flow control according to IEEE clause 37. 3035 **/ 3036 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3037 { 3038 u32 links2, anlp1_reg, autoc_reg, links; 3039 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3040 3041 /* 3042 * On backplane, bail out if 3043 * - backplane autoneg was not completed, or if 3044 * - we are 82599 and link partner is not AN enabled 3045 */ 3046 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3047 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3048 DEBUGOUT("Auto-Negotiation did not complete\n"); 3049 goto out; 3050 } 3051 3052 if (hw->mac.type == ixgbe_mac_82599EB) { 3053 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3054 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3055 DEBUGOUT("Link partner is not AN enabled\n"); 3056 goto out; 3057 } 3058 } 3059 /* 3060 * Read the 10g AN autoc and LP ability registers and resolve 3061 * local flow control settings accordingly 3062 */ 3063 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3064 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3065 3066 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3067 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3068 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3069 3070 out: 3071 return ret_val; 3072 } 3073 3074 /** 3075 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3076 * @hw: pointer to hardware structure 3077 * 3078 * Enable flow control according to IEEE clause 37. 3079 **/ 3080 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3081 { 3082 u16 technology_ability_reg = 0; 3083 u16 lp_technology_ability_reg = 0; 3084 3085 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3086 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3087 &technology_ability_reg); 3088 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3089 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3090 &lp_technology_ability_reg); 3091 3092 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3093 (u32)lp_technology_ability_reg, 3094 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3095 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3096 } 3097 3098 /** 3099 * ixgbe_fc_autoneg - Configure flow control 3100 * @hw: pointer to hardware structure 3101 * 3102 * Compares our advertised flow control capabilities to those advertised by 3103 * our link partner, and determines the proper flow control mode to use. 3104 **/ 3105 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3106 { 3107 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3108 ixgbe_link_speed speed; 3109 bool link_up; 3110 3111 DEBUGFUNC("ixgbe_fc_autoneg"); 3112 3113 /* 3114 * AN should have completed when the cable was plugged in. 3115 * Look for reasons to bail out. Bail out if: 3116 * - FC autoneg is disabled, or if 3117 * - link is not up. 3118 */ 3119 if (hw->fc.disable_fc_autoneg) { 3120 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3121 "Flow control autoneg is disabled"); 3122 goto out; 3123 } 3124 3125 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3126 if (!link_up) { 3127 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3128 goto out; 3129 } 3130 3131 switch (hw->phy.media_type) { 3132 /* Autoneg flow control on fiber adapters */ 3133 case ixgbe_media_type_fiber_fixed: 3134 case ixgbe_media_type_fiber_qsfp: 3135 case ixgbe_media_type_fiber: 3136 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3137 ret_val = ixgbe_fc_autoneg_fiber(hw); 3138 break; 3139 3140 /* Autoneg flow control on backplane adapters */ 3141 case ixgbe_media_type_backplane: 3142 ret_val = ixgbe_fc_autoneg_backplane(hw); 3143 break; 3144 3145 /* Autoneg flow control on copper adapters */ 3146 case ixgbe_media_type_copper: 3147 if (ixgbe_device_supports_autoneg_fc(hw)) 3148 ret_val = ixgbe_fc_autoneg_copper(hw); 3149 break; 3150 3151 default: 3152 break; 3153 } 3154 3155 out: 3156 if (ret_val == IXGBE_SUCCESS) { 3157 hw->fc.fc_was_autonegged = TRUE; 3158 } else { 3159 hw->fc.fc_was_autonegged = FALSE; 3160 hw->fc.current_mode = hw->fc.requested_mode; 3161 } 3162 } 3163 3164 /* 3165 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3166 * @hw: pointer to hardware structure 3167 * 3168 * System-wide timeout range is encoded in PCIe Device Control2 register. 3169 * 3170 * Add 10% to specified maximum and return the number of times to poll for 3171 * completion timeout, in units of 100 microsec. Never return less than 3172 * 800 = 80 millisec. 3173 */ 3174 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3175 { 3176 s16 devctl2; 3177 u32 pollcnt; 3178 3179 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3180 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3181 3182 switch (devctl2) { 3183 case IXGBE_PCIDEVCTRL2_65_130ms: 3184 pollcnt = 1300; /* 130 millisec */ 3185 break; 3186 case IXGBE_PCIDEVCTRL2_260_520ms: 3187 pollcnt = 5200; /* 520 millisec */ 3188 break; 3189 case IXGBE_PCIDEVCTRL2_1_2s: 3190 pollcnt = 20000; /* 2 sec */ 3191 break; 3192 case IXGBE_PCIDEVCTRL2_4_8s: 3193 pollcnt = 80000; /* 8 sec */ 3194 break; 3195 case IXGBE_PCIDEVCTRL2_17_34s: 3196 pollcnt = 34000; /* 34 sec */ 3197 break; 3198 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3199 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3200 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3201 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3202 default: 3203 pollcnt = 800; /* 80 millisec minimum */ 3204 break; 3205 } 3206 3207 /* add 10% to spec maximum */ 3208 return (pollcnt * 11) / 10; 3209 } 3210 3211 /** 3212 * ixgbe_disable_pcie_master - Disable PCI-express master access 3213 * @hw: pointer to hardware structure 3214 * 3215 * Disables PCI-Express master access and verifies there are no pending 3216 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3217 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3218 * is returned signifying master requests disabled. 3219 **/ 3220 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3221 { 3222 s32 status = IXGBE_SUCCESS; 3223 u32 i, poll; 3224 u16 value; 3225 3226 DEBUGFUNC("ixgbe_disable_pcie_master"); 3227 3228 /* Always set this bit to ensure any future transactions are blocked */ 3229 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3230 3231 /* Exit if master requests are blocked */ 3232 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3233 IXGBE_REMOVED(hw->hw_addr)) 3234 goto out; 3235 3236 /* Poll for master request bit to clear */ 3237 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3238 usec_delay(100); 3239 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3240 goto out; 3241 } 3242 3243 /* 3244 * Two consecutive resets are required via CTRL.RST per datasheet 3245 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3246 * of this need. The first reset prevents new master requests from 3247 * being issued by our device. We then must wait 1usec or more for any 3248 * remaining completions from the PCIe bus to trickle in, and then reset 3249 * again to clear out any effects they may have had on our device. 3250 */ 3251 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3252 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3253 3254 if (hw->mac.type >= ixgbe_mac_X550) 3255 goto out; 3256 3257 /* 3258 * Before proceeding, make sure that the PCIe block does not have 3259 * transactions pending. 3260 */ 3261 poll = ixgbe_pcie_timeout_poll(hw); 3262 for (i = 0; i < poll; i++) { 3263 usec_delay(100); 3264 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3265 if (IXGBE_REMOVED(hw->hw_addr)) 3266 goto out; 3267 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3268 goto out; 3269 } 3270 3271 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3272 "PCIe transaction pending bit also did not clear.\n"); 3273 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3274 3275 out: 3276 return status; 3277 } 3278 3279 /** 3280 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3281 * @hw: pointer to hardware structure 3282 * @mask: Mask to specify which semaphore to acquire 3283 * 3284 * Acquires the SWFW semaphore through the GSSR register for the specified 3285 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3286 **/ 3287 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3288 { 3289 u32 gssr = 0; 3290 u32 swmask = mask; 3291 u32 fwmask = mask << 5; 3292 u32 timeout = 200; 3293 u32 i; 3294 3295 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3296 3297 for (i = 0; i < timeout; i++) { 3298 /* 3299 * SW NVM semaphore bit is used for access to all 3300 * SW_FW_SYNC bits (not just NVM) 3301 */ 3302 if (ixgbe_get_eeprom_semaphore(hw)) 3303 return IXGBE_ERR_SWFW_SYNC; 3304 3305 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3306 if (!(gssr & (fwmask | swmask))) { 3307 gssr |= swmask; 3308 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3309 ixgbe_release_eeprom_semaphore(hw); 3310 return IXGBE_SUCCESS; 3311 } else { 3312 /* Resource is currently in use by FW or SW */ 3313 ixgbe_release_eeprom_semaphore(hw); 3314 msec_delay(5); 3315 } 3316 } 3317 3318 /* If time expired clear the bits holding the lock and retry */ 3319 if (gssr & (fwmask | swmask)) 3320 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3321 3322 msec_delay(5); 3323 return IXGBE_ERR_SWFW_SYNC; 3324 } 3325 3326 /** 3327 * ixgbe_release_swfw_sync - Release SWFW semaphore 3328 * @hw: pointer to hardware structure 3329 * @mask: Mask to specify which semaphore to release 3330 * 3331 * Releases the SWFW semaphore through the GSSR register for the specified 3332 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3333 **/ 3334 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3335 { 3336 u32 gssr; 3337 u32 swmask = mask; 3338 3339 DEBUGFUNC("ixgbe_release_swfw_sync"); 3340 3341 ixgbe_get_eeprom_semaphore(hw); 3342 3343 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3344 gssr &= ~swmask; 3345 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3346 3347 ixgbe_release_eeprom_semaphore(hw); 3348 } 3349 3350 /** 3351 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3352 * @hw: pointer to hardware structure 3353 * 3354 * Stops the receive data path and waits for the HW to internally empty 3355 * the Rx security block 3356 **/ 3357 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3358 { 3359 #define IXGBE_MAX_SECRX_POLL 40 3360 3361 int i; 3362 int secrxreg; 3363 3364 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3365 3366 3367 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3368 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3369 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3370 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3371 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3372 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3373 break; 3374 else 3375 /* Use interrupt-safe sleep just in case */ 3376 usec_delay(1000); 3377 } 3378 3379 /* For informational purposes only */ 3380 if (i >= IXGBE_MAX_SECRX_POLL) 3381 DEBUGOUT("Rx unit being enabled before security " 3382 "path fully disabled. Continuing with init.\n"); 3383 3384 return IXGBE_SUCCESS; 3385 } 3386 3387 /** 3388 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3389 * @hw: pointer to hardware structure 3390 * @locked: bool to indicate whether the SW/FW lock was taken 3391 * @reg_val: Value we read from AUTOC 3392 * 3393 * The default case requires no protection so just to the register read. 3394 */ 3395 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3396 { 3397 *locked = FALSE; 3398 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3399 return IXGBE_SUCCESS; 3400 } 3401 3402 /** 3403 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3404 * @hw: pointer to hardware structure 3405 * @reg_val: value to write to AUTOC 3406 * @locked: bool to indicate whether the SW/FW lock was already taken by 3407 * previous read. 3408 * 3409 * The default case requires no protection so just to the register write. 3410 */ 3411 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3412 { 3413 UNREFERENCED_1PARAMETER(locked); 3414 3415 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3416 return IXGBE_SUCCESS; 3417 } 3418 3419 /** 3420 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3421 * @hw: pointer to hardware structure 3422 * 3423 * Enables the receive data path. 3424 **/ 3425 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3426 { 3427 u32 secrxreg; 3428 3429 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3430 3431 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3432 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3433 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3434 IXGBE_WRITE_FLUSH(hw); 3435 3436 return IXGBE_SUCCESS; 3437 } 3438 3439 /** 3440 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3441 * @hw: pointer to hardware structure 3442 * @regval: register value to write to RXCTRL 3443 * 3444 * Enables the Rx DMA unit 3445 **/ 3446 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3447 { 3448 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3449 3450 if (regval & IXGBE_RXCTRL_RXEN) 3451 ixgbe_enable_rx(hw); 3452 else 3453 ixgbe_disable_rx(hw); 3454 3455 return IXGBE_SUCCESS; 3456 } 3457 3458 /** 3459 * ixgbe_blink_led_start_generic - Blink LED based on index. 3460 * @hw: pointer to hardware structure 3461 * @index: led number to blink 3462 **/ 3463 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3464 { 3465 ixgbe_link_speed speed = 0; 3466 bool link_up = 0; 3467 u32 autoc_reg = 0; 3468 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3469 s32 ret_val = IXGBE_SUCCESS; 3470 bool locked = FALSE; 3471 3472 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3473 3474 if (index > 3) 3475 return IXGBE_ERR_PARAM; 3476 3477 /* 3478 * Link must be up to auto-blink the LEDs; 3479 * Force it if link is down. 3480 */ 3481 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3482 3483 if (!link_up) { 3484 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3485 if (ret_val != IXGBE_SUCCESS) 3486 goto out; 3487 3488 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3489 autoc_reg |= IXGBE_AUTOC_FLU; 3490 3491 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3492 if (ret_val != IXGBE_SUCCESS) 3493 goto out; 3494 3495 IXGBE_WRITE_FLUSH(hw); 3496 msec_delay(10); 3497 } 3498 3499 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3500 led_reg |= IXGBE_LED_BLINK(index); 3501 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3502 IXGBE_WRITE_FLUSH(hw); 3503 3504 out: 3505 return ret_val; 3506 } 3507 3508 /** 3509 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3510 * @hw: pointer to hardware structure 3511 * @index: led number to stop blinking 3512 **/ 3513 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3514 { 3515 u32 autoc_reg = 0; 3516 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3517 s32 ret_val = IXGBE_SUCCESS; 3518 bool locked = FALSE; 3519 3520 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3521 3522 if (index > 3) 3523 return IXGBE_ERR_PARAM; 3524 3525 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3526 if (ret_val != IXGBE_SUCCESS) 3527 goto out; 3528 3529 autoc_reg &= ~IXGBE_AUTOC_FLU; 3530 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3531 3532 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3533 if (ret_val != IXGBE_SUCCESS) 3534 goto out; 3535 3536 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3537 led_reg &= ~IXGBE_LED_BLINK(index); 3538 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3539 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3540 IXGBE_WRITE_FLUSH(hw); 3541 3542 out: 3543 return ret_val; 3544 } 3545 3546 /** 3547 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3548 * @hw: pointer to hardware structure 3549 * @san_mac_offset: SAN MAC address offset 3550 * 3551 * This function will read the EEPROM location for the SAN MAC address 3552 * pointer, and returns the value at that location. This is used in both 3553 * get and set mac_addr routines. 3554 **/ 3555 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3556 u16 *san_mac_offset) 3557 { 3558 s32 ret_val; 3559 3560 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3561 3562 /* 3563 * First read the EEPROM pointer to see if the MAC addresses are 3564 * available. 3565 */ 3566 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3567 san_mac_offset); 3568 if (ret_val) { 3569 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3570 "eeprom at offset %d failed", 3571 IXGBE_SAN_MAC_ADDR_PTR); 3572 } 3573 3574 return ret_val; 3575 } 3576 3577 /** 3578 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3579 * @hw: pointer to hardware structure 3580 * @san_mac_addr: SAN MAC address 3581 * 3582 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3583 * per-port, so set_lan_id() must be called before reading the addresses. 3584 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3585 * upon for non-SFP connections, so we must call it here. 3586 **/ 3587 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3588 { 3589 u16 san_mac_data, san_mac_offset; 3590 u8 i; 3591 s32 ret_val; 3592 3593 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3594 3595 /* 3596 * First read the EEPROM pointer to see if the MAC addresses are 3597 * available. If they're not, no point in calling set_lan_id() here. 3598 */ 3599 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3600 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3601 goto san_mac_addr_out; 3602 3603 /* make sure we know which port we need to program */ 3604 hw->mac.ops.set_lan_id(hw); 3605 /* apply the port offset to the address offset */ 3606 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3607 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3608 for (i = 0; i < 3; i++) { 3609 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3610 &san_mac_data); 3611 if (ret_val) { 3612 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3613 "eeprom read at offset %d failed", 3614 san_mac_offset); 3615 goto san_mac_addr_out; 3616 } 3617 san_mac_addr[i * 2] = (u8)(san_mac_data); 3618 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3619 san_mac_offset++; 3620 } 3621 return IXGBE_SUCCESS; 3622 3623 san_mac_addr_out: 3624 /* 3625 * No addresses available in this EEPROM. It's not an 3626 * error though, so just wipe the local address and return. 3627 */ 3628 for (i = 0; i < 6; i++) 3629 san_mac_addr[i] = 0xFF; 3630 return IXGBE_SUCCESS; 3631 } 3632 3633 /** 3634 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3635 * @hw: pointer to hardware structure 3636 * @san_mac_addr: SAN MAC address 3637 * 3638 * Write a SAN MAC address to the EEPROM. 3639 **/ 3640 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3641 { 3642 s32 ret_val; 3643 u16 san_mac_data, san_mac_offset; 3644 u8 i; 3645 3646 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3647 3648 /* Look for SAN mac address pointer. If not defined, return */ 3649 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3650 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3651 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3652 3653 /* Make sure we know which port we need to write */ 3654 hw->mac.ops.set_lan_id(hw); 3655 /* Apply the port offset to the address offset */ 3656 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3657 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3658 3659 for (i = 0; i < 3; i++) { 3660 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3661 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3662 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3663 san_mac_offset++; 3664 } 3665 3666 return IXGBE_SUCCESS; 3667 } 3668 3669 /** 3670 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3671 * @hw: pointer to hardware structure 3672 * 3673 * Read PCIe configuration space, and get the MSI-X vector count from 3674 * the capabilities table. 3675 **/ 3676 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3677 { 3678 u16 msix_count = 1; 3679 u16 max_msix_count; 3680 u16 pcie_offset; 3681 3682 switch (hw->mac.type) { 3683 case ixgbe_mac_82598EB: 3684 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3685 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3686 break; 3687 case ixgbe_mac_82599EB: 3688 case ixgbe_mac_X540: 3689 case ixgbe_mac_X550: 3690 case ixgbe_mac_X550EM_x: 3691 case ixgbe_mac_X550EM_a: 3692 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3693 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3694 break; 3695 default: 3696 return msix_count; 3697 } 3698 3699 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3700 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3701 if (IXGBE_REMOVED(hw->hw_addr)) 3702 msix_count = 0; 3703 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3704 3705 /* MSI-X count is zero-based in HW */ 3706 msix_count++; 3707 3708 if (msix_count > max_msix_count) 3709 msix_count = max_msix_count; 3710 3711 return msix_count; 3712 } 3713 3714 /** 3715 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3716 * @hw: pointer to hardware structure 3717 * @addr: Address to put into receive address register 3718 * @vmdq: VMDq pool to assign 3719 * 3720 * Puts an ethernet address into a receive address register, or 3721 * finds the rar that it is already in; adds to the pool list 3722 **/ 3723 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3724 { 3725 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3726 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3727 u32 rar; 3728 u32 rar_low, rar_high; 3729 u32 addr_low, addr_high; 3730 3731 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3732 3733 /* swap bytes for HW little endian */ 3734 addr_low = addr[0] | (addr[1] << 8) 3735 | (addr[2] << 16) 3736 | (addr[3] << 24); 3737 addr_high = addr[4] | (addr[5] << 8); 3738 3739 /* 3740 * Either find the mac_id in rar or find the first empty space. 3741 * rar_highwater points to just after the highest currently used 3742 * rar in order to shorten the search. It grows when we add a new 3743 * rar to the top. 3744 */ 3745 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3746 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3747 3748 if (((IXGBE_RAH_AV & rar_high) == 0) 3749 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3750 first_empty_rar = rar; 3751 } else if ((rar_high & 0xFFFF) == addr_high) { 3752 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3753 if (rar_low == addr_low) 3754 break; /* found it already in the rars */ 3755 } 3756 } 3757 3758 if (rar < hw->mac.rar_highwater) { 3759 /* already there so just add to the pool bits */ 3760 ixgbe_set_vmdq(hw, rar, vmdq); 3761 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3762 /* stick it into first empty RAR slot we found */ 3763 rar = first_empty_rar; 3764 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3765 } else if (rar == hw->mac.rar_highwater) { 3766 /* add it to the top of the list and inc the highwater mark */ 3767 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3768 hw->mac.rar_highwater++; 3769 } else if (rar >= hw->mac.num_rar_entries) { 3770 return IXGBE_ERR_INVALID_MAC_ADDR; 3771 } 3772 3773 /* 3774 * If we found rar[0], make sure the default pool bit (we use pool 0) 3775 * remains cleared to be sure default pool packets will get delivered 3776 */ 3777 if (rar == 0) 3778 ixgbe_clear_vmdq(hw, rar, 0); 3779 3780 return rar; 3781 } 3782 3783 /** 3784 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3785 * @hw: pointer to hardware struct 3786 * @rar: receive address register index to disassociate 3787 * @vmdq: VMDq pool index to remove from the rar 3788 **/ 3789 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3790 { 3791 u32 mpsar_lo, mpsar_hi; 3792 u32 rar_entries = hw->mac.num_rar_entries; 3793 3794 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3795 3796 /* Make sure we are using a valid rar index range */ 3797 if (rar >= rar_entries) { 3798 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3799 "RAR index %d is out of range.\n", rar); 3800 return IXGBE_ERR_INVALID_ARGUMENT; 3801 } 3802 3803 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3804 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3805 3806 if (IXGBE_REMOVED(hw->hw_addr)) 3807 goto done; 3808 3809 if (!mpsar_lo && !mpsar_hi) 3810 goto done; 3811 3812 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3813 if (mpsar_lo) { 3814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3815 mpsar_lo = 0; 3816 } 3817 if (mpsar_hi) { 3818 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3819 mpsar_hi = 0; 3820 } 3821 } else if (vmdq < 32) { 3822 mpsar_lo &= ~(1 << vmdq); 3823 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3824 } else { 3825 mpsar_hi &= ~(1 << (vmdq - 32)); 3826 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3827 } 3828 3829 /* was that the last pool using this rar? */ 3830 if (mpsar_lo == 0 && mpsar_hi == 0 && 3831 rar != 0 && rar != hw->mac.san_mac_rar_index) 3832 hw->mac.ops.clear_rar(hw, rar); 3833 done: 3834 return IXGBE_SUCCESS; 3835 } 3836 3837 /** 3838 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3839 * @hw: pointer to hardware struct 3840 * @rar: receive address register index to associate with a VMDq index 3841 * @vmdq: VMDq pool index 3842 **/ 3843 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3844 { 3845 u32 mpsar; 3846 u32 rar_entries = hw->mac.num_rar_entries; 3847 3848 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3849 3850 /* Make sure we are using a valid rar index range */ 3851 if (rar >= rar_entries) { 3852 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3853 "RAR index %d is out of range.\n", rar); 3854 return IXGBE_ERR_INVALID_ARGUMENT; 3855 } 3856 3857 if (vmdq < 32) { 3858 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3859 mpsar |= 1 << vmdq; 3860 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3861 } else { 3862 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3863 mpsar |= 1 << (vmdq - 32); 3864 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3865 } 3866 return IXGBE_SUCCESS; 3867 } 3868 3869 /** 3870 * This function should only be involved in the IOV mode. 3871 * In IOV mode, Default pool is next pool after the number of 3872 * VFs advertized and not 0. 3873 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3874 * 3875 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3876 * @hw: pointer to hardware struct 3877 * @vmdq: VMDq pool index 3878 **/ 3879 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3880 { 3881 u32 rar = hw->mac.san_mac_rar_index; 3882 3883 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3884 3885 if (vmdq < 32) { 3886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3888 } else { 3889 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3890 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3891 } 3892 3893 return IXGBE_SUCCESS; 3894 } 3895 3896 /** 3897 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3898 * @hw: pointer to hardware structure 3899 **/ 3900 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3901 { 3902 int i; 3903 3904 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3905 DEBUGOUT(" Clearing UTA\n"); 3906 3907 for (i = 0; i < 128; i++) 3908 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3909 3910 return IXGBE_SUCCESS; 3911 } 3912 3913 /** 3914 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3915 * @hw: pointer to hardware structure 3916 * @vlan: VLAN id to write to VLAN filter 3917 * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if 3918 * vlanid not found 3919 * 3920 * 3921 * return the VLVF index where this VLAN id should be placed 3922 * 3923 **/ 3924 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3925 { 3926 s32 regindex, first_empty_slot; 3927 u32 bits; 3928 3929 /* short cut the special case */ 3930 if (vlan == 0) 3931 return 0; 3932 3933 /* if vlvf_bypass is set we don't want to use an empty slot, we 3934 * will simply bypass the VLVF if there are no entries present in the 3935 * VLVF that contain our VLAN 3936 */ 3937 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3938 3939 /* add VLAN enable bit for comparison */ 3940 vlan |= IXGBE_VLVF_VIEN; 3941 3942 /* Search for the vlan id in the VLVF entries. Save off the first empty 3943 * slot found along the way. 3944 * 3945 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3946 */ 3947 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3948 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3949 if (bits == vlan) 3950 return regindex; 3951 if (!first_empty_slot && !bits) 3952 first_empty_slot = regindex; 3953 } 3954 3955 /* If we are here then we didn't find the VLAN. Return first empty 3956 * slot we found during our search, else error. 3957 */ 3958 if (!first_empty_slot) 3959 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3960 3961 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3962 } 3963 3964 /** 3965 * ixgbe_set_vfta_generic - Set VLAN filter table 3966 * @hw: pointer to hardware structure 3967 * @vlan: VLAN id to write to VLAN filter 3968 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3969 * @vlan_on: boolean flag to turn on/off VLAN 3970 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3971 * 3972 * Turn on/off specified VLAN in the VLAN filter table. 3973 **/ 3974 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3975 bool vlan_on, bool vlvf_bypass) 3976 { 3977 u32 regidx, vfta_delta, vfta; 3978 s32 ret_val; 3979 3980 DEBUGFUNC("ixgbe_set_vfta_generic"); 3981 3982 if (vlan > 4095 || vind > 63) 3983 return IXGBE_ERR_PARAM; 3984 3985 /* 3986 * this is a 2 part operation - first the VFTA, then the 3987 * VLVF and VLVFB if VT Mode is set 3988 * We don't write the VFTA until we know the VLVF part succeeded. 3989 */ 3990 3991 /* Part 1 3992 * The VFTA is a bitstring made up of 128 32-bit registers 3993 * that enable the particular VLAN id, much like the MTA: 3994 * bits[11-5]: which register 3995 * bits[4-0]: which bit in the register 3996 */ 3997 regidx = vlan / 32; 3998 vfta_delta = 1 << (vlan % 32); 3999 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 4000 4001 /* 4002 * vfta_delta represents the difference between the current value 4003 * of vfta and the value we want in the register. Since the diff 4004 * is an XOR mask we can just update the vfta using an XOR 4005 */ 4006 vfta_delta &= vlan_on ? ~vfta : vfta; 4007 vfta ^= vfta_delta; 4008 4009 /* Part 2 4010 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4011 */ 4012 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4013 vfta, vlvf_bypass); 4014 if (ret_val != IXGBE_SUCCESS) { 4015 if (vlvf_bypass) 4016 goto vfta_update; 4017 return ret_val; 4018 } 4019 4020 vfta_update: 4021 /* Update VFTA now that we are ready for traffic */ 4022 if (vfta_delta) 4023 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4024 4025 return IXGBE_SUCCESS; 4026 } 4027 4028 /** 4029 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4030 * @hw: pointer to hardware structure 4031 * @vlan: VLAN id to write to VLAN filter 4032 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4033 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4034 * @vfta_delta: pointer to the difference between the current value of VFTA 4035 * and the desired value 4036 * @vfta: the desired value of the VFTA 4037 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4038 * 4039 * Turn on/off specified bit in VLVF table. 4040 **/ 4041 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4042 bool vlan_on, u32 *vfta_delta, u32 vfta, 4043 bool vlvf_bypass) 4044 { 4045 u32 bits; 4046 s32 vlvf_index; 4047 4048 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4049 4050 if (vlan > 4095 || vind > 63) 4051 return IXGBE_ERR_PARAM; 4052 4053 /* If VT Mode is set 4054 * Either vlan_on 4055 * make sure the vlan is in VLVF 4056 * set the vind bit in the matching VLVFB 4057 * Or !vlan_on 4058 * clear the pool bit and possibly the vind 4059 */ 4060 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4061 return IXGBE_SUCCESS; 4062 4063 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4064 if (vlvf_index < 0) 4065 return vlvf_index; 4066 4067 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4068 4069 /* set the pool bit */ 4070 bits |= 1 << (vind % 32); 4071 if (vlan_on) 4072 goto vlvf_update; 4073 4074 /* clear the pool bit */ 4075 bits ^= 1 << (vind % 32); 4076 4077 if (!bits && 4078 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4079 /* Clear VFTA first, then disable VLVF. Otherwise 4080 * we run the risk of stray packets leaking into 4081 * the PF via the default pool 4082 */ 4083 if (*vfta_delta) 4084 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4085 4086 /* disable VLVF and clear remaining bit from pool */ 4087 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4088 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4089 4090 return IXGBE_SUCCESS; 4091 } 4092 4093 /* If there are still bits set in the VLVFB registers 4094 * for the VLAN ID indicated we need to see if the 4095 * caller is requesting that we clear the VFTA entry bit. 4096 * If the caller has requested that we clear the VFTA 4097 * entry bit but there are still pools/VFs using this VLAN 4098 * ID entry then ignore the request. We're not worried 4099 * about the case where we're turning the VFTA VLAN ID 4100 * entry bit on, only when requested to turn it off as 4101 * there may be multiple pools and/or VFs using the 4102 * VLAN ID entry. In that case we cannot clear the 4103 * VFTA bit until all pools/VFs using that VLAN ID have also 4104 * been cleared. This will be indicated by "bits" being 4105 * zero. 4106 */ 4107 *vfta_delta = 0; 4108 4109 vlvf_update: 4110 /* record pool change and enable VLAN ID if not already enabled */ 4111 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4112 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4113 4114 return IXGBE_SUCCESS; 4115 } 4116 4117 /** 4118 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4119 * @hw: pointer to hardware structure 4120 * 4121 * Clears the VLAN filer table, and the VMDq index associated with the filter 4122 **/ 4123 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4124 { 4125 u32 offset; 4126 4127 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4128 4129 for (offset = 0; offset < hw->mac.vft_size; offset++) 4130 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4131 4132 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4133 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4134 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 4136 } 4137 4138 return IXGBE_SUCCESS; 4139 } 4140 4141 /** 4142 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4143 * @hw: pointer to hardware structure 4144 * 4145 * Contains the logic to identify if we need to verify link for the 4146 * crosstalk fix 4147 **/ 4148 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4149 { 4150 4151 /* Does FW say we need the fix */ 4152 if (!hw->need_crosstalk_fix) 4153 return FALSE; 4154 4155 /* Only consider SFP+ PHYs i.e. media type fiber */ 4156 switch (hw->mac.ops.get_media_type(hw)) { 4157 case ixgbe_media_type_fiber: 4158 case ixgbe_media_type_fiber_qsfp: 4159 break; 4160 default: 4161 return FALSE; 4162 } 4163 4164 return TRUE; 4165 } 4166 4167 /** 4168 * ixgbe_check_mac_link_generic - Determine link and speed status 4169 * @hw: pointer to hardware structure 4170 * @speed: pointer to link speed 4171 * @link_up: TRUE when link is up 4172 * @link_up_wait_to_complete: bool used to wait for link up or not 4173 * 4174 * Reads the links register to determine if link is up and the current speed 4175 **/ 4176 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4177 bool *link_up, bool link_up_wait_to_complete) 4178 { 4179 u32 links_reg, links_orig; 4180 u32 i; 4181 4182 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4183 4184 /* If Crosstalk fix enabled do the sanity check of making sure 4185 * the SFP+ cage is full. 4186 */ 4187 if (ixgbe_need_crosstalk_fix(hw)) { 4188 u32 sfp_cage_full; 4189 4190 switch (hw->mac.type) { 4191 case ixgbe_mac_82599EB: 4192 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4193 IXGBE_ESDP_SDP2; 4194 break; 4195 case ixgbe_mac_X550EM_x: 4196 case ixgbe_mac_X550EM_a: 4197 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4198 IXGBE_ESDP_SDP0; 4199 break; 4200 default: 4201 /* sanity check - No SFP+ devices here */ 4202 sfp_cage_full = FALSE; 4203 break; 4204 } 4205 4206 if (!sfp_cage_full) { 4207 *link_up = FALSE; 4208 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4209 return IXGBE_SUCCESS; 4210 } 4211 } 4212 4213 /* clear the old state */ 4214 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4215 4216 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4217 4218 if (links_orig != links_reg) { 4219 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4220 links_orig, links_reg); 4221 } 4222 4223 if (link_up_wait_to_complete) { 4224 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4225 if (links_reg & IXGBE_LINKS_UP) { 4226 *link_up = TRUE; 4227 break; 4228 } else { 4229 *link_up = FALSE; 4230 } 4231 msec_delay(100); 4232 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4233 } 4234 } else { 4235 if (links_reg & IXGBE_LINKS_UP) 4236 *link_up = TRUE; 4237 else 4238 *link_up = FALSE; 4239 } 4240 4241 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4242 case IXGBE_LINKS_SPEED_10G_82599: 4243 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4244 if (hw->mac.type >= ixgbe_mac_X550) { 4245 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4246 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4247 } 4248 break; 4249 case IXGBE_LINKS_SPEED_1G_82599: 4250 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4251 break; 4252 case IXGBE_LINKS_SPEED_100_82599: 4253 *speed = IXGBE_LINK_SPEED_100_FULL; 4254 if (hw->mac.type == ixgbe_mac_X550) { 4255 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4256 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4257 } 4258 break; 4259 case IXGBE_LINKS_SPEED_10_X550EM_A: 4260 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4261 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4262 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4263 *speed = IXGBE_LINK_SPEED_10_FULL; 4264 break; 4265 default: 4266 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4267 } 4268 4269 return IXGBE_SUCCESS; 4270 } 4271 4272 /** 4273 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4274 * the EEPROM 4275 * @hw: pointer to hardware structure 4276 * @wwnn_prefix: the alternative WWNN prefix 4277 * @wwpn_prefix: the alternative WWPN prefix 4278 * 4279 * This function will read the EEPROM from the alternative SAN MAC address 4280 * block to check the support for the alternative WWNN/WWPN prefix support. 4281 **/ 4282 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4283 u16 *wwpn_prefix) 4284 { 4285 u16 offset, caps; 4286 u16 alt_san_mac_blk_offset; 4287 4288 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4289 4290 /* clear output first */ 4291 *wwnn_prefix = 0xFFFF; 4292 *wwpn_prefix = 0xFFFF; 4293 4294 /* check if alternative SAN MAC is supported */ 4295 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4296 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4297 goto wwn_prefix_err; 4298 4299 if ((alt_san_mac_blk_offset == 0) || 4300 (alt_san_mac_blk_offset == 0xFFFF)) 4301 goto wwn_prefix_out; 4302 4303 /* check capability in alternative san mac address block */ 4304 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4305 if (hw->eeprom.ops.read(hw, offset, &caps)) 4306 goto wwn_prefix_err; 4307 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4308 goto wwn_prefix_out; 4309 4310 /* get the corresponding prefix for WWNN/WWPN */ 4311 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4312 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4313 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4314 "eeprom read at offset %d failed", offset); 4315 } 4316 4317 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4318 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4319 goto wwn_prefix_err; 4320 4321 wwn_prefix_out: 4322 return IXGBE_SUCCESS; 4323 4324 wwn_prefix_err: 4325 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4326 "eeprom read at offset %d failed", offset); 4327 return IXGBE_SUCCESS; 4328 } 4329 4330 /** 4331 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4332 * @hw: pointer to hardware structure 4333 * @bs: the fcoe boot status 4334 * 4335 * This function will read the FCOE boot status from the iSCSI FCOE block 4336 **/ 4337 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4338 { 4339 u16 offset, caps, flags; 4340 s32 status; 4341 4342 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4343 4344 /* clear output first */ 4345 *bs = ixgbe_fcoe_bootstatus_unavailable; 4346 4347 /* check if FCOE IBA block is present */ 4348 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4349 status = hw->eeprom.ops.read(hw, offset, &caps); 4350 if (status != IXGBE_SUCCESS) 4351 goto out; 4352 4353 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4354 goto out; 4355 4356 /* check if iSCSI FCOE block is populated */ 4357 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4358 if (status != IXGBE_SUCCESS) 4359 goto out; 4360 4361 if ((offset == 0) || (offset == 0xFFFF)) 4362 goto out; 4363 4364 /* read fcoe flags in iSCSI FCOE block */ 4365 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4366 status = hw->eeprom.ops.read(hw, offset, &flags); 4367 if (status != IXGBE_SUCCESS) 4368 goto out; 4369 4370 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4371 *bs = ixgbe_fcoe_bootstatus_enabled; 4372 else 4373 *bs = ixgbe_fcoe_bootstatus_disabled; 4374 4375 out: 4376 return status; 4377 } 4378 4379 /** 4380 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4381 * @hw: pointer to hardware structure 4382 * @enable: enable or disable switch for MAC anti-spoofing 4383 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4384 * 4385 **/ 4386 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4387 { 4388 int vf_target_reg = vf >> 3; 4389 int vf_target_shift = vf % 8; 4390 u32 pfvfspoof; 4391 4392 if (hw->mac.type == ixgbe_mac_82598EB) 4393 return; 4394 4395 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4396 if (enable) 4397 pfvfspoof |= (1 << vf_target_shift); 4398 else 4399 pfvfspoof &= ~(1 << vf_target_shift); 4400 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4401 } 4402 4403 /** 4404 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4405 * @hw: pointer to hardware structure 4406 * @enable: enable or disable switch for VLAN anti-spoofing 4407 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4408 * 4409 **/ 4410 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4411 { 4412 int vf_target_reg = vf >> 3; 4413 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4414 u32 pfvfspoof; 4415 4416 if (hw->mac.type == ixgbe_mac_82598EB) 4417 return; 4418 4419 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4420 if (enable) 4421 pfvfspoof |= (1 << vf_target_shift); 4422 else 4423 pfvfspoof &= ~(1 << vf_target_shift); 4424 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4425 } 4426 4427 /** 4428 * ixgbe_get_device_caps_generic - Get additional device capabilities 4429 * @hw: pointer to hardware structure 4430 * @device_caps: the EEPROM word with the extra device capabilities 4431 * 4432 * This function will read the EEPROM location for the device capabilities, 4433 * and return the word through device_caps. 4434 **/ 4435 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4436 { 4437 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4438 4439 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4440 4441 return IXGBE_SUCCESS; 4442 } 4443 4444 /** 4445 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4446 * @hw: pointer to hardware structure 4447 * 4448 **/ 4449 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4450 { 4451 u32 regval; 4452 u32 i; 4453 4454 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4455 4456 /* Enable relaxed ordering */ 4457 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4458 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4459 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4460 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4461 } 4462 4463 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4464 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4465 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4466 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4467 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4468 } 4469 4470 } 4471 4472 /** 4473 * ixgbe_calculate_checksum - Calculate checksum for buffer 4474 * @buffer: pointer to EEPROM 4475 * @length: size of EEPROM to calculate a checksum for 4476 * Calculates the checksum for some buffer on a specified length. The 4477 * checksum calculated is returned. 4478 **/ 4479 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4480 { 4481 u32 i; 4482 u8 sum = 0; 4483 4484 DEBUGFUNC("ixgbe_calculate_checksum"); 4485 4486 if (!buffer) 4487 return 0; 4488 4489 for (i = 0; i < length; i++) 4490 sum += buffer[i]; 4491 4492 return (u8) (0 - sum); 4493 } 4494 4495 /** 4496 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4497 * @hw: pointer to the HW structure 4498 * @buffer: command to write and where the return status will be placed 4499 * @length: length of buffer, must be multiple of 4 bytes 4500 * @timeout: time in ms to wait for command completion 4501 * 4502 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4503 * else returns semaphore error when encountering an error acquiring 4504 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4505 * 4506 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4507 * by the caller. 4508 **/ 4509 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4510 u32 timeout) 4511 { 4512 u32 hicr, i, fwsts; 4513 u16 dword_len; 4514 4515 DEBUGFUNC("ixgbe_hic_unlocked"); 4516 4517 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4518 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4519 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4520 } 4521 4522 /* Set bit 9 of FWSTS clearing FW reset indication */ 4523 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4524 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4525 4526 /* Check that the host interface is enabled. */ 4527 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4528 if (!(hicr & IXGBE_HICR_EN)) { 4529 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4530 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4531 } 4532 4533 /* Calculate length in DWORDs. We must be DWORD aligned */ 4534 if (length % sizeof(u32)) { 4535 DEBUGOUT("Buffer length failure, not aligned to dword"); 4536 return IXGBE_ERR_INVALID_ARGUMENT; 4537 } 4538 4539 dword_len = length >> 2; 4540 4541 /* The device driver writes the relevant command block 4542 * into the ram area. 4543 */ 4544 for (i = 0; i < dword_len; i++) 4545 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4546 i, IXGBE_CPU_TO_LE32(buffer[i])); 4547 4548 /* Setting this bit tells the ARC that a new command is pending. */ 4549 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4550 4551 for (i = 0; i < timeout; i++) { 4552 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4553 if (!(hicr & IXGBE_HICR_C)) 4554 break; 4555 msec_delay(1); 4556 } 4557 4558 /* Check command completion */ 4559 if ((timeout && i == timeout) || 4560 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4561 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4562 "Command has failed with no status valid.\n"); 4563 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4564 } 4565 4566 return IXGBE_SUCCESS; 4567 } 4568 4569 /** 4570 * ixgbe_host_interface_command - Issue command to manageability block 4571 * @hw: pointer to the HW structure 4572 * @buffer: contains the command to write and where the return status will 4573 * be placed 4574 * @length: length of buffer, must be multiple of 4 bytes 4575 * @timeout: time in ms to wait for command completion 4576 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4577 * Needed because FW structures are big endian and decoding of 4578 * these fields can be 8 bit or 16 bit based on command. Decoding 4579 * is not easily understood without making a table of commands. 4580 * So we will leave this up to the caller to read back the data 4581 * in these cases. 4582 * 4583 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4584 * else returns semaphore error when encountering an error acquiring 4585 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4586 **/ 4587 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4588 u32 length, u32 timeout, bool return_data) 4589 { 4590 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4591 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4592 u16 buf_len; 4593 s32 status; 4594 u32 bi; 4595 u32 dword_len; 4596 4597 DEBUGFUNC("ixgbe_host_interface_command"); 4598 4599 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4600 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4601 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4602 } 4603 4604 /* Take management host interface semaphore */ 4605 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4606 if (status) 4607 return status; 4608 4609 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4610 if (status) 4611 goto rel_out; 4612 4613 if (!return_data) 4614 goto rel_out; 4615 4616 /* Calculate length in DWORDs */ 4617 dword_len = hdr_size >> 2; 4618 4619 /* first pull in the header so we know the buffer length */ 4620 for (bi = 0; bi < dword_len; bi++) { 4621 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4622 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4623 } 4624 4625 /* 4626 * If there is any thing in data position pull it in 4627 * Read Flash command requires reading buffer length from 4628 * two byes instead of one byte 4629 */ 4630 if (resp->cmd == 0x30) { 4631 for (; bi < dword_len + 2; bi++) { 4632 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4633 bi); 4634 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4635 } 4636 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4637 & 0xF00) | resp->buf_len; 4638 hdr_size += (2 << 2); 4639 } else { 4640 buf_len = resp->buf_len; 4641 } 4642 if (!buf_len) 4643 goto rel_out; 4644 4645 if (length < buf_len + hdr_size) { 4646 DEBUGOUT("Buffer not large enough for reply message.\n"); 4647 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4648 goto rel_out; 4649 } 4650 4651 /* Calculate length in DWORDs, add 3 for odd lengths */ 4652 dword_len = (buf_len + 3) >> 2; 4653 4654 /* Pull in the rest of the buffer (bi is where we left off) */ 4655 for (; bi <= dword_len; bi++) { 4656 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4657 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4658 } 4659 4660 rel_out: 4661 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4662 4663 return status; 4664 } 4665 4666 /** 4667 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4668 * @hw: pointer to the HW structure 4669 * @maj: driver version major number 4670 * @min: driver version minor number 4671 * @build: driver version build number 4672 * @sub: driver version sub build number 4673 * @len: unused 4674 * @driver_ver: unused 4675 * 4676 * Sends driver version number to firmware through the manageability 4677 * block. On success return IXGBE_SUCCESS 4678 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4679 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4680 **/ 4681 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4682 u8 build, u8 sub, u16 len, 4683 const char *driver_ver) 4684 { 4685 struct ixgbe_hic_drv_info fw_cmd; 4686 int i; 4687 s32 ret_val = IXGBE_SUCCESS; 4688 4689 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4690 UNREFERENCED_2PARAMETER(len, driver_ver); 4691 4692 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4693 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4694 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4695 fw_cmd.port_num = (u8)hw->bus.func; 4696 fw_cmd.ver_maj = maj; 4697 fw_cmd.ver_min = min; 4698 fw_cmd.ver_build = build; 4699 fw_cmd.ver_sub = sub; 4700 fw_cmd.hdr.checksum = 0; 4701 fw_cmd.pad = 0; 4702 fw_cmd.pad2 = 0; 4703 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4704 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4705 4706 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4707 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4708 sizeof(fw_cmd), 4709 IXGBE_HI_COMMAND_TIMEOUT, 4710 TRUE); 4711 if (ret_val != IXGBE_SUCCESS) 4712 continue; 4713 4714 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4715 FW_CEM_RESP_STATUS_SUCCESS) 4716 ret_val = IXGBE_SUCCESS; 4717 else 4718 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4719 4720 break; 4721 } 4722 4723 return ret_val; 4724 } 4725 4726 /** 4727 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4728 * @hw: pointer to hardware structure 4729 * @num_pb: number of packet buffers to allocate 4730 * @headroom: reserve n KB of headroom 4731 * @strategy: packet buffer allocation strategy 4732 **/ 4733 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4734 int strategy) 4735 { 4736 u32 pbsize = hw->mac.rx_pb_size; 4737 int i = 0; 4738 u32 rxpktsize, txpktsize, txpbthresh; 4739 4740 /* Reserve headroom */ 4741 pbsize -= headroom; 4742 4743 if (!num_pb) 4744 num_pb = 1; 4745 4746 /* Divide remaining packet buffer space amongst the number of packet 4747 * buffers requested using supplied strategy. 4748 */ 4749 switch (strategy) { 4750 case PBA_STRATEGY_WEIGHTED: 4751 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4752 * buffer with 5/8 of the packet buffer space. 4753 */ 4754 rxpktsize = (pbsize * 5) / (num_pb * 4); 4755 pbsize -= rxpktsize * (num_pb / 2); 4756 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4757 for (; i < (num_pb / 2); i++) 4758 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4759 /* fall through - configure remaining packet buffers */ 4760 case PBA_STRATEGY_EQUAL: 4761 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4762 for (; i < num_pb; i++) 4763 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4764 break; 4765 default: 4766 break; 4767 } 4768 4769 /* Only support an equally distributed Tx packet buffer strategy. */ 4770 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4771 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4772 for (i = 0; i < num_pb; i++) { 4773 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4774 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4775 } 4776 4777 /* Clear unused TCs, if any, to zero buffer size*/ 4778 for (; i < IXGBE_MAX_PB; i++) { 4779 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4780 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4781 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4782 } 4783 } 4784 4785 /** 4786 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4787 * @hw: pointer to the hardware structure 4788 * 4789 * The 82599 and x540 MACs can experience issues if TX work is still pending 4790 * when a reset occurs. This function prevents this by flushing the PCIe 4791 * buffers on the system. 4792 **/ 4793 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4794 { 4795 u32 gcr_ext, hlreg0, i, poll; 4796 u16 value; 4797 4798 /* 4799 * If double reset is not requested then all transactions should 4800 * already be clear and as such there is no work to do 4801 */ 4802 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4803 return; 4804 4805 /* 4806 * Set loopback enable to prevent any transmits from being sent 4807 * should the link come up. This assumes that the RXCTRL.RXEN bit 4808 * has already been cleared. 4809 */ 4810 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4811 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4812 4813 /* Wait for a last completion before clearing buffers */ 4814 IXGBE_WRITE_FLUSH(hw); 4815 msec_delay(3); 4816 4817 /* 4818 * Before proceeding, make sure that the PCIe block does not have 4819 * transactions pending. 4820 */ 4821 poll = ixgbe_pcie_timeout_poll(hw); 4822 for (i = 0; i < poll; i++) { 4823 usec_delay(100); 4824 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4825 if (IXGBE_REMOVED(hw->hw_addr)) 4826 goto out; 4827 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4828 goto out; 4829 } 4830 4831 out: 4832 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4833 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4834 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4835 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4836 4837 /* Flush all writes and allow 20usec for all transactions to clear */ 4838 IXGBE_WRITE_FLUSH(hw); 4839 usec_delay(20); 4840 4841 /* restore previous register values */ 4842 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4843 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4844 } 4845 4846 /** 4847 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 4848 * 4849 * @hw: pointer to hardware structure 4850 * @cmd: Command we send to the FW 4851 * @status: The reply from the FW 4852 * 4853 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 4854 **/ 4855 #define IXGBE_BYPASS_BB_WAIT 1 4856 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 4857 { 4858 int i; 4859 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 4860 u32 esdp; 4861 4862 if (!status) 4863 return IXGBE_ERR_PARAM; 4864 4865 *status = 0; 4866 4867 /* SDP vary by MAC type */ 4868 switch (hw->mac.type) { 4869 case ixgbe_mac_82599EB: 4870 sck = IXGBE_ESDP_SDP7; 4871 sdi = IXGBE_ESDP_SDP0; 4872 sdo = IXGBE_ESDP_SDP6; 4873 dir_sck = IXGBE_ESDP_SDP7_DIR; 4874 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4875 dir_sdo = IXGBE_ESDP_SDP6_DIR; 4876 break; 4877 case ixgbe_mac_X540: 4878 sck = IXGBE_ESDP_SDP2; 4879 sdi = IXGBE_ESDP_SDP0; 4880 sdo = IXGBE_ESDP_SDP1; 4881 dir_sck = IXGBE_ESDP_SDP2_DIR; 4882 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4883 dir_sdo = IXGBE_ESDP_SDP1_DIR; 4884 break; 4885 default: 4886 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 4887 } 4888 4889 /* Set SDP pins direction */ 4890 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4891 esdp |= dir_sck; /* SCK as output */ 4892 esdp |= dir_sdi; /* SDI as output */ 4893 esdp &= ~dir_sdo; /* SDO as input */ 4894 esdp |= sck; 4895 esdp |= sdi; 4896 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4897 IXGBE_WRITE_FLUSH(hw); 4898 msec_delay(IXGBE_BYPASS_BB_WAIT); 4899 4900 /* Generate start condition */ 4901 esdp &= ~sdi; 4902 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4903 IXGBE_WRITE_FLUSH(hw); 4904 msec_delay(IXGBE_BYPASS_BB_WAIT); 4905 4906 esdp &= ~sck; 4907 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4908 IXGBE_WRITE_FLUSH(hw); 4909 msec_delay(IXGBE_BYPASS_BB_WAIT); 4910 4911 /* Clock out the new control word and clock in the status */ 4912 for (i = 0; i < 32; i++) { 4913 if ((cmd >> (31 - i)) & 0x01) { 4914 esdp |= sdi; 4915 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4916 } else { 4917 esdp &= ~sdi; 4918 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4919 } 4920 IXGBE_WRITE_FLUSH(hw); 4921 msec_delay(IXGBE_BYPASS_BB_WAIT); 4922 4923 esdp |= sck; 4924 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4925 IXGBE_WRITE_FLUSH(hw); 4926 msec_delay(IXGBE_BYPASS_BB_WAIT); 4927 4928 esdp &= ~sck; 4929 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4930 IXGBE_WRITE_FLUSH(hw); 4931 msec_delay(IXGBE_BYPASS_BB_WAIT); 4932 4933 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4934 if (esdp & sdo) 4935 *status = (*status << 1) | 0x01; 4936 else 4937 *status = (*status << 1) | 0x00; 4938 msec_delay(IXGBE_BYPASS_BB_WAIT); 4939 } 4940 4941 /* stop condition */ 4942 esdp |= sck; 4943 esdp &= ~sdi; 4944 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4945 IXGBE_WRITE_FLUSH(hw); 4946 msec_delay(IXGBE_BYPASS_BB_WAIT); 4947 4948 esdp |= sdi; 4949 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4950 IXGBE_WRITE_FLUSH(hw); 4951 4952 /* set the page bits to match the cmd that the status it belongs to */ 4953 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 4954 4955 return IXGBE_SUCCESS; 4956 } 4957 4958 /** 4959 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 4960 * 4961 * If we send a write we can't be sure it took until we can read back 4962 * that same register. It can be a problem as some of the feilds may 4963 * for valid reasons change inbetween the time wrote the register and 4964 * we read it again to verify. So this function check everything we 4965 * can check and then assumes it worked. 4966 * 4967 * @u32 in_reg - The register cmd for the bit-bang read. 4968 * @u32 out_reg - The register returned from a bit-bang read. 4969 **/ 4970 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 4971 { 4972 u32 mask; 4973 4974 /* Page must match for all control pages */ 4975 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 4976 return FALSE; 4977 4978 switch (in_reg & BYPASS_PAGE_M) { 4979 case BYPASS_PAGE_CTL0: 4980 /* All the following can't change since the last write 4981 * - All the event actions 4982 * - The timeout value 4983 */ 4984 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 4985 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 4986 BYPASS_WDTIMEOUT_M | 4987 BYPASS_WDT_VALUE_M; 4988 if ((out_reg & mask) != (in_reg & mask)) 4989 return FALSE; 4990 4991 /* 0x0 is never a valid value for bypass status */ 4992 if (!(out_reg & BYPASS_STATUS_OFF_M)) 4993 return FALSE; 4994 break; 4995 case BYPASS_PAGE_CTL1: 4996 /* All the following can't change since the last write 4997 * - time valid bit 4998 * - time we last sent 4999 */ 5000 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 5001 if ((out_reg & mask) != (in_reg & mask)) 5002 return FALSE; 5003 break; 5004 case BYPASS_PAGE_CTL2: 5005 /* All we can check in this page is control number 5006 * which is already done above. 5007 */ 5008 break; 5009 } 5010 5011 /* We are as sure as we can be return TRUE */ 5012 return TRUE; 5013 } 5014 5015 /** 5016 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 5017 * 5018 * @hw: pointer to hardware structure 5019 * @cmd: The control word we are setting. 5020 * @event: The event we are setting in the FW. This also happens to 5021 * be the mask for the event we are setting (handy) 5022 * @action: The action we set the event to in the FW. This is in a 5023 * bit field that happens to be what we want to put in 5024 * the event spot (also handy) 5025 **/ 5026 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5027 u32 action) 5028 { 5029 u32 by_ctl = 0; 5030 u32 cmd, verify; 5031 u32 count = 0; 5032 5033 /* Get current values */ 5034 cmd = ctrl; /* just reading only need control number */ 5035 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5036 return IXGBE_ERR_INVALID_ARGUMENT; 5037 5038 /* Set to new action */ 5039 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5040 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5041 return IXGBE_ERR_INVALID_ARGUMENT; 5042 5043 /* Page 0 force a FW eeprom write which is slow so verify */ 5044 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5045 verify = BYPASS_PAGE_CTL0; 5046 do { 5047 if (count++ > 5) 5048 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5049 5050 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5051 return IXGBE_ERR_INVALID_ARGUMENT; 5052 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5053 } else { 5054 /* We have give the FW time for the write to stick */ 5055 msec_delay(100); 5056 } 5057 5058 return IXGBE_SUCCESS; 5059 } 5060 5061 /** 5062 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5063 * 5064 * @hw: pointer to hardware structure 5065 * @addr: The bypass eeprom address to read. 5066 * @value: The 8b of data at the address above. 5067 **/ 5068 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5069 { 5070 u32 cmd; 5071 u32 status; 5072 5073 5074 /* send the request */ 5075 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5076 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5077 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5078 return IXGBE_ERR_INVALID_ARGUMENT; 5079 5080 /* We have give the FW time for the write to stick */ 5081 msec_delay(100); 5082 5083 /* now read the results */ 5084 cmd &= ~BYPASS_WE; 5085 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5086 return IXGBE_ERR_INVALID_ARGUMENT; 5087 5088 *value = status & BYPASS_CTL2_DATA_M; 5089 5090 return IXGBE_SUCCESS; 5091 } 5092 5093 /** 5094 * ixgbe_get_orom_version - Return option ROM from EEPROM 5095 * 5096 * @hw: pointer to hardware structure 5097 * @nvm_ver: pointer to output structure 5098 * 5099 * if valid option ROM version, nvm_ver->or_valid set to TRUE 5100 * else nvm_ver->or_valid is FALSE. 5101 **/ 5102 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5103 struct ixgbe_nvm_version *nvm_ver) 5104 { 5105 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5106 5107 nvm_ver->or_valid = FALSE; 5108 /* Option Rom may or may not be present. Start with pointer */ 5109 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5110 5111 /* make sure offset is valid */ 5112 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5113 return; 5114 5115 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5116 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5117 5118 /* option rom exists and is valid */ 5119 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5120 eeprom_cfg_blkl == NVM_VER_INVALID || 5121 eeprom_cfg_blkh == NVM_VER_INVALID) 5122 return; 5123 5124 nvm_ver->or_valid = TRUE; 5125 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5126 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5127 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5128 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5129 } 5130 5131 /** 5132 * ixgbe_get_oem_prod_version - Return OEM Product version 5133 * 5134 * @hw: pointer to hardware structure 5135 * @nvm_ver: pointer to output structure 5136 * 5137 * if valid OEM product version, nvm_ver->oem_valid set to TRUE 5138 * else nvm_ver->oem_valid is FALSE. 5139 **/ 5140 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5141 struct ixgbe_nvm_version *nvm_ver) 5142 { 5143 u16 rel_num, prod_ver, mod_len, cap, offset; 5144 5145 nvm_ver->oem_valid = FALSE; 5146 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5147 5148 /* Return is offset to OEM Product Version block is invalid */ 5149 if (offset == 0x0 && offset == NVM_INVALID_PTR) 5150 return; 5151 5152 /* Read product version block */ 5153 hw->eeprom.ops.read(hw, offset, &mod_len); 5154 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5155 5156 /* Return if OEM product version block is invalid */ 5157 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5158 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5159 return; 5160 5161 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5162 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5163 5164 /* Return if version is invalid */ 5165 if ((rel_num | prod_ver) == 0x0 || 5166 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5167 return; 5168 5169 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5170 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5171 nvm_ver->oem_release = rel_num; 5172 nvm_ver->oem_valid = TRUE; 5173 } 5174 5175 /** 5176 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5177 * 5178 * @hw: pointer to hardware structure 5179 * @nvm_ver: pointer to output structure 5180 * 5181 * word read errors will return 0xFFFF 5182 **/ 5183 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5184 { 5185 u16 etk_id_l, etk_id_h; 5186 5187 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5188 etk_id_l = NVM_VER_INVALID; 5189 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5190 etk_id_h = NVM_VER_INVALID; 5191 5192 /* The word order for the version format is determined by high order 5193 * word bit 15. 5194 */ 5195 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5196 nvm_ver->etk_id = etk_id_h; 5197 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 5198 } else { 5199 nvm_ver->etk_id = etk_id_l; 5200 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 5201 } 5202 } 5203 5204 5205 /** 5206 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5207 * @hw: pointer to hardware structure 5208 * @map: pointer to u8 arr for returning map 5209 * 5210 * Read the rtrup2tc HW register and resolve its content into map 5211 **/ 5212 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5213 { 5214 u32 reg, i; 5215 5216 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5217 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5218 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5219 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5220 return; 5221 } 5222 5223 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5224 { 5225 u32 pfdtxgswc; 5226 u32 rxctrl; 5227 5228 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5229 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5230 if (hw->mac.type != ixgbe_mac_82598EB) { 5231 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5232 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5233 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5234 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5235 hw->mac.set_lben = TRUE; 5236 } else { 5237 hw->mac.set_lben = FALSE; 5238 } 5239 } 5240 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5241 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5242 } 5243 } 5244 5245 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5246 { 5247 u32 pfdtxgswc; 5248 u32 rxctrl; 5249 5250 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5251 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5252 5253 if (hw->mac.type != ixgbe_mac_82598EB) { 5254 if (hw->mac.set_lben) { 5255 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5256 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5257 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5258 hw->mac.set_lben = FALSE; 5259 } 5260 } 5261 } 5262 5263 /** 5264 * ixgbe_mng_present - returns TRUE when management capability is present 5265 * @hw: pointer to hardware structure 5266 */ 5267 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5268 { 5269 u32 fwsm; 5270 5271 if (hw->mac.type < ixgbe_mac_82599EB) 5272 return FALSE; 5273 5274 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5275 5276 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5277 } 5278 5279 /** 5280 * ixgbe_mng_enabled - Is the manageability engine enabled? 5281 * @hw: pointer to hardware structure 5282 * 5283 * Returns TRUE if the manageability engine is enabled. 5284 **/ 5285 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5286 { 5287 u32 fwsm, manc, factps; 5288 5289 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5290 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5291 return FALSE; 5292 5293 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5294 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5295 return FALSE; 5296 5297 if (hw->mac.type <= ixgbe_mac_X540) { 5298 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5299 if (factps & IXGBE_FACTPS_MNGCG) 5300 return FALSE; 5301 } 5302 5303 return TRUE; 5304 } 5305 5306 /** 5307 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5308 * @hw: pointer to hardware structure 5309 * @speed: new link speed 5310 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 5311 * 5312 * Set the link speed in the MAC and/or PHY register and restarts link. 5313 **/ 5314 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5315 ixgbe_link_speed speed, 5316 bool autoneg_wait_to_complete) 5317 { 5318 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5319 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5320 s32 status = IXGBE_SUCCESS; 5321 u32 speedcnt = 0; 5322 u32 i = 0; 5323 bool autoneg, link_up = FALSE; 5324 5325 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5326 5327 /* Mask off requested but non-supported speeds */ 5328 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5329 if (status != IXGBE_SUCCESS) 5330 return status; 5331 5332 speed &= link_speed; 5333 5334 /* Try each speed one by one, highest priority first. We do this in 5335 * software because 10Gb fiber doesn't support speed autonegotiation. 5336 */ 5337 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5338 speedcnt++; 5339 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5340 5341 /* Set the module link speed */ 5342 switch (hw->phy.media_type) { 5343 case ixgbe_media_type_fiber_fixed: 5344 case ixgbe_media_type_fiber: 5345 ixgbe_set_rate_select_speed(hw, 5346 IXGBE_LINK_SPEED_10GB_FULL); 5347 break; 5348 case ixgbe_media_type_fiber_qsfp: 5349 /* QSFP module automatically detects MAC link speed */ 5350 break; 5351 default: 5352 DEBUGOUT("Unexpected media type.\n"); 5353 break; 5354 } 5355 5356 /* Allow module to change analog characteristics (1G->10G) */ 5357 msec_delay(40); 5358 5359 status = ixgbe_setup_mac_link(hw, 5360 IXGBE_LINK_SPEED_10GB_FULL, 5361 autoneg_wait_to_complete); 5362 if (status != IXGBE_SUCCESS) 5363 return status; 5364 5365 /* Flap the Tx laser if it has not already been done */ 5366 ixgbe_flap_tx_laser(hw); 5367 5368 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5369 * Section 73.10.2, we may have to wait up to 500ms if KR is 5370 * attempted. 82599 uses the same timing for 10g SFI. 5371 */ 5372 for (i = 0; i < 5; i++) { 5373 /* Wait for the link partner to also set speed */ 5374 msec_delay(100); 5375 5376 /* If we have link, just jump out */ 5377 status = ixgbe_check_link(hw, &link_speed, 5378 &link_up, FALSE); 5379 if (status != IXGBE_SUCCESS) 5380 return status; 5381 5382 if (link_up) 5383 goto out; 5384 } 5385 } 5386 5387 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5388 speedcnt++; 5389 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5390 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5391 5392 /* Set the module link speed */ 5393 switch (hw->phy.media_type) { 5394 case ixgbe_media_type_fiber_fixed: 5395 case ixgbe_media_type_fiber: 5396 ixgbe_set_rate_select_speed(hw, 5397 IXGBE_LINK_SPEED_1GB_FULL); 5398 break; 5399 case ixgbe_media_type_fiber_qsfp: 5400 /* QSFP module automatically detects link speed */ 5401 break; 5402 default: 5403 DEBUGOUT("Unexpected media type.\n"); 5404 break; 5405 } 5406 5407 /* Allow module to change analog characteristics (10G->1G) */ 5408 msec_delay(40); 5409 5410 status = ixgbe_setup_mac_link(hw, 5411 IXGBE_LINK_SPEED_1GB_FULL, 5412 autoneg_wait_to_complete); 5413 if (status != IXGBE_SUCCESS) 5414 return status; 5415 5416 /* Flap the Tx laser if it has not already been done */ 5417 ixgbe_flap_tx_laser(hw); 5418 5419 /* Wait for the link partner to also set speed */ 5420 msec_delay(100); 5421 5422 /* If we have link, just jump out */ 5423 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 5424 if (status != IXGBE_SUCCESS) 5425 return status; 5426 5427 if (link_up) 5428 goto out; 5429 } 5430 5431 /* We didn't get link. Configure back to the highest speed we tried, 5432 * (if there was more than one). We call ourselves back with just the 5433 * single highest speed that the user requested. 5434 */ 5435 if (speedcnt > 1) 5436 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5437 highest_link_speed, 5438 autoneg_wait_to_complete); 5439 5440 out: 5441 /* Set autoneg_advertised value based on input link speed */ 5442 hw->phy.autoneg_advertised = 0; 5443 5444 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5445 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5446 5447 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5448 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5449 5450 return status; 5451 } 5452 5453 /** 5454 * ixgbe_set_soft_rate_select_speed - Set module link speed 5455 * @hw: pointer to hardware structure 5456 * @speed: link speed to set 5457 * 5458 * Set module link speed via the soft rate select. 5459 */ 5460 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5461 ixgbe_link_speed speed) 5462 { 5463 s32 status; 5464 u8 rs, eeprom_data; 5465 5466 switch (speed) { 5467 case IXGBE_LINK_SPEED_10GB_FULL: 5468 /* one bit mask same as setting on */ 5469 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5470 break; 5471 case IXGBE_LINK_SPEED_1GB_FULL: 5472 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5473 break; 5474 default: 5475 DEBUGOUT("Invalid fixed module speed\n"); 5476 return; 5477 } 5478 5479 /* Set RS0 */ 5480 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5481 IXGBE_I2C_EEPROM_DEV_ADDR2, 5482 &eeprom_data); 5483 if (status) { 5484 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5485 goto out; 5486 } 5487 5488 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5489 5490 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5491 IXGBE_I2C_EEPROM_DEV_ADDR2, 5492 eeprom_data); 5493 if (status) { 5494 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5495 goto out; 5496 } 5497 5498 /* Set RS1 */ 5499 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5500 IXGBE_I2C_EEPROM_DEV_ADDR2, 5501 &eeprom_data); 5502 if (status) { 5503 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5504 goto out; 5505 } 5506 5507 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5508 5509 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5510 IXGBE_I2C_EEPROM_DEV_ADDR2, 5511 eeprom_data); 5512 if (status) { 5513 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5514 goto out; 5515 } 5516 out: 5517 return; 5518 } 5519